Readout Circuit for a Dual-Mode Semiconductor Single-Photon Detector

Abstract

The present invention provides a readout circuit for a dual-mode semiconductor single-photon detector, which relates to the technical field of single-photon detection. The readout circuit includes: a control module for generating a control signal based on an external gating signal and an avalanche detection signal; an amplification module for controlling the single-photon detector to exit the Geiger mode when the control signal is in a low-level state, and for controlling the single-photon detector to enter the Geiger mode when the control signal is in a high-level state; an avalanche extraction module for extracting an avalanche signal to obtain a pulsed avalanche detection signal. When the gating signal is in a low-level state, the control module keeps the control signal in a low-level state. When the gating signal is in a high-level state, the control module makes the control signal become a low-level state based on the avalanche detection signal to quench the avalanche signal, and controls the control signal to become a high-level state again after a preset delay duration.

Description

Technical Field

[0001] The present invention relates to the technical field of single-photon detection, and particularly to a readout circuit for a dual-mode semiconductor single-photon detector. Background Art

[0002] Semiconductor single-photon detectors have detection sensitivities at the quantum limit and are important tools for detecting weak light, and are widely used in technical fields such as quantum communication, lidar, and life sciences.

[0003] A single-photon avalanche photodiode and a readout circuit are two core components of a semiconductor single-photon detector. According to the function of the readout circuit, semiconductor single-photon detectors can be divided into two operating modes: a free-running mode and a gated mode. In the free-running mode, the single-photon detector can detect photons arriving at any time, but is susceptible to strong light in the environment; the gated mode can effectively shield periodic strong light in the environment, but is generally used for detecting periodic signal light.

[0004] In some application scenarios, it is necessary to shield periodic strong light and detect randomly arriving signal photons, so a dual-mode single-photon detector is required. However, for readout circuits with a large gate width, there is still no suitable technical solution to achieve dual-mode operation. Summary of the Invention

[0005] In view of this, the present invention provides a readout circuit for a dual-mode semiconductor single-photon detector, which can enable the semiconductor single-photon detector to be compatible with the free-running mode and the gated mode.

[0006] As an aspect of an embodiment of the present invention, there is provided a readout circuit for a dual-mode semiconductor single-photon detector, including: a control module, configured to generate a control signal based on an external gated signal and an avalanche detection signal; an amplification module, configured to control the single-photon detector to exit the Geiger mode when the control signal is in a low level state; and to control the single-photon detector to enter the Geiger mode when the control signal is in a high level state; an avalanche extraction module, configured to extract the avalanche signal to obtain a pulsed avalanche detection signal, where the avalanche signal is generated by the single-photon detector being excited by signal photons in the Geiger mode; wherein, when the gated signal is in a low level state, the control module keeps the control signal in a low level state; when the gated signal is in a high level state, the control module makes the control signal become a low level state based on the avalanche detection signal, quenches the avalanche signal, and controls the control signal to become a high level state again after a preset delay duration.

[0007] According to an embodiment of the present invention, the cathode of the above single-photon detector is connected to a first power supply; the above amplification module is configured to: when the above control signal is in the low-level state, provide a first voltage to the anode of the above single-photon detector, so that the voltage difference between the first power supply and the voltage of the anode of the above single-photon detector is lower than the avalanche breakdown voltage, so that the above single-photon detector exits the Geiger mode; when the above control signal is in the high-level state, provide a second voltage to the anode of the above single-photon detector, so that the voltage difference between the first power supply and the voltage of the anode of the above single-photon detector is higher than the avalanche breakdown voltage, so that the above single-photon detector enters the Geiger mode; wherein, the second voltage is lower than the first voltage.

[0008] According to an embodiment of the present invention, the above control module is further configured to generate an active recovery signal at the rising edge when controlling the control signal to change back to the high-level state after a preset delay duration; the above amplification module is further configured to, based on the active recovery signal, control the voltage provided to the anode of the above single-photon detector to switch from the first voltage to the second voltage, so as to shorten the conversion time of the voltage of the anode of the above single-photon detector from the first voltage to the second voltage, improve the saturation count rate of the above single-photon detector, and reduce the afterpulse probability.

[0009] According to an embodiment of the present invention, the above amplification module includes: a first transistor, the source electrode of the first transistor is grounded, and the gate electrode of the first transistor is connected to the output end of the above control module; a first sub-unit, connected to the drain electrode of the first transistor, the first sub-unit, in response to the first transistor being cut off, controls the anode of the above single-photon detector to be conducted with a second power supply, so that the bias voltage on the PN junction of the above single-photon detector is lower than the avalanche breakdown voltage, and the above single-photon detector exits the Geiger mode; a second sub-unit, connected to the first sub-unit, in response to the first transistor being conducted, controls the anode of the above single-photon detector to be grounded, so that the bias voltage on the PN junction of the above single-photon detector is higher than the avalanche breakdown voltage, and the above single-photon detector enters the Geiger mode.

[0010] According to an embodiment of the present invention, the first sub-unit includes: a second transistor, the drain of the second transistor is connected to the second power supply; a first current-limiting resistor, one end of the first current-limiting resistor is connected to the drain of the second transistor, and the other end of the first current-limiting resistor is connected to the gate of the second transistor; a zener diode, the cathode of the zener diode is connected to the gate of the second transistor; a first diode, the anode of the first diode is connected to the anode of the zener diode, and the cathode of the first diode is connected to the source of the second transistor; a second diode, the anode of the second diode is connected to the cathode of the first diode, and the cathode of the second diode is connected to the anode of the single-photon detector.

[0011] According to an embodiment of the present invention, the first sub-unit further includes: an inductor, connected in series between the first current-limiting resistor and the gate of the second transistor.

[0012] According to an embodiment of the present invention, the second sub-unit includes: a third transistor, the source of the third transistor is grounded, the drain of the third transistor is connected to the source of the second transistor, and the gate of the third transistor is used to receive the active recovery signal; a fourth transistor, the source of the fourth transistor is grounded, the drain of the fourth transistor is connected to the anode of the single-photon detector, and the gate of the fourth transistor is used to receive the active recovery signal.

[0013] According to an embodiment of the present invention, the avalanche extraction module includes: a sampling resistor, one end of the sampling resistor is connected to the anode of the single-photon detector, the other end of the sampling resistor is grounded, and the sampling resistor is used to convert the avalanche signal into the avalanche detection signal.

[0014] According to an embodiment of the present invention, the avalanche extraction module further includes: a fifth transistor, the gate of the fifth transistor is connected to the third power supply, the source of the fifth transistor is grounded through the sampling resistor, and the drain of the fifth transistor is connected to the anode of the single-photon detector; a sixth transistor, the source of the sixth transistor is grounded, the drain of the sixth transistor is connected to the source of the fifth transistor, and the gate of the sixth transistor is used to receive the active recovery signal.

[0015] According to an embodiment of the present invention, the device further includes: a second current-limiting resistor, connected in series between the first power supply and the cathode of the single-photon detector.

[0016] The readout circuit of the dual-mode semiconductor single-photon detector according to an embodiment of the present invention realizes a dual-mode readout method of free-running mode and gated mode. On the one hand, the control module can generate a control signal based on the avalanche signal, and the amplification module, based on the control signal, enables the single-photon detector to immediately enter the idle state (exit the Geiger mode) after detecting the avalanche signal, realizing active quenching, and enabling the single-photon detector to quickly return to the enabled state (enter the Geiger mode) after a preset delay duration, thereby realizing photon detection in the free-running mode. On the other hand, the externally input gated signal can be a "closed door" signal or an "open door" signal. The control module can make the single-photon detector enter the idle state based on the externally input "closed door" signal, avoiding damage and signal interference to the single-photon detector caused by ambient strong light, and when the externally input "open door" signal is received, enabling the single-photon detector to detect randomly arriving signal photons in the free-running mode, improving the detection accuracy of the single-photon detector and extending the service life of the single-photon detector. Brief Description of the Drawings

[0017] Through the following description of the embodiments of the present invention with reference to the drawings, the above and other objects, features, and advantages of the present invention will become clearer. In the drawings:

[0018] Figure 1 The schematic diagram of the readout circuit of the dual-mode semiconductor single-photon detector according to an embodiment of the present invention is shown;

[0019] Figure 2 The circuit diagram of the amplification module according to an embodiment of the present invention is shown;

[0020] Figure 3 The circuit diagram of the avalanche extraction module according to an embodiment of the present invention is shown;

[0021] Figure 4 The schematic diagram of the readout circuit of the dual-mode semiconductor single-photon detector according to another embodiment of the present invention is shown.

[0022] The description of the reference numerals is as follows:

[0023] 1 - Control module;

[0024] 2 - Amplification module;

[0025] 21 - First sub-unit;

[0026] 22 - Second sub-unit;

[0027] 3 - Avalanche extraction module;

[0028] D1 - First diode;

[0029] D2 - Second diode;

[0030] L - Inductor;

[0031] N1 - First transistor;

[0032] N2 - Second transistor;

[0033] N3 - Third transistor;

[0034] N4 - Fourth transistor;

[0035] N5 - Fifth transistor;

[0036] P1 - First power supply;

[0037] P2 - Second power supply;

[0038] P3 - Third power supply;

[0039] R1 - First current - limiting resistor;

[0040] R2 - Second current - limiting resistor;

[0041] R3 - Sampling resistor;

[0042] ZD - Zener diode. Detailed implementation manners

[0043] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the following further elaborates on the present invention in detail with reference to specific embodiments and the accompanying drawings.

[0044] The terms used herein are merely for describing specific embodiments and are not intended to limit the present invention. The terms "including", "comprising", etc. used herein indicate the presence of the described features, steps, operations and / or components, but do not exclude the presence or addition of one or more other features, steps, operations or components.

[0045] All terms used herein, including technical and scientific terms, have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0046] In the case of using expressions such as "at least one of A, B, and C, etc.", generally, it should be interpreted according to the meaning that those skilled in the art usually understand this expression. For example, "a system having at least one of A, B, and C" should include, but not be limited to, a system having only A, only B, only C, having A and B, having A and C, having B and C, and / or having A, B, and C, etc. In the case of using expressions such as "at least one of A, B, or C, etc.", generally, it should be interpreted according to the meaning that those skilled in the art usually understand this expression. For example, "a system having at least one of A, B, or C" should include, but not be limited to, a system having only A, only B, only C, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.

[0047] It should also be noted that the directional terms mentioned in the embodiments, such as "up", "down", "front", "back", "left", "right", etc., are only references to the directions in the accompanying drawings and are not used to limit the protection scope of the present invention. Throughout the accompanying drawings, the same elements are denoted by the same or similar reference numerals. When it may cause confusion in the understanding of the present invention, the conventional structures or configurations will be omitted.

[0048] In the process of implementing the present invention, it is found that in some application scenarios, signal photons often arrive at the detector following a strong pulsed excitation light. When using a single-photon detector to detect such signals, on the one hand, the strong pulsed excitation light may damage the detector in the working state; on the other hand, the weak signal photons may be submerged in the quenching time or afterpulse count of the single-photon detector, reducing the signal-to-noise ratio of the detection.

[0049] Figure 1 The schematic diagram of the readout circuit of the dual-mode semiconductor single-photon detector according to an embodiment of the present invention is shown.

[0050] As an aspect of an embodiment of the present invention, a readout circuit of a dual-mode semiconductor single-photon detector is provided. As Figure 1As shown, the readout circuit of the dual-mode semiconductor single-photon detector includes a control module 1, an amplification module 2, and an avalanche extraction module 3. The control module 1 is used to generate a control signal based on an external gating signal and an avalanche detection signal. The amplification module 2 is used to control the single-photon detector to exit the Geiger mode when the control signal is in the low-level state; and to control the single-photon detector to enter the Geiger mode when the control signal is in the high-level state. The avalanche extraction module 3 is used to extract the avalanche signal to obtain a pulsed avalanche detection signal, and the avalanche signal is a weak current signal generated by the single-photon detector under the excitation of a signal photon in the Geiger mode. Among them, when the gating signal is in the low-level state, the control module keeps the control signal in the low-level state; when the gating signal is in the high-level state, the control module makes the control signal become the low-level state based on the avalanche detection signal, quenches the avalanche signal, and controls the control signal to become the high-level state again after a preset delay duration.

[0051] The readout circuit of the dual-mode semiconductor single-photon detector according to the embodiment of the present invention realizes a dual-mode readout method of free-running mode and gated mode. On the one hand, the control module can generate a control signal based on the avalanche signal, and the amplification module, based on the control signal, makes the single-photon detector immediately enter the idle state (exit the Geiger mode) after detecting the avalanche signal, realizing active quenching, and making the single-photon detector quickly return to the enabled state (enter the Geiger mode) after a preset delay duration, so as to realize photon detection in the free-running mode. On the other hand, the externally input gating signal can be a "closing" signal or an "opening" signal. The control module can make the single-photon detector enter the idle state based on the externally input "closing" signal, avoiding damage and signal interference caused by ambient strong light to the single-photon detector, and making the single-photon detector detect randomly arriving signal photons in the free-running mode when the externally input "opening" signal is received, improving the detection accuracy of the single-photon detector and extending the service life of the single-photon detector.

[0052] According to the embodiment of the present invention, the single-photon detector is a semiconductor single-photon detector, for example, it can be a single-photon avalanche diode (Single Photon Avalanche Diode, SPAD). When the reverse bias voltage of the single-photon avalanche diode is close to or exceeds the avalanche breakdown voltage, when a signal photon is absorbed by the single-photon avalanche diode SPAD, an avalanche effect will be triggered inside the device, generating a detectable avalanche signal.

[0053] In a schematic embodiment, the laser emits pulsed laser light, and the pulsed laser light irradiates the detection target to generate signal photons.

[0054] According to an embodiment of the present invention, the control module 1 may include a Field-Programmable Gate Array (FPGA), a D flip-flop, or the like.

[0055] According to an embodiment of the present invention, the range of the preset delay duration may include 50 - 100 nanoseconds (ns), for example, it may be any value among 50 ns, 60 ns, 70 ns, 80 ns, 90 ns, and 100 ns, etc.

[0056] In a schematic embodiment, the control signal is a level signal. When the control signal is in the high-level state, it indicates that the level signal is in a higher voltage state, which can be represented by logic "1". When the control signal is in the low-level state, it indicates that the level signal is in a lower voltage state, which can be represented by logic "0". When the control signal transitions between the high-level state and the low-level state, two characteristics will be generated: the rising edge and the falling edge. The rising edge and the falling edge can be used as trigger signals respectively to start an operation or trigger a series of logical actions.

[0057] In such an embodiment, when the control signal is in the high-level state, the control module, based on the rising edge of the avalanche detection signal, changes the control signal to the low-level state, causing the single-photon detector to quickly quench, reducing the possibility that weak signal photons are submerged in the quenching time or after-pulse count of the single-photon detector, thereby improving the signal-to-noise ratio.

[0058] According to an embodiment of the present invention, the external gating signal can set the duration of being in the "open door" signal and the duration of being in the "closed door" signal according to specific application scenarios.

[0059] According to an embodiment of the present invention, as Figure 1 shown, the cathode of the single-photon detector is connected to the first power supply P1. The amplification module 2 is used to provide a first voltage to the anode of the single-photon detector when the control signal is in the low-level state, so that the voltage difference between the first power supply and the anode of the single-photon detector is lower than the avalanche breakdown voltage, causing the single-photon detector to exit the Geiger mode. The amplification module 2 is used to provide a second voltage to the anode of the single-photon detector when the control signal is in the high-level state, so that the voltage difference between the first power supply and the anode of the single-photon detector is higher than the avalanche breakdown voltage, causing the single-photon detector to enter the Geiger mode. Among them, the second voltage is lower than the first voltage.

[0060] According to an embodiment of the present invention, the first voltage can be a high voltage of 30 V - 60V. It can be understood that the voltage range of the first voltage can also be any voltage range among 30 - 40V, 35 - 55V, or 40 - 60V, etc. For example, the first voltage can be any value among 30V, 40V, 50V, and 60V, etc.

[0061] According to an embodiment of the present invention, the second voltage can be a low voltage around 0V. For example, the second voltage can be any value among 0V, 0.5V, and 1V, etc.

[0062] According to an embodiment of the present invention, the control module 1 is further configured to generate an active recovery signal at the rising edge when the control signal returns to the high - level state again after a preset delay duration. The amplification module 2 is further configured to control the voltage provided to the anode of the single - photon detector to switch from the first voltage to the second voltage based on the active recovery signal, so as to shorten the conversion time of the voltage of the anode of the single - photon detector from the first voltage to the second voltage, improve the saturation count rate of the single - photon detector, and reduce the after - pulse probability.

[0063] In the process of implementing the present invention, it is found that in the absence of an active recovery signal, the voltage of the anode of the single - photon detector takes a very long time to recover from the first voltage (e.g., 60V) to the second voltage (e.g., 0V), on the order of ms. During this period, the single - photon detector cannot perform photon detection.

[0064] Based on the active recovery signal, the amplification module can quickly restore the voltage of the anode of the single - photon detector to the second voltage (e.g., 0V), which only takes on the order of ns (e.g., 10 - 20 ns). Therefore, the saturation count rate of the single - photon detector can be greatly improved, and the after - pulse probability can be reduced. Reducing the after - pulse probability means that in the single - photon detector, the probability of false pulses (i.e., after - pulses) caused by the previous photon detection event is reduced through technical means.

[0065] According to an embodiment of the present invention, the active recovery signal is a pulse signal.

[0066] In such an embodiment, the amplification module can enable the single - photon detector to allow a higher operating voltage (e.g., it can exceed 55V), which can improve the detection efficiency and detection performance of the single - photon detector.

[0067] According to an embodiment of the present invention, when the single-photon detector detects an avalanche of signal photons, based on the avalanche signal, the avalanche extraction module outputs an avalanche detection signal in a high-level state. Based on the avalanche detection signal in the high-level state, the control module causes the control signal to change to a low-level state. Based on the control signal in the low-level state, the amplification module controls to provide a second voltage to the anode of the single-photon detector of the single-photon detector, causing the single-photon detector to exit the Geiger mode. After a preset delay duration (for example, it can be 50-100 ns), the control module causes the control signal to become high-level again. While the control signal becomes high-level again (based on the rising edge of the control signal), the control module generates an active recovery signal. The amplification module can, based on the active recovery signal, quickly switch the voltage of the anode of the single-photon detector from the first voltage to the second voltage, enabling the single-photon detector to quickly enter the Geiger mode.

[0068] In such an embodiment, when the external gating signal is an "open door" signal, the single-photon detector is in the free-running module and can perform multiple detections and counting of signal photons.

[0069] Figure 2 The circuit diagram of the amplification module according to an embodiment of the present invention is shown.

[0070] According to an embodiment of the present invention, as Figure 2 shown, the amplification module 2 includes a first transistor N1, a first sub-unit 21, and a second sub-unit 22. The source of the first transistor N1 is grounded, the gate of the first transistor N1 is connected to the output terminal of the control module, and the gate of the first transistor is used to receive the control signal. The first sub-unit 21 is connected to the drain of the first transistor N1. In response to the first transistor N1 being cut off, the first sub-unit 21 controls the anode of the single-photon detector to conduct with the second power supply P2, so that the bias voltage on the PN junction of the single-photon detector is lower than the avalanche breakdown voltage, and the single-photon detector exits the Geiger mode. The second sub-unit 22 is connected to the first sub-unit 21. In response to the first transistor N1 being turned on, the second sub-unit 22 controls the anode of the single-photon detector to be grounded, so that the bias voltage on the PN junction of the single-photon detector is higher than the avalanche breakdown voltage, and the single-photon detector enters the Geiger mode. In such an embodiment, the second power supply P2 can provide the first voltage for the single-photon detector. The voltage difference between the first power supply P1 and the second power supply P2 is lower than the avalanche breakdown voltage of the single-photon detector, causing the single-photon detector to enter the linear mode. The single-photon detector entering the linear mode means that the single-photon detector operates in a low-gain state opposite to the Geiger mode. In the linear mode, the bias voltage of the single-photon detector is lower than the avalanche breakdown voltage, and the output signal is proportional to the incident light intensity, similar to the working mode of an ordinary photodiode.

[0071] In a schematic embodiment, the second power supply P2 can be a low-noise high-voltage DC power supply, and the voltage value of the second power supply P2 can be 60V. The voltage value of the second power supply P2 can also be other values, which are not limited herein.

[0072] In a schematic embodiment, the first transistor N1 can be an NMOS transistor (N-channel Metal-Oxide-Semiconductor Field-Effect Transistor).

[0073] In a schematic embodiment, when the control signal is in the low-level state, the source-drain voltage of the first transistor N1 is lower than the threshold voltage of the first transistor N1, and the first transistor N1 is in the cut-off state. In response to the first transistor N1 being cut off, the first sub-unit 21 raises the anode of the single-photon detector to the first voltage provided by the second power supply P2, so that the bias voltage between the cathode and the anode of the single-photon detector is lower than the avalanche breakdown voltage, and the single-photon detector exits the Geiger mode and enters the linear mode.

[0074] When the control signal is in the high-level state, the source-drain voltage of the first transistor N1 is higher than the threshold voltage of the first transistor N1, and the first transistor N1 is in the conducting state. The drain voltage of the first transistor N1 is close to zero. In response to the first transistor N1 being conducting, the second sub-unit 22 grounds the anode of the single-photon detector, and the voltage of the anode of the single-photon detector is pulled down to the second voltage (close to 0V), so that the bias voltage between the cathode and the anode of the single-photon detector is higher than the avalanche breakdown voltage, and the single-photon detector enters the Geiger mode, realizing the fast turn-on of the single-photon detector.

[0075] According to an embodiment of the present invention, as Figure 2 shown, the first sub-unit 21 includes a second transistor N2, a first current-limiting resistor R1, a voltage-regulator diode ZD, a first diode D1, and a second diode D2. The drain of the second transistor N2 is connected to the second power supply P2. One end of the first current-limiting resistor R1 is connected to the drain of the second transistor N2, and the other end of the first current-limiting resistor R1 is connected to the gate of the second transistor N2. The cathode of the voltage-regulator diode ZD is connected to the gate of the second transistor N2. The anode of the first diode D1 is connected to the anode of the voltage-regulator diode ZD, and the cathode of the first diode D1 is connected to the source of the second transistor N2. The anode of the second diode D2 is connected to the cathode of the first diode D1, and the cathode of the second diode D2 is connected to the anode of the single-photon detector.

[0076] In a schematic embodiment, the second transistor N2 can be an NMOS transistor. The second diode D2 can be a low-reverse-current diode.

[0077] In a schematic embodiment, when the control signal is in the low level state, the first transistor N1 is in the cut-off state, and current flows through the zener diode ZD, so that the gate-source voltage of the second transistor N2 is clamped above the threshold voltage of the second transistor N2, and the second transistor N2 is in the conducting state. The source voltage of the second transistor N2 is stabilized at 60V under the action of the second power supply P2, thereby pulling up the voltage of the anode of the single-photon detector to about 55V or 60V. The gate-source voltage of the second transistor N2 being clamped above the threshold voltage of the second transistor N2 means that the gate-source voltage of the second transistor N2 is always greater than or equal to the threshold voltage of the second transistor N2 to ensure that the second transistor is in the conducting state.

[0078] When the control signal is in the high level state, the first transistor N1 is in the conducting state, the drain of the first transistor N1 is grounded, and the gate voltage of the second transistor N2 approaches zero, so that the second transistor N2 is in the cut-off state.

[0079] According to an embodiment of the present invention, as Figure 2 shown, the second sub-unit 22 includes a third transistor N3 and a fourth transistor N4. The source of the third transistor N3 is grounded, the drain of the third transistor N3 is connected to the source of the second transistor N2, and the gate of the third transistor N3 is used to receive the active recovery signal. The source of the fourth transistor N4 is grounded, the drain of the fourth transistor N4 is connected to the anode of the single-photon detector, and the gate of the fourth transistor N4 is used to receive the active recovery signal.

[0080] In a schematic embodiment, the third transistor N3 and the fourth transistor N4 can be NMOS transistors.

[0081] In a schematic embodiment, when the pulsed laser ends and the signal photon has not reached the single-photon detector, the control signal is switched from the low level state to the high level state, the avalanche detection signal is in the low level state, the first transistor N1 is in the conducting state, and the second transistor N2 is in the cut-off state. The control module generates an active recovery signal based on the rising edge of the control signal. The gates of the third transistor N3 and the fourth transistor N4 both receive the active recovery signal, and the third transistor N3 and the fourth transistor N4 conduct, making the voltage of the anode of the single-photon detector close to 0V, and the single-photon detector quickly enters the Geiger mode.

[0082] In a schematic embodiment, after the single-photon detector detects a signal photon and generates an avalanche signal, the avalanche extraction module generates an avalanche detection signal according to the avalanche signal, that is, the avalanche detection signal changes from a low-level state to a high-level state. Based on the rising edge of the avalanche detection signal, the control module makes the control signal change to a low-level state, and the control signal in the low-level state quenches the avalanche signal through the amplification module 2, effectively reducing the avalanche duration, thereby suppressing the afterpulse effect.

[0083] The control module starts timing based on the rising edge of the avalanche detection signal, and makes the control signal become high-level again after a preset delay duration. At the same time, the control module generates an active recovery signal based on the rising edge of the control signal.

[0084] The gates of the third transistor N3 and the fourth transistor N4 both receive the active recovery signal, the third transistor N3 and the fourth transistor N4 are turned on, the drain voltages of the third transistor N3 and the fourth transistor N4 are close to zero, and the voltage of the anode of the single-photon detector is pulled down to close to 0V, enabling the single-photon detector to quickly enter the Geiger mode.

[0085] According to an embodiment of the present invention, as Figure 2 shown, the first sub-unit 21 further includes an inductor L. The inductor L is connected in series between the first current-limiting resistor R1 and the gate of the second transistor N2.

[0086] In such an embodiment, by setting the inductor L, when the control signal is in the low-level state, the inductor L can be charged by the second power supply P2, and after the control signal switches from the low-level state to the high-level state, the inductor L discharges quickly, so that the source voltage of the second transistor N2 is quickly clamped above the threshold of the second transistor N2, the second transistor N2 is turned on, and the source voltage of the second transistor N2 rises rapidly under the action of the second power supply P2, realizing the rapid quenching of the avalanche signal.

[0087] In a schematic embodiment, when the control signal is in the high-level state, the first transistor N1 is in the on state and the second transistor N2 is in the off state. The control module makes the single-photon detector enter the Geiger mode through the fast recovery signal generated based on the rising edge of the control signal. After the recovery signal ends, current flows through the inductor L and a part of it is stored on the inductor L.

[0088] In the case where a signal photon is detected by a single-photon detector to generate an avalanche signal, the avalanche detection signal output by the avalanche extraction module changes from a low level state to a high level state. The control module makes the control signal in a low level state based on the rising edge of the avalanche detection signal, and the first transistor N1 is in a cut-off state. The current stored in the inductor L quickly flows through the zener diode ZD, causing the second transistor N2 to be in a conducting state, quickly pulling up the anode of the single-photon detector, and realizing the rapid quenching of the avalanche signal.

[0089] According to an embodiment of the present invention, when the control signal is in a low level state, the amplification module controls the voltage of the anode of the single-photon detector to decrease, so that the single-photon detector is in a linear state (a state of exiting the Geiger mode) to avoid the illumination of strong light (such as pulsed laser).

[0090] When the control signal is in a high level state, the amplification module quickly turns on the detection working mode of the single-photon detector (entering the Geiger mode state) based on the control signal and the fast recovery signal, and stores part of the current on the inductor. The single-photon detector generates an avalanche signal, the avalanche extraction module extracts the avalanche detection signal, the control module changes to a low level state based on the avalanche detection signal, and the amplification module makes the current stored on the inductor quickly flow through the zener diode based on the control signal in the low level state, realizing the rapid quenching of the avalanche signal, so that the single-photon detector quickly exits the Geiger mode; after a preset delay duration after the single-photon detector has an avalanche, the amplification module makes the single-photon detector quickly enter the Geiger mode again based on the recovery signal.

[0091] Figure 3 The circuit diagram of the avalanche extraction module according to an embodiment of the present invention is shown.

[0092] According to an embodiment of the present invention, as Figure 3 shown, the avalanche extraction module 3 includes a sampling resistor R3. One end of the sampling resistor R3 is connected to the anode of the single-photon detector, and the other end of the sampling resistor R3 is grounded. The sampling resistor R3 is used to convert the avalanche signal into an avalanche detection signal.

[0093] According to an embodiment of the present invention, as Figure 3 shown, the avalanche extraction module 3 further includes a fifth transistor N5 and a sixth transistor N6. The gate of the fifth transistor N5 is connected to the third power supply P3, the source of the fifth transistor N5 is grounded through the sampling resistor R3, and the drain of the fifth transistor N5 is connected to the anode of the single-photon detector. The source of the sixth transistor N6 is grounded, the drain of the sixth transistor N6 is connected to the source of the fifth transistor N5, and the gate of the sixth transistor N6 is used to receive the active recovery signal.

[0094] In a schematic embodiment, the fifth transistor N5 and the sixth transistor N6 can be NMOS transistors.

[0095] In a schematic embodiment, the third power supply P3 may be a low-noise high-voltage DC power supply, and the voltage value of the third power supply P3 may be 4V. It can be understood that the voltage value of the third power supply P3 may also be any value among 3V, 3.5V, 4V, 4.5V, 5V, etc.

[0096] In a schematic embodiment, when the single-photon detector does not detect a signal photon, the source voltage of the fifth transistor N5 is close to zero. Under the action of the third power supply P3, the fifth transistor N5 is in a conducting state. The avalanche detection signal output by the avalanche extraction module 3 is in a low-level state.

[0097] In a schematic embodiment, when the single-photon detector detects a signal photon, the single-photon detector generates an avalanche signal, and the sampling resistor R3 quickly extracts the avalanche signal, causing the source voltage of the fifth transistor N5 to rise. The avalanche detection signal output by the avalanche extraction module 3 changes from a low-level state to a high-level state.

[0098] After the source voltage of the fifth transistor N5 rises such that the gate-source voltage of the fifth transistor N5 is less than its threshold voltage, the fifth transistor N5 turns off, causing the source voltage of the fifth transistor N5 to not be higher than the voltage value of the third power supply P3 (for example, 4V), thereby protecting the subsequent low-voltage circuit.

[0099] Based on the avalanche detection signal, the control module converts the control signal from a high-level state to a low-level state, and quickly quenches the avalanche signal through the amplification module. The control module starts timing based on the falling edge of the control signal. After a preset delay duration, the control module switches the control signal from a low-level state to a high-level state, and the control module generates an active recovery signal based on the rising edge of the control signal. The gate of the sixth transistor N6 is connected to the active recovery signal, the sixth transistor N6 conducts, and the drain voltage of the sixth transistor N6 is close to zero, that is, the source voltage of the fifth transistor N5 drops to close to zero, causing the fifth transistor N5 to conduct again.

[0100] The maximum number of signal photons that a single-photon detector can detect within a certain period of time is called the saturation counting rate. When the number of incident signal photons exceeds the saturation counting rate, the single-photon detector will not be able to effectively detect all signal photons, resulting in a decrease in detection efficiency.

[0101] According to the embodiments of the present invention, the avalanche extraction module can quickly extract weak avalanche signals through the sampling resistor, and can also shield large-amplitude voltage signals for turning on and off the anode of the single-photon detector through the fifth transistor N5 and the sixth transistor N6, which not only protects the subsequent low-voltage circuit, but also shortens the extraction time of the avalanche signal, improves the saturation counting rate of the single-photon detector, and thus improves the detection efficiency.

[0102] Figure 4 Shows a schematic diagram of the readout circuit of a dual-mode semiconductor single-photon detector according to another embodiment of the present invention.

[0103] According to an embodiment of the present invention, as Figure 4 shown, the readout circuit further includes a second current-limiting resistor R2. The second current-limiting resistor R2 is connected in series between the first power supply P1 and the cathode of the single-photon detector.

[0104] According to an embodiment of the present invention, when the control signal is in the low-level state, the amplification module 2 causes the single-photon detector to exit the Geiger mode.

[0105] When the control signal is in the high-level state and the single-photon detector does not detect a signal photon, the avalanche detection signal output by the avalanche extraction module 3 is in the low-level state, and the amplification module 2 causes the single-photon detector to enter the Geiger mode based on the control signal.

[0106] In a schematic embodiment, when the control signal is in the high-level state, if the single-photon detector detects a signal photon and generates an avalanche signal, the avalanche extraction module 3 extracts the avalanche signal, and the output avalanche detection signal changes from the low-level state to the high-level state. Based on the rising edge of the avalanche detection signal, the control module 1 changes the control signal to the low-level state. The amplification module quenches the avalanche signal based on the control signal in the low-level state. After a preset delay duration, the control module controls the control signal in the low-level state to return to the high-level state after a preset delay duration, and generates an active recovery signal based on the rising edge of the control signal. Based on the active recovery signal, the avalanche extraction module 3 causes the source voltage of the fifth transistor N5 to drop to nearly zero, preparing for the detection of the next avalanche signal.

[0107] Further, after a delay of approximately 50 ns, the control module 1 changes the control signal from the low-level state back to the high-level state. Based on the rising edge of the control signal, the amplification module 2 causes the voltage of the anode of the single-photon detector to drop to about 0V within 20 ns, and the single-photon detector quickly re-enters the Geiger mode.

[0108] When the control signal is in the high-level state, the amplification module 2 causes the drain voltage of the third transistor N3 and the drain voltage of the fourth transistor N4 to be nearly zero based on the control signal and the active recovery signal. Within approximately 10 ns, the amplification module 2 pulls down the voltage of the anode of the single-photon detector to 0V, and the single-photon detector enters the Geiger mode again. The single-photon detector has completed the detection of the signal photon this time and resumes the detection working mode (that is, re-enters the Geiger mode), waiting for the next single-photon detection.

[0109] In a schematic embodiment, when the single-photon detector is in the free-running mode, when the next pulse laser is emitted by the laser, the control signal becomes low level. Within 20 ns, the voltage of the anode of the single-photon detector is raised to 55 V by the amplification module 2, and the single-photon detector exits the Geiger mode. When the intense light of the next pulse laser irradiates the single-photon detector, the detection working mode of the single-photon detector is turned off (i.e., exits the Geiger mode).

[0110] According to an embodiment of the present invention, when the single-photon detector is in the free-running mode, the time taken for a single signal photon detection is about 50 ns, and a saturation counting rate of up to 20 Mcps can be achieved.

[0111] The embodiments of the present invention have been described above. However, these embodiments are for illustrative purposes only and not for limiting the scope of the present invention. Although the embodiments are described separately above, this does not mean that the measures in each embodiment cannot be used in combination advantageously. Without departing from the scope of the present invention, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should fall within the scope of the present invention.

Claims

1. A readout circuit for a dual-mode semiconductor single-photon detector, characterized in that, Comprising: A control module for generating a control signal based on an external gating signal and an avalanche detection signal; An amplification module for controlling the single-photon detector to exit the Geiger mode when the control signal is in a low level state; And controlling the single-photon detector to enter the Geiger mode when the control signal is in a high level state; the cathode of the single-photon detector is connected to a first power supply; An avalanche extraction module, comprising: A sampling resistor, one end of which is connected to the anode of the single-photon detector and the other end is grounded. The sampling resistor is used to convert the avalanche signal into an avalanche detection signal; the avalanche signal is generated by the excitation of the signal photon when the single-photon detector is in the Geiger mode; A fifth transistor, the gate of the fifth transistor is connected to a third power supply, the source of the fifth transistor is grounded through the sampling resistor, and the drain of the fifth transistor is connected to the anode of the single-photon detector; A sixth transistor, the source of the sixth transistor is grounded, the drain of the sixth transistor is connected to the source of the fifth transistor, and the gate of the sixth transistor is used to receive an active recovery signal; When the gating signal is in a low level state, the control module keeps the control signal in a low level state; when the gating signal is in a high level state, the control module makes the control signal become a low level state based on the avalanche detection signal, quenches the avalanche signal, and controls the control signal to become a high level state again after a preset delay duration, and generates an active recovery signal based on the rising edge when the control signal becomes a high level state again after the preset delay duration.

2. The readout circuit according to claim 1, wherein: The amplification module is configured to: When the control signal is in the low level state, provide a first voltage to the anode of the single-photon detector, so that the voltage difference between the first power supply and the anode of the single-photon detector is lower than the avalanche breakdown voltage, so that the single-photon detector exits the Geiger mode; When the control signal is in the high level state, provide a second voltage to the anode of the single-photon detector, so that the voltage difference between the first power supply and the anode of the single-photon detector is higher than the avalanche breakdown voltage, so that the single-photon detector enters the Geiger mode; wherein, the second voltage is lower than the first voltage.

3. The readout circuit according to claim 2, wherein: The amplification module is further configured to control the voltage provided to the anode of the single-photon detector to switch from the first voltage to the second voltage based on the active recovery signal, so as to shorten the conversion time of the voltage of the anode of the single-photon detector from the first voltage to the second voltage, improve the saturation count rate of the single-photon detector, and reduce the afterpulse probability.

4. The readout circuit according to claim 3, wherein The amplification module includes: A first transistor, the source of the first transistor is grounded, and the gate of the first transistor is connected to the output end of the control module; A first sub-unit, connected to the drain of the first transistor, the first sub-unit, in response to the first transistor being turned off, controls the anode of the single-photon detector to conduct with the second power supply, so that the bias voltage across the PN junction of the single-photon detector is lower than the avalanche breakdown voltage, and the single-photon detector exits the Geiger mode; A second sub-unit, connected to the first sub-unit, in response to the first transistor being turned on, controls the anode of the single-photon detector to be grounded, so that the bias voltage across the PN junction of the single-photon detector is higher than the avalanche breakdown voltage, and the single-photon detector enters the Geiger mode.

5. The readout circuit according to claim 4, wherein The first sub-unit includes: A second transistor, the drain of the second transistor is connected to the second power supply; A first current-limiting resistor, one end of the first current-limiting resistor is connected to the drain of the second transistor, and the other end of the first current-limiting resistor is connected to the gate of the second transistor; A zener diode, the cathode of the zener diode is connected to the gate of the second transistor; A first diode, the anode of the first diode is connected to the anode of the zener diode, and the cathode of the first diode is connected to the source of the second transistor; A second diode, the anode of the second diode is connected to the cathode of the first diode, and the cathode of the second diode is connected to the anode of the single-photon detector.

6. The readout circuit according to claim 5, wherein The first sub-unit further includes: An inductor, connected in series between the first current-limiting resistor and the gate of the second transistor.

7. The readout circuit according to claim 5, characterized in that, The second sub-unit includes: A third transistor, the source of the third transistor is grounded, the drain of the third transistor is connected to the source of the second transistor, and the gate of the third transistor is used to receive the active recovery signal; A fourth transistor, the source of the fourth transistor is grounded, the drain of the fourth transistor is connected to the anode of the single-photon detector, and the gate of the fourth transistor is used to receive the active recovery signal.

8. The readout circuit according to any one of claims 2-7, characterized in that, Further included: A second current-limiting resistor, connected in series between the first power supply and the cathode of the single-photon detector.

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