Ultrasonic echo signal acquisition error correction method and device and ultrasonic flaw detection equipment

Abstract

The invention belongs to the technical field of signal acquisition, and provides an ultrasonic echo signal acquisition error correction method and device and ultrasonic flaw detection equipment, and the technical scheme is as follows: receiving an FCLK frame signal, and decoding the FCLK frame signal; judging whether the decoding result of the FCLK frame signal meets a set condition or not, if the decoding result of the FCLK frame signal does not meet the set condition, determining that decoding of parallel echo data acquisition channels has dislocation, pausing a data acquisition process, generating a shift pulse, and performing a shift operation on parallel output echo data until the decoding result meets the set condition; if yes, decoding is correct, echo data collection is started, and ultrasonic echo signals are obtained. By determining the generation opportunity of the shift pulse, decoding errors are found and corrected under the condition that normal work is not affected, subsequent step time consumption caused by data errors is reduced to the minimum, and the working efficiency of ultrasonic flaw detection equipment is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of signal acquisition, and in particular relates to an ultrasonic echo signal acquisition error correction method and device, and ultrasonic flaw detection equipment. Background Art

[0002] The statements in this section merely provide background information related to the present invention and do not necessarily constitute prior art.

[0003] In an ultrasound system, the system needs to collect echo data for imaging analysis, so an ADC chip is needed to convert analog signals into digital signals that the system can process. The frequency of ultrasound signals is generally between hundreds of kHz and tens of MHz. According to the sampling theorem, the ADC sampling speed is at least twice that of the ultrasound signal. In this case, the ADC must use high-speed data transmission technology to output the converted data in a timely manner. LVDS is a communication technology used by many high-speed multi-channel ADCs.

[0004] Traditional high-speed ADC chips have built-in LVDS output data test modes. After the FPGA master chip is powered on, in order to confirm whether the ADC output data is correct, the LVDS interface of the ADC chip will be set to test mode first. In test mode, the output data of the LVDS DATA data channel is usually in certain specific formats, such as all 1s or all 0s, which is used to assist the FPGA master in bit error correction. After the error correction is completed, the FPGA master sets the ADC's LVDS interface to normal working mode before the system starts working.

[0005] Traditionally, system startup requires two steps, namely test mode and normal mode. The startup time is long, and the switching cannot be guaranteed to be synchronous. It is possible that the test mode is normal but the normal mode data is misplaced, resulting in system startup failure. Summary of the invention

[0006] In order to solve at least one technical problem existing in the above-mentioned background technology, the present invention provides an ultrasonic echo signal acquisition error correction method, device and ultrasonic flaw detection equipment, which can detect and correct decoding errors without affecting normal operation by confirming the generation timing of the bitslip pulse, thereby minimizing the time consumption of subsequent steps caused by data errors and improving the working efficiency of the ultrasonic flaw detection equipment.

[0007] In order to achieve the above object, the present invention adopts the following technical solution: A first aspect of the present invention provides an ultrasonic echo signal acquisition error correction method, comprising the following steps: Configure ultrasonic echo signal acquisition to enter normal working mode; Receive the FCLK frame signal and decode the FCLK frame signal; Determine whether the decoding result of the FCLK frame signal meets the set conditions. If not, there is a misalignment in the decoding of the parallel echo data acquisition channel. The data acquisition process is suspended, a shift pulse is generated, and a shift operation is performed on the parallel output echo data until the decoding result meets the set conditions. If it matches, the decoding is correct, echo data acquisition starts, and the ultrasonic echo signal is obtained.

[0008] Furthermore, when the decoding result of the FCLK frame signal is not all 1 or all 0, there is a misalignment in the decoding of the parallel echo data acquisition channels.

[0009] Furthermore, the FCLK frame signal is connected to the ISERDESE2 module for decoding as data input, and other ultrasonic echo signal acquisition data channels are connected to the corresponding ISERDESE2 modules. There are multiple parallel ISERDESE2 modules in the system, one module decodes the FCLK frame signal, and other modules decode the ultrasonic echo signal data channels.

[0010] Furthermore, if there is a misalignment in the decoding of the parallel echo data acquisition channels, a bitslip pulse is generated to the ISERDESE2 module to perform an overall shift operation on the parallel output data, and adjust the output data to move to the bit order of the correct data.

[0011] Furthermore, a set time is waited after the shift operation is performed, and the set time is consistent with the time required for internal shifting after receiving the bitslip pulse.

[0012] A second aspect of the present invention provides an ultrasonic echo signal acquisition and error correction device, comprising: A working module configuration module is used to configure the ultrasonic echo signal acquisition to enter a normal working mode; A signal decoding module, used for receiving the FCLK frame signal and decoding the FCLK frame signal; The signal error correction module is used to determine whether the decoding result of the FCLK frame signal meets the set conditions. If the set conditions are not met, there is a misalignment in the decoding of the parallel echo data acquisition channel, and the data acquisition process is suspended, a shift pulse is generated, and a shift operation is performed on the parallel output echo data until the decoding result meets the set conditions; If it matches, the decoding is correct, echo data acquisition starts, and the ultrasonic echo signal is obtained.

[0013] Furthermore, the FCLK frame signal is connected to the ISERDESE2 module for decoding as data input, and other ultrasonic echo signal acquisition data channels are connected to the corresponding ISERDESE2 modules. There are multiple parallel ISERDESE2 modules in the system, one module decodes the FCLK frame signal, and other modules decode the ultrasonic echo signal data channels.

[0014] Furthermore, in the signal error correction module, when the decoding result of the FCLK frame signal is not all 1 or all 0, there is a misalignment in the decoding of the parallel echo data acquisition channels.

[0015] Furthermore, a set time is waited after the shift operation is performed, and the set time is consistent with the time required for internal shifting after receiving the bitslip pulse.

[0016] A third aspect of the present invention provides a computer-readable storage medium.

[0017] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps in the ultrasonic echo signal acquisition and error correction method as described above.

[0018] A fourth aspect of the present invention provides a computer device.

[0019] A computer device comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the steps in the ultrasonic echo signal acquisition and error correction method as described above are implemented.

[0020] Compared with the prior art, the present invention has the following beneficial effects: 1. The present invention determines the generation timing of the bitslip pulse, discovers and corrects decoding errors without affecting normal operation, reduces the time consumption of subsequent steps caused by data errors to a minimum, and improves the working efficiency of ultrasonic flaw detection equipment.

[0021] 2. The present invention is generally applicable to most high-speed multi-channel ADC data acquisition occasions that use LVDS for communication, and is not targeted at a specific FPGA platform. This solution describes the situation where the ISERDESE2 module is used for decoding on the Xilinx ZYNQ platform. The decoding modules may be different in different FPGA integration solutions, but the method of using FCLK as data input and decoding comparison is universal.

[0022] 3. The present invention is applicable to data misalignment correction of ADCs with different bit numbers. Accordingly, the present system method can be used after only adjusting the number of bits of all 1 or all 0 to be compared.

[0023] 4. The error correction of the method of the present invention is short. Taking 50MHz system clock and decoding 10-bit ADC data as an example, in the worst case of 10-bit full error to the left or right, only 10×(3+1)=40 system clocks are needed to complete the error correction, and the time consumption is 40×(1000000000 / 50000000)=800ns, which can meet the real-time requirements of the entire acquisition system. Compared with the traditional method of first configuring the ADC to the test mode, then performing comparison and error correction, and then configuring the ADC back to the normal mode, the efficiency is greatly improved, and it can also be used for ADCs that do not support the test mode.

[0024] 5. The present invention does not need to determine the specific data of the data source. The comparison data only comes from the result of decoding FCLK by the decoding module. The comparison result is used to control the bitslip shift operation of the decoding module, which reduces the complexity of system design and simplifies the development process.

[0025] Advantages of additional aspects of the present invention will be given in part in the following description, and in part will become obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings in the specification, which constitute a part of the present invention, are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0027] Figure 1 This is a schematic diagram of LVDS signal; Figure 2 This is a schematic diagram of the LVDS data transmission channel; Figure 3 This is a schematic diagram of the ISERDESE2 decoding process; Figure 4 is a flow chart of the ultrasonic echo signal acquisition and error correction method provided in this embodiment; Figure 5 It is a schematic diagram of the bitslip operation process provided in this embodiment. DETAILED DESCRIPTION

[0028] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0029] It should be noted that the following detailed descriptions are all illustrative and intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present invention belongs.

[0030] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0031] Explanation of terms LVDS (Low Voltage Differential Signaling) is a high-speed data transmission technology, such as Figure 1 As shown, it transmits data through differential signals and has the advantages of low power consumption, low noise, high bandwidth, and long-distance transmission. LVDS signals are usually composed of a pair of differential pairs CLKP and CLKN, and a pair of differential pairs can transmit one bit of data.

[0032] Bitslip is a function used in ISERDES (Input Serial to Parallel Converter) to rearrange the order of parallel data streams entering the FPGA logic. Bitslip solves the data boundary alignment problem by delaying data transmission by one clock cycle so that the data can be realigned to the word boundary.

[0033] Under normal working conditions, LVDS transmission has at least three channels: bit clock channel, FCLK frame clock channel and DATA data channel. Infinity Fabric Clock (FCLK) is a clock used in AMD processors to control the frequency of the Infinity Fabric communication bus. FCLK determines the operating performance of Infinity Fabric and directly affects the data transmission speed and efficiency between components inside the processor.

[0034] like Figure 2The figure shows the LVDS data transmission channel. FCLK is the indication signal for data frame output. The high and low levels of FCLK represent a frame of data output on the DATA data line. The DATA channel is the data output channel. A 10-bit data frame appears on the DATA channel in sequence from the high bit. Its changing frequency is the clock signal frequency on the BIT clock channel. The edge of FCLK is the beginning of a data frame. ADC data is serially output through the LVDS data channel. The frame clock indicates a complete ADC data through its high and low levels. For example, the data of ADC channel 1 is transmitted during the high level period, and the data of ADC channel 2 is transmitted during the low level period. The output is alternating to improve the utilization of the data line. The bit clock is used to indicate when the receiving end receives a new bit. The data bit is usually valid at the bit clock transition edge, that is, DDR. The data output frequency is twice the bit clock.

[0035] LVDS is usually used in situations where high-speed data transmission is required, and an FPGA platform is generally used for decoding and subsequent operations.

[0036] Use Xilinx's Zynq platform for decoding. The platform provides the ISERDESE2 module for receiving and decoding operations, such as Figure 3 As shown, it is a serial-to-parallel module, the D interface is the serial data input interface, EDCBA are the bit data of the serial input, Q1-Q8 are the parallel output ports, the serial data is serially input through the D interface, and after several clocks, it is output in parallel at the data output ports Q1-Q8, CLK_RX is the clock of the serial data at the D end, and CLKDIV_RX is the divided version of the serial data clock at the D end, which is used to provide data boundary distinction.

[0037] It is difficult to accurately predict the time from when the chip is powered on to when the clock is stable, so it is not easy to determine the starting position of the data. Figure 2 It can be seen that the boundary between two independent data is distinguished by the level of the FCLK clock. The unstable state after power-on can easily cause the starting position of the data to be misaligned. Therefore, the decoding module needs to provide an operation that can dynamically adjust the starting position of the decoded data through a pulse input signal to correct the data shift error.

[0038] There is also a problem. Even after the correct bit order has been adjusted, the high-speed clock will jitter due to temperature rise and other issues, resulting in data misalignment. Therefore, a reference data that is not affected by temperature or changes synchronously with the clock data is needed to dynamically adjust the bitslip to achieve data alignment.

[0039] Traditionally, high-speed ADC chips have built-in LVDS output data test modes. After the FPGA master chip is powered on, in order to confirm whether the ADC output data is correct, the LVDS interface of the ADC chip will be set to test mode first. In test mode, the output data of the LVDS DATA data channel is usually in certain specific formats, such as all 1s or all 0s, which is used to assist the FPGA master in bit error correction. After the error correction is completed, the FPGA master will set the ADC's LVDS interface to normal working mode before the system starts working.

[0040] Traditionally, system startup requires two steps, namely test mode and normal mode. The startup time is long, and the switching cannot be guaranteed to be synchronous. It is possible that the test mode is normal but the normal mode data is misplaced, resulting in system startup failure.

[0041] The present invention abandons the traditional two-step startup mode. When the system is powered on, the ADC is directly configured to enter the normal mode. The FPGA master control end monitors the frame clock data output in real time and in parallel through the scheme of the present invention. When an error is found, the correction process is started, and bitslip pulses are dynamically generated to realize automatic data error correction, which greatly improves the startup speed of the system and reduces the probability of system startup failure.

[0042] Embodiment 1 like Figure 4 As shown, this embodiment provides a data acquisition error correction method. The present invention abandons the traditional two-step startup mode. When the system is powered on, the ADC is directly configured to enter the normal mode. Through this solution, the FPGA master control end monitors the frame clock data output in real time and in parallel. When an error is found, the correction process is started, and bitslip pulses are dynamically generated to realize automatic data error correction, which greatly improves the system startup speed and reduces the probability of system startup failure.

[0043] The specific steps include: Step 1: Configure echo data acquisition to enter normal working mode; Traditionally, system startup requires two steps, namely test mode and normal mode. The startup time is long, and the switching cannot be guaranteed to be synchronous. It is possible that the test mode is normal but the normal mode data is misplaced, resulting in system startup failure.

[0044] In this embodiment, the ADC is directly configured to enter the normal mode; Step 2: Receive the FCLK frame signal and decode the FCLK frame signal; The FCLK frame signal is used as data input to be connected to the ISERDESE2 module for decoding, and other ultrasonic echo signal acquisition data channels are connected to the corresponding ISERDESE2 modules; in this way, there are multiple parallel ISERDESE2 modules in the system, one module decodes FCLK, and other modules decode DATA channels; FCLK (Infinity Fabric Clock) is the internal bus frequency used to connect different cores and caches in AMD processors. FCLK is mainly used to coordinate data transmission between different modules inside the CPU to ensure data consistency and efficient transmission.

[0045] In this embodiment, decoding the FCLK frame signal specifically includes: connecting the FCLK frame to the D data input port of ISERDESE2, the data input clock is the bit clock, and finally outputting the data decoded from FCLK at the output port of ISERDESE2.

[0046] Step 3: Determine whether the decoding result of the FCLK frame signal meets the set conditions. If not, there is a misalignment in the decoding of the parallel echo data acquisition channel. The data acquisition process is suspended, a shift pulse is generated, and a shift operation is performed on the parallel output echo data until the decoding result meets the set conditions. If yes, the decoding is correct, and echo data acquisition is started to obtain an ultrasonic echo signal. In this embodiment, the ISERDESE2 module is used to decode the FCLK frame signal as an example. Figure 2 As shown in the figure, the duration of FCLK high or low is the same as the duration of a complete ADC data, that is, D 0 -D 9 The duration of D is the same as the high level duration of FCLK. 0 -D 9 is a complete ADC data bit, that is, 10 bits of data, which are D 0, D 1, ... D 8， D 9 , its duration is 10 times the period of the bit clock. Therefore, in the case of no misalignment in decoding, the decoding output result of ISERDESE2 input by FCLK should be all 1 or all 0, and the number of output bits should be the same as the number of bits of ADC output data. Next, determine whether the decoding result of ISERDESE2 input by FCLK is all 1 (or all 0, low level situation); Therefore, if the decoding result is not all 1s (or all 0s, low level condition), it can be determined that there is a misalignment in the ISERDESE2 module decoding.

[0047] In this embodiment, when there is a misalignment in the decoding of the ISERDESE2 module, a bitslip pulse is generated to the ISERDESE2 module to perform an overall shift operation on the parallel output data to adjust the output data to move to the bit sequence of the correct data.

[0048] The ISERDESE2 module provides bitslip operation, i.e., bit sliding. The external program only needs to give a pulse signal to the bitslip port at the appropriate time, and the ISERDESE2 module can automatically start a shift operation, such as Figure 5 As shown, Figure 5 This is the block diagram of the bitslip function module of the Xilinx 7 series FPGA ISERDES2 module. The D interface is the input bit data, which is ABCD in sequence and cyclically output. CLK is the clock of the bit data, CLKDIV is the two-divided version of CLK, Q4-Q1 is the parallel output data of the ISERDES2 module, and bitslip is the shift pulse input to ISERDES2. Before the bitslip pulse, the output of Q4-Q1 is CDAB, but the normal data input should be ABCD, so shift adjustment is required. After the bitslip pulse, the output of Q4-Q1 is BCDA, which is one position right-shifted compared to the Q4-Q1 before the bitslip pulse. If the bitslip pulse is given in sequence, Q4-Q1 can be output as ABCD, and the output shift error correction is completed.

[0049] The above is only a simple example. In actual situations, the decoding output shift is different each time the system is powered on. This embodiment solves the problem of misalignment in ISERDESE2 module decoding by giving a pulse signal to the bitslip port at an appropriate time.

[0050] Wait for three clocks (the time required for ISERDESE2 to shift internally after receiving a bitslip pulse), and then repeat the above judgment process again until the decoded output is all 1 (or all 0, low level); After the FCLK is decoded correctly, the system outputs a pulse signal to indicate that the data processing and storage modules can operate normally; During the normal operation of the data processing and storage modules, the system will continue to monitor the FCLK decoding results until the system detects a decoding error again (the decoding result is not all 1 or all 0). The system sends a data error pulse to the subsequent data processing and storage modules, suspends subsequent processing, and then the system will enter the error correction process again until the error correction is completed.

[0051] The data acquisition error correction method of the present invention is applicable to most high-speed multi-channel ADC data acquisition occasions that use LVDS for communication. It is not targeted at a specific FPGA platform. This embodiment is illustrated using the ISERDESE2 module decoding on the Xilinx ZYNQ platform as an example. The decoding modules may be different in different FPGA integration solutions, but the method of using FCLK as data input and decoding comparison is universal.

[0052] The data acquisition error correction method of the present invention is applicable to data misalignment error correction of ADCs with different bit numbers. Correspondingly, the present system method can be used after only adjusting the number of bits of all 1s or all 0s to be compared.

[0053] The error correction of this system method is short. Taking 50MHz system clock and decoding 10-bit ADC data as an example, in the worst case of 10-bit full error to the left or right, it only takes 10×(3+1)=40 system clocks to complete the error correction, and the time consumption is 40×(1000000000 / 50000000)=800ns, which can meet the real-time requirements of the entire acquisition system. Compared with the traditional method of first configuring the ADC to test mode, then comparing and correcting errors, and then configuring the ADC back to normal mode, the efficiency is greatly improved, and it can also be used for ADCs that do not support test mode.

[0054] This solution does not need to determine the specific data of the data source. The comparison data only comes from the result of ISERDESE2 decoding FCLK. The comparison result is used to control the bitslip shift operation of the decoding module, which reduces the complexity of system design and simplifies the development process.

[0055] Embodiment 2 This embodiment provides a data acquisition error correction device, including: A working module configuration module is used to configure the ultrasonic echo signal acquisition to enter a normal working mode; A signal decoding module, used for receiving the FCLK frame signal and decoding the FCLK frame signal; The signal error correction module is used to determine whether the decoding result of the FCLK frame signal meets the set conditions. If the set conditions are not met, there is a misalignment in the decoding of the parallel echo data acquisition channel. The data acquisition process is suspended, a shift pulse is generated, and a shift operation is performed on the parallel output echo data until the decoding result meets the set conditions. If it meets the conditions, the decoding is correct, and echo data acquisition is started to obtain an ultrasonic echo signal.

[0056] In this embodiment, the FCLK frame signal is connected to the ISERDESE2 module for decoding as data input, and other ultrasonic echo signal acquisition data channels are connected to the corresponding ISERDESE2 modules. There are multiple parallel ISERDESE2 modules, one module decodes the FCLK frame signal, and other modules decode the ultrasonic echo signal data channels.

[0057] In this embodiment, in the signal error correction module, when the decoding result of the FCLK frame signal is not all 1 or all 0, there is a misalignment in the decoding of the parallel echo data acquisition channels.

[0058] In this embodiment, in the signal error correction module, if there is a misalignment in the decoding of the parallel echo data acquisition channels, a bitslip pulse is generated to the ISERDESE2 module to perform an overall shift operation on the parallel output data and adjust the output data to move to the bit order of the correct data.

[0059] In this embodiment, a set time is waited after the shift operation is performed, and the set time is consistent with the time required for internal shifting after receiving the bitslip pulse.

[0060] The device is used in highly integrated ultrasonic data acquisition systems, such as portable ultrasonic equipment and ADC acquisition and error correction parts of ultrasonic flaw detection equipment, to solve the data misalignment problem that occurs during high-speed ultrasonic data acquisition.

[0061] Embodiment 3 This embodiment provides an ultrasonic flaw detection device, including an ADC acquisition module and the data acquisition and error correction device described in the second embodiment, wherein the ADC acquisition module and the data acquisition and error correction device are connected.

[0062] The specific implementation process of the data acquisition and error correction device is consistent with that of the second embodiment.

[0063] Embodiment 4 This embodiment provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the steps in the ultrasonic echo signal acquisition and error correction method as described above are implemented.

[0064] Embodiment 5 This embodiment provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, the steps in the ultrasonic echo signal acquisition and error correction method described above are implemented.

[0065] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. An ultrasonic echo signal acquisition error correction method, characterized in that: The steps include: Configure ultrasonic echo signal acquisition to enter normal working mode; Receive the FCLK frame signal and decode the FCLK frame signal; Determine whether the decoding result of the FCLK frame signal meets the set conditions. If not, there is a misalignment in the decoding of the parallel echo data acquisition channel. The data acquisition process is suspended, a shift pulse is generated, and a shift operation is performed on the parallel output echo data until the decoding result meets the set conditions. If it matches, the decoding is correct, echo data acquisition starts, and the ultrasonic echo signal is obtained.

2. The ultrasonic echo signal acquisition error correction method according to claim 1, characterized in that: When the decoding result of the FCLK frame signal is not all 1 or all 0, there is a misalignment in the decoding of the parallel echo data acquisition channels.

3. The ultrasonic echo signal acquisition and error correction method according to claim 1, characterized in that: The FCLK frame signal is used as data input to be connected to the ISERDESE2 module for decoding, and other ultrasonic echo signal acquisition data channels are connected to the corresponding ISERDESE2 modules. There are multiple parallel ISERDESE2 modules in the memory, one module decodes the FCLK frame signal, and other modules decode the ultrasonic echo signal data channels.

4. The ultrasonic echo signal acquisition and error correction method according to claim 1, characterized in that: If there is a misalignment in the decoding of the parallel echo data acquisition channels, a bitslip pulse is generated to the ISERDESE2 module to perform an overall shift operation on the parallel output data and adjust the output data to move to the bit order of the correct data.

5. The ultrasonic echo signal acquisition and error correction method according to claim 1, characterized in that: After executing the shift operation, wait for a set time, which is consistent with the time required for internal shifting after receiving the bitslip pulse.

6. An ultrasonic echo signal acquisition and error correction device, characterized in that: include: A working module configuration module is used to configure the ultrasonic echo signal acquisition to enter a normal working mode; A signal decoding module, used for receiving the FCLK frame signal and decoding the FCLK frame signal; The signal error correction module is used to determine whether the decoding result of the FCLK frame signal meets the set conditions. If the set conditions are not met, there is a misalignment in the decoding of the parallel echo data acquisition channel, and the data acquisition process is suspended, a shift pulse is generated, and a shift operation is performed on the parallel output echo data until the decoding result meets the set conditions; If it matches, the decoding is correct, echo data acquisition starts, and the ultrasonic echo signal is obtained.

7. The ultrasonic echo signal acquisition and error correction device according to claim 6, characterized in that: The FCLK frame signal is used as data input to be connected to the ISERDESE2 module for decoding, and other ultrasonic echo signal acquisition data channels are connected to the corresponding ISERDESE2 modules. There are multiple parallel ISERDESE2 modules in the memory, one module decodes the FCLK frame signal, and other modules decode the ultrasonic echo signal data channels.

8. The ultrasonic echo signal acquisition and error correction device according to claim 6, characterized in that: In the signal error correction module, when the decoding result of the FCLK frame signal is not all 1 or all 0, there is a misalignment in the decoding of the parallel echo data acquisition channel.

9. The ultrasonic echo signal acquisition and error correction device according to claim 6, characterized in that: After executing the shift operation, wait for a set time, which is consistent with the time required for internal shifting after receiving the bitslip pulse.

10. Ultrasonic flaw detection equipment, characterized in that: It comprises an ADC acquisition module and the ultrasonic echo signal acquisition and error correction device according to any one of claims 6 to 9, wherein the ADC acquisition module is connected to the data acquisition and error correction device.

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