Josephson junction resistance testing method and application thereof
By setting superconducting contacts with a harder harder than the superconducting metal layer on the surface of the Josephson junction, and using a probe to insert these contacts for resistance testing, the problem that the probe cannot pierce the oxide layer is solved, and accurate measurement and efficient testing of the Josephson junction resistance are achieved.
Patent Information
- Application Number
- CN202311398587.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-25
- Publication Date
- 2025-04-25
AI Technical Summary
In the prior art, the probe cannot easily pierce the niobium or tantalum oxide layer, resulting in the inability to effectively test the room temperature resistance of the Josephson junction, or multiple tests are required, which is inefficient.
Superconducting contacts with a hardness less than that of the superconducting metal layer are provided on the surface of the Josephson junction, and superconducting contacts with probes are inserted into these contacts to form a test loop and conduct resistance testing.
Through this method, the problem that the probe cannot puncture the oxide layer can be effectively avoided, accurate measurement of Josephson's junction resistance can be achieved, and testing efficiency can be improved.
Smart Images
Figure CN119881453A_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the technical field of quantum chip preparation, and in particular, relates to a Josephson junction resistance testing method and its application. Background Art
[0002] The key structure on the superconducting quantum chip is the superconducting quantum bit, and the key structure of the superconducting quantum bit is the Josephson junction. In order to ensure the performance of the superconducting quantum chip, the frequency parameters of the superconducting quantum bit must be strictly controlled. The room temperature resistance characterization of the superconducting quantum bit is important information for the reaction frequency parameters, and the resistance of the Josephson junction is the key to the room temperature resistance characterization of the superconducting quantum bit. The test of the Josephson junction mainly uses 4 probes or 2 probes inserted into the two ends of the Josephson junction, and the resistance of the Josephson junction is tested by DC test current and voltage.
[0003] At present, the improved quantum chip transmission lines often use niobium film or tantalum film. These materials have excellent superconducting properties, but the oxide layer formed after oxidation is very hard and the probe cannot easily pierce it, resulting in the inability to perform room temperature resistance testing on the Josephson junction, or multiple tests are required, resulting in reduced efficiency. Summary of the invention
[0004] The purpose of this application is to provide a Josephson junction resistance testing method and its application, so as to solve the problem in the prior art that the probe cannot penetrate the niobium and tantalum oxide layers, avoid the problem that the probe cannot penetrate due to the excessive hardness of the oxide layer, and realize accurate measurement of the Josephson junction resistance.
[0005] In order to solve the above technical problems, the present invention provides a Josephson junction resistance testing method, comprising:
[0006] Providing a substrate having a Josephson junction formed on the surface thereof, wherein the Josephson junction comprises two partially overlapping superconducting metal layers;
[0007] Disposing superconducting contacts with a hardness lower than that of the superconducting metal layer on the surfaces of the two superconducting metal layers respectively;
[0008] A probe is inserted into the two superconducting contacts to form a test loop and perform a resistance test.
[0009] Preferably, the material of the superconducting metal layer is niobium or tantalum;
[0010] The material of the superconducting contact is aluminum.
[0011] Preferably, the step of respectively providing superconducting contacts having a hardness less than that of the superconducting metal layer on the surfaces of the two superconducting metal layers comprises:
[0012] A photoresist layer covering the two superconducting metal layers is formed on the superconducting metal layer;
[0013] By photolithography, a first window and a second window are formed on the photoresist layer, wherein the first window and the second window expose the surfaces of the two superconducting metal layers respectively;
[0014] Two superconducting contacts are respectively arranged on the surfaces of the two superconducting metal layers through the first window and the second window.
[0015] Preferably, before respectively setting two superconducting contacts on the surfaces of the two superconducting metal layers through the first window and the second window, the method further comprises:
[0016] The oxide layer on the surface of the superconducting metal layer in the first window and the second window is removed by etching.
[0017] Preferably, the photoresist layer includes a first photoresist layer and a second photoresist layer;
[0018] The first photoresist layer is formed on the superconducting metal layer;
[0019] The second photoresist layer is formed on the first photoresist layer;
[0020] The first window and the second window penetrate the second photoresist layer and the first photoresist layer;
[0021] The first window and the second window are in an undercut structure.
[0022] Preferably, the method of using a probe to penetrate the two superconducting contacts to form a test loop and perform a resistance test further comprises:
[0023] The two superconducting contacts are removed by etching.
[0024] Preferably, after the etching removes the two superconducting contacts, the method further comprises:
[0025] The photoresist layer is removed.
[0026] The present invention also provides an application of the Josephson junction resistance testing method described in any one of the aforementioned embodiments in manufacturing a Josephson junction.
[0027] Preferably, the Josephson junction resistance testing method is used for quantum chip bit performance testing.
[0028] Compared with the prior art, the present application coats an aluminum film on the Josephson junction probe area, and the aluminum film is electrically connected to the superconducting metal layer, so that the probe can pierce the aluminum film oxide layer and test the Josephson junction resistance through the aluminum film. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Figure 1A schematic diagram of a Josephson junction resistance test structure provided by an embodiment of the present invention;
[0030] Figure 2 A schematic diagram of a Josephson junction resistance testing method provided by an embodiment of the present invention;
[0031] Figure 3 and Figure 4 A schematic diagram of the steps of a Josephson junction resistance testing method provided in an embodiment of the present invention.
[0032] Explanation of the reference numerals: 1 - substrate, 2 - superconducting metal layer, 21 - Josephson junction, 3 - superconducting contact, 4 - photoresist layer, 41 - first photoresist layer, 42 - second photoresist layer, 43 - first window, 44 - second window. DETAILED DESCRIPTION
[0033] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.
[0034] In the description of the present invention, it is necessary to understand that the terms "center", "up", "down", "left", "right", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.
[0035] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.
[0036] As disclosed in the background technology, in the field of quantum chip preparation technology, the key structure on the superconducting quantum chip is the Josephson junction; in order to ensure the performance of the superconducting quantum chip, the frequency parameters of the superconducting quantum bit must be strictly controlled, and the room temperature resistance characterization of the superconducting quantum bit is important information for the reaction frequency parameters, among which the key to the room temperature resistance of the superconducting quantum bit is the resistance of the Josephson junction; in the prior art, 4 probes or 2 probes are generally used to penetrate the two ends of the Josephson junction, and the resistance of the Josephson junction is tested by testing the current and voltage; for the quantum chip transmission line, niobium and tantalum are both superconducting materials with excellent performance, and niobium film or tantalum film is used as the design of the transmission line. When testing the room temperature resistance of the Josephson junction, due to the high hardness of the oxide layer of the niobium film and the tantalum film, the probe cannot easily penetrate the oxide layer, resulting in the inability to test the room temperature resistance of the Josephson junction, or multiple tests are required, thereby reducing the efficiency.
[0037] Please refer to Figure 1 In order to solve the above problems, the present invention provides a method for testing the resistance of a Josephson junction 21 and its application. When the resistance test of the Josephson junction 21 is required and the probe cannot be easily inserted into the superconducting metal layer 2, two superconducting contacts 3 with a hardness less than that of the superconducting metal layer 2 are plated on the surface of the superconducting metal layer 2 and electrically connected thereto. It is worth noting that the superconducting contacts 3 are located in the superconducting metal regions at both ends of the Josephson junction, and their size can be adjusted according to the size of the superconducting contacts 3 and the transmission line, but cannot exceed the etching channel, otherwise it will affect the performance of the superconducting quantum chip; in this case, it is only necessary to insert the probe into the two superconducting contacts 3 with smaller hardness, and apply the test current and voltage to form a loop, so as to perform a room temperature resistance test on the Josephson junction 21, and finally the superconducting contacts 3 can be retained or removed according to subsequent needs.
[0038] The embodiment of the present invention provides a method for testing the resistance of a Josephson junction 21, which can be used to measure the resistance of a Josephson junction 21 made of superconducting materials such as niobium or tantalum. The specific method is to set a superconducting contact 3 on a superconducting metal layer 2 to prevent the superconducting metal layer 2 from being oxidized in the air. The hardness of the oxide layer is too high, and the probe cannot be easily penetrated, resulting in the inability to measure the Josephson junction 21 or requiring multiple measurements to reduce efficiency. It is worth noting that the hardness of the superconducting contact 3 material is less than the hardness of the superconducting metal layer 2 material.
[0039] Please refer to Figure 2 The Josephson junction 21 resistance test method provided by the embodiment of the present invention comprises the following steps:
[0040] S1: providing a substrate 1 having a Josephson junction 21 formed on the surface thereof, wherein the Josephson junction 21 includes two partially overlapped superconducting metal layers 2.
[0041] Specifically, first, a substrate is provided, which may be a silicon substrate 1, a silicon dioxide substrate 1 or a sapphire substrate 1, and a superconducting metal layer 2 is deposited or electroplated on the substrate; a portion of the superconducting metal layer 2 is overlapped to form a Josephson junction 21 structure, and when the superconducting metal layer 2 is exposed to the air, an oxide layer is rapidly generated, that is, the surface portion of the superconducting metal layer 2 is oxidized, which can serve as a basic condition for overlapping to form a Josephson junction 21.
[0042] S2: Superconducting contacts 3 with a hardness lower than that of the superconducting metal layer 2 are respectively arranged on the surfaces of the two superconducting metal layers 2 .
[0043] In one embodiment of the present application, the material of the superconducting metal layer 2 is niobium or tantalum, and the material of the superconducting contact 3 is aluminum; wherein niobium and tantalum are both superconducting materials with excellent performance, and are currently widely used in the field of superconducting quantum chips, but when niobium or tantalum is used as a superconducting transmission line design, due to the high hardness of its oxide layer, it will cause the probe to be unable to easily pierce the oxide layer when testing the Josephson junction 21 at room temperature, or multiple tests are required, thereby reducing the efficiency. In one embodiment of the present invention, aluminum superconducting contacts 3 are set at both ends of the Josephson junction 21 (on the superconducting metal layer 2). Since the hardness of the oxide layer of the aluminum film is relatively low, when performing the resistance test of the Josephson junction 21, it is only necessary to insert the probe into the superconducting contact 3, and apply a DC test current and a test voltage to test the resistance of the Josephson junction 21; the advantage of doing so is that it can not only improve the efficiency of the resistance test of the Josephson junction 21, but also the superconducting contact 3 can be completely removed after the test is completed, without affecting its superconducting performance.
[0044] Please refer to Figure 3 The specific steps are: forming a photoresist layer 4 covering the two superconducting metal layers 2 on the superconducting metal layer 2;
[0045] By photolithography, a first window 43 and a second window 44 are formed on the photoresist layer 4, wherein the first window 43 and the second window 44 expose the surfaces of the two superconducting metal layers 2 respectively.
[0046] Two superconducting contacts 3 are respectively arranged on the surfaces of the two superconducting metal layers 2 through the first window 43 and the second window 44 .
[0047] It is worth noting that, since the tests are all conducted in the atmosphere, metal will oxidize when in contact with air, and will still be oxidized if it continues to be exposed to the air even after being removed. Before two superconducting contacts 3 are respectively set on the surfaces of the two superconducting metal layers 2 through the first window 43 and the second window 44, the oxide layer on the surface of the superconducting metal layer 2 in the first window 43 and the second window 44 should be removed by etching to ensure that the superconducting contact 3 can be electrically connected to the superconducting metal layer 2. When testing the resistance of the Josephson junction 21, the probe is inserted into the superconducting contact 3, and a DC test current and voltage can form a complete and limited circuit to ensure the accuracy of the test.
[0048] In one embodiment of the present application, the photoresist layer 4 includes a first photoresist layer 41 and a second photoresist layer 42; the first photoresist layer 41 is formed on the superconducting metal layer 2; the second photoresist is formed on the first photoresist layer 41; and the first window 43 and the second window 44 penetrate the second photoresist layer 42 and the first photoresist layer 41.
[0049] Among them, the development rates of the first photoresist and the second photoresist are inconsistent, specifically, the development rate of the first photoresist layer 41 is faster than the development rate of the second photoresist layer 42; in specific implementation, the first photoresist layer 41 can use S1813 photoresist as the first photoresist layer 41 and use Lor5B photoresist as the second photoresist layer 42.
[0050] Alternatively, the photoresist layer 4 may also be a layer of negative photoresist, which presents an undercut structure after development and exposure.
[0051] After the photoresist layer 4 is exposed and developed, the first window 43 and the second window 44 have an undercut structure, that is, a structure that is narrow at the top and wide at the bottom is formed. When the superconducting contact 3 is subsequently set, the aluminum material is prevented from being plated on the inner side of the first window 43 and the second window 44, so that the photoresist layer is separated or partially separated from the internal space of the first window 43 and the second window 44. As a result, when the photoresist layer 4 is subsequently removed, it is not easy for the solution to completely contact the photoresist layer 4, making the photoresist layer 4 difficult to dissolve, affecting the subsequent process flow.
[0052] S3: Use a probe to penetrate the two superconducting contacts 3 to form a test loop and perform a resistance test.
[0053] Please refer to Figure 4 Specifically, 4 probes or 2 probes are inserted at both ends of the Josephson junction 21, that is, the oxide layer of the superconducting contact 3 located on the surface of the superconducting metal layer 2 is pierced, and the superconducting contact 3 is electrically connected. A test loop is formed between the probe, the superconducting layer, and the Josephson junction 21, and a DC current and voltage are tested to perform a resistance test on the Josephson junction 21, and finally the parameter results are obtained.
[0054] After the room temperature resistance test of the Josephson junction 21 is completed, the two superconducting contacts 3 can be removed by etching, and the photoresist layer 4 can be removed by immersion.
[0055] In another embodiment of the present application, four probes or two probes are used to penetrate two superconducting contacts 3 respectively, and a test loop is formed between the probes, the superconducting metal layer 2 and the Josephson junction 21. Before the resistance test, the steps of respectively setting superconducting contacts 3 having a hardness less than that of the superconducting metal layer 2 on the surfaces of the two superconducting metal layers 2 also include: removing the photoresist layer 4; that is, after the superconducting contacts 3 are set and before the normal temperature resistance test of the Josephson junction 21, the photoresist layer 4 and the aluminum film on the photoresist layer 4 are firstly removed by immersion, and then the four probes or two probes are used to penetrate the superconducting contacts 3 and the resistance test of the Josephson junction 21 is performed, and after the test is completed, the superconducting contacts 3 are retained. In an environment where the influence of the superconducting contacts 3 can be ignored, retaining the superconducting contacts 3 can achieve the purpose of measuring the resistance of the Josephson junction 21 at any time and multiple tests.
[0056] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example" or "specific example" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.
[0057] The above describes in detail the structure, features and effects of the present application based on the embodiments shown in the drawings. The above is only a preferred embodiment of the present application, but the present application does not limit the scope of implementation to what is shown in the drawings. Any changes made in accordance with the concept of the present application, or modifications to equivalent embodiments with equivalent changes, which still do not exceed the spirit covered by the description and drawings, should be within the protection scope of the present application.
Claims
1. A Josephson junction resistance testing method, characterized in that: include: Providing a substrate (1) having a Josephson junction (21) formed on the surface thereof, wherein the Josephson junction (21) comprises two partially overlapping superconducting metal layers (2); Superconducting contacts (3) having a hardness less than that of the superconducting metal layers (2) are respectively arranged on the surfaces of the two superconducting metal layers (2); A probe is inserted into the two superconducting contacts (3) to form a test loop and perform a resistance test.
2. The Josephson junction resistance testing method according to claim 1, characterized in that: The material of the superconducting metal layer (2) is niobium or tantalum; The material of the superconducting contact (3) is aluminum.
3. The Josephson junction resistance testing method according to claim 1 or 2, characterized in that: The step of respectively arranging superconducting contacts (3) having a hardness less than that of the superconducting metal layers (2) on the surfaces of the two superconducting metal layers (2) comprises: A photoresist layer (4) covering the two superconducting metal layers (2) is formed on the superconducting metal layer (2); A first window (43) and a second window (44) are formed separately on the photoresist layer (4) by photolithography, wherein the first window (43) and the second window (44) respectively expose the surfaces of the two superconducting metal layers (2); Two superconducting contacts (3) are respectively arranged on the surfaces of the two superconducting metal layers (2) through the first window (43) and the second window (44).
4. The Josephson junction resistance testing method according to claim 3, characterized in that: Before the two superconducting contacts (3) are respectively arranged on the surfaces of the two superconducting metal layers (2) through the first window (43) and the second window (44), the method further comprises: The oxide layer on the surface of the superconducting metal layer (2) in the first window (43) and the second window (44) is removed by etching.
5. The Josephson junction resistance testing method according to claim 4, characterized in that: The photoresist layer (4) comprises a first photoresist layer (41) and a second photoresist layer (42); The first photoresist layer (41) is formed on the superconducting metal layer (2); The second photoresist layer (42) is formed on the first photoresist layer (41); The first window (43) and the second window (44) penetrate the second photoresist layer (42) and the first photoresist layer (41); The first window (43) and the second window (44) are in an undercut structure.
6. The Josephson junction resistance testing method according to claim 3, characterized in that: After the test loop is formed by piercing the two superconducting contacts (3) with a probe and performing a resistance test, the method further comprises: The two superconducting contacts (3) are removed by etching.
7. The Josephson junction resistance testing method according to claim 6, characterized in that: After the etching removes the two superconducting contacts, the method further comprises: The photoresist layer (4) is removed.
8. The Josephson node testing method according to claim 3, characterized in that: Before the test loop is formed by piercing the two superconducting contacts (3) with a probe and performing a resistance test, the step of respectively arranging superconducting contacts (3) having a hardness less than that of the superconducting metal layer (2) on the surfaces of the two superconducting metal layers (2) further comprises: The photoresist layer (4) is removed.
9. Application of the Josephson junction resistance testing method according to any one of claims 1 to 8 in manufacturing a Josephson junction (21).
10. The use according to claim 9, characterized in that: The Josephson junction resistance test method is used to test the bit performance of quantum chips.