Contact hole photoetching process condition design method and semiconductor structure

Abstract

The invention provides a contact hole photoetching process condition design method and a semiconductor structure, and the method comprises the steps: obtaining the parameters of a front-layer film of a substrate to be coated with an anti-reflection layer, and carrying out the simulation selection of the target film thickness and target exposure anchor points of the anti-reflection layer to be coated and a light resistor; the illumination condition parameters are changed for photoetching process verification, a target exposure anchor point with the minimum contact hole edge roughness obtained through photoetching is selected as a selected exposure anchor point, and the corresponding illumination condition parameters are contact hole photoetching process conditions. According to the method, the illumination condition parameters of photoetching are iteratively optimized, and the edge roughness of the photoetching contact hole is obviously improved; meanwhile, a target exposure anchor point is screened through a process window design condition before iterative optimization, so that the improved contact hole meets the process window design condition and is suitable for a photoetching process with a high-precision requirement; in addition, by obtaining the optimal photoetching process conditions of the contact holes corresponding to different processes in advance, the photoetching condition change caused by the process change can be quickly changed.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor integrated circuit manufacturing, and in particular relates to a contact hole photolithography process condition design method and a semiconductor structure. Background Art

[0002] In the back-end process of advanced process nodes, when the line edge roughness, line width roughness and VIA (contact hole) edge roughness of the photoresist are too large, it will cause metal connection short circuit defects. If the line edge roughness transferred to the final pattern through etching is too large, it will cause defects that cannot be filled with subsequent copper materials, thereby reducing the resistance, capacitance and other parameter performance of the back-end connection.

[0003] As the process nodes shrink, the requirements for the edge roughness of vias (VIA) become higher and higher, and it becomes important to improve the process. The current methods for optimizing the edge roughness of VIA include: increasing the concentration of photoresist PAG (Photo-Acid Generator), moderately increasing the post-exposure baking temperature or time, and spraying chemical liquid on the surface of the photolithography pattern before development (chemical trim). However, increasing the PAG concentration will make the exposure dose more sensitive, resulting in a decrease in EL (energy latitude), thereby reducing the process window; and increasing the post-exposure baking temperature or time is only applicable to photoresists with high deprotection energy during post-exposure baking, and cannot be applied to photoresists that require shorter baking times or lower temperatures, so its applicable scenarios are limited; the cost of using chemical liquid spray treatment is high, and the applicable scenarios are also limited.

[0004] Therefore, there is an urgent need for a structure or method that can reduce the edge roughness of contact holes in the back-end process of advanced processes and meet process window conditions and has a wide range of applications.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology part of the present application. Summary of the invention

[0006] In view of the above shortcomings of the prior art, the purpose of the present invention is to provide a contact hole lithography process condition design method and a semiconductor structure, which are used to solve the problem that it is difficult to improve the contact hole edge roughness while satisfying the process window conditions and having a wide range of applicability in the back-end process of the advanced process in the prior art.

[0007] To achieve the above object, the present invention provides a method for designing contact hole photolithography process conditions, the design method comprising:

[0008] Providing a substrate to be coated with an anti-reflection layer, the substrate comprising a substrate and n thin films deposited on the substrate, where n is an integer greater than or equal to 1; measuring and obtaining parameters of a front thin film of the substrate to be coated with the anti-reflection layer, the front thin film parameters comprising a film thickness and a corresponding extinction coefficient of each thin film in m thin films starting from the topmost thin film of the substrate, where m is an integer greater than or equal to 1 and less than or equal to n;

[0009] Performing photolithography simulation based on the obtained parameters of the front-layer thin film to obtain a curve of the relationship between the simulated film thickness and the extinction coefficient of the anti-reflection layer to be coated, and then selecting a target film thickness of the anti-reflection layer to be coated;

[0010] Performing photolithography simulation according to the parameters of the front film layer and the target film thickness and extinction coefficient of the anti-reflection layer to be coated, obtaining a relationship curve between the simulated film thickness and reflectivity of the photoresist set on the anti-reflection layer to be coated, and then selecting the target film thickness of the photoresist;

[0011] According to the parameters of the front film, the target film thickness and extinction coefficient of the anti-reflection layer to be coated, and the target film thickness of the photoresist, a candidate exposure anchor point is selected, and the photolithography parameters to be optimized and the illumination mode parameters are fixed to perform photolithography simulation to obtain at least one target exposure anchor point;

[0012] By changing the illumination condition parameters on the substrate, the lithography process conditions obtained in the above steps are verified, the target exposure anchor point with the smallest contact hole edge roughness obtained by lithography is selected as the selected exposure anchor point, and the illumination condition parameters corresponding to the selected exposure anchor point are obtained, so as to determine the contact hole lithography process conditions; the illumination condition parameters include: numerical aperture, outer ring pupil relative radius and inner ring pupil relative radius; the lithography process conditions obtained in the above steps include: target film thickness of the anti-reflection layer to be coated, target film thickness of the photoresist, the illumination mode parameters and the at least one target exposure anchor point.

[0013] Optionally, n is greater than or equal to 4, and m is greater than or equal to 4.

[0014] Optionally, the step of selecting a target film thickness of the anti-reflection layer to be applied further comprises:

[0015] Obtaining the second minimum point of the relationship curve between the simulated film thickness and the extinction coefficient of the anti-reflection layer to be coated;

[0016] The simulated film thickness of the anti-reflection layer to be coated corresponding to the second minimum point is selected as the target film thickness of the anti-reflection coating.

[0017] Optionally, the step of obtaining a target film thickness of the photoresist at least includes:

[0018] Input the parameters of the front layer film and the target film thickness and the corresponding extinction coefficient of the anti-reflection coating into the photolithography simulation software for simulation, obtain the relationship curve between the simulated film thickness and the reflectivity of the photoresist set on the anti-reflection layer to be coated, and select at least one minimum point in the curve whose absolute value of the slope is close to 0;

[0019] The simulated film thickness of the photoresist corresponding to at least one minimum point where the absolute value of the slope is close to 0 is selected as the target film thickness of the photoresist.

[0020] Optionally, the lighting method parameters include an exposure light source lighting mode and an exposure light source polarization state.

[0021] Optionally, the step of acquiring at least one target exposure anchor point further includes:

[0022] Selecting a series of characteristic patterns as the candidate exposure anchor points;

[0023] Fix the lithography parameters and illumination mode parameters to be optimized to perform lithography simulation, and obtain one or more parameters of the key line width, line width uniformity parameter, mask error enhancement factor, energy margin or focus depth corresponding to the candidate exposure anchor point as preset screening parameters;

[0024] At least one candidate exposure anchor point whose preset screening parameters satisfy the photolithography process window design conditions among the candidate exposure anchor points is obtained as the target exposure anchor point.

[0025] Optionally, the series of characteristic patterns include: a preset period dense pattern, a preset period semi-dense pattern, a preset period semi-dense pattern with exposure auxiliary patterns added based on preset rules, and / or an isolated pattern in a sparse area.

[0026] Optionally, the step of changing the lighting condition parameters on the substrate further comprises:

[0027] Selecting a set of lighting condition parameters as an initial parameter set, and changing one or more lighting condition parameters to perform iteration based on the initial parameter set;

[0028] When the change of the contact hole edge roughness obtained by photolithography is less than the preset change value, the illumination condition parameters obtained at this time are used as a new initial parameter group;

[0029] After repeated iterations for a preset number of times, the obtained illumination condition parameters with the minimum roughness of the contact hole edge are used as the contact hole photolithography process conditions.

[0030] Optionally, the design method further comprises:

[0031] Determining whether the edge roughness of the contact hole obtained by photolithography under the illumination condition parameters corresponding to the selected exposure anchor point is higher than a reference threshold;

[0032] If the edge roughness is higher than the reference threshold, the lighting condition parameters are adjusted to re-perform the photolithography process verification to obtain a new selected exposure anchor point; if the edge roughness is not higher than the reference threshold, the iteration is terminated and the lighting condition parameters corresponding to the contact hole edge roughness are output.

[0033] The present invention also provides a semiconductor structure, which adopts any one of the contact hole lithography process condition design methods described above to obtain lithography process conditions for setting contact holes on the semiconductor structure, and the semiconductor structure includes a substrate and n layers of thin films deposited on the substrate, where n is an integer greater than or equal to 1.

[0034] As described above, the contact hole lithography process condition design method and semiconductor structure of the present invention have the following beneficial effects:

[0035] The present invention improves the edge roughness of the contact hole obtained by photolithography by iteratively optimizing the illumination condition parameters of photolithography, and the improvement effect is obvious;

[0036] The present invention selects the target exposure anchor point through the process window design conditions before iterative optimization, so that the contact hole with improved edge roughness meets the process window design conditions and is suitable for the lithography process of 28nm and below technology nodes;

[0037] The present invention uses a contact hole lithography process condition design method to quickly adapt lithography process conditions according to changes in lithography conditions caused by lithography processes corresponding to a Tri-layer structure and a Bi-layer structure, thereby ensuring that the edge roughness of the contact hole and the lithography process window conditions can still be guaranteed when the process is changed. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It shows a flowchart of the steps in step 1 of the method for designing contact hole photolithography process conditions in embodiment 1 of the present invention.

[0039] Figure 2 It is a schematic diagram showing the structure of the substrate in step 1 of the method for designing contact hole photolithography process conditions in embodiment 1 of the present invention.

[0040] Figure 3 It is a schematic diagram showing a preset periodic dense pattern in an example of step 4 of the method for designing contact hole photolithography process conditions in embodiment 1 of the present invention.

[0041] Figure 4 It is a schematic diagram showing a preset periodic semi-dense pattern in an example of step 4 of the method for designing contact hole photolithography process conditions in embodiment 1 of the present invention.

[0042] Figure 5It is a schematic diagram showing a preset periodic semi-dense pattern of adding an exposure auxiliary pattern based on a preset rule in an example of step 4 of the method for designing contact hole photolithography process conditions in embodiment 1 of the present invention.

[0043] Figure 6 It is a schematic diagram showing isolated patterns in a sparse area in an example of step 4 of the method for designing contact hole photolithography process conditions in embodiment 1 of the present invention.

[0044] Figure 7 It shows a schematic diagram of the structure of the substrate in the method for designing contact hole photolithography process conditions in Example 2 of the present invention.

[0045] Figure 8 Shown is a corresponding parameter record table of each selected exposure anchor point during the iteration process in an example of a contact hole photolithography process condition design method according to embodiment 2 of the present invention.

[0046] Fig. 9 It shows a schematic diagram of the structure presented by Tri-layer in the method for designing contact hole photolithography process conditions in Example 3 of the present invention.

[0047] Fig.10 It shows a schematic diagram of the structure presented by the Bi-layer in the method for designing contact hole photolithography process conditions in Example 3 of the present invention.

[0048] Description of Figure Numbers

[0049] 10. Base; 11. Substrate; 12. Thin film; 13. NDC; 14. TEOS2; 15. BD2; 16. BD1; 17. TEOS1;

[0050] 18. TiN; 19. SOC;

[0051] 21. Photoresist; 22. Anti-reflective layer. DETAILED DESCRIPTION

[0052] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0053] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the schematic diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0054] For convenience of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings.

[0055] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0056] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0057] In the back-end process of semiconductor manufacturing, especially in advanced process nodes, if the line edge roughness, line width roughness and VIA (contact hole) edge roughness of the photoresist are too large, a series of serious defects will be caused. When the edge roughness is too large, it may cause a short circuit problem between metal wires, thereby affecting the normal operation of the entire circuit. In addition, if the problem of excessive line edge roughness is transferred to the final pattern during the etching process, then in the subsequent copper material filling process, the situation of filling failure may occur, which will directly affect the key parameter performance of the resistance and capacitance of the back-end connection, thereby reducing the performance of the entire circuit. With the continuous reduction of process nodes, the requirements for the edge roughness of the vias VIA become higher and higher, therefore, the process of improving its edge roughness becomes particularly important.

[0058] At present, some methods for optimizing VIA edge roughness have been proposed in the industry. For example, the roughness can be improved by increasing the concentration of PAG (Photo-Acid Generator) in the photoresist. However, one disadvantage of this method is that increasing the PAG concentration makes the exposure dose more sensitive, resulting in a decrease in EL (energy latitude), which reduces the process window and makes the process fault tolerance worse. Another method is to moderately increase the baking temperature or time after exposure. This method is suitable for photoresists with high deprotection energy during the post-exposure baking process. However, this method is not suitable for photoresists that require shorter baking times and lower temperatures, so its scope of application is relatively limited. Another method is to spray the surface of the photolithography pattern with a chemical liquid before development, which is called chemical trim. Although this method can effectively improve the roughness in some cases, it is expensive and has limited applicable scenarios.

[0059] The present invention provides the following solution for improving the edge roughness of the contact hole to meet the process requirements of a smaller size.

[0060] Embodiment 1:

[0061] like Figure 1 As shown, this embodiment provides a method for designing process conditions for contact holes photolithography. The method for designing process conditions for contact holes photolithography of the present invention will be described in detail below. It should be noted that the above sequence does not strictly represent the sequence of the method for designing process conditions for contact holes photolithography protected by the present invention, and those skilled in the art may change it according to the actual design steps.

[0062] First, proceed to step 1, such as Figure 2 As shown, a substrate 10 to be coated with an anti-reflection layer is provided, the substrate 10 includes a substrate 11 and n thin films 12 deposited on the substrate 11, n is an integer greater than or equal to 1; the front film stack parameters of the substrate 10 to be coated with the anti-reflection layer are measured and obtained, the front film parameters include the film thickness and corresponding extinction coefficient of each thin film 12 in the m thin film layers 12 starting from the topmost thin film 12 of the substrate 10, m is an integer greater than or equal to 1 and less than or equal to n.

[0063] The present invention can perform lithography simulation on the existing substrate 10 by obtaining the front-layer thin film parameters of the substrate 10 including the film thickness and the extinction coefficient, so that the parameters can be iteratively optimized and adjusted in the lithography simulation for the substrate 10, so that the optimized contact hole lithography process conditions can be obtained without conducting actual experiments, which greatly reduces the cost of optimizing the lithography parameters. At the same time, various possibilities can be widely explored, which is conducive to improving the accuracy of the optimization results; at the same time, when different substrates 10 are involved, the lithography simulation model of the substrate 10 can be directly replaced, and then the specified iterative program can be executed, so as to quickly respond to the contact hole lithography process conditions required for different substrates 10, to ensure that the corresponding contact hole edge improvements can be achieved for different substrate 10 structures.

[0064] In one embodiment, n is greater than or equal to 4, and m is greater than or equal to 4.

[0065] Preferably, m is equal to 4.

[0066] The present invention can obtain the best optimized iterative result for the contact hole lithography process conditions by setting the front film parameters including the film thickness and extinction coefficient corresponding to the four layers of films 12 starting from the top film 12, and further improve the improvement effect on the contact hole edge.

[0067] In one embodiment, the substrate 11 is a silicon substrate 11 .

[0068] In one embodiment, the anti-reflection layer to be coated is a spin-on carbon layer (Spin-On Carbon, SOC).

[0069] Then, step 2 is performed to perform photolithography simulation using the obtained parameters of the front-layer film to obtain a curve of relationship between the simulated film thickness and the extinction coefficient of the anti-reflection layer to be coated, and then a target film thickness of the anti-reflection layer to be coated is selected.

[0070] Specifically, by selecting a simulated film thickness of the anti-reflection layer that can achieve a minimum extinction coefficient, the anti-reflection layer can increase the transmittance of the exposure light when the structure is photolithographically processed, thereby avoiding intensity attenuation of the exposure light when passing through the anti-reflection layer. At the same time, the scattering loss of the exposure light on the surface of the anti-reflection layer is reduced, thereby reducing the anchor effect, improving the accuracy of the photolithography pattern, and also facilitating the improvement of the edge of the contact hole.

[0071] In one embodiment, the step of selecting a target film thickness of the anti-reflection layer to be applied further comprises:

[0072] Obtaining the second minimum point of the relationship curve between the simulated film thickness and the extinction coefficient of the anti-reflection layer to be coated;

[0073] The simulated film thickness of the anti-reflection layer to be coated corresponding to the second minimum point is selected as the target film thickness of the anti-reflection coating.

[0074] The present invention obtains the second minimum point of the relationship curve between the simulated film thickness and the extinction coefficient of the anti-reflection layer, thereby avoiding the problem that the extinction coefficient obtained is not representative due to poor surface flatness when the film thickness is too small, thereby further making the target film thickness obtained by lithography simulation closer to the actual situation.

[0075] Next, proceed to step 3, perform photolithography simulation based on the parameters of the previous thin film and the target film thickness and extinction coefficient of the anti-reflection layer to be coated, obtain the simulated film thickness and reflectivity relationship curve (swing curve) of the photoresist 21 set on the anti-reflection layer to be coated, and then select the target film thickness of the photoresist 21.

[0076] In one embodiment, the step of obtaining the target film thickness of the photoresist 21 at least includes:

[0077] Input the parameters of the front layer film and the target film thickness and the corresponding extinction coefficient of the anti-reflection coating into the photolithography simulation software for simulation, obtain the relationship curve between the simulated film thickness and the reflectivity of the photoresist 21 set on the anti-reflection layer to be coated, and select at least one minimum point in the curve whose absolute value of the slope is close to 0;

[0078] The simulated film thickness of the photoresist 21 corresponding to at least one minimum point where the absolute value of the slope is close to 0 is selected as the target film thickness of the photoresist 21 .

[0079] Specifically, there are multiple minimum points where the absolute value of the slope of the curve of the relationship between the simulated film thickness and the reflectivity of the photoresist 21 is close to 0, and at least one of the valley points can be selected according to actual needs.

[0080] Specifically, the absolute value of the slope of the curve is close to 0. The specific definition of “close to 0” can be set according to actual measurement tools and accuracy requirements, and is not excessively limited in this article.

[0081] The present invention selects a minimum point where the absolute value of the slope of the reflectivity relationship curve is close to 0 in the lithography simulation, thereby ensuring that the photoresist 21 of the film thickness can ensure stable reflectivity during the lithography process, while achieving relative minimization of the reflectivity of the photoresist 21, thereby working together to improve the accuracy and uniformity of the lithography, and also facilitating the improvement of the edge of the contact hole.

[0082] Then, proceed to step 4, select candidate exposure anchor points (anchor points) according to the parameters of the front film, the target film thickness and extinction coefficient of the anti-reflection layer to be coated, and the target film thickness of the photoresist 21, fix the lithography parameters to be optimized and the illumination mode parameters to perform lithography simulation, and obtain at least one target exposure anchor point.

[0083] The present invention selects candidate exposure anchor points that meet the requirements as target exposure anchor points according to preset standards, thereby ensuring that all target exposure anchor points used for optimizing and iterating contact hole lithography process conditions meet the preset standards.

[0084] In one embodiment, the illumination method parameters include an exposure light source illumination mode and an exposure light source polarization state.

[0085] In one embodiment, the exposure light source illumination mode used is annular illumination, and the exposure light source polarization state is TE polarization.

[0086] Specifically, the lighting mode parameters may also be selected in appropriate combinations according to requirements as lighting mode parameters of the target exposure anchor point.

[0087] In one embodiment, the step of acquiring at least one target exposure anchor point further comprises:

[0088] Selecting a series of characteristic patterns as the candidate exposure anchor points;

[0089] Fix the lithography parameters and illumination mode parameters to be optimized to perform lithography simulation, and obtain one or more parameters of the key line width, line width uniformity parameter, mask error enhancement factor, energy margin (EL, Exposure Latitude) or depth of focus (DOF, Depth of Field) corresponding to the candidate exposure anchor point as preset screening parameters;

[0090] At least one candidate exposure anchor point whose preset screening parameters satisfy the photolithography process window design conditions among the candidate exposure anchor points is obtained as the target exposure anchor point.

[0091] In one embodiment, by measuring the simulated two-dimensional graphic of the contact hole, the key line width, line width uniformity parameter, and mask error enhancement factor are obtained.

[0092] The present invention uses one or more parameters including the key line width, line width uniformity parameter, mask error enhancement factor, energy margin (EL) or depth of focus (DOF) corresponding to the candidate exposure anchor points as preset screening parameters, so as to select candidate exposure anchor points that meet the process window conditions as target exposure anchor points, thereby ensuring that the target exposure anchor points all meet the process window conditions.

[0093] Preferably, the critical line width, line width uniformity parameter, mask error enhancement factor, energy margin (EL) or depth of focus (DOF) are all used as preset screening parameters to ensure that the process window conditions are met; but it is also possible to selectively focus on several of these parameters as preset screening parameters to improve iteration efficiency. Those skilled in the art can make appropriate adjustments as needed, which are all within the scope of protection of the present invention.

[0094] In one embodiment, the series of characteristic patterns include: Figure 3 The preset cycle intensive graphics shown, such as Figure 4 The preset period semi-dense pattern shown, such as Figure 5 The preset periodic semi-dense pattern and / or the preset periodic semi-dense pattern of adding the exposure auxiliary pattern (Sub-Resolution Assist Feature, SRAF) based on the preset rule as shown Figure 6 Isolated graphics within the sparse area shown.

[0095] The present invention selects a series of characteristic patterns with different densities to ensure that the contact hole photolithography process conditions finally obtained can be simultaneously applicable to the preparation of contact holes with various pattern densities, thereby improving the improvement effect on the edges of each contact hole in the overall product.

[0096] Finally, step 5 is performed to verify the photolithography process conditions obtained in the above steps by changing the illumination condition parameters on the substrate 10, select the target exposure anchor point with the smallest contact hole edge roughness obtained by lithography as the selected exposure anchor point, and obtain the illumination condition parameters corresponding to the selected exposure anchor point, so as to determine the contact hole lithography process conditions; the illumination condition parameters include: numerical aperture (NA), outer ring pupil relative radius (σ out ) and the relative radius of the inner pupil (σ in ); The photolithography process conditions obtained in the above steps include: the target film thickness of the anti-reflection layer to be coated, the target film thickness of the photoresist 21, the illumination method parameters and the at least one target exposure anchor point.

[0097] The present invention determines the film thickness of the anti-reflection layer and the photoresist 21 with the best lithography effect, the illumination mode parameters and the target exposure anchor point that meets the process window conditions in sequence through lithography simulation, and then optimizes and iterates the illumination condition parameters to obtain the selected exposure anchor point with the smallest contact hole edge. At the same time, the design method can be used to determine the corresponding optimal lithography process conditions for the contact holes in advance by comparing the contact hole preparation corresponding to different processes such as Tri-layer or Bi-layer, and the lithography conditions can be quickly adapted when the process changes, so that the contact holes prepared under different processes can achieve smaller edge roughness.

[0098] Specifically, the design method of contact hole lithography process conditions of the present invention can be applied to various technology nodes. Among them, since the technology nodes of 28nm and below have higher requirements on the graphic accuracy of the contact holes and need to minimize the edges of the contact holes, the technology nodes of 28nm and below need to use the solution of the present invention to improve the edge roughness of the contact holes.

[0099] In one embodiment, the design scheme of the present invention is used in an immersion lithography process. Specifically, it can also be applied to other suitable lithography processes (such as non-immersion lithography processes) according to requirements, all of which are within the protection scope of the present invention.

[0100] In one embodiment, the step of changing the lighting condition parameters on the substrate 11 further comprises:

[0101] Selecting a set of lighting condition parameters as an initial parameter set, and changing one of the lighting condition parameters to perform iteration based on the initial parameter set;

[0102] When the change of the contact hole edge roughness obtained by photolithography is less than the preset change value, the illumination condition parameters obtained at this time are used as a new initial parameter group, and the illumination condition parameters that have not been iterated are selected for iteration;

[0103] After repeated iterations for a preset number of times, the obtained illumination condition parameters with the minimum roughness of the contact hole edge are used as the contact hole photolithography process conditions.

[0104] Specifically, the preset change value can be set to a suitable value based on experience, which proves that the contact hole edge roughness obtained by the illumination condition parameters based on the initial parameter group is close to the minimum value and almost unchanged, and the iteration under the illumination condition parameters can be stopped.

[0105] In one embodiment, the preset number of times is 3-5. Specifically, those skilled in the art can also design other iteration times according to requirements. In a specific operation, generally 3-5 iterations are performed to obtain the minimum contact hole edge roughness under the lighting condition parameters.

[0106] In one embodiment, Figure 1 As shown, the design method further comprises:

[0107] Step 6: Determine whether the edge roughness of the contact hole obtained by photolithography under the illumination condition parameters corresponding to the selected exposure anchor point is higher than a reference threshold;

[0108] If the edge roughness is higher than the reference threshold, the lighting condition parameters are adjusted to re-perform the lithography process verification in step 5 to obtain a new selected exposure anchor point; if the edge roughness is not higher than the reference threshold, the iteration is terminated and the lighting condition parameters corresponding to the obtained contact hole edge roughness are output.

[0109] Specifically, those skilled in the art may select other appropriate reference thresholds according to needs to meet the requirements of the specific technology node used for the contact hole edge roughness, which are all within the protection scope of the present invention.

[0110] In one embodiment, the above steps can all be input into the lithography program and simulation software to realize automated iterative calculation and improve iterative optimization efficiency.

[0111] Embodiment 2:

[0112] This embodiment provides a method for designing contact hole photolithography process conditions. The design method is basically the same as other features in Embodiment 1, except that:

[0113] In this embodiment, the design method is applied in the photolithography process of the following substrate 10 structure:

[0114] like Figure 7 As shown, the substrate 10 is composed of NDC (Nitride Doped Carbon) 13, TEOS2 (Tetraethyl orthosilicate) 14, BD2 (Blocking Layer) 15, BD1 (16), TEOS1 (17), TiN 18, and SOC 19 (Spin-On Carbon) from bottom to top.

[0115] In this embodiment, the thickness of NDC13 is 250 angstroms, the thickness of TEOS2(14) is 150 angstroms, the thickness of BD2(15) is 150 angstroms, the thickness of BD1(16) is 150 angstroms, the thickness of TEOS1(17) is 200 angstroms, and the thickness of TiN18 is 210 angstroms.

[0116] In this embodiment, Figure 8 The table shows a partial data of various illumination condition parameters and corresponding energy margin (EL), depth of focus (DOF), and hole edge roughness (CER) during a parameter iteration of the substrate 10. When changing the illumination condition parameters on the substrate 11: a group of illumination condition parameters is selected as an initial parameter group, and two or more illumination condition parameters are changed at the same time based on the initial parameter group for iteration;

[0117] When the change of the contact hole edge roughness obtained by photolithography is less than the preset change value (the edge roughness can be almost unchanged according to experience or actual program measurement), the illumination condition parameters obtained at this time are used as the new initial parameter group;

[0118] After repeated iterations for a preset number of times, the obtained illumination condition parameters with the minimum roughness of the contact hole edge are used as the contact hole photolithography process conditions.

[0119] The present invention performs large-step iteration by simultaneously changing more than two lighting condition parameters. Although some lighting condition parameters with smaller contact hole edge roughness may be missed, a rough lighting condition parameter range can be confirmed using the above-mentioned iteration method first. Then, when a single lighting condition parameter is changed for further small-step iteration, it can be ensured that the lighting condition parameters are all within a relatively optimal range, thereby improving the efficiency of iterative optimization and reducing the number of optimization times.

[0120] In this embodiment, the line width / line spacing of the target exposure anchor point obtained in step 4 is 108 μm / 72 μm, and the numerical aperture (NA) corresponding to the selected exposure anchor point obtained by using annular illumination is 1.35, and the relative radius of the outer ring pupil (σ out ) is 0.7, the relative radius of the inner pupil (σ in ) is 0.5, and the contact hole edge roughness (Circle Edge Roughness, CER) obtained by the method of simultaneous iteration of multiple illumination condition parameters can be reduced from the initial 4.46 to 2.44. It can be seen that after 5 iterations, the contact hole edge roughness is halved, and the improvement effect is obvious.

[0121] Embodiment 3:

[0122] This embodiment provides a method for designing contact hole photolithography process conditions. The design method is basically the same as other features in Embodiment 1, except that:

[0123] In this embodiment, the design method is applied in a photolithography process in which the structure on the substrate 11 is a Tri-layer structure.

[0124] In one embodiment, Fig. 9 As shown, the Tri-layer structure includes a photoresist (PR, also known as photoresist 21), an anti-reflective layer 22 and a spin-on carbon layer (SOC 19) from top to bottom.

[0125] The present invention applies the contact hole lithography process condition design method to the Tri-layer lithography structure, which not only reduces the reflection of exposure light to improve pattern clarity, reduces the edge roughness of the contact hole, but also improves the etching selectivity. Compared with the Bi-layer lithography structure, it is suitable for more advanced process nodes (such as 28nm and below), but the process of spin coating SOC19 is more complicated, and an additional spin coating process is required, so the cost is relatively higher.

[0126] Embodiment 4:

[0127] This embodiment provides a method for designing contact hole photolithography process conditions. The design method is basically the same as other features in Embodiment 1, except that:

[0128] In this embodiment, the design method is applied in a photolithography process in which the structure on the substrate 11 is a Bi-layer.

[0129] In one embodiment, Fig.10 As shown, the Bi-layer structure includes a photoresist (photoresist 21 ) and an anti-reflection layer 22 from top to bottom.

[0130] The present invention applies the contact hole lithography process condition design method to the Bi-layer lithography structure, which is mainly used to reduce the reflection of exposure light to improve pattern clarity. Compared with the Tri-layer lithography structure, it is suitable for cost-sensitive applications, has a simpler process and relatively lower costs.

[0131] Embodiment 5:

[0132] The present invention provides a semiconductor structure, which adopts the contact hole lithography process condition design method described in any one of Examples 1-4 to obtain the lithography process conditions for setting contact holes on the semiconductor structure, and the semiconductor structure includes a substrate 11 and n layers of thin films 12 deposited on the substrate 11, where n is an integer greater than or equal to 1.

[0133] Preferably, n is greater than or equal to 4.

[0134] The present invention optimizes the iterative effect of the roughness of the edge of the contact hole that can be obtained by the semiconductor structure by setting the number of thin films 12 in the semiconductor structure.

[0135] In summary, the contact hole lithography process condition design method and semiconductor structure of the present invention can improve the edge roughness of the contact hole obtained by lithography by iteratively optimizing the illumination condition parameters of the lithography, and the improvement effect is obvious; at the same time, before performing iterative optimization, the target exposure anchor point is screened through the process window design conditions, so that the contact hole with improved edge roughness meets the process window design conditions, and is suitable for the lithography process of 28nm and below technology nodes; in addition, through the contact hole lithography process condition design method, the lithography process conditions can be quickly adapted to the changes in lithography conditions brought about by the processes corresponding to the Tri-layer structure and the Bi-layer structure, so as to ensure that the edge roughness of the contact hole and the lithography process window conditions can still be guaranteed when the process is changed.

[0136] Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0137] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for designing contact hole lithography process conditions, characterized in that: The design method comprises: Providing a substrate to be coated with an anti-reflection layer, the substrate comprising a substrate and n thin films deposited on the substrate, where n is an integer greater than or equal to 1; measuring and obtaining parameters of a front thin film of the substrate to be coated with the anti-reflection layer, the front thin film parameters comprising a film thickness and a corresponding extinction coefficient of each thin film in m thin films starting from the topmost thin film of the substrate, where m is an integer greater than or equal to 1 and less than or equal to n; Performing photolithography simulation based on the obtained parameters of the front-layer thin film to obtain a curve of the relationship between the simulated film thickness and the extinction coefficient of the anti-reflection layer to be coated, and then selecting a target film thickness of the anti-reflection layer to be coated; Performing photolithography simulation according to the parameters of the front film layer and the target film thickness and extinction coefficient of the anti-reflection layer to be coated, obtaining a relationship curve between the simulated film thickness and reflectivity of the photoresist set on the anti-reflection layer to be coated, and then selecting the target film thickness of the photoresist; According to the parameters of the front film, the target film thickness and extinction coefficient of the anti-reflection layer to be coated, and the target film thickness of the photoresist, a candidate exposure anchor point is selected, and the photolithography parameters to be optimized and the illumination mode parameters are fixed to perform photolithography simulation to obtain at least one target exposure anchor point; By changing the illumination condition parameters on the substrate, the lithography process conditions obtained in the above steps are verified, the target exposure anchor point with the smallest contact hole edge roughness obtained by lithography is selected as the selected exposure anchor point, and the illumination condition parameters corresponding to the selected exposure anchor point are obtained, so as to determine the contact hole lithography process conditions; the illumination condition parameters include: numerical aperture, outer ring pupil relative radius and inner ring pupil relative radius; the lithography process conditions obtained in the above steps include: target film thickness of the anti-reflection layer to be coated, target film thickness of the photoresist, the illumination mode parameters and the at least one target exposure anchor point.

2. The contact hole lithography process condition design method according to claim 1, characterized in that: n is greater than or equal to 4, m is greater than or equal to 4.

3. The contact hole lithography process condition design method according to claim 1, characterized in that: The step of selecting a target film thickness of the anti-reflection layer to be applied further comprises: Obtaining the second minimum point of the relationship curve between the simulated film thickness and the extinction coefficient of the anti-reflection layer to be coated; The simulated film thickness of the anti-reflection layer to be coated corresponding to the second minimum point is selected as the target film thickness of the anti-reflection coating.

4. The contact hole lithography process condition design method according to claim 1, characterized in that: The step of obtaining the target film thickness of the photoresist at least includes: Input the parameters of the front layer film and the target film thickness and the corresponding extinction coefficient of the anti-reflection coating into the photolithography simulation software for simulation, obtain the relationship curve between the simulated film thickness and the reflectivity of the photoresist set on the anti-reflection layer to be coated, and select at least one minimum point in the curve whose absolute value of the slope is close to 0; The simulated film thickness of the photoresist corresponding to at least one minimum point where the absolute value of the slope is close to 0 is selected as the target film thickness of the photoresist.

5. The contact hole lithography process condition design method according to claim 1, characterized in that: The illumination mode parameters include the exposure light source illumination mode and the exposure light source polarization state.

6. The method for designing contact hole photolithography process conditions according to claim 1, characterized in that: The step of obtaining at least one target exposure anchor point further includes: Selecting a series of characteristic patterns as the candidate exposure anchor points; Fix the lithography parameters and illumination mode parameters to be optimized to perform lithography simulation, and obtain one or more parameters of the key line width, line width uniformity parameter, mask error enhancement factor, energy margin or focus depth corresponding to the candidate exposure anchor point as preset screening parameters; At least one candidate exposure anchor point whose preset screening parameters satisfy the photolithography process window design conditions among the candidate exposure anchor points is obtained as the target exposure anchor point.

7. The contact hole photolithography process condition design method according to claim 6, characterized in that: The series of characteristic patterns include: a preset period dense pattern, a preset period semi-dense pattern, a preset period semi-dense pattern with exposure auxiliary patterns added based on preset rules, and / or an isolated pattern in a sparse area.

8. The contact hole lithography process condition design method according to claim 1, characterized in that: The step of changing the lighting condition parameters on the substrate further comprises: Selecting a set of lighting condition parameters as an initial parameter set, and changing one or more lighting condition parameters to perform iteration based on the initial parameter set; When the change of the contact hole edge roughness obtained by photolithography is less than the preset change value, the illumination condition parameters obtained at this time are used as a new initial parameter group; After repeated iterations for a preset number of times, the obtained illumination condition parameters with the minimum roughness of the contact hole edge are used as the contact hole photolithography process conditions.

9. The contact hole lithography process condition design method according to claim 1, characterized in that: The design method further comprises: Determining whether the edge roughness of the contact hole obtained by photolithography under the illumination condition parameters corresponding to the selected exposure anchor point is higher than a reference threshold; If the edge roughness is higher than the reference threshold, the lighting condition parameters are adjusted to re-perform the photolithography process verification to obtain a new selected exposure anchor point; if the edge roughness is not higher than the reference threshold, the iteration is terminated and the lighting condition parameters corresponding to the contact hole edge roughness are output.

10. A semiconductor structure, characterized in that: The semiconductor structure adopts the contact hole lithography process condition design method described in any one of claims 1-9 to obtain the lithography process conditions for setting contact holes on the semiconductor structure. The semiconductor structure includes a substrate and n layers of thin films deposited on the substrate, where n is an integer greater than or equal to 1.

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