PCIe Switch-based Port reset linkage PHY reset method and storage medium

Abstract

The invention discloses a PCIe Switch-based Port reset linkage PHY reset method and a storage medium, and the method comprises the steps: employing different linkage modes according to reset types, and the reset types comprise basic reset and hot reset; when the reset type is basic reset, the Port reset processing module latches the basic reset and maps the basic reset into corresponding Port reset according to ports contained in a domain; the Port reset is sent to a PHY reset processing module for PHY reset; when the PCIe Port controller receives the reset, the PCIe Port controller carries out corresponding reset; when the reset type is hot reset, outputting a hot reset signal to a PCIe Switch module reset processing module; the PCIe Switch module reset processing module converts the hot reset signal into a pulse effective signal and sends the pulse effective signal to the Port reset processing module; the Port reset processing module judges and processes the hot reset signal to form Port hot reset; the Port hot reset is sent to a PHY reset processing module for PHY reset; and the PCIe Port controller works normally after being released and reset.

Description

Technical Field

[0001] The present invention relates to the PCIe field, and in particular to a method and storage medium for linking a Port reset with a PHY reset based on a PCIe Switch. Background Art

[0002] PCI-Express (peripheral component interconnect express), referred to as PCIe, is a high-speed serial computer expansion bus standard, mainly used to expand the computer system bus data throughput and improve the communication speed of devices.

[0003] The PCIe basic reset is automatically handled by the hardware, which will reset the entire PCIe device, initialize all hardware logic related to the state machine, port status, and configuration registers in the configuration space.

[0004] PCIe Hot Reset is an In-band reset that does not use sideband signals. The PCIe device sends several TS1 Ordered Sets (where bit0 of the fifth character is 1) to the devices adjacent to its link. These TS1OS are sent simultaneously on all lanes and last for about 2ms. When the PCIe device receives a hot reset, the LTSSM enters the Recovery and Hot Reset state, then returns to the Detect state, and restarts the link initialization training. All state machines, hardware logic, port states, and registers in the configuration space (except Sticky bits) of the PCIe device will be initialized to the default state.

[0005] Conventional PCIe reset only processes the reset release sequence of Port reset and PHY reset during power-on initialization, and does not perform special processing on Port reset and PHY reset during operation. Summary of the invention

[0006] To achieve the above-mentioned purpose and other related purposes, the present invention discloses a method for linking a PHY reset with a Port reset based on a PCIe Switch, comprising: Different linkage modes are adopted according to the reset type, which includes basic reset and hot reset; When the reset type is base reset: The port reset processing module latches the basic reset and maps it to the corresponding port reset according to the ports included in the domain; Send the Port reset to the PHY reset processing module to reset the PHY; The PCIe Port controller performs a corresponding reset when receiving a reset; When the reset type is warm reset: Outputting the hot reset signal to the PCIe Switch module reset processing module; The PCIe Switch module reset processing module converts the hot reset signal into a pulse valid signal and sends it to the Port reset processing module; The port reset processing module judges and processes the hot reset signal to form a port hot reset; Send the Port hot reset to the PHY reset processing module to perform PHY reset; The PCIe Port controller operates normally after releasing reset.

[0007] Further, the port reset processing module latches the basic reset and maps the basic reset to the corresponding port reset according to the ports included in the domain, including: The basic reset is obtained by the software configuration register Virtual Switch; The port reset processing module latches the VS basic reset and maps it to the corresponding port reset according to the ports included in the Virtual Switch domain.

[0008] Further, when the reset type is a basic reset, sending the Port reset to the PHY reset processing module to perform a PHY reset includes: The port reset is divided into two paths, one is sent to the PHY reset processing module, and the other is sent to the PCIe Switch module reset processing module; The PHY reset processing module determines whether to link the PHY reset according to the basic reset linkage controller register, and generates a PHY reset if the basic reset linkage controller register is valid.

[0009] Further, when the reset type is a basic reset, sending the Port reset to the PCIe Switch module reset processing module includes: The PCIe Switch module reset processing module generates PL reset, TL reset, and sticky register reset.

[0010] Further, the step of outputting the hot reset signal to the PCIe Switch module reset processing module includes: When the PCIe Port controller detects a UP hot reset or a DP hot reset, it outputs it to the reset processing module of the PCIe Switch module.

[0011] Furthermore, the PCIe Switch module reset processing module converts the hot reset signal into a pulse valid signal and sends it to the Port reset processing module, including: The PCIe Switch module reset processing module generates PL reset, TL reset and non-sticky register reset and reset hold, and converts the hot reset into a pulse valid signal and outputs it to the Port reset processing module.

[0012] Further, the port reset processing module judges and processes the hot reset signal to form a port hot reset including: If it is a UP hot reset, the UP hot reset is mapped to the Port hot reset of all ports in the Virtual Switch domain where the UP hot reset is located; If it is a DP hot reset, it is mapped to the hot reset of the Port itself.

[0013] Further, sending the Port hot reset to the PHY reset processing module to perform PHY reset includes: Port hot reset is divided into two paths, one is sent to the PHY reset processing module, and the other is sent to the PCIe Switch module reset processing module; The PHY reset processing module determines whether to link the PHY reset according to the hot reset linkage controller register, and generates a PHY reset if the hot reset linkage controller register is valid; At the same time, the reset processing module of the PCIe Switch module detects the UP / DP hot reset release, and releases the PL reset, TL reset, and non-sticky register reset.

[0014] On the other hand, the present invention further provides a computer-readable storage medium having a computer program stored thereon, which implements the above method when executed by a processor.

[0015] By adopting the above technical solution, the linkage between Port reset and PHY reset can be achieved during the PCIe operation process, thereby improving the convenience of use. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present disclosure. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements, among which: Figure 1 is a flow chart of an embodiment of the present invention. DETAILED DESCRIPTION

[0017] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0018] Reference Figure 1 The embodiment of the present invention provides a method for linking a PHY reset with a Port reset based on a PCIe Switch, comprising the following steps: S1: Different linkage modes are adopted according to the reset type, which includes basic reset and hot reset; S2: When the reset type is basic reset: S21: The port reset processing module latches the basic reset and maps it into a corresponding port reset according to the ports included in the domain; Specifically include: The basic reset is obtained by the software configuration register Virtual Switch; The port reset processing module latches the VS basic reset and maps it to the corresponding port reset according to the ports included in the Virtual Switch domain.

[0019] S22: Send the Port reset to the PHY reset processing module to perform PHY reset; Specifically include: The port reset is divided into two paths, one is sent to the PHY reset processing module, and the other is sent to the PCIe Switch module reset processing module; The PHY reset processing module determines whether to link the PHY reset according to the basic reset linkage controller register, and generates a PHY reset if the basic reset linkage controller register is valid; At the same time, the PCIe Switch module reset processing module generates PL reset (physical layer reset), TL reset (transition layer reset) and sticky register reset.

[0020] S23: The PCIe Port controller performs a corresponding reset upon receiving the reset.

[0021] S3: When the reset type is warm reset: S31: Outputting a hot reset signal to a reset processing module of a PCIe Switch module; Specifically include: When the PCIe Port controller detects a UP hot reset or a DP hot reset, it outputs it to the reset processing module of the PCIe Switch module.

[0022] Among them, UP hot reset is a hot reset operation initiated by the upstream device of the link. In a PCIe link, the upstream device is usually a device close to the root complex, which is responsible for sending data from the downstream device (such as an expansion card) to the upstream (such as the CPU or the main chipset). When the upstream device needs to reinitialize the link or solve the link problem, it can initiate a UP hot reset to quickly restore the link status without restarting the entire system.

[0023] DP hot reset is a hot reset operation initiated by the downstream device of the link. Downstream devices are usually devices far away from the root complex, such as expansion cards or endpoint devices, which receive data from the upstream and process it. When the downstream device needs to reinitialize the link or solve link problems, it can initiate a DP hot reset to quickly restore the link status without restarting the entire system.

[0024] S32: The PCIe Switch module reset processing module converts the hot reset signal into a pulse valid signal and sends it to the port reset processing module; Specifically include: The PCIe Switch module reset processing module generates PL reset, TL reset and non-sticky register reset and reset hold, and converts the hot reset into a pulse valid signal and outputs it to the Port reset processing module.

[0025] S33: The port reset processing module judges and processes the hot reset signal to form a port hot reset; Specifically include: If it is a UP hot reset, the UP hot reset is mapped to the Port hot reset of all ports in the Virtual Switch domain where the UP hot reset is located; If it is a DP hot reset, it is mapped to the hot reset of the Port itself.

[0026] S34: Sending the Port hot reset to the PHY reset processing module to perform PHY reset; Specifically include: Port hot reset is divided into two paths, one is sent to the PHY reset processing module, and the other is sent to the PCIe Switch module reset processing module; The PHY reset processing module determines whether to link the PHY reset according to the hot reset linkage controller register, and generates a PHY reset if the hot reset linkage controller register is valid; At the same time, the reset processing module of the PCIe Switch module detects the UP / DP hot reset release, and releases the PL reset, TL reset, and non-sticky register reset.

[0027] S35: The PCIe Port controller operates normally after releasing reset.

[0028] The above-mentioned implementation method based on PCIe Switch Port reset linkage with PHY reset can also be used for reset design of other protocols; the implementation method based on PCIe Switch Port reset linkage with PHY reset is not only used in chip design, but also in other technologies such as FPGA design, and is also applicable to the present invention.

[0029] An embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the above method is implemented.

[0030] Those skilled in the art will appreciate that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by those skilled in the art in the art to which the present invention belongs. It should also be understood that terms such as those defined in general dictionaries should be understood to have meanings consistent with the meanings in the context of the prior art, and will not be interpreted with idealized or overly formal meanings unless specifically defined.

[0031] For the method embodiments, for the sake of simplicity, they are all described as a series of action combinations, but those skilled in the art should know that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0032] It can be known from the description of the above implementation modes that those skilled in the art can clearly understand that the present application can be implemented by means of software plus a necessary general hardware platform. Based on such an understanding, the technical solution of the present application can be essentially or partly contributed to the prior art in the form of a software product, which can be stored in a storage medium such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes several instructions for enabling a computer device (which can be a personal computer, a server or a network device, etc.) to execute the methods described in the various implementation modes of the present application or certain parts of the implementation modes.

[0033] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for linking a port reset with a PHY reset based on a PCIe Switch, characterized in that: include: Different linkage modes are adopted according to the reset type, which includes basic reset and hot reset; When the reset type is base reset: The port reset processing module latches the basic reset and maps it to the corresponding port reset according to the ports included in the domain; Send the Port reset to the PHY reset processing module to reset the PHY; The PCIe Port controller performs a corresponding reset when receiving a reset; When the reset type is warm reset: Outputting the hot reset signal to the PCIe Switch module reset processing module; The PCIe Switch module reset processing module converts the hot reset signal into a pulse valid signal and sends it to the Port reset processing module; The port reset processing module judges and processes the hot reset signal to form a port hot reset; Send the Port hot reset to the PHY reset processing module to perform PHY reset; The PCIe Port controller operates normally after releasing reset.

2. The method according to claim 1, characterized in that The port reset processing module latches the basic reset and maps the basic reset to the corresponding port reset according to the ports included in the domain, including: The basic reset is obtained by the software configuration register Virtual Switch; The port reset processing module latches the VS basic reset and maps it to the corresponding port reset according to the ports included in the Virtual Switch domain.

3. The method according to claim 1, characterized in that When the reset type is a basic reset, sending the Port reset to the PHY reset processing module to perform a PHY reset includes: The port reset is divided into two paths, one is sent to the PHY reset processing module, and the other is sent to the PCIe Switch module reset processing module; The PHY reset processing module determines whether to link the PHY reset according to the basic reset linkage controller register, and generates a PHY reset if the basic reset linkage controller register is valid.

4. The method according to claim 3, characterized in that When the reset type is a basic reset, sending the Port reset to the PCIe Switch module reset processing module includes: The PCIe Switch module reset processing module generates PL reset, TL reset, and sticky register reset.

5. The method according to claim 1, characterized in that The step of outputting the hot reset signal to the PCIe Switch module reset processing module includes: When the PCIe Port controller detects a UP hot reset or a DP hot reset, it outputs it to the reset processing module of the PCIe Switch module.

6. The method according to claim 1, characterized in that The PCIe Switch module reset processing module converts the hot reset signal into a pulse valid signal and sends it to the Port reset processing module, including: The PCIe Switch module reset processing module generates PL reset, TL reset and non-sticky register reset and reset hold, and converts the hot reset into a pulse valid signal and outputs it to the Port reset processing module.

7. The method according to claim 5, characterized in that The port reset processing module judges and processes the hot reset signal, and the port hot reset includes: If it is a UP hot reset, the UP hot reset is mapped to the Port hot reset of all ports in the Virtual Switch domain where the UP hot reset is located; If it is a DP hot reset, it is mapped to the hot reset of the Port itself.

8. The method according to claim 5, characterized in that When the reset type is a hot reset, sending the Port hot reset to the PHY reset processing module to perform a PHY reset includes: Port hot reset is divided into two paths, one is sent to the PHY reset processing module, and the other is sent to the PCIe Switch module reset processing module; The PHY reset processing module determines whether to link the PHY reset according to the hot reset linkage controller register, and generates a PHY reset if the hot reset linkage controller register is valid; At the same time, the reset processing module of the PCIe Switch module detects the UP / DP hot reset release, and releases the PL reset, TL reset, and non-sticky register reset.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the method described in any one of claims 1 to 8 is implemented.

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