Nonvolatile memory and erasing method and erasing system thereof

Abstract

The invention provides a nonvolatile memory as well as an erasing method and an erasing system thereof. A mark register is arranged in the nonvolatile memory; the erasing method comprises the following steps: in response to a received first erasing instruction, determining a plurality of first sectors corresponding to the first erasing instruction, and setting a first erasing mark corresponding to each first sector in a mark register; executing an erasure verification operation on each first sector to obtain an erasure verification result of each first sector; in response to the fact that the erasure verification result of any first sector is passed, resetting and updating a first erasure mark corresponding to the first sector in the same mark register into a second erasure mark; determining the first sector marked as the first erasure mark in the same mark register as a target erasure sector; and executing an erase operation of the target erase sector. According to the method, the erasing speed is greatly increased, the erasing time is shortened, the unnecessary erasing frequency can be reduced to eliminate or reduce the over-erasing phenomenon, the service life of the chip is prolonged, and the reliability of the chip is improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a non-volatile memory and an erasing method and an erasing system thereof. Background Art

[0002] Currently, in the circuit design of Nor Flash (non-volatile flash memory technology), reading, writing, and erasing are all essential operations. Among them, the erasing operation is the most time-consuming, and the Fowler-Nordheim (a model describing electron tunneling) tunneling effect is usually used, which is a quantum mechanical process that removes the stored charge or electrons from the non-volatile memory cell to reset it to an unprogrammed state or an erased state, and the time consumed needs to be in the order of milliseconds.

[0003] The Fowler-Nordheim tunneling erase operation is accomplished by applying a negative high voltage to the control gate of the memory cell and a positive high voltage to the body (or p-well). The high voltage across the memory cell induces a strong electric field in the oxide or ONO (a dielectric layer) layer, so the electrons or negative charges of the memory cell gain enough energy to tunnel through the oxide barrier. The memory logic controller performs an erase verification step to ensure that the memory cell is at the expected threshold voltage for the erased state.

[0004] The erase operation can be divided into chip erase (CE), block erase (BE), half-block erase (HBE), and sector erase (SE). Sector erase generally takes more than tens of milliseconds and is usually accompanied by over-erasure, which requires over-erasure repair. Chip erase includes erasing of many blocks, and block erase includes erasing of multiple sectors. Since the erase area of ​​chip erase and block erase is larger than that of sector erase, it takes longer and the over-erasure phenomenon will be more serious.

[0005] The more serious the over-erase phenomenon is, the easier it is for the storage unit storing data "0" to be misread as storing data "1", and the over-erase repair time is too long, causing the erase time to exceed the expected specification. When erasing a block, some sectors are already in the erase state, or when erasing the entire chip, some blocks are already in the erase state. If the erase operation is performed at this time, the over-erase phenomenon will become more serious, and the chip life will be shortened and the reliability will be reduced. Summary of the invention

[0006] The technical problem to be solved by the present disclosure is to overcome the defects in the prior art that over-erasure is prone to occur in block erasure and whole chip erasure, resulting in a shortened chip life and poor reliability, and to provide a non-volatile memory and an erasing method and an erasing system thereof.

[0007] The present invention solves the above technical problems through the following technical solutions:

[0008] According to a first aspect of the present disclosure, a method for erasing a non-volatile memory is provided, wherein a flag register is provided in the non-volatile memory;

[0009] The erasing method includes:

[0010] In response to receiving a first erase instruction, determining a plurality of first sectors corresponding to the first erase instruction, and setting a first erase mark corresponding to each of the first sectors in the mark register; the first erase mark indicates that an erase operation needs to be performed;

[0011] Performing an erasure verification operation on each of the first sectors, and obtaining an erasure verification result of each of the first sectors;

[0012] In response to the erase verification result of any of the first sectors being passed, resetting and updating the first erase mark corresponding to the first sector in the same mark register to a second erase mark; the second erase mark indicates that no erase operation needs to be performed;

[0013] Determining the first sector marked as the first erase mark in the same mark register as a target erase sector;

[0014] An erase operation of the target erase sector is performed.

[0015] Preferably, the step of performing the erasing operation of the target erasing sector comprises:

[0016] Performing an erase operation, an over-erase repair operation and an erase verification operation on the target erase sector in sequence, and obtaining the erase verification result of each target erase sector;

[0017] In response to the erase verification result of the target erase sector being passed, resetting and updating the first erase mark corresponding to the target erase sector in the same mark register to the second erase mark;

[0018] Based on the first erase mark in the mark register, the new target erase sector is determined, and the steps of sequentially performing an erase operation, an over-erase repair operation and an erase verification operation on the target erase sector are returned to be executed.

[0019] Preferably, the non-volatile memory is provided with an erasure count;

[0020] After the steps of sequentially performing an erasing operation, an over-erasure repair operation and an erasure verification operation on the target erasure sector, the erasing method further comprises:

[0021] Accumulate the current number of erasures to obtain the accumulated number of erasures;

[0022] In response to the accumulated number of erasures being equal to a preset number of erasures, it is determined that the erasure operation is abnormal.

[0023] Preferably, the erasing method further comprises:

[0024] In response to the flag registers all containing the second erase flag, determining that the erase operation is completed;

[0025] and / or,

[0026] After determining that the erasing operation is completed, the erasing method further includes: clearing the erasing times in the erasing times storage area.

[0027] Preferably, before the step of determining the first sector marked as the first erasure mark in the same mark register as the target erasure sector, the erasure method further comprises:

[0028] Determine the first sector marked as the second erase mark in the same mark register as a second sector, and perform an over-erasure repair operation on the second sector;

[0029] and / or,

[0030] After the step of determining the first sector corresponding to the first erasure mark in the same mark register as a target erasure sector and before the step of performing an erasure operation on the target erasure sector, the erasure method further includes:

[0031] A pre-programming operation is performed on each of the target erase sectors.

[0032] Preferably, the erase instruction includes at least one of a block erase instruction, a half block erase instruction, and a sector erase instruction;

[0033] and / or,

[0034] The length of the flag register is smaller than a preset threshold.

[0035] According to a second aspect of the present disclosure, a method for erasing a non-volatile memory is provided, the method comprising:

[0036] In response to receiving a second erase instruction representing full-chip erase, determining a number of blocks corresponding to the second erase instruction;

[0037] A first erasing instruction corresponding to each of the blocks is generated, and the erasing method described in the first aspect of the present disclosure is used to sequentially perform erasing operations on a number of the blocks until the erasing operations on all the blocks are completed.

[0038] According to a third aspect of the present disclosure, there is provided a non-volatile memory erasing system, wherein the non-volatile memory is provided with a flag register;

[0039] The erasure system includes a first determination module, an erasure verification module, a reset module, a second determination module and a first erasure module;

[0040] The first determination module is used for determining a plurality of first sectors corresponding to the first erase instruction in response to receiving the first erase instruction, and setting a first erase mark corresponding to each of the first sectors in the mark register; the first erase mark indicates that an erase operation needs to be performed;

[0041] The erasure verification module is used to perform an erasure verification operation on each of the first sectors and obtain an erasure verification result of each of the first sectors;

[0042] The reset module is used for resetting and updating the first erasure mark corresponding to the first sector in the same flag register to a second erasure mark in response to the erasure verification result of any of the first sectors being passed; the second erasure mark indicates that no erasure operation needs to be performed;

[0043] The second determination module is used to determine the first sector marked as the first erase mark in the same mark register as a target erase sector;

[0044] The first erasing module is used to perform an erasing operation on the target erasing sector.

[0045] According to a fourth aspect of the present disclosure, there is provided a non-volatile memory erasing system, the erasing system comprising a third determination module and a second erasing module;

[0046] The third determination module is used for determining a number of blocks corresponding to the second erase instruction in response to receiving the second erase instruction representing the entire chip erase;

[0047] The second erasing module is used to generate a first erasing instruction corresponding to each of the blocks, and uses the erasing system described in the third aspect of the present disclosure to sequentially execute erasing operations on several of the blocks until the erasing operations on all of the blocks are completed to complete the entire chip erasing operation.

[0048] According to a fifth aspect of the present disclosure, a nonvolatile memory is provided, wherein the nonvolatile memory includes the erasure system described in the third aspect of the present disclosure, or the erasure system described in the fourth aspect of the present disclosure.

[0049] On the basis of being in accordance with the common sense in the art, the above-mentioned preferred conditions can be arbitrarily combined to obtain the preferred embodiments of the present disclosure.

[0050] The positive progressive effect of the present disclosure is that by multiplexing the tag register, not only can the erasing speed be greatly accelerated and the erasing time be reduced, but also the number of unnecessary erasing times can be reduced to eliminate or reduce the over-erasure phenomenon, increase the life and reliability of the chip, and achieve great optimization of block erasing and whole-chip erasing. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 is a first flow chart of the method for erasing a non-volatile memory in Embodiment 1 of the present disclosure;

[0052] Figure 2 This is a flowchart of step S17 of the method for erasing a non-volatile memory in Embodiment 1 of the present disclosure;

[0053] Figure 3 is a second flow chart of the method for erasing a non-volatile memory in Embodiment 1 of the present disclosure;

[0054] Figure 4 is a first flow chart of a method for erasing a non-volatile memory in Embodiment 2 of the present disclosure;

[0055] Figure 5 is a second flow chart of the method for erasing a non-volatile memory in Embodiment 2 of the present disclosure;

[0056] Figure 6 This is a module schematic diagram of the erasing system of the non-volatile memory in Embodiment 3 of the present disclosure;

[0057] Figure 7 This is a module diagram of the erasing system of the non-volatile memory in Embodiment 4 of the present disclosure. DETAILED DESCRIPTION

[0058] The present disclosure is further described below by way of examples, but the present disclosure is not limited to the scope of the examples.

[0059] Prefixes such as "first" and "second" are used in the embodiments of the present disclosure only to distinguish different description objects, and have no limiting effect on the position, order, priority, quantity or content of the described objects. The use of prefixes such as ordinal numbers to distinguish description objects in the embodiments of the present disclosure does not constitute a limitation on the described objects. For the statement of the described objects, please refer to the description in the context of the claims or embodiments, and no unnecessary limitation should be constituted due to the use of such prefixes. In addition, in the description of the present embodiment, unless otherwise specified, the meaning of "plurality" is two or more.

[0060] In the embodiments of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved are in compliance with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0061] Example 1

[0062] In a specific embodiment of the present disclosure, a method for erasing a non-volatile memory is provided, wherein a flag register is provided in the non-volatile memory;

[0063] like Figure 1 As shown, the erasing method includes:

[0064] S11, in response to receiving a first erase instruction, determining a plurality of first sectors corresponding to the first erase instruction, and setting a first erase mark corresponding to each first sector in a mark register; the first erase mark indicates that an erase operation needs to be performed;

[0065] S12, performing an erasure verification operation on each first sector, and obtaining an erasure verification result of each first sector;

[0066] S13, in response to a pass result of the erasure verification of any first sector, resetting and updating the first erasure mark corresponding to the first sector in the same mark register to a second erasure mark; the second erasure mark indicates that no erasure operation needs to be performed;

[0067] S15, determining the first sector marked as the first erase mark in the same mark register as the target erase sector;

[0068] S17, executing an erase operation of the target erase sector.

[0069] Specifically, when the first erase instruction is received, step S11 determines the first sector to be erased according to the first erase instruction, and sets the first erase mark corresponding to each first sector in the mark register to mark that each first sector needs to perform an erase operation, for example, setting the first erase mark corresponding to each first sector to "1".

[0070] The first erase instruction may include a block erase instruction, a half-block erase instruction, a sector erase instruction, etc. Taking the 8Mb Nor Flash as an example, there are 256 blocks, each block has 16 sectors, and each sector has 16 pages. When a block erase instruction is received, the block to be erased is initialized internally, and the 16 first sectors to be erased corresponding to the block erase instruction are determined (for ease of explanation, the 16 sectors are named sector1-sector16 respectively), and the first erase marks corresponding to sectors1-sector16 are set to "1" in the mark register.

[0071] Similarly, when a half-block erase instruction is received, eight first sectors to be erased corresponding to the half-block erase instruction can be determined; when a sector erase instruction is received, one first sector to be erased corresponding to the sector erase instruction can be determined.

[0072] Since the erase operation changes the high voltage threshold of the storage unit into a low voltage threshold, in order to speed up the erase speed and reduce the over-erasure phenomenon, before performing the erase operation on sector1-sector16, an erase verification operation is first performed on sector1-sector16 through step S12 to determine whether the threshold voltage of each first sector is less than the preset voltage threshold. If so, the erase verification result of the first sector is determined to be passed, otherwise it is determined to be failed.

[0073] Then, in step S13, the first erase mark in the mark register corresponding to the first sector with the erase verification result of passing is reset and updated to the second erase mark, so as to mark that the first sector does not need to perform the erase operation. For example, if the erase verification results of sector3 and sector4 are passed, the first erase mark "1" of sector3 and sector4 in the mark register is reset and updated to the second erase mark "0", thereby marking the first sectors that need to perform the erase operation and do not need to perform the erase operation in the block erase instruction respectively, which not only avoids the over-erasure phenomenon caused by performing the erase operation on the sectors that do not need to perform the erase operation, but also can greatly speed up the erase speed and reduce the erase time.

[0074] In step S15, the target erasing sectors that need to be erased, namely, sector1-sector2 and sector5-sector16, are determined by the first erase flag in the flag register, and then the erase operation is performed on the target erasing sectors in step S17.

[0075] Of course, the first erasure mark may be "0", and the second erasure mark may be "1", which may be set according to actual needs.

[0076] It should be noted that the entire erasing method shares a tag register, and the length of the tag register is less than a preset threshold, wherein the length of the tag register only needs to be able to store the erase mark of each sector corresponding to the block erase instruction, for example, the length of the tag register is 16 bits (bits) to store the erase marks corresponding to 16 sectors, thereby greatly reducing the space occupied by the tag register in the non-volatile memory. Of course, a spare tag register can also be set in the non-volatile memory to enable it when the current tag register fails to ensure the effective execution of the erasing method; in addition, a tag register for other functions can also be set in the non-volatile memory, which is not limited in this embodiment.

[0077] This specific implementation method can not only greatly speed up the erasing speed and reduce the erasing time by multiplexing the tag register, but also reduce the number of unnecessary erasing times to eliminate or reduce the over-erasure phenomenon, increase the life and reliability of the chip, and achieve great optimization of block erasing and whole-chip erasing.

[0078] In a specific implementation, before step S15, the erasing method further includes:

[0079] S14: Determine the first sector marked as the second erase mark in the same mark register as the second sector, and perform an over-erasure repair operation on the second sector.

[0080] Specifically, since the storage unit may be affected during the erasure process, resulting in the threshold voltage being too low (lower than the normal low voltage threshold range), and thus over-erasure may occur, after the erase verification result of each first sector is obtained through step S13, in order to ensure the read result of the first sector that passes the erase verification, sector3-sector4 that passes the erase verification is determined as the second sector according to the second erase mark in the mark register, and an over-erasure repair operation is performed on the second sector, so that the threshold voltage of the second sector returns to the normal low voltage threshold range.

[0081] In a specific implementation, after step S15 and before step S17, the erasing method further includes:

[0082] S16. Perform a pre-programming operation on each target erase sector.

[0083] Specifically, before performing the erase operation, a pre-programming operation is performed on each target erase sector to improve the performance of the non-volatile memory.

[0084] In a specific embodiment, Figure 2 As shown, step S17 includes:

[0085] S171, performing an erase operation, an over-erase repair operation, and an erase verification operation on the target erase sector in sequence, and obtaining an erase verification result of each target erase sector;

[0086] S172, in response to the erase verification result of the target erase sector being passed, resetting and updating the first erase mark corresponding to the target erase sector in the same mark register to a second erase mark;

[0087] S173. Based on the first erase mark in the mark register, determine a new target erase sector, and return to execute step S171.

[0088] In a specific implementation, the erasing method further includes: S18, in response to the second erasing flag being in the flag register, determining that the erasing operation is completed.

[0089] Specifically, after determining the target erase sector to be erased, perform an erase operation, an over-erase repair operation and an erase verification operation on the target erase sector in sequence, and obtain the erase verification result of each target erase sector. For example, if the erase verification result of sector1-sector2 is passed and the erase verification result of sector5-sector16 is failed, then the first erase mark in the mark register corresponding to the target erase sector that passed the erase verification result is reset and updated to the second erase mark, that is, the first erase mark "1" of sector1 and sector2 in the mark register is reset and updated to the second erase mark "0", and then the new target erase sector can be determined to be sector5-sector16 according to the first erase mark in the mark register, and return to step S171 to perform an erase operation, an over-erase repair operation and an erase verification operation on sector5-sector16 in sequence, and obtain the erase verification result of each target erase sector, until the erase marks of all first sectors in the mark register are the second erase marks, and it is determined that the erase operation is completed.

[0090] In a specific implementation, the non-volatile memory is provided with an erasure count;

[0091] After step S171, the erasing method further includes:

[0092] S174, accumulating the current erasure times to obtain the accumulated erasure times;

[0093] S175. In response to the accumulated number of erasures being equal to the preset number of erasures, determining that the erasure operation is abnormal.

[0094] After determining that the erasing operation is completed, the erasing method further includes: clearing the erasing times in the erasing times storage area.

[0095] Specifically, the non-volatile memory is also provided with an erasure count, and the initial value of the erasure count is 0. After each execution of step S171, the current erasure count is accumulated. For example, after executing the erasure operation, the over-erasure repair operation and the erasure verification operation on sector1-sector2 and sector5-sector16 in turn, and obtaining the erasure verification result of each target erased sector, the erasure count is accumulated to obtain 1. Since sector1-sector2 passes the erasure verification, while sector5-sector16 fails the erasure verification, the erasure operation, the over-erasure repair operation and the erasure verification operation are executed on sector5-sector16, and the erasure verification result of each target erased sector is obtained, the erasure count is accumulated to obtain 2, and so on. After it is determined that the erasure operation is completed, the erasure count is initialized to 0, and the erasure count record for the next time the erasure instruction is received is performed.

[0096] When the number of erasures reaches a preset number of erasures (eg, 128), and there are still sectors that have not been completely erased, it means that the chip has reached the end of its life span and can no longer perform the data storage function. The erasure operation is determined to be abnormal, and the current erasure operation is terminated.

[0097] In a specific example, if Figure 3 As shown, after receiving the block erase instruction; the block to be erased is initialized internally; then the first erase mark is set for each sector in the block to be erased in the mark register; then the erase verification operation is performed on each sector, if the current sector passes the erase verification, the first erase mark corresponding to the current sector in the mark register is reset and updated to the second erase mark, otherwise the next sector is used as the current sector to determine whether it passes the erase verification; then the over-erasure repair operation is performed on the sectors corresponding to the second erase mark in the mark register in turn; after completing the over-erasure repair operation of all sectors corresponding to the second erase marks Afterwards, the sectors corresponding to the first erase mark in the mark register are pre-programmed in sequence; then the erase operation is performed on the sectors corresponding to the first erase mark in the mark register at the same time, and then the erase repair operation and the erase verification operation are performed on the sectors that perform the erase operation, and the first erase mark in the mark register corresponding to the sector that passes the erase verification operation is reset and updated to the second erase mark. If there is still a first erase mark in the mark register, return to the step of performing the erase operation on the sectors corresponding to the first erase mark in the mark register at the same time, until the mark register is full of second erase marks, and it is determined that the erase operation is completed.

[0098] This embodiment can not only greatly speed up the erasing speed and reduce the erasing time by multiplexing the tag register, but also reduce the number of unnecessary erasing times to eliminate or reduce the over-erasure phenomenon, increase the life and reliability of the chip, and achieve great optimization of block erasing and whole-chip erasing.

[0099] Example 2

[0100] In a specific embodiment of the present disclosure, a method for erasing a non-volatile memory is provided, such as Figure 4 As shown, the erasing method includes:

[0101] S21, in response to receiving a second erase instruction representing full-chip erase, determining a number of blocks corresponding to the second erase instruction;

[0102] S22, generating a first erasing instruction corresponding to each block, and using the erasing method described in any of the above embodiments to sequentially perform erasing operations on a plurality of blocks until the erasing operations on all blocks are completed.

[0103] Specifically, Figure 5 As shown, after receiving the whole chip erase instruction, the entire chip is initialized internally, and a block erase instruction corresponding to each block in the entire chip is generated. The erase method in Example 1 is used to perform the erase operation of each block in turn according to the block erase instruction of each block until the erase operation of all blocks is completed.

[0104] This embodiment can not only greatly speed up the erasing speed and reduce the erasing time by multiplexing the tag register, but also reduce the number of unnecessary erasing times to eliminate or reduce the over-erasure phenomenon, increase the life and reliability of the chip, and achieve great optimization of block erasing and whole-chip erasing.

[0105] Example 3

[0106] In a specific embodiment of the present disclosure, a non-volatile memory erasing system is provided, wherein a flag register is provided in the non-volatile memory;

[0107] The erasure system includes a first determination module 101, an erasure verification module 102, a reset module 103, a second determination module 104 and a first erasure module 105;

[0108] The first determination module 101 is used for determining a plurality of first sectors corresponding to the first erase instruction in response to receiving the first erase instruction, and setting a first erase mark corresponding to each first sector in a mark register; the first erase mark indicates that an erase operation needs to be performed;

[0109] The erasure verification module 102 is used to perform an erasure verification operation on each first sector and obtain an erasure verification result of each first sector;

[0110] The reset module 103 is used for resetting and updating the first erasure mark corresponding to the first sector in the same mark register to a second erasure mark in response to the erasure verification result of any first sector being passed; the second erasure mark indicates that no erasure operation needs to be performed;

[0111] The second determination module 104 is used to determine the first sector marked as the first erasure mark in the same mark register as the target erasure sector;

[0112] The first erasing module 105 is used to perform an erasing operation on a target erasing sector.

[0113] As for the system embodiment, since it basically corresponds to the method embodiment, the relevant parts can refer to the partial description of the method embodiment. The system embodiment described above is only illustrative, wherein the units described as separate components may or may not be physically separated, and the components as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the disclosed solution.

[0114] This embodiment can not only greatly speed up the erasing speed and reduce the erasing time by multiplexing the tag register, but also reduce the number of unnecessary erasing times to eliminate or reduce the over-erasure phenomenon, increase the life and reliability of the chip, and achieve great optimization of block erasing and whole-chip erasing.

[0115] Example 4

[0116] In a specific embodiment of the present disclosure, a non-volatile memory erasing system is provided, the erasing system includes a third determination module 201 and a second erasing module 202;

[0117] The third determination module 201 is used for determining a number of blocks corresponding to the second erase instruction in response to receiving the second erase instruction representing the entire chip erase;

[0118] The second erasing module 202 is used to generate a first erasing instruction corresponding to each block, and use the erasing system described in any of the above embodiments to sequentially execute the erasing operation of several blocks until the erasing operation of all blocks is completed to complete the entire chip erasing operation.

[0119] As for the system embodiment, since it basically corresponds to the method embodiment, the relevant parts can refer to the partial description of the method embodiment. The system embodiment described above is only illustrative, wherein the units described as separate components may or may not be physically separated, and the components as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the disclosed solution.

[0120] This embodiment can not only greatly speed up the erasing speed and reduce the erasing time by multiplexing the tag register, but also reduce the number of unnecessary erasing times to eliminate or reduce the over-erasure phenomenon, increase the life and reliability of the chip, and achieve great optimization of block erasing and whole-chip erasing.

[0121] Example 5

[0122] In a specific embodiment of the present disclosure, a non-volatile memory is provided, and the non-volatile memory includes the erasing system described in any of the above embodiments.

[0123] Among them, the non-volatile memory includes Nor Flash.

[0124] This embodiment can not only greatly speed up the erasing speed and reduce the erasing time by multiplexing the tag register, but also reduce the number of unnecessary erasing times to eliminate or reduce the over-erasure phenomenon, increase the life and reliability of the chip, and achieve great optimization of block erasing and whole-chip erasing.

[0125] Although the specific embodiments of the present disclosure are described above, those skilled in the art should understand that this is only an example, and the protection scope of the present disclosure is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present disclosure, but these changes and modifications all fall within the protection scope of the present disclosure.

Claims

1. A method for erasing a non-volatile memory, characterized in that: The non-volatile memory is provided with a tag register; The erasing method comprises: In response to receiving a first erase instruction, determining a plurality of first sectors corresponding to the first erase instruction, and setting a first erase mark corresponding to each of the first sectors in the mark register; the first erase mark indicates that an erase operation needs to be performed; Performing an erasure verification operation on each of the first sectors, and obtaining an erasure verification result of each of the first sectors; In response to the erase verification result of any of the first sectors being passed, resetting and updating the first erase mark corresponding to the first sector in the same mark register to a second erase mark; the second erase mark indicates that no erase operation needs to be performed; Determining the first sector marked as the first erase mark in the same mark register as a target erase sector; An erase operation of the target erase sector is performed.

2. The erasing method according to claim 1, characterized in that: The step of performing the erasing operation of the target erasing sector comprises: Performing an erase operation, an over-erase repair operation and an erase verification operation on the target erase sector in sequence, and obtaining the erase verification result of each target erase sector; In response to the erase verification result of the target erase sector being passed, resetting and updating the first erase mark corresponding to the target erase sector in the same mark register to the second erase mark; Based on the first erase mark in the mark register, the new target erase sector is determined, and the steps of sequentially performing an erase operation, an over-erase repair operation and an erase verification operation on the target erase sector are returned to be executed.

3. The erasing method according to claim 2, characterized in that: The non-volatile memory is provided with an erasure count; After the steps of sequentially performing an erasing operation, an over-erasure repair operation and an erasure verification operation on the target erasure sector, the erasing method further comprises: Accumulate the current number of erasures to obtain the accumulated number of erasures; In response to the accumulated number of erasures being equal to a preset number of erasures, it is determined that the erasure operation is abnormal.

4. The erasing method according to claim 3, characterized in that: The erasing method further comprises: In response to the flag registers all containing the second erase flag, determining that the erase operation is completed; and / or, After determining that the erasing operation is completed, the erasing method further includes: clearing the erasing times in the erasing times storage area.

5. The erasing method according to any one of claims 1 to 4, characterized in that: Before the step of determining the first sector marked as the first erasure mark in the same mark register as a target erasure sector, the erasure method further includes: Determine the first sector marked as the second erase mark in the same mark register as a second sector, and perform an over-erasure repair operation on the second sector; and / or, After the step of determining the first sector corresponding to the first erasure mark in the same mark register as a target erasure sector and before the step of performing an erasure operation on the target erasure sector, the erasure method further includes: A pre-programming operation is performed on each of the target erase sectors.

6. The erasing method according to any one of claims 1 to 4, characterized in that: The erase instruction includes at least one of a block erase instruction, a half block erase instruction, and a sector erase instruction; and / or, The length of the flag register is smaller than a preset threshold.

7. A method for erasing a non-volatile memory, characterized in that: The erasing method comprises: In response to receiving a second erase instruction representing full-chip erase, determining a number of blocks corresponding to the second erase instruction; A first erasing instruction corresponding to each of the blocks is generated, and the erasing operation of several of the blocks is sequentially performed using the erasing method according to any one of claims 1 to 6 until the erasing operation of all the blocks is completed.

8. A non-volatile memory erasing system, characterized in that: The non-volatile memory is provided with a tag register; The erasure system includes a first determination module, an erasure verification module, a reset module, a second determination module and a first erasure module; The first determination module is used for determining a plurality of first sectors corresponding to the first erase instruction in response to receiving the first erase instruction, and setting a first erase mark corresponding to each of the first sectors in the mark register; The first erasure mark indicates that an erasure operation needs to be performed; The erasure verification module is used to perform an erasure verification operation on each of the first sectors and obtain an erasure verification result of each of the first sectors; The reset module is used for resetting and updating the first erasure mark corresponding to the first sector in the same flag register to a second erasure mark in response to the erasure verification result of any of the first sectors being passed; The second erasure mark indicates that no erasure operation needs to be performed; The second determination module is used to determine the first sector marked as the first erase mark in the same mark register as a target erase sector; The first erasing module is used to perform an erasing operation on the target erasing sector.

9. A non-volatile memory erasing system, characterized in that: The erasure system includes a third determination module and a second erasure module; The third determination module is used for determining a number of blocks corresponding to the second erase instruction in response to receiving the second erase instruction representing the entire chip erase; The second erasing module is used to generate a first erasing instruction corresponding to each of the blocks, and use the erasing system as described in claim 8 to sequentially execute the erasing operations of several of the blocks until the erasing operations of all the blocks are completed to complete the entire chip erasing operation.

10. A non-volatile memory, characterized in that: The non-volatile memory comprises the erasure system as claimed in claim 8, or, the erasure system as claimed in claim 9.

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