Storage and calculation integrated operational circuit based on memristor

Abstract

The invention provides a storage and calculation integrated operation circuit based on memristors. The storage and calculation integrated operation circuit comprises an input module, a plurality of memristor sub-arrays, a plurality of address gating modules, a plurality of memristor resistance value read-write modules, a plurality of potential holding circuit modules, a plurality of odd-even detection circuit modules and an XOR tree module. Wherein each memristor subarray is connected with an address gating module, a memristor resistance value read-write module and a potential holding circuit module, each potential holding circuit module is connected with an odd-even detection circuit module, and each odd-even detection circuit module is connected with an XOR tree module; in each memristor sub-array, each AND operation unit in each row completes AND calculation and then outputs current and accumulates the current to obtain accumulated current of each row; and the accumulated current is input into the parity detection circuit module through the potential holding circuit module, and after the parity of the flip times of a trigger in the parity detection circuit module is determined, an initial XOR operation value is output.

Description

Technical Field

[0001] The present invention relates to the field of storage-computing integrated technology, and in particular to a storage-computing integrated computing circuit based on a memristor. Background Art

[0002] The emergence of quantum computers has had a huge impact on existing cryptographic systems. In order to cope with the quantum threat, the research on Post-Quantum Cryptography (PQC) has invested extensive resources in recent years and has developed rapidly. The LPN (Learning parity with noise) problem has the advantages of simple arithmetic structure and resistance to quantum solving, and has become one of the strong candidates for constructing efficient PQC protocols. In this context, studying efficient LPN solvers has important practical significance for verifying the actual security of cryptographic systems based on LPN problems.

[0003] Heuristic algorithms perform well in dealing with complex optimization and decision-making problems and have great development potential in solving LPN problems. When solving LPN problems, heuristic algorithms often need to perform multiple matrix-vector product operations on the binary domain. When performing this operation on a traditional hardware platform, the large public matrix of LPN needs to be transmitted between the computing module and the memory module, resulting in a transmission bottleneck, which affects the computing efficiency and poses a great obstacle to building an efficient LPN solver based on heuristic algorithms.

[0004] The storage-computing integrated technology can store data in memory units for direct calculation, which can greatly reduce memory access overhead and efficiently implement intensive computing, effectively breaking through the bottleneck of data transmission between computing modules and memory modules. As a new type of non-volatile storage device, memristor (RRAM) has the advantages of being reprogrammable and having a high number of programmable times, and is well compatible with commercial CMOS (complementary metal oxide semiconductor) processes.

[0005] Therefore, considering the characteristics of heuristic algorithms for solving LPN problems, it is urgent to design an RRAM storage-computing integrated circuit that can not only realize simple Boolean operations but also avoid transmission bottlenecks. Summary of the invention

[0006] In view of the above-mentioned deficiencies, the main purpose of the present invention is to provide a storage-computation integrated circuit based on a memristor.

[0007] In order to achieve the above-mentioned purpose, the present invention provides a storage-computation integrated operation circuit based on a memristor, comprising an input module, a plurality of memristor sub-arrays, a plurality of address selection modules, a plurality of memristor resistance reading and writing modules, a plurality of potential holding circuit modules, a plurality of parity detection circuit modules, and an XOR tree module; wherein each memristor sub-array is connected to an address selection module, a memristor resistance reading and writing module, and a potential holding circuit module, each potential holding circuit module is connected to a parity detection circuit module, and each parity detection circuit module is connected to an XOR tree module; in each memristor sub-array, each AND operation unit in each row outputs a current and accumulates it after completing the AND calculation to obtain the accumulated current of each row; and the accumulated current is input into the parity detection circuit module via the potential holding circuit module, and after determining the parity of the number of flip-flops in the parity detection circuit module, an initial XOR operation value is output.

[0008] In the above scheme, the potential holding circuit module includes a first PMOS tube and a second PMOS tube; wherein the potential holding circuit module is connected to the memristor subarray on a side of the first PMOS tube away from the second PMOS tube; and the potential holding circuit module is connected to the parity detection circuit module on a side of the second PMOS tube away from the first PMOS tube.

[0009] In the above scheme, the parity detection circuit module includes a capacitor, a first NMOS tube and a second NMOS tube; wherein the first NMOS tube and the second NMOS tube constitute a reset circuit of the parity detection circuit module to discharge the capacitor; the global reset signal Rst1 controls the first NMOS tube; and the local reset signal Rst2 controls the second NMOS tube.

[0010] In the above scheme, the parity detection circuit module also includes a threshold judgment module, a trigger, a first inverter, a second inverter and a third inverter; wherein, when the accumulated current flows through the parity detection circuit module to charge the capacitor, the voltage value of the capacitor increases; when the voltage value of the capacitor is less than or equal to the preset threshold, the threshold judgment module continuously outputs a high level.

[0011] In the above scheme, when the voltage value of the capacitor is greater than the preset threshold value, the threshold judgment module outputs a low level; the low level output by the threshold judgment module is output as a high level after passing through the first inverter, the second inverter and the third inverter in sequence, and respectively causes the trigger to flip and the capacitor to discharge; and the voltage value of the capacitor is reset to zero, and the threshold judgment module outputs a reset high level.

[0012] In the above scheme, the initial value of the trigger is set, the parity of the flip-flop number is determined by outputting 0 or 1 of the trigger, and the initial XOR operation value is output.

[0013] In the above scheme, the threshold judgment module includes a third PMOS transistor, a third NMOS transistor, a fourth NMOS transistor and a fifth NMOS transistor; wherein the preset threshold is determined by a circuit composed of the third NMOS transistor, the fourth NMOS transistor and the fifth NMOS transistor.

[0014] In the above scheme, the XOR tree module includes a first XOR gate, a second XOR gate and a third XOR gate; wherein the third XOR gate is connected to the first XOR gate and the second XOR gate respectively; the first XOR gate, the second XOR gate and the third XOR gate perform secondary XOR on the initial XOR operation value output by each parity detection circuit module to obtain a target XOR operation value.

[0015] The technical solution of the embodiment of the present invention has at least the following beneficial effects:

[0016] (1) The operation circuit directly maps the 0 or 1 data of the large public matrix of LPN to the resistance state of the memristor, and directly completes the calculation in the storage and calculation unit with the memristor as the core. Data does not need to be transmitted between the calculation module and the memory module, breaking through the data transmission bottleneck and eliminating the memory access overhead. At the same time, the array adopts parallel calculation and parallel output, which can efficiently realize intensive calculations. When the memristor is in a high-resistance state, under the action of the folded common-gate amplifier structure, the output tube enters the cutoff region, reducing the leakage current output from the calculation unit, increasing the equivalent impedance of the high resistance value of the memristor, and improving the calculation accuracy.

[0017] (2) The circuit of the potential holding circuit module makes the voltage value of the output node of each row of the memristor subarray fluctuate less, reducing the impact of the accumulated current on the capacitor charging. This module can not only improve the calculation accuracy, but also does not require the use of a too complex circuit structure.

[0018] (3) The parity detection circuit based on flip-flop flipping is simple and reliable in structure and consumes less computation, which is very suitable for the operation requirements of large arrays and small bits. Not only does the calculation process make full use of the advantage of the memristor array in efficiently realizing multiplication and accumulation operations, but it also consumes less computing resources in the subsequent conversion process, which perfectly adapts to the parity operation requirements.

[0019] (4) The memristor storage and computing array is split and optimized into multiple multi-input and multi-output memristor storage and computing sub-arrays, and then the calculation results of the multiple sub-arrays are subjected to secondary XOR through the XOR logic tree to obtain the final XOR output. This partitioning scheme can solve the problem that the accuracy of the accumulated current decreases as the number of memristor storage and computing units involved in the calculation increases, and improve the overall calculation accuracy. At the same time, through this partitioning method, each sub-array has high repeatability. When larger-scale calculations need to be performed, it can be achieved by simply increasing the number of sub-arrays and the number of layers of the XOR tree. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 The overall architecture of a memristor-based storage-computation integrated circuit according to an embodiment of the present invention is schematically shown;

[0021] Figure 2 A schematic diagram of a structure of an AND operation unit circuit according to an embodiment of the present invention is shown;

[0022] Figure 3 A circuit structure diagram of a potential holding circuit module according to an embodiment of the present invention is schematically shown;

[0023] Figure 4 The circuit structure diagram of the parity detection circuit module according to the embodiment of the present invention is schematically shown;

[0024] Figure 5 The circuit structure diagram of the threshold judgment module according to the embodiment of the present invention is schematically shown;

[0025] Figure 6 The circuit structure diagram of the XOR tree module according to an embodiment of the present invention is schematically shown. DETAILED DESCRIPTION

[0026] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0027] Figure 1 The overall architecture diagram of a memristor-based storage-computation-in-one computing circuit according to an embodiment of the present invention is schematically shown.

[0028] Please refer to Figure 1 An embodiment of the present invention provides a storage-computation integrated circuit based on a memristor, comprising: an input module 100, a plurality of memristor sub-arrays 101, a plurality of address selection modules 102, a plurality of memristor resistance reading and writing modules 103, a plurality of potential holding circuit modules 104, a plurality of parity detection circuit modules 105, and an XOR tree module 106; wherein each memristor sub-array 101 is connected to an address selection module 102, a memristor resistance reading and writing module 103, and a potential holding circuit module 104, each potential holding circuit module 104 is connected to a parity detection circuit module 105, and each parity detection circuit module 105 is connected to an XOR tree module 106.

[0029] For example, Figure 1As shown, the operation circuit includes an input module 100, and four memristor sub-arrays 101 are connected to the input module 100. Each memristor sub-array 101 is connected to an address selection module 102, a memristor resistance reading and writing module 103 and a potential holding circuit module 104. Each potential holding circuit module 104 is connected to each parity detection circuit module 105. The four parity detection circuit modules 105 are all connected to the same XOR tree module 106.

[0030] In an embodiment of the present invention, the address selection module 102 and the memristor resistance reading and writing module 103 are used to complete the weight reading and writing of the memristor; the potential holding circuit module 104 is used to improve the accuracy of the accumulated current; the memristor array is partitioned and reconstructed into four memristor sub-arrays 101, thereby improving the calculation accuracy of the memristor array.

[0031] Figure 2 The structure diagram of the AND operation unit circuit according to an embodiment of the present invention is schematically shown.

[0032] In the embodiment of the present invention, in each memristor sub-array 101, each AND operation unit in each row outputs current after completing AND calculation and accumulates the current to obtain an accumulated current of each row.

[0033] For example, Figure 2 As shown, each AND operation unit mainly includes a memristor 201, a sixth NMOS transistor 204, a seventh NMOS transistor 205, a third PMOS transistor 203, a fourth PMOS transistor 206 and a fifth PMOS transistor 207, wherein the AND operation unit is also connected to a fourth inverter 202.

[0034] In an embodiment of the present invention, in each AND operation unit, as Figure 2 As shown, the low resistance and high resistance of the memristor 201 represent the element a ij The 1 and 0 of the PMOS tube are turned on and off by the element s j The 0 and 1 control.

[0035] Further, in an embodiment of the present invention, the computational paradigm of the binary matrix-vector product operation can be expressed as , the matrix form is ,in Represents the AND operation between two elements. Represents the XOR operation between two elements. The input voltage value of the memristor array represents the vector S, and the output voltage value of the XOR tree module represents the result vector y, and the high level represents logic 1 and the low level represents logic 0. At the same time, the elements of the large matrix A and the elements of the vector b are mapped to the resistance and conductance states of the memristor. If a ij (bi )=1, the state of the memristor is low resistance and high conductance; if a ij (b i )=0, the state of the memristor is high resistance and low conductance.

[0036] Furthermore, whether the PMOS tube outputs unit current represents a ij and j The result of the AND operation between two elements is 0 or 1; that is, if the PMOS tube outputs unit current, it means that the result of the AND operation between the two elements is 1, and if the PMOS tube does not output unit current, it means that the result of the AND operation between the two elements is 0.

[0037] Further, the sixth NMOS transistor 204 and the seventh NMOS transistor 205 form a current source, and the current output by the current source flows through the memristor 201. When the memristor 201 is in a high-resistance state and the third PMOS transistor 203 is turned on, the voltage across the memristor 201 is high, causing the source voltage of the fourth PMOS transistor 206 to be pulled down, entering the cut-off region, and not outputting unit current. This structure can reduce the leakage current caused when the memristor is in a high-resistance state and the third PMOS transistor 203 is turned on, causing the fourth PMOS transistor 206 to enter the cut-off region, increasing the equivalent impedance of the high resistance value of the memristor, and improving the calculation accuracy.

[0038] Through the above, that is, in this embodiment, in a memristor subarray 101, each memristor 201 and the voltage input by the input module 100 complete the AND calculation between two elements and generate an output current. The memristor subarray 101 accumulates the output currents of all the operation units in a row and then inputs them into the parity detection circuit module 105 through the potential holding circuit module 104, and finally obtains the initial XOR operation value.

[0039] Through the embodiment of the present invention, the operation circuit directly maps the data of 0 or 1 of the large public matrix of LPN to the resistance state of the memristor, and directly completes the calculation in the storage and calculation unit with the memristor as the core. Data does not need to be transmitted between the calculation module and the memory module, breaking through the data transmission bottleneck and eliminating the memory access overhead. At the same time, the array adopts parallel calculation and parallel output, which can efficiently realize intensive calculation. When the memristor is in a high-resistance state and the third PMOS transistor 203 is turned on, under the action of the sixth NMOS transistor 204, the seventh NMOS transistor 205, the fourth PMOS transistor 206 and the fifth PMOS transistor 207 of the folded common-gate amplifier structure, the output tube enters the cut-off region, reducing the leakage current output by the calculation unit, increasing the equivalent impedance of the high resistance value of the memristor, and improving the calculation accuracy.

[0040] In the embodiment of the present invention, the accumulated current is input to the parity detection circuit module 105 via the potential holding circuit module 104, and after determining the parity of the flip-flop 408 flip-flop number in the parity detection circuit module 105, an initial XOR operation value is output.

[0041] In the embodiment of the present invention, the memristor sub-array 101, the parity detection circuit module 105 and the XOR tree module 106 are core modules of the operation circuit, and both the AND operation and the XOR operation are completed through these three core modules.

[0042] Figure 3 The circuit structure diagram of the potential holding circuit module according to the embodiment of the present invention is schematically shown.

[0043] In an embodiment of the present invention, the potential holding circuit module 104 includes a first PMOS tube 301 and a second PMOS tube 302; wherein the potential holding circuit module 104 is connected to the memristor sub-array 101 on a side of the first PMOS tube 301 away from the second PMOS tube 302; and the potential holding circuit module 104 is connected to the parity detection circuit module 105 on a side of the second PMOS tube 302 away from the first PMOS tube 301.

[0044] like Figure 3 As shown, the potential holding circuit module 104 includes a first PMOS tube 301 and a second PMOS tube 302. The potential holding circuit module 104 is connected to an output node of any row outputting accumulated current in the memristor subarray 101 at a side of the first PMOS tube 301 away from the second PMOS tube 302; the potential holding circuit module 104 is connected to a parity detection circuit module 105 at a side of the second PMOS tube 302 away from the first PMOS tube 301. When any row of accumulated current is input to the parity detection circuit module 105 to charge the capacitor, the potential holding circuit module 104 makes the voltage fluctuation of the output node of the memristor subarray 101 outputting the accumulated current smaller, reduces the influence of the accumulated current on the charging of the capacitor, and improves the calculation accuracy.

[0045] Through the embodiments of the present invention, the circuit of the potential holding circuit module makes the voltage value of the output node of each row of the memristor subarray fluctuate less, reducing the influence of the accumulated current on the capacitor charging. The module can not only improve the calculation accuracy, but also does not need to use a too complicated circuit structure.

[0046] Figure 4 The circuit structure diagram of the parity detection circuit module according to the embodiment of the present invention is schematically shown.

[0047] In the embodiment of the present invention, the parity detection circuit module 105 includes a capacitor 402, a first NMOS transistor 401, and a second NMOS transistor 403; wherein the first NMOS transistor 401 and the second NMOS transistor 403 constitute a reset circuit of the parity detection circuit module 105 to discharge the capacitor 402. The global reset signal Rst1 controls the first NMOS transistor 401; the local reset signal Rst2 controls the second NMOS transistor 403.

[0048] Furthermore, the parity detection circuit module 105 also includes a threshold judgment module 404, a trigger 408, a first inverter 405, a second inverter 406 and a third inverter 407; wherein, when the accumulated current flows through the parity detection circuit module 105 to charge the capacitor 402, the voltage value of the capacitor 402 increases; when the voltage value of the capacitor 402 is less than or equal to the preset threshold, the threshold judgment module 404 continues to output a high level.

[0049] Furthermore, when the voltage value of capacitor 402 is greater than a preset threshold value, the threshold judgment module 404 outputs a low level; the low level output by the threshold judgment module 404 is output as a high level after passing through the first inverter 405, the second inverter 406 and the third inverter 407 in sequence, and respectively causes the trigger 408 to flip and the capacitor 402 to discharge; and the voltage value of the capacitor 402 is reset to zero, and the threshold judgment module 404 outputs a reset high level.

[0050] Further, the initial value of the trigger 408 is set, and the parity of the flip-flop 408 flip-flop 408 is determined by outputting 0 or 1, and an initial XOR operation value is output.

[0051] For example, Figure 4 As shown, the parity detection circuit module 105 includes a capacitor 402, a first NMOS transistor 401, a second NMOS transistor 403, and a threshold judgment module 404, a trigger 408, a first inverter 405, a second inverter 406, and a third inverter 407. The first NMOS transistor 401 and the second NMOS transistor 403 form a reset circuit to discharge the capacitor 402, and the global reset signal Rst1 controls the first NMOS transistor 401; the local reset signal Rst2 controls the second NMOS transistor 403.

[0052] Furthermore, when the accumulated current charges the capacitor 402, the voltage V charge The value increases, and the threshold judgment module 404 also continues to output a high level. charge Once the value exceeds the threshold V thWhen the output of the threshold judgment module 404 is low level, the output low level is output as high level after passing through the first inverter 405, the second inverter 406 and the third inverter 407 in sequence, and the trigger 408 is flipped and the capacitor 402 is discharged, and the voltage V charge The value is reset to 0, and the output of the threshold determination module 404 is reset to a high level.

[0053] Further, the above process is repeated until the global reset signal Rst1 controls the first NMOS tube 401 to complete the global reset. In one working cycle, after passing through the first inverter 405, the second inverter 406 and the third inverter 407 in sequence, the output is high level, and the trigger 408 is flipped and the capacitor 402 is discharged respectively. The number of times the output of the threshold judgment module 404 is reset to a high level is equal to the Hamming weight of the accumulated current, that is, the number of flips of the trigger 408 is equal to the Hamming weight of the accumulated current. Therefore, it is only necessary to set the initial value of the trigger, and the output of the trigger 408 0 or 1 represents the parity of the flip number of the trigger. In this way, the final output of the trigger 408 is the initial XOR operation value.

[0054] Through the embodiments of the present invention, the parity detection circuit based on flip-flop can convert the accumulated current value into an XOR operation value. The accumulated current is fed into the capacitor for charging. Under the cooperation of the reset circuit and the threshold judgment module, the third inverter generates a high-level pulse with the same number of accumulated unit currents, and the high-level pulse controls the flip-flop to flip. Through the above process, the flip-flop flip times are the same as the accumulated unit current number. It is only necessary to set the initial value of the trigger, and the result of the final output of the trigger is the initial XOR operation value.

[0055] That is, the conversion of the accumulated current value into an XOR operation value is essentially equivalent to determining whether the number of accumulated unit currents is an odd number or an even number. Therefore, it is only necessary to determine the parity of the Hamming weight of the accumulated current to obtain the initial XOR operation value.

[0056] Through the embodiments of the present invention, the parity detection circuit based on flip-flop flipping is simple and reliable in structure and has low computational consumption, which is very suitable for the operation requirements of large arrays and small bits. Not only does the calculation process of the operation fully utilize the advantage of the memristor array in efficiently realizing multiplication and accumulation operations, but also consumes less computing resources in the subsequent conversion process, perfectly adapting to the parity operation requirements.

[0057] Figure 5 The circuit structure diagram of the threshold judgment module according to the embodiment of the present invention is schematically shown.

[0058] In an embodiment of the present invention, the threshold judgment module 404 includes a third PMOS transistor 501, a third NMOS transistor 502, a fourth NMOS transistor 503 and a fifth NMOS transistor 504; wherein the preset threshold is determined by a circuit composed of the third NMOS transistor 502, the fourth NMOS transistor 503 and the fifth NMOS transistor 504.

[0059] Specifically, if Figure 5 As shown, the circuit of the threshold judgment module mainly includes a third PMOS transistor 501, a third NMOS transistor 502, a fourth NMOS transistor 503 and a fifth NMOS transistor 504. When the capacitor voltage is not higher than the threshold, the threshold judgment module always maintains a high level; in addition, the circuit composed of the third NMOS transistor 502, the fourth NMOS transistor 503 and the fifth NMOS transistor 504 can determine the preset threshold, so that the threshold judgment module will output a low level only when the input needs to increase to a higher value.

[0060] According to the embodiment of the present invention, the circuit structure of the threshold judgment module does not require an external input of a threshold voltage, and consumes less hardware resources than a traditional comparator.

[0061] Figure 6 The circuit structure diagram of the XOR tree module according to an embodiment of the present invention is schematically shown.

[0062] In an embodiment of the present invention, the XOR tree module 106 includes a first XOR gate 601, a second XOR gate 602 and a third XOR gate 603; wherein the third XOR gate 603 is connected to the first XOR gate 601 and the second XOR gate 602 respectively; the first XOR gate 601, the second XOR gate 602 and the third XOR gate 603 perform a secondary XOR on the initial XOR operation value output by each parity detection circuit module 105 to obtain a target XOR operation value.

[0063] Specifically, if Figure 6 As shown, the XOR tree module 106 mainly includes three XOR gates, namely the first XOR gate 601, the second XOR gate 602 and the third XOR gate 603. This circuit can perform a secondary XOR on the initial XOR results output by the parity detection circuit module 105 of the four memristor sub-arrays 101, thereby obtaining a target XOR operation value. At the same time, this method consumes very little hardware resources, and can obtain better performance in terms of power consumption and other aspects.

[0064] Through the embodiments of the present invention, the memristor storage and computing array is split and optimized into multiple multi-input and multi-output memristor storage and computing sub-arrays, and then the calculation results of the multiple sub-arrays are subjected to secondary XOR through an XOR logic tree to obtain the final XOR output. This partitioning scheme can solve the problem that the accuracy of the accumulated current decreases as the number of memristor storage and computing units involved in the calculation increases, and improve the overall calculation accuracy. At the same time, through this partitioning method, each sub-array has a high repeatability. When it is necessary to perform larger-scale calculations, it can be achieved by simply increasing the number of sub-arrays and the number of layers of the XOR tree.

[0065] The above specific embodiments further illustrate the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A memristor-based storage and computing integrated circuit, characterized in that: It comprises an input module (100), a plurality of memristor sub-arrays (101), a plurality of address gating modules (102), a plurality of memristor resistance reading and writing modules (103), a plurality of potential holding circuit modules (104), a plurality of parity detection circuit modules (105), and an XOR tree module (106); Each of the memristor sub-arrays (101) is connected to an address gating module (102), a memristor resistance reading and writing module (103) and a potential holding circuit module (104); each of the potential holding circuit modules (104) is connected to the parity detection circuit module (105); and each of the parity detection circuit modules (105) is connected to an XOR tree module (106); In each of the memristor sub-arrays (101), each AND operation unit in each row outputs current after completing AND calculation and accumulates the current to obtain an accumulated current of each row; and The accumulated current is input into the parity detection circuit module (105) via the potential holding circuit module (104), and after determining the parity of the flip-flop (408) flip-flop number in the parity detection circuit module (105), an initial XOR operation value is output.

2. The memristor-based integrated storage and computing circuit according to claim 1, characterized in that: The potential holding circuit module (104) comprises a first PMOS tube (301) and a second PMOS tube (302); Wherein, the potential holding circuit module (104) is connected to the memristor sub-array (101) at a side of the first PMOS tube (301) away from the second PMOS tube (302); and The potential holding circuit module (104) is connected to the parity detection circuit module (105) on a side of the second PMOS tube (302) away from the first PMOS tube (301).

3. The memristor-based integrated storage and computing circuit according to claim 1 or 2, characterized in that: The parity detection circuit module (105) comprises a capacitor (402), a first NMOS transistor (401) and a second NMOS transistor (403); The first NMOS transistor (401) and the second NMOS transistor (403) constitute a reset circuit of the parity detection circuit module (105) to discharge the capacitor (402); The global reset signal Rst1 controls the first NMOS tube (401); The local reset signal Rst2 controls the second NMOS tube (403).

4. The memristor-based integrated storage and computing circuit according to claim 3, characterized in that: The parity detection circuit module (105) further comprises a threshold determination module (404), a trigger (408), a first inverter (405), a second inverter (406) and a third inverter (407); When the accumulated current flows through the parity detection circuit module (105) to charge the capacitor (402), the voltage value of the capacitor (402) increases; when the voltage value of the capacitor (402) is less than or equal to a preset threshold, the threshold judgment module (404) continuously outputs a high level.

5. The memristor-based integrated storage and computing circuit according to claim 4, characterized in that: When the voltage value of the capacitor (402) is greater than a preset threshold, the threshold determination module (404) outputs a low level; The low level output by the threshold judgment module (404) is output as a high level after being sequentially passed through the first inverter (405), the second inverter (406) and the third inverter (407), and respectively causes the trigger (408) to flip and the capacitor (402) to discharge; and The voltage value of the capacitor (402) is reset to zero, and the threshold determination module (404) outputs a reset high level.

6. The memristor-based integrated storage and computing circuit according to claim 1 or 5, characterized in that: The initial value of the trigger (408) is set, the trigger (408) outputs 0 or 1 to determine the parity of the flip-flop (408) flip-flop number, and an initial XOR operation value is output.

7. The memristor-based integrated storage and computing circuit according to claim 4 or 5, characterized in that: The threshold determination module (404) comprises a third PMOS transistor (501), a third NMOS transistor (502), a fourth NMOS transistor (503) and a fifth NMOS transistor (504); The preset threshold is determined by a circuit composed of the third NMOS transistor (502), the fourth NMOS transistor (503) and the fifth NMOS transistor (504).

8. The memristor-based integrated storage and computing circuit according to claim 1, characterized in that: The XOR tree module (106) comprises a first XOR gate (601), a second XOR gate (602) and a third XOR gate (603); Wherein, the third XOR gate (603) is connected to the first XOR gate (601) and the second XOR gate (602) respectively; The first XOR gate (601), the second XOR gate (602) and the third XOR gate (603) perform secondary XOR on the initial XOR operation value output by each parity detection circuit module (105) to obtain a target XOR operation value.

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