Circuit implementation method for trigonometric function hardware acceleration

Abstract

The invention discloses a circuit implementation method for trigonometric function hardware acceleration, and the method comprises the steps: a single-precision floating point input preprocessing circuit which is used for preprocessing the single-precision floating point input x of a trigonometric function, and obtaining a corresponding subinterval of x; the coefficient table look-up circuit is used for performing two-stage table look-up according to the corresponding subinterval of x, and obtaining quadratic function coefficients C0, C1 and C2 of the corresponding subinterval from the coefficient storage table; the multiply-accumulate calculation circuit is used for carrying out base 4Booth compression coding on x and carrying out parallel calculation by adopting a three-level Wallace tree structure to obtain a fixed-point calculation result; and the post-processing circuit is used for rounding and normalizing the fixed-point calculation result to obtain a floating-point output value. The invention relates to the technical field of computer hardware acceleration, and solves the technical problem that a traditional trigonometric function calculation method is difficult to balance in the aspects of real-time performance, high precision and low resource occupation.

Description

Technical Field

[0001] The invention belongs to the technical field of computer hardware acceleration, and in particular is a circuit implementation method for trigonometric function hardware acceleration. Background Art

[0002] Trigonometric functions (such as sine, cosine, inverse tangent, etc.) are widely used in many fields and are the basic operations of digital computing. However, due to their nonlinear complexity, traditional software calculations are difficult to meet the real-time, high-precision and low-power requirements in embedded systems and resource-constrained hardware environments.

[0003] For example, although the table lookup method is simple to implement and has a fast calculation speed, when dealing with high-precision or large-scale calculation problems, the required table lookup items and table size will increase rapidly, which not only increases the storage burden, but also makes it difficult to dynamically adjust the calculation accuracy. In addition, the table lookup method cannot effectively handle input values ​​that exceed the preset range, and usually requires additional logic to support such situations. The accuracy of the CORDIC algorithm is limited by the number of iterations. For high-precision calculation requirements, more iterations are required, resulting in larger delays. At the same time, the fixed-point calculations and shift operations involved in the CORDIC algorithm may introduce rounding errors, which will become a limiting factor in scenarios with high precision requirements. In the polynomial approximation method, when high-order polynomials are used, the computational complexity will increase significantly, which may lead to increased delays and resource consumption in hardware implementation, and the error distribution of the polynomial approximation method is difficult to control evenly, and the problem of reduced accuracy will occur in certain specific intervals. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art; to this end, the present invention proposes a circuit implementation method for hardware acceleration of trigonometric functions, which is used to solve the problem that traditional trigonometric function calculation methods are difficult to balance in terms of real-time performance, high precision and low resource occupancy.

[0005] To achieve the above object, a first aspect of the present invention provides a circuit implementation method for hardware acceleration of trigonometric functions, comprising:

[0006] Single-precision floating-point input preprocessing circuit, coefficient table lookup circuit, multiplication and accumulation calculation circuit and output post-processing circuit; wherein,

[0007] The single-precision floating-point input preprocessing circuit is used to preprocess the single-precision floating-point input x of the trigonometric function to obtain a corresponding subinterval of x;

[0008] The coefficient table lookup circuit is used to perform a two-level table lookup according to the corresponding sub-interval of x, and obtain the quadratic function coefficients C0, C1 and C2 of the corresponding sub-interval from the coefficient storage table; wherein the data in the coefficient storage table is stored in the SRAM of the chip;

[0009] The multiplication-accumulation calculation circuit is used to perform radix-4 Booth compression encoding on x and use a three-level Wallace tree structure to perform parallel calculation to obtain a fixed-point calculation result;

[0010] The post-processing circuit is used to perform rounding and normalization operations on the fixed-point calculation results to obtain floating-point output values.

[0011] Based on the above technical process, the present invention achieves a significant improvement in the accuracy and efficiency of trigonometric function calculations, while effectively reducing resource usage. Compared with the traditional software calculation method, the method of the present invention can quickly and accurately calculate the trigonometric function values ​​with its efficient five-stage pipeline structure and hardware module optimization, ensuring the real-time and smoothness of the system, and can complete the trigonometric function calculation task in a shorter time.

[0012] Furthermore, the preprocessing of the single-precision floating-point input x of the trigonometric function includes:

[0013] A1, divide the domain of trigonometric functions into several subintervals, and use the quadratic function y=C0+(C1+C2x)x to approximate it; where C0 is the constant term coefficient, C1 is the linear term coefficient, C2 is the quadratic term coefficient, x is the input independent variable, and y is the output dependent variable;

[0014] A2, divides the input floating-point independent variable x into an exponent part and a mantissa part, and obtains a corresponding subinterval of the independent variable x according to the exponent part and the mantissa part.

[0015] Furthermore, the domain of the trigonometric function is divided into several sub-intervals, including:

[0016] A1-1, divide the domain of the trigonometric function evenly into 512 initial subintervals to obtain several initial subintervals;

[0017] A1-2, evenly divide the first several initial sub-intervals and the last several initial sub-intervals to obtain several small intervals;

[0018] A1-3, mark the several small intervals and the remaining initial sub-intervals as several sub-intervals to obtain several sub-intervals.

[0019] Furthermore, the evenly dividing the first several initial sub-intervals and the last several initial sub-intervals includes:

[0020] The first several initial sub-intervals are further divided evenly with a width of 0.00001, and the next several initial sub-intervals are further divided evenly with a width of 0.001 to obtain several small intervals.

[0021] When the input is close to 0, the trigonometric function changes rapidly and requires more precise segmentation; when the input is close to π / 2 or 1, the curve is relatively flat and a wider interval is required. The segmentation strategy is further adjusted for special intervals to achieve better approximation effects, effectively reduce overall calculation errors, meet high-precision calculation requirements, and provide accurate calculation results.

[0022] Furthermore, obtaining a corresponding subinterval of the independent variable x according to the exponent part and the mantissa part includes:

[0023] A2-1, using the pre-designed interval division rule, obtain the large interval to which the independent variable x belongs according to the exponential part;

[0024] A2-2, using the pre-built small interval indexing mechanism, the large interval is further reduced to a small interval according to the mantissa part, a small interval index is obtained, and the small interval index is used to index the corresponding subinterval of the independent variable x.

[0025] Furthermore, the coefficient storage table is obtained by:

[0026] The quadratic function coefficients C0, C1 and C2 of several sub-intervals are calculated by using the minimum maximum error method, and the quadratic function coefficients of several sub-intervals are stored in a fixed-point format to obtain a coefficient storage table.

[0027] Furthermore, the circuit is implemented using a five-stage pipeline structure, wherein:

[0028] The first stage pipeline is used to complete the single-precision floating-point input preprocessing and table lookup operation to obtain coefficients C0, C1 and C2;

[0029] And, convert the input floating-point independent variable x into a fixed-point number x';

[0030] The second stage pipeline is used to obtain C2 and the fixed-point number x' of the first stage pipeline, calculate C2x' using Booth encoding technology and fixed-point multiplier, and obtain the calculation result of C2x';

[0031] The third-stage pipeline is used to obtain C1 and the fixed-point number x' of the first-stage pipeline, and obtain the calculation result of C2x' of the second-stage pipeline, and use the Wallace tree structure to perform cumulative calculation to obtain the calculation result of (C1+C2x')x';

[0032] The fourth stage pipeline is used to obtain C0 of the first stage pipeline, obtain the calculation result of (C1+C2x')x' of the third stage pipeline, use a high-precision fixed-point adder and a carry-save adder to perform calculations, and store the calculation results in a fixed-point format to obtain a fixed-point calculation result of C0+(C1+C2x')x';

[0033] The fifth stage pipeline is used to obtain the fixed-point calculation result of C0+(C1+C2x')x' of the fourth stage pipeline, and convert the fixed-point calculation result into a floating-point number to obtain a floating-point output value.

[0034] A five-stage pipeline structure is adopted, and the calculation process is divided into five stages: table lookup and floating-point to fixed-point conversion, multiplication calculation, accumulation calculation, final accumulation, and fixed-point to floating-point conversion. Each stage of the pipeline operates independently and is executed in parallel, which greatly improves the calculation speed and allows multiple calculation tasks to be performed in parallel, making full use of hardware resources and reducing calculation time.

[0035] Furthermore, converting the fixed-point calculation result into a floating-point number includes:

[0036] B1, performs a fixed-point shift operation on the fixed-point calculation result of C0+(C1+C2x)x of the fourth-stage pipeline, and converts the fixed-point calculation result into a format in which the highest bit is 1 and the decimal point is after the highest bit;

[0037] B2, remove the highest bit of the fixed-point calculation result to obtain the converted floating-point mantissa;

[0038] B3, calculating the number of shift bits in the shift operation, and subtracting the number of shift bits from the fixed offset value of the floating-point exponent to obtain the floating-point exponent; wherein the fixed offset value of the floating-point exponent refers to a fixed value defined under the IEEE754 standard, which is 127;

[0039] B4, marking the sign bit of the fixed-point calculation result as a floating-point sign bit, and combining the floating-point sign bit, the floating-point mantissa, and the floating-point exponent to obtain a converted floating-point number.

[0040] Further, the single-precision floating-point input preprocessing circuit and the coefficient table lookup circuit are used to execute a first-stage pipeline;

[0041] The multiplication-accumulation calculation circuit is used to execute the second to fourth stage pipeline;

[0042] The post-processing circuit is used to execute the fifth stage pipeline.

[0043] In the multiplication-accumulation calculation circuit, the multiplier uses Booth coding to reduce the number of operations, introduces and incorporates Wallace tree to parallelize partial products to improve multiplication efficiency, and uses a fixed-point adder with a bit width of 34 bits to support high-precision calculations, and uses a carry-save adder (CSA) to reduce latency. These hardware module optimization measures effectively reduce computational complexity, reduce hardware resource usage, improve computational efficiency, and ensure computational accuracy.

[0044] Compared with the prior art, the present invention has the following beneficial effects:

[0045] Compared with the table lookup method, the present invention avoids the large amount of storage space required for large-scale table lookup by storing the coefficients in a fixed-point format in a small space. This has obvious advantages when processing high-precision or large-scale calculations, reduces the storage burden, and is more suitable for resource-constrained environments.

[0046] Compared with the polynomial approximation method, the piecewise quadratic function fitting model adopted in the present invention, combined with hardware optimization measures such as Booth coding and Wallace tree structure, effectively reduces the complexity of multiplication and accumulation calculations, avoids the high computational complexity and hardware resource consumption problems caused by high-order polynomials, and reduces the delay of hardware implementation;

[0047] Compared with the CORDIC algorithm, the present invention avoids the delay problem caused by the increase in the number of iterations while ensuring higher accuracy through reasonable interval division and coefficient calculation methods, achieving a better balance between accuracy and delay, and is more suitable for application scenarios that require both accuracy and real-time performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0049] Figure 1 A schematic diagram of the operation of a single-precision floating-point input preprocessing circuit and floating-point to fixed-point conversion in the circuit design provided by the present invention;

[0050] Figure 2 A schematic diagram of the operation of a multiplication-accumulation calculation circuit in the circuit design provided by the present invention;

[0051] Figure 3 A schematic diagram of the operation of a post-processing circuit in the circuit design provided by the present invention;

[0052] Figure 4 The error diagram of the sine function result obtained by the method of the present invention is provided by the present invention;

[0053] Figure 5 The inverse tangent function result error diagram obtained by the method of the present invention is provided by the present invention;

[0054] Figure 6 A schematic flow chart of a circuit implementation method for hardware acceleration of trigonometric functions provided by the present invention. DETAILED DESCRIPTION

[0055] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0056] See also Figure 6 The first aspect of the present invention provides a circuit implementation method for hardware acceleration of trigonometric functions, including:

[0057] Single-precision floating-point input preprocessing circuit, coefficient table lookup circuit, multiplication and accumulation calculation circuit and output post-processing circuit; wherein,

[0058] The single-precision floating-point input preprocessing circuit is used to preprocess the single-precision floating-point input x of the trigonometric function to obtain a corresponding subinterval of x;

[0059] The coefficient table lookup circuit is used to perform a two-level table lookup according to the corresponding sub-interval of x, and obtain the quadratic function coefficients C0, C1 and C2 of the corresponding sub-interval from the coefficient storage table; wherein the data in the coefficient storage table is stored in the SRAM of the chip;

[0060] The multiplication-accumulation calculation circuit is used to perform radix-4 Booth compression encoding on x and use a three-level Wallace tree structure to perform parallel calculation to obtain a fixed-point calculation result;

[0061] The post-processing circuit is used to perform rounding and normalization operations on the fixed-point calculation results to obtain floating-point output values.

[0062] Trigonometric functions (such as sine, cosine, and inverse tangent) are mathematically nonlinear functions, and the cost of direct calculation is high. The present invention divides its domain into multiple small intervals, and each interval is approximately represented by a fitted quadratic function: y=C0+(C1-C2·x)·x; where C0 is the constant term coefficient, C1 is the linear term coefficient, C2 is the quadratic term coefficient, and x is the input variable, which participates in the calculation after floating point to fixed point conversion.

[0063] In this embodiment, the C0, C1, and C2 coefficients of each interval are determined by the following process:

[0064] First, according to the changing characteristics of the function curve, the domain is divided into several sub-intervals:

[0065] For the sine and cosine functions, the domain is Divided into 512 intervals, each interval width is 0.001953125; for the inverse tangent function, the domain is [0,1], also divided into 512 intervals;

[0066] Then the first several initial subintervals (i.e., the subintervals where the input is close to 0) are further divided evenly with a width of 0.00001, and the last several initial subintervals (i.e., for the sine and cosine functions, the subintervals where the input is close to When the input of the inverse tangent function is close to 1, the subintervals are evenly divided with a width of 0.001 to obtain several small intervals;

[0067] Marking a number of small intervals and the remaining initial subintervals (i.e., excluding the first several initial subintervals and the last several initial subintervals) as a number of subintervals to obtain a number of subintervals;

[0068] Next, the coefficients are calculated using the minimum and maximum error method:

[0069] Construct an error function to measure the sum of squares of deviations between the sampling value and the fitting function, and find the minimum parameter value of the error function. In mathematical derivation, assume that there are n sampling points in the interval, and define the error function as: Among them, y i = sin(x i ) is the actual function value;

[0070] Then, the partial derivative of the parameters of the error function is calculated and set to zero to solve the system of equations to obtain a set of coefficients C0, C1, and C2 corresponding to the fitted quadratic function in each subinterval; the coefficients are then stored in a fixed-point format to obtain a coefficient storage table corresponding to each coefficient to reduce storage space and reading time.

[0071] Next, the hardware design adopts a five-stage pipeline structure to ensure efficient parallel computing:

[0072] The first stage of the pipeline performs table lookup and floating point to fixed point conversion:

[0073] The input floating-point independent variable x is divided into an exponent part and a mantissa part, and then the large interval to which the independent variable x belongs is obtained according to the exponent part using the pre-designed interval partitioning rule, and the large interval is further reduced to a small interval according to the mantissa part using the pre-built small interval indexing mechanism, and the small interval index is obtained, and the corresponding subinterval of the independent variable x is indexed using the small interval;

[0074] Specifically, first extract the 8-bit exponent part from the input floating-point number; then, according to the value of the exponent, map the independent variable x to the corresponding large interval through the pre-designed interval division rule. For example, when the exponent part is set to be greater than a certain threshold (such as 150), it means that the independent variable x is large and belongs to the high interval; if the exponent is less than 150, it means that the independent variable x is small and belongs to the low interval; then, use the pre-built small interval index mechanism to carry out subsequent operations, and assign the mantissa to a fixed number of small intervals according to the value range of the mantissa. For example, for a 23-bit mantissa value, assuming it is mapped to 256 small intervals, the mantissa value can be used to determine the specific small interval where the independent variable x is located, and then the small interval index can be used to determine the corresponding sub-interval of the independent variable x;

[0075] Next, the quadratic function coefficients C0, C1 and C2 of the corresponding subinterval are obtained from the coefficient storage table using the table lookup method;

[0076] Then, the input floating-point independent variable x is converted to a fixed-point number x' to adapt to subsequent hardware operations;

[0077] The second-stage pipeline performs multiplication calculation: obtain C2 and the fixed-point number x' of the first-stage pipeline, use the fixed-point multiplier to calculate, retain the high bits of the result to improve the accuracy, and introduce Booth coding to optimize the generation of partial products, reduce the complexity of the multiplier, and obtain the calculation result of C2x';

[0078] The third-stage pipeline performs cumulative calculations: obtains C1 and the fixed-point number x' of the first-stage pipeline, and obtains the calculation result of C2x' of the second-stage pipeline, and uses the Wallace tree structure to perform cumulative calculations to further improve the operation speed, obtains the calculation result of (C1+C2x')x', and directly passes the calculation result to the next stage to reduce the register read and write delay;

[0079] The fourth-stage pipeline performs the final accumulation: obtain C0 of the first-stage pipeline, obtain the calculation result of (C1+C2x')x' of the third-stage pipeline, use the high-precision fixed-point adder and the carry-save adder to perform the calculation, and store the calculation result in a fixed-point format to obtain the fixed-point calculation result of C0+(C1+C2x')x';

[0080] The fifth-stage pipeline performs fixed-point to floating-point conversion: converting the fixed-point calculation result into a floating-point output, using a priority encoder to determine the most significant bit, adjusting the exponent, and generating a floating-point number that complies with the IEEE754 standard through shifting and truncation processing to obtain a floating-point output value.

[0081] like Figure 1As shown in the figure, the single-precision floating-point input preprocessing circuit and coefficient table lookup circuit play a key role in data preprocessing and coefficient acquisition in the entire trigonometric function hardware acceleration process. Its function is to convert the input floating-point number into a fixed-point number format suitable for subsequent calculations, and synchronously obtain the corresponding quadratic function coefficients. The specific operation process is as follows:

[0082] First, because the representation range of floating point is larger than that of fixed point, it is necessary to select the appropriate fixed-point format during conversion, that is, to determine the bit width of the fixed-point number, that is, to clarify how many bits the integer part and the decimal part occupy respectively, and to determine whether the sign bit is required to participate in the operation. For example, according to the specific requirements of trigonometric function calculations and the actual situation of hardware resources, the Q1.31 format can be selected, which contains 1 sign bit, 1 integer bit, and 31 decimal bits;

[0083] Then, the received floating-point number is decomposed into three parts according to the standard format, namely the sign bit, the exponent part and the mantissa part: Taking the common 32-bit IEEE754 standard floating-point number as an example, the highest bit (the 31st bit) is the sign bit, which is used to indicate the positive or negative of the number; the 8 bits from the 30th to the 23rd bit are the exponent part, which is used to determine the position of the decimal point; and the 23 bits from the 22nd bit to the lowest bit (the 0th bit) are the mantissa part, which contains the valid digital information;

[0084] Next, calculate the difference between the exponent of the floating-point number and the exponent specified by the selected fixed-point format. This difference is the number of bits that need to be shifted in the mantissa. This is done to accurately adjust the significant digits of the floating-point number to the appropriate position of the fixed-point number to accommodate subsequent fixed-point calculations. For example, if the exponent of the floating-point number is large, then the mantissa needs to be shifted to the right by the corresponding number of bits so that the decimal point moves to the left to the appropriate position; conversely, if the exponent of the floating-point number is small, the mantissa can be shifted to the left;

[0085] Finally, the sign bit is combined with the mantissa after the shift operation to obtain the final fixed-point number. Rounding or truncation operations are usually involved in the merging conversion process because floating-point numbers have a higher representation range and conversion to fixed-point numbers may lose some precision in some cases.

[0086] At the same time, the table lookup circuit is used in parallel to perform floating-point table lookup operations: by using the interval information determined by the exponent and mantissa of the input floating-point number, the quadratic function coefficients C0, C1 and C2 required for subsequent multiplication and accumulation calculations are quickly searched and obtained in the table of pre-stored coefficients.

[0087] Figure 2This is the calculation flow chart of the multiplication and accumulation calculation circuit. Based on the characteristics of the quadratic function, the fitted quadratic function is designed as a two-level multiplication and accumulation structure at the hardware circuit level, decomposing the calculation process into multiplication and accumulation operations so that efficient algorithms can be used for subsequent optimization.

[0088] First, the Wallace Tree algorithm is used to perform multiplication and accumulation operations. The Wallace Tree algorithm is widely used in the computing field to implement multiplication calculations or parallel calculations of multiplication and addition. Its basic idea is to convert a series of multiplication operations into parallel addition and subtraction operations, thereby achieving highly parallelized multiplication and accumulation operations on hardware. In this way, multiple addition operations can be performed in parallel within one clock cycle, greatly improving computing efficiency.

[0089] To further improve the efficiency of multiplication and accumulation, Booth coding technology is introduced. Booth coding is a technology specifically used to optimize binary multiplication operations, and plays an important role in hardware multiplication optimization in the field of high-performance computing. Its core principle is to use different bit block states to represent the information of adjacent bits, and then encode the multiplier, so as to reduce the number of partial multiplications that actually need to be performed in the multiplier and reduce the computational complexity;

[0090] Specifically, in this embodiment, the binary number is divided into a plurality of bit blocks, each of which is composed of several consecutive bits. For signed Booth codes, additional sign bits are usually added at both ends to handle positive and negative numbers. For each bit block, a Booth code is generated according to its bit pattern, where the consecutive 00 states indicate no operation (equivalent to multiplication by 0), the 01 state indicates an addition operation, and the 10 state indicates a subtraction operation. The corresponding operation is performed according to the coding state, and this process is repeated for each bit block until all bit blocks are processed, which can effectively reduce the number of multiplier operations and improve the calculation speed.

[0091] The two-stage multiplication-accumulation operations are evenly distributed within three clock cycles to achieve efficient pipeline calculation.

[0092] In the first cycle, the Booth algorithm calculation based on the multiplicand is first completed to generate the partial product of the Wallace tree, and the calculation of the partial product of the three layers (l0, l1, l2) is realized at the same time. Finally, the calculated partial product is output to the carry save adder (CSA) 4-2 (4 inputs, 2 outputs) and the result is generated;

[0093] In the second cycle, the 34-bit full adder and the second multiplication-accumulation Booth and Wallace tree level partial product 4-2 compression calculation are implemented. In this cycle, the Booth coding and Wallace tree algorithm are further used to process the partial products, and the addition calculation is combined with the high-precision 34-bit full adder to gradually complete some calculation tasks in the two-level multiplication-accumulation, pushing the calculation process forward;

[0094] In the third cycle, the final calculation of the CSA4-2 adder and the 34-bit full adder is realized. Through the preparation of the first two cycles, the final accumulation calculation is completed in this cycle to obtain the final multiplication-accumulation result. It should be noted that the three-layer Wallace tree can calculate up to 16 partial products (pp0-pp15) and generate carry partial products (pp16) at the same time. However, since the maximum bit width of the multiplication of the present invention is 30 bits, only 15 partial products are needed to complete the operation. Therefore, pp15 is replaced by all zeros in this process to ensure the accuracy and efficiency of the calculation process.

[0095] Figure 3 It is a fixed-point floating-point normalization flow chart, which aims to convert the fixed-point calculation results obtained by two-stage multiplication and addition calculations into single-precision floating-point format output that conforms to the IEEE standard, that is, the fifth-stage pipeline. The specific operation steps are as follows:

[0096] First, perform a shift operation on the fixed-point calculation result to adjust its representation format so that the highest bit becomes 1 and the decimal point is located after the highest bit. Then, the fixed-point number is stripped of the highest 23 bits to obtain the converted floating-point mantissa. For example, if the original fixed-point number is [1010101010101010101010101010101010] (this is just an example, the actual bit width and value depend on the calculation result), it is shifted to [1.01010101010101010101010101010101010] (assuming that the decimal point is after the highest bit 1). At this time, the high 23 bits [0101010101010101010101010] are the floating-point mantissa part (hidden bits are not considered for the time being). This step is the basis for converting fixed-point numbers to floating-point numbers. The format adjustment enables the fixed-point number to match the mantissa representation of the floating-point number.

[0097] Next, calculate the number of bits of the shift operation in the previous step, and subtract it from the shift code of the floating-point exponent to obtain the final floating-point exponent. In the IEEE standard single-precision floating-point number, the exponent part is represented by a shift code. By calculating the number of shift bits, the size of the floating-point exponent can be determined to accurately represent the range of the value. For example, if the number of shift bits is 5 (indicating that the decimal point of the fixed-point number is moved 5 bits to the left), and the offset of the floating-point exponent shift code is 127 (the exponent offset of the IEEE754 standard single-precision floating-point number), the calculated floating-point exponent is 127+5=132 (converted to binary representation and filled to the exponent bit). This step ensures that the floating-point number can correctly reflect the magnitude of the original fixed-point number, and is one of the key links in achieving accurate conversion from fixed-point to floating-point;

[0098] The sign bit of the fixed-point number is directly used as the sign bit of the converted floating-point number. This simple and direct correspondence ensures the consistency of the positive and negative values ​​during the conversion process. For example, if the sign bit of the fixed-point number is 0, indicating a positive number, then the sign bit of the converted floating-point number is also 0; if the sign bit of the fixed-point number is 1, indicating a negative number, the sign bit of the floating-point number is also 1; this helps to maintain the logical consistency of data between different numerical representations and avoid incorrect calculation results due to sign conversion errors;

[0099] Finally, the determined sign bit, exponent part and mantissa part are merged according to the single-precision floating-point format of the IEEE standard to obtain the final floating-point number. In the merging process, the encoding specifications of the floating-point number must be strictly followed to ensure that the position and representation of each part are correct. For example, the 1-bit sign bit, the 8-bit exponent bit (such as the 8-bit representation of 132 calculated previously converted to binary) and the 23-bit mantissa bit (such as the previously determined [01010101010101010101010], and hidden bits and other situations are considered as needed) are combined in sequence to form a 32-bit floating-point number, completing the conversion from fixed-point numbers to IEEE standard floating-point numbers, so that the calculation results can be correctly identified and used in a wide range of computing environments.

[0100] During the entire conversion process, since the mantissa of the floating-point number has only 24 bits (1 hidden bit, 23 floating-point mantissa bits), and the decimal point of the fixed-point number in this embodiment is fixed to the highest bit, if the bit width of the fixed-point number is greater than 24 bits, some precision will inevitably be lost after the conversion process. Therefore, rounding or truncation operations are usually required to deal with the excess digits. According to the specific rounding strategy (such as rounding to the nearest even number, rounding to zero, etc.), the mantissa is adjusted to complete the conversion while ensuring a certain accuracy. A reasonable rounding strategy can effectively reduce the error accumulation caused by conversion and improve the reliability of the calculation results;

[0101] At the same time, in the fifth cycle of the pipeline execution cycle, the fixed-point to floating-point conversion is realized through the priority encoder and shift logic, which also involves floating-point normalization and rounding operations. This reflects the optimization of the conversion process in time and space by the hardware design, ensuring that the conversion operation can be completed efficiently and accurately, matching the rhythm of the entire computing pipeline, and improving the overall performance of the system.

[0102] See also Figure 4 - Figure 5 The second aspect of the present invention provides a performance evaluation comparison example of trigonometric function hardware acceleration, including:

[0103] The trigonometric function hardware instructions of the C2000 series processors used in the motor control field of TI (Texas Instruments) were selected as the comparison object, and the method of the present invention was compared horizontally in terms of calculation accuracy and efficiency. Under the same test environment, a large amount of test data was input into the two methods, and the respective calculation results were obtained. The error between the results and the standard results (the CPU calculation results under the x86 architecture were introduced as the standard results) was calculated to evaluate the calculation accuracy; at the same time, the number of clock cycles and system clock frequency required to execute the instructions were recorded, and the execution time was calculated, so as to evaluate the calculation efficiency. The comparison results are shown in the figure below. Figure 4 , Figure 5 As shown:

[0104] In terms of efficiency, the trigonometric function hardware instruction execution of C2000 requires 4 system clock cycles, the system clock frequency is 100MHz, and the execution time is 40ns; while the system clock frequency of the present invention is 400MHz clock, the instruction execution requires five cycles, and the execution time is 12.5ns, which reduces the time consumption by 68.75%, and the efficiency can be theoretically improved by up to 220%;

[0105] In terms of result accuracy, 81.35% of the results in the million-input level test are consistent with C2000, and the CPU calculation results under the x86 architecture are introduced as standard results for reference. Among the inconsistent data, the results of the present invention are closer to the standard results. Since the [0,1] interval represented by floating-point numbers is not uniformly distributed, the numbers near 0 are far more than the numbers near 1, so 50,000 valid input data within the definition domain are used for testing. Among them, Figure 4 The red curve in the figure is the error between the present invention and the standard result, and the blue curve is the error between TIC2000 and the standard result. It can be seen that in most cases the blue curve covers the red curve, that is, the error of TIC2000 is greater than that of the present invention design;

[0106] Due to the different design and implementation algorithms of both parties, the error of C2000 tends to be above the x-axis, while the error of the design floats on the left and right sides of the x-axis. Therefore, the blue curve in the second half of the curve only covers the part above the x-axis of the red curve. However, from the comparison of the absolute value of the test result errors, it can be obtained that 68.89% of the test results of the sine function instruction of the present invention are consistent with those of C2000, 27.46% of the test results are more accurate than C2000, and only 3.65% of the test results are less accurate than C200028x49c, which proves the correctness and effectiveness of the present invention.

[0107] exist Figure 5 In the comparison results of the inverse tangent function, the red curve is the error between the invention and the standard result, and the blue curve is the error between TIC2000 and the standard result. The input interval is the same as [0,1]. In most cases, the blue curve covers the red curve. Due to the different design and implementation algorithms of both parties, the TI error tends to be below the x-axis, while the error of the invention floats on both sides of the x-axis. Therefore, the blue curve in the second half of the curve only covers the part below the x-axis of the red curve. However, from the comparison of the absolute value of the test result errors, it can be obtained that 63.54% of the test results of the inverse tangent function instructions of the invention are consistent with C2000, 35.22% of the test results are more accurate than C2000, and only 1.24% of the test results are less accurate than C2000.

[0108] Part of the data in the above formula is calculated by removing the dimension and taking its numerical value. The formula is a formula closest to the actual situation obtained by software simulation of a large amount of collected data; the preset parameters and preset thresholds in the formula are set by technical personnel in this field according to actual conditions or obtained through simulation of a large amount of data.

[0109] Working principle of the present invention:

[0110] First, the domain of the trigonometric function is divided into several subintervals, and the quadratic function y=C0+(C1+C2x)x is used to approximate it. Among them, the sine and cosine functions are in [1,π / 2], and the inverse tangent function is in [0,1]. 512 initial subintervals are evenly divided first, and then the interval width is adjusted according to the change of the function curve. The fast-changing area is finely divided, and the division width is increased in the slowly changing area, so that the quadratic function fits better and the final subinterval is determined.

[0111] Then, the quadratic function coefficients C0, C1 and C2 of the several sub-intervals are calculated by using the minimum maximum error method, and the quadratic function coefficients of the several sub-intervals are stored in a fixed-point format to obtain three independent coefficient storage tables;

[0112] Finally, a five-stage pipeline structure is designed to calculate the output values ​​in several subintervals and obtain the trigonometric function calculation results. The first stage prepares the data, and the subsequent stages perform multiplication, accumulation, final accumulation, and fixed-point to floating-point conversion in turn. Hardware optimization (such as high-precision adders, etc.) and algorithms (Booth coding, Wallace tree algorithm) are used to improve speed and accuracy, make full use of hardware resources, and improve the real-time performance of the method.

[0113] The above embodiments are only used to illustrate the technical method of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical method of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical method of the present invention.

Claims

1. A circuit implementation method for trigonometric function hardware acceleration, characterized in that: include: Single-precision floating-point input preprocessing circuit, coefficient table lookup circuit, multiplication and accumulation calculation circuit and output post-processing circuit; wherein, The single-precision floating-point input preprocessing circuit is used to preprocess the single-precision floating-point input x of the trigonometric function to obtain a corresponding subinterval of x; The coefficient table lookup circuit is used to perform a two-level table lookup according to the corresponding sub-interval of x, and obtain the quadratic function coefficients C0, C1 and C2 of the corresponding sub-interval from the coefficient storage table; wherein the data in the coefficient storage table is stored in the SRAM of the chip; The multiplication-accumulation calculation circuit is used to perform radix-4 Booth compression encoding on x and use a three-level Wallace tree structure to perform parallel calculation to obtain a fixed-point calculation result; The post-processing circuit is used to perform rounding and normalization operations on the fixed-point calculation results to obtain floating-point output values.

2. The circuit implementation method for trigonometric function hardware acceleration according to claim 1, characterized in that: The preprocessing of the single-precision floating-point input x of the trigonometric function includes: A1, divide the domain of trigonometric functions into several subintervals, and use the quadratic function y=C0+(C1+C2x)x to approximate it; where C0 is the constant term coefficient, C1 is the linear term coefficient, C2 is the quadratic term coefficient, x is the input independent variable, and y is the output dependent variable; A2, divides the input floating-point independent variable x into an exponent part and a mantissa part, and obtains a corresponding subinterval of the independent variable x according to the exponent part and the mantissa part.

3. The circuit implementation method for trigonometric function hardware acceleration according to claim 2, characterized in that: The domain of the trigonometric function is divided into several sub-intervals, including: A1-1, divide the domain of the trigonometric function evenly into 512 initial subintervals to obtain several initial subintervals; A1-2, evenly divide the first several initial sub-intervals and the last several initial sub-intervals to obtain several small intervals; A1-3, mark the several small intervals and the remaining initial sub-intervals as several sub-intervals to obtain several sub-intervals.

4. The circuit implementation method for trigonometric function hardware acceleration according to claim 3, characterized in that: The evenly dividing the first several initial sub-intervals and the last several initial sub-intervals comprises: The first several initial sub-intervals are further divided evenly with a width of 0.00001, and the next several initial sub-intervals are further divided evenly with a width of 0.001 to obtain several small intervals.

5. The circuit implementation method for trigonometric function hardware acceleration according to claim 2, characterized in that: The step of obtaining the corresponding subinterval of the independent variable x according to the exponent part and the mantissa part includes: A2-1, using the pre-designed interval division rule, obtain the large interval to which the independent variable x belongs according to the exponential part; A2-2, using the pre-built small interval indexing mechanism, the large interval is further reduced to a small interval according to the mantissa part, a small interval index is obtained, and the small interval index is used to index the corresponding subinterval of the independent variable x.

6. The circuit implementation method for trigonometric function hardware acceleration according to claim 1, characterized in that: The method of obtaining the coefficient storage table includes: The quadratic function coefficients C0, C1 and C2 of several sub-intervals are calculated by using the minimum maximum error method, and the quadratic function coefficients of several sub-intervals are stored in a fixed-point format to obtain a coefficient storage table.

7. The circuit implementation method for trigonometric function hardware acceleration according to claim 1, characterized in that: The circuit is implemented using a five-stage pipeline structure, where: The first stage pipeline is used to complete the single-precision floating-point input preprocessing and table lookup operation to obtain coefficients C0, C1 and C2; And, convert the input floating-point independent variable x into a fixed-point number x'; The second stage pipeline is used to obtain C2 and the fixed-point number x' of the first stage pipeline, calculate C2x' using Booth encoding technology and fixed-point multiplier, and obtain the calculation result of C2x'; The third-stage pipeline is used to obtain C1 and the fixed-point number x' of the first-stage pipeline, and obtain the calculation result of C2x' of the second-stage pipeline, and use the Wallace tree structure to perform cumulative calculation to obtain the calculation result of (C1+C2x')x'; The fourth stage pipeline is used to obtain C0 of the first stage pipeline, obtain the calculation result of (C1+C2x')x' of the third stage pipeline, use a high-precision fixed-point adder and a carry-save adder to perform calculations, and store the calculation results in a fixed-point format to obtain a fixed-point calculation result of C0+(C1+C2x')x'; The fifth stage pipeline is used to obtain the fixed-point calculation result of C0+(C1+C2x')x' of the fourth stage pipeline, and convert the fixed-point calculation result into a floating-point number to obtain a floating-point output value.

8. The circuit implementation method for trigonometric function hardware acceleration according to claim 7, characterized in that: The converting the fixed-point calculation result into a floating-point number comprises: B1, performs a fixed-point shift operation on the fixed-point calculation result of C0+(C1+C2x)x of the fourth-stage pipeline, and converts the fixed-point calculation result into a format in which the highest bit is 1 and the decimal point is after the highest bit; B2, remove the highest bit of the fixed-point calculation result to obtain the converted floating-point mantissa; B3, calculating the number of shift bits in the shift operation, and subtracting the number of shift bits from the fixed offset value of the floating-point exponent to obtain the floating-point exponent; wherein the fixed offset value of the floating-point exponent refers to a fixed value defined under the IEEE754 standard, which is 127; B4, marking the sign bit of the fixed-point calculation result as a floating-point sign bit, and combining the floating-point sign bit, the floating-point mantissa, and the floating-point exponent to obtain a converted floating-point number.

9. The circuit implementation method for trigonometric function hardware acceleration according to claim 1, characterized in that: The single-precision floating-point input preprocessing circuit and the coefficient table lookup circuit are used to execute the first-stage pipeline; The multiplication-accumulation calculation circuit is used to execute the second to fourth stage pipeline; The post-processing circuit is used to execute the fifth stage pipeline.

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