Method for upgrading programmable chip, board card system and electronic equipment
By controlling the FPGA upgrade process, the problem of high FPGA upgrade cost and power-off in the existing technology is solved, and FPGA upgrade without power-off is achieved, reducing the upgrade cost.
Patent Information
- Application Number
- CN202411954991.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-27
- Publication Date
- 2025-04-25
AI Technical Summary
The existing FPGA upgrade solution has the problem of high upgrade costs and requires power outage and restart to achieve upgrades.
By receiving operation instructions issued by the upper computer, the control chip determines whether the FPGA needs to be upgraded, and the target configuration file is written to the memory chip. When the configuration file is correctly written, the control chip pulls down the specific pin signal, allowing the programmable chip to automatically load the target configuration file in the memory chip, achieving an FPGA upgrade without power-off and restart.
It realizes the FPGA upgrade without power off and restarting, reducing the cost of FPGA upgrade.
Smart Images
Figure CN119883323A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of industrial control technology, and in particular to a method for upgrading a programmable chip, a board system, and an electronic device. Background Art
[0002] With the rapid development of industrial control technology, the complexity of robot control systems is increasing, and field programmable gate arrays (FPGAs) are required for various control scenarios of robots. Due to the advantages of FPGAs such as flexibility and reconfigurability, FPGAs are often combined with microprocessors to form embedded systems for use in autonomous driving, industrial control, chip prototype verification, and aerospace and other innovative and high-performance computing scenarios. In addition, most board systems use FPGAs for functional deployment during design, so there are many options for upgrading FPGAs.
[0003] In the related art, there are several common solutions for near-end and remote upgrades of FPGA. The first is to use different download software and corresponding downloaders to directly configure and update the content of the storage chip (fast large area scan, FLASH) through the standard test interface (Joint Test Action Group, JTAG); the second is to upgrade the content of FLASH of FPGA through the serial port, and update the content of FLASH after receiving, converting, erasing and writing the upper file through the related logic circuits added inside the FPGA; the third is to upgrade the FLASH of FPGA through a digital signal processor (Digital Signal Processor, DSP).
[0004] However, when upgrading FPGA based on related technologies, the first solution has the problem that after the update, the power needs to be turned off and restarted to reload the program in the FPGA, and this upgrade operation also requires a specific downloader and development environment, which will greatly increase the upgrade cost; although the second solution reduces the limitations of the development environment and downloader, it limits the FLASH selection to a parallel bus to achieve partition selection, which greatly increases the difficulty and cost of FPGA upgrades; the third solution cannot directly update the FPGA after the FLASH content is upgraded, and the FPGA upgrade still needs to be powered off and restarted. Therefore, the solutions of related technologies have the problem that the FPGA upgrade cost is high and the FPGA upgrade needs to be powered off and restarted to achieve the problem. Summary of the invention
[0005] The purpose of this application is to provide a method for upgrading a programmable chip, a board system, and an electronic device, which can achieve the effect of upgrading the FPGA without powering off and restarting, and reducing the cost of FPGA upgrading.
[0006] The embodiment of the present application is implemented as follows:
[0007] In a first aspect of an embodiment of the present application, a method for upgrading a programmable chip is provided. The method is applied to a board system, wherein the board system includes: a control chip, and a programmable chip and a storage chip that are communicatively connected to the control chip. The method includes:
[0008] The control chip obtains the operation instruction sent by the host computer, and determines whether to upgrade the programmable chip according to the operation instruction;
[0009] If yes, the control chip loads the target configuration file into the data buffer area of the control chip, and writes the target configuration file in the data buffer area into the storage chip;
[0010] The control chip reads the configuration file to be verified actually stored in the storage chip back to the control chip, and compares the target configuration file with the configuration file to be verified to determine whether the target configuration file matches the configuration to be verified;
[0011] If so, the control chip pulls down the signal of the first pin connecting the control chip and the programmable chip within a preset time period;
[0012] After the programmable chip recognizes the signal of the first pin after being pulled low, the programmable chip automatically loads the target configuration file in the storage chip.
[0013] As a possible implementation method, after the programmable chip automatically loads the target configuration file in the storage chip, it also includes:
[0014] If the target configuration file is loaded successfully, the programmable chip pulls high the signal of the second pin connecting the control chip and the programmable chip;
[0015] After the control chip recognizes the signal of the second pin after being pulled high, the upgrade process ends and waits for a new upgrade instruction.
[0016] As a possible implementation method, after the programmable chip automatically loads the target configuration file in the storage chip, it also includes:
[0017] If a data error occurs when the programmable chip automatically loads the target configuration file, the programmable chip pulls down the signal of the third pin connecting the control chip and the programmable chip so that the signal of the second pin connecting the control chip and the programmable chip will not be pulled up.
[0018] As a possible implementation manner, the method for upgrading the programmable chip further includes:
[0019] The control chip pulls up the signal of the first pin and the signal of the third pin, reloads the target configuration file into the data buffer area of the control chip, and writes the target configuration file in the data buffer area into the storage chip.
[0020] As a possible implementation method, writing the target configuration file in the data cache area into the storage chip includes:
[0021] The historical configuration file in the storage chip is erased, and after the historical configuration file is completely erased, the target configuration file in the data cache area is written into the storage chip according to the bus timing of the storage chip.
[0022] As a possible implementation method, the target configuration file and the configuration file to be verified are compared to determine whether the target configuration file matches the configuration to be verified, including:
[0023] If the verification code in the configuration file to be verified is consistent with the verification code in the target configuration file, and the configuration data in the configuration file to be verified is consistent with the configuration data in the target configuration file, then it is determined that the target configuration file matches the configuration to be verified;
[0024] Otherwise, it is determined that the target configuration file does not match the configuration to be verified.
[0025] As a possible implementation manner, after determining whether to perform an upgrade operation on the programmable chip according to the operation instruction, the method further includes:
[0026] According to the operation instruction, determine the upgrade operation type of the programmable chip, the upgrade operation type including: near-end upgrade or far-end upgrade;
[0027] Determine the target transfer method for the target configuration file based on the upgrade operation type.
[0028] As a possible implementation method, the upgrade operation type of the programmable chip is determined according to the operation instruction, including:
[0029] If the operation instruction indicates that signals are upgraded between logic blocks in the programmable chip, determining that the upgrade operation type of the programmable chip is near-end upgrade;
[0030] If the operation instruction indicates to perform signal upgrade between the programmable chip and the external circuit, it is determined that the upgrade operation type of the programmable chip is remote upgrade.
[0031] According to a second aspect of an embodiment of the present application, a board system is provided, the board system comprising: a control chip, and a programmable chip and a storage chip that are communicatively connected to the control chip;
[0032] The board system is used to execute the steps of the method for upgrading the programmable chip described in the first aspect above.
[0033] A third aspect of the embodiments of the present application provides an electronic device in which the board system described in the second aspect is deployed.
[0034] The beneficial effects of the embodiments of the present application include:
[0035] A method for upgrading a programmable chip provided in an embodiment of the present application includes receiving an operation instruction issued by a host computer through a control chip, and judging whether it is necessary to perform an upgrade operation on the programmable chip according to the received operation instruction; if it is determined that the programmable chip needs to be upgraded, the control chip loads a target configuration file into a data cache area of the control chip through a network or a mobile storage device, and writes the target configuration file cached in the data cache area into the storage chip; when the target configuration file is completely written into the storage chip, the control chip performs a data read operation, and the control chip reads back a configuration file to be verified currently actually stored in the storage chip via a serial data interface, and compares the configuration file to be verified read back with the target configuration file cached in the data cache area to determine whether the configuration file to be verified in the storage chip matches the target configuration file; if it is determined that the configuration file to be verified actually stored in the storage chip matches the target configuration file, the control chip pulls down the signal of the first pin connecting the control chip and the programmable chip within a preset time period; when the programmable chip recognizes that the signal of the first pin connecting the programmable chip and the control chip is pulled down, the programmable chip automatically loads the target configuration file in the storage chip. The control chip controls the signal level of the first pin according to whether the target configuration file is correctly written into the storage chip, and the programmable chip determines whether to automatically read the target configuration file from the storage chip according to the signal level of the first pin, so that the upgrade operation of the programmable chip can be completed without powering off and restarting. In this way, the FPGA upgrade can be achieved without powering off and restarting, and the cost of FPGA upgrade can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.
[0037] Figure 1 It is an existing FPGA upgrade flow chart;
[0038] Figure 2 Upgrade flow chart for another existing FPGA;
[0039] Figure 3 A system block diagram of a board system provided in an embodiment of the present application;
[0040] Figure 4 A flowchart of a first method for upgrading a programmable chip provided in an embodiment of the present application;
[0041] Figure 5 A flowchart of a second method for upgrading a programmable chip provided in an embodiment of the present application;
[0042] Figure 6 A flowchart of a third method for upgrading a programmable chip provided in an embodiment of the present application;
[0043] Figure 7 A flowchart of a fourth method for upgrading a programmable chip provided in an embodiment of the present application;
[0044] Figure 8 A flowchart of a fifth method for upgrading a programmable chip provided in an embodiment of the present application;
[0045] Fig. 9 An operation flow chart of a control chip provided in an embodiment of the present application;
[0046] Fig.10 A loading timing diagram of an FPGA loading target configuration file provided in an embodiment of the present application;
[0047] Fig.11 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application.
[0048] Description of the drawings: 10: board system; 101: control chip; 102: programmable chip; 103: storage chip; 20: electronic device. DETAILED DESCRIPTION
[0049] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.
[0050] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.
[0051] At present, there are several common solutions for near-end and remote upgrades of FPGA. The first is to use different download software and corresponding downloaders to directly configure and update the content of the storage chip (fast large area scan, referred to as FLASH) through the standard test interface (Joint Test Action Group, referred to as JTAG); the second is to upgrade the content of FLASH of FPGA through the serial port, and update the content of FLASH after receiving, converting, erasing and writing the upper file through the relevant logic circuit added inside the FPGA; the third is to upgrade the FLASH of FPGA through the digital signal processor (Digital Signal Processor, referred to as DSP). However, all of the above solutions have the problem of high FPGA upgrade cost and the need to power off and restart to achieve FPGA upgrade.
[0052] To this end, the embodiment of the present application provides a method for upgrading a programmable chip, wherein the control chip obtains an operation instruction issued by a host computer, and determines whether to perform an upgrade operation on the FPGA according to the operation instruction; if so, the target configuration file is loaded into the data cache area of the control chip, and the historical configuration file in the storage chip is erased. After the storage chip is erased, the control chip writes the target configuration file in the data cache area into the storage chip according to the bus timing of the storage chip; the control chip reads back the configuration file to be verified actually stored in the storage chip, and compares the read configuration file to be verified with the target configuration file to determine whether the target configuration file matches the configuration file to be verified; if so, the control chip pulls down the signal of the first pin for a period of time; when the FPGA recognizes the signal of the first pin after being pulled down, the FPGA actively loads the target configuration file in the storage chip. In this way, the effect of realizing FPGA upgrade without powering off and restarting and reducing the cost of FPGA upgrade can be achieved.
[0053] Figure 1 For an existing FPGA upgrade flow chart, see Figure 1 This FPGA upgrade method is to upgrade the FPGA FLASH content through the serial port, and to update the FLASH content after adding corresponding logic circuits inside the FPGA to realize the reception, conversion, erasure, and writing of the upper file. This solution reduces the restrictions on the development environment and downloader, but it increases the cost of the FPGA program and the complexity of the board system. In addition, this solution requires the selection of a parallel bus in the FLASH selection to realize the FLASH partition selection.
[0054] Figure 2 For another existing FPGA upgrade flow chart, see Figure 2This FPGA upgrade method is to upgrade the FPGA's FLASH through DSP, but this solution cannot directly update the FPGA after upgrading the FLASH content. It still needs to be powered off and restarted before the program can be upgraded to the FPGA and run.
[0055] In addition, in traditional board systems, FPGAs are often used in combination with microprocessors to form high-performance embedded systems. Board systems all have corresponding MCU control chips used in conjunction with FPGAs, and FPGAs often use a static random access memory SRAM lookup table structure. This structure requires the FPGA to be restarted after power failure to complete the reconfiguration of the FPGA, so data will be lost after power failure.
[0056] Furthermore, the logic blocks of FPGA are embedded in a smaller size and are interconnected in a distributed manner, which makes FPGA perform better in data-intensive applications, but also increases the risk of data loss after power failure. Therefore, when using FPGA, it is equipped with an external FLASH device to save the program to ensure that the program is not lost after power failure.
[0057] However, in some more complex working environments, the control cabinets of some aerospace equipment or robotic arms are installed at a higher position, and when there are many devices on site, it is impossible to power off and restart a single device. The implementation of the above FPGA upgrade solution will add many additional operating conditions, making the FPGA upgrade process more complicated and the FPGA upgrade cost higher.
[0058] The following is a detailed explanation of the method for upgrading a programmable chip, a board system, and an electronic device provided in the embodiments of the present application in conjunction with the accompanying drawings.
[0059] Figure 3 A system block diagram of a board system provided in this application, see Figure 3 The board system 10 provided in the embodiment of the present application includes: a control chip 101, and a programmable chip 102 and a storage chip 103 that are communicatively connected to the control chip 101. The programmable chip 102 can be implemented by a field programmable gate array FPGA, and the storage chip 103 can be implemented by FLASH. The control chip 101 is communicatively connected to the programmable chip 102 and the storage chip 103 via a serial data bus SPI, and the control chip 101 is also connected to the programmable chip 102 via a first pin, a second pin, and a third pin.
[0060] It is worth noting that the first pin can be implemented by the PROG pin, the second pin can be implemented by the DONE pin, and the third pin can be implemented by the INIT pin, that is, the signal of the first pin is the PROG signal, the signal of the second pin is the DONE signal, and the signal of the third pin is the INIT signal. Among them, the PROG signal is used to indicate whether the storage chip 103 has correctly written the configuration file, the DONE signal is used to indicate whether the programmable chip 102 has successfully loaded the configuration file in the FLASH, and the INIT signal is used to indicate whether there is a loading data error when the programmable chip 102 loads the configuration file in the FLASH. In addition, PROG is controlled by the control chip 101, and the DONE signal and the INIT signal are controlled by the programmable chip 102, and this application does not make specific limitations on this.
[0061] Figure 4 This is a flowchart of a method for upgrading a programmable chip provided by the present application, which can be applied to the board system 10. Figure 4 , an embodiment of the present application provides a method for upgrading a programmable chip, comprising:
[0062] S401, the control chip obtains the operation instruction sent by the host computer, and determines whether to upgrade the programmable chip according to the operation instruction.
[0063] Optionally, the host computer refers to a computer that can directly issue operating instructions. The host computer is usually a PC, a host computer or a main computer. The host computer exchanges data and transmits instructions with the control chip through a communication interface. The host computer can realize the monitoring, configuration, data collection and analysis functions of the board system, etc. This application does not make specific limitations on this.
[0064] Optionally, the control chip is used as a core component of the board system. The control chip is not only used to control and coordinate the operation of the storage chip and the programmable chip in the board system, but also used to receive operation instructions issued by the host computer. The operation instruction is a command or instruction sent by the host computer to the board system to be executed. The operation instruction can be an upgrade instruction, an update instruction, etc., which is not specifically limited in this application.
[0065] Optionally, the control chip determines whether to perform an upgrade operation on the programmable chip according to the instruction of the received operation instruction, and the upgrade operation is used to indicate the update of the configuration information in the programmable chip. It is worth noting that if the operation instruction sent by the host computer indicates that the board system needs to perform an upgrade operation, the operation instruction contains the configuration information required for the upgrade, and the control chip can perform the upgrade operation according to the configuration information contained in the operation instruction.
[0066] S402: If yes, the control chip loads the target configuration file into the data buffer area of the control chip, and writes the target configuration file in the data buffer area into the storage chip.
[0067] Optionally, the target configuration file is configuration information pre-set by the user. The target configuration file can be stored in the host computer, such as in the upgrade program issued by the host computer; it can also be stored in a mobile storage device, such as in a mobile USB flash drive. This application does not make specific limitations on this.
[0068] It is worth noting that the target configuration file contains various information such as verification code, address and configuration data, and this application does not make specific limitations on this.
[0069] Among them, the target configuration file is a general configuration file generated by a dedicated development environment. The target configuration file is often in a bin or bit file format, and this application does not make specific limitations on this.
[0070] Optionally, the data cache refers to a memory space or storage medium for temporarily storing configuration files in a storage chip, and the data cache can realize fast access and reading of data. Among them, when the control chip determines that the programmable chip needs to be upgraded according to the instructions of the operation instructions issued by the host computer, the control chip downloads the target configuration file to the data cache of the control chip via the network or U disk, and writes the target configuration file to the storage chip via the serial data bus SPI. It is worth noting that when the control chip writes the target configuration file to the storage chip via the serial data bus SPI, it is necessary to follow the bus timing of the serial data bus of the storage chip to write the target configuration file to the storage chip.
[0071] In addition, if the control chip determines that there is no need to upgrade the programmable chip based on the operation instructions sent by the host computer, the control chip will not actively read the target configuration file pre-set by the user. Only when triggered by the upgrade operation instructions sent by the host computer will the control chip cache the target configuration file to the data cache area of the control chip.
[0072] S403: The control chip reads the configuration file to be verified actually stored in the storage chip back to the control chip, and compares the target configuration file with the configuration file to be verified to determine whether the target configuration file matches the configuration to be verified.
[0073] Optionally, the configuration file to be verified refers to the configuration file actually stored in the storage chip after the control chip writes the target configuration file to the storage chip. The configuration file to be verified may be consistent with the target configuration file or different from the target configuration file, and this application does not make specific restrictions on this.
[0074] Optionally, after the control chip writes all the target configuration files stored in the data cache area into the storage chip via the serial data bus SPI, the control chip starts the data reading operation, and the control chip reads the configuration file to be verified actually stored in the storage chip at the current moment from the storage chip via the serial data bus SPI; after the control chip completes the data reading operation, the read configuration file to be verified is compared with the target configuration file to determine whether the target configuration file is consistent with the configuration file to be verified.
[0075] It is worth noting that the comparison between the target configuration file and the configuration file to be verified is mainly to compare whether the verification code of the target configuration file is consistent with the verification code of the configuration file to be verified, and whether the configuration information contained in the target configuration file is consistent with the configuration information contained in the configuration file to be verified. If the verification code and configuration information of the target configuration file and the configuration file to be verified are consistent, then the target configuration file is considered to match the configuration file to be verified.
[0076] S404: If yes, the control chip pulls down the signal of the first pin connecting the control chip and the programmable chip within a preset time period.
[0077] Optionally, the preset time period refers to a time interval set in advance by the user, and the preset time period may be 10 seconds, 15 seconds, 30 seconds, etc., and this application does not make any specific limitation on this.
[0078] Optionally, the first pin connecting the control chip and the programmable chip is implemented by PROG, which is specifically used to indicate a one-time programmable read-only register, and the signal of the first pin is a PROG signal, which is specifically used to indicate whether the storage chip correctly writes the target configuration signal of the data cache area of the control chip. If the PROG signal is pulled low by the control chip, it means that the storage chip correctly writes the target configuration file; if PROG remains in the initialized state, it means that the storage chip does not correctly write the target configuration file, that is, there is a write error in the storage chip writing the target configuration file.
[0079] Optionally, if the control chip determines that the configuration file to be verified read back from the storage chip matches the target configuration file cached in the data cache area of the control chip, the control chip pulls down the signal of the first pin PROG connecting the control chip and the programmable chip within a preset time period to inform the programmable chip that the storage chip has correctly written the target configuration file at the current moment, and the programmable chip can load the configuration file stored in the storage chip.
[0080] Optionally, if the control chip determines that the configuration file to be verified read back from the storage chip does not match the target configuration file cached in the data cache area of the control chip, the control chip maintains the initial state of the signal of the first pin PROG connecting the control chip to the programmable chip to inform the programmable chip that there is an error in writing the target configuration file to the storage chip at the current moment, and the programmable chip cannot load the configuration file stored in the storage chip. The control chip needs to rewrite the target configuration file to the storage chip, and after the data write operation is completed, read back the configuration file to be verified actually stored in the storage chip, and adjust the signal of the first pin connecting the control chip to the programmable chip according to the matching degree between the read-back configuration file to be verified and the target configuration file.
[0081] It is worth noting that the control chip can only control the signal of the first pin to be pulled low within the preset time period and continue to perform the next upgrade operation after the storage chip correctly writes the target configuration file; when there is a configuration file writing error in the storage chip, the control chip needs to rewrite the target configuration file to the storage chip until the storage chip correctly writes the target configuration file, and then informs the programmable chip that the target configuration file in the storage chip can be loaded. Among them, before writing the configuration file to the storage chip each time, the data in the storage chip needs to be erased to avoid the influence of other data stored in the storage chip on the newly written data, so as to improve the data integrity and security of the newly written configuration file.
[0082] In addition, when the control chip determines that the configuration file to be verified read back matches the target configuration file cached in the data cache area, the control chip pulls down the PROG signal of the first pin connecting the control chip to the programmable chip, and releases the control right of the serial data bus SPI connected between the control chip and the storage chip.
[0083] S405 , after the programmable chip recognizes the signal of the first pin being pulled low, the programmable chip automatically loads the target configuration file in the storage chip.
[0084] Optionally, when the programmable chip recognizes that the signal of the first pin connecting the control chip and the programmable chip is pulled low, the programmable chip automatically loads the target configuration file from the storage chip.
[0085] It is worth noting that the configuration mode of the programmable chip is MSPI mode, that is, the configuration mode of the programmable chip is active serial mode. Among them, when the power is actively established, the programmable chip will actively send out the clock signal of the serial data interface, and actively read the target configuration file from the storage chip, and load it into the programmable chip for execution.
[0086] In an embodiment of the present application, an operation instruction issued by a host computer is received by a control chip, and according to the received operation instruction, it is determined whether an upgrade operation is required for the programmable chip; if it is determined that an upgrade operation is required for the programmable chip, the control chip loads a target configuration file into a data cache area of the control chip through a network or a mobile storage device, and writes the target configuration file cached in the data cache area into the storage chip; when the target configuration file is completely written into the storage chip, the control chip performs a data read operation, and the control chip reads back the configuration file to be verified currently actually stored in the storage chip via a serial data interface, and compares the configuration file to be verified read back with the target configuration file cached in the data cache area to determine whether the configuration file to be verified in the storage chip matches the target configuration file; if it is determined that the configuration file to be verified actually stored in the storage chip matches the target configuration file, the control chip pulls down the signal of the first pin connecting the control chip and the programmable chip within a preset time period; when the programmable chip recognizes that the signal of the first pin connecting the programmable chip and the control chip is pulled low, the programmable chip automatically loads the target configuration file in the storage chip. The control chip controls the signal level of the first pin according to whether the target configuration file is correctly written into the storage chip, and the programmable chip determines whether to automatically read the target configuration file from the storage chip according to the signal level of the first pin, so that the upgrade operation of the programmable chip can be completed without powering off and restarting. In this way, the FPGA upgrade can be achieved without powering off and restarting, and the cost of FPGA upgrade can be reduced.
[0087] In an optional embodiment, see Figure 5 After the programmable chip automatically loads the target configuration file in the storage chip in the above step S405, the following steps are also included:
[0088] S501: If the target configuration file is loaded successfully, the programmable chip pulls up the signal of the second pin connecting the control chip and the programmable chip.
[0089] Optionally, when the programmable chip successfully reads the target configuration file from the storage chip, the programmable chip pulls up the signal of the second pin DONE connecting the control chip and the programmable chip. After the control chip receives the pulled-up DONE signal, it can be determined that the programmable chip has been successfully upgraded.
[0090] S502: After the control chip recognizes the signal of the second pin that has been pulled high, the upgrade process ends and a new upgrade instruction is waited for.
[0091] Optionally, when the control chip recognizes that the DONE signal of the second pin connecting the control chip and the programmable chip is pulled high, the control chip determines that the programmable chip has successfully loaded the target configuration file, and the programmable chip completes the upgrade operation. The control chip continues to wait for the arrival of the next upgrade operation instruction. After the control chip receives the new upgrade operation instruction sent by the host computer, it re-executes the upgrade operation.
[0092] Optionally, the upgrade instruction refers to a control instruction sent by the host computer to the board system for the programmable chip to perform an upgrade operation, and the new upgrade instruction refers to the upgrade instruction sent by the host computer again received by the control chip in the board system after the programmable chip completes the current upgrade operation.
[0093] In an optional embodiment, see Figure 5 After the programmable chip automatically loads the target configuration file in the storage chip in the above step S405, the following steps are also included:
[0094] S503. If a data error occurs when the programmable chip automatically loads the target configuration file, the programmable chip pulls down the signal of the third pin connecting the control chip and the programmable chip so that the signal of the second pin connecting the control chip and the programmable chip will not be pulled up.
[0095] Optionally, when a data read error occurs when the programmable chip automatically reads the target configuration file stored in the storage chip, the programmable chip pulls down the INIT signal of the third pin connecting the control chip and the programmable chip, and at the same time, the DONE signal of the second pin connecting the control chip and the programmable chip maintains the initialization state. When the control chip recognizes that the INIT signal of the third pin connecting the control chip and the programmable chip is pulled down, the control chip determines that the programmable chip has not successfully loaded the target configuration file in the storage chip, the control chip interrupts the current upgrade operation, and the programmable chip stops loading the target configuration file in the storage chip.
[0096] In an optional implementation manner, the method for upgrading a programmable chip further includes:
[0097] The control chip pulls up the signal of the first pin and the signal of the third pin, reloads the target configuration file into the data buffer area of the control chip, and writes the target configuration file in the data buffer area into the storage chip.
[0098] Optionally, when the control chip recognizes that the INIT signal of the third pin connecting the control chip and the programmable chip is pulled low, the control chip determines that an upgrade error occurs in the programmable chip, and the control chip pulls up the PROG signal of the first pin connecting the control chip and the programmable chip, so that the programmable chip no longer continues to read the target configuration file in the storage chip. At the same time, the control chip also pulls up the INIT signal of the third pin connecting the control chip and the programmable chip, so that the programmable chip no longer sends a signal of a target configuration file loading error to the control chip.
[0099] Optionally, after the programmable chip erroneously loads the target configuration file in the storage chip, the control chip prohibits the programmable chip from continuing to read the target configuration file in the storage chip, and reloads the target configuration file to the data cache area of the control chip via the network or a mobile USB flash drive, and after erasing the target configuration file currently stored in the storage chip, rewrites the newly cached target storage file in the data cache area into the storage chip, and verifies again whether the storage chip has correctly written the target configuration file. When the storage chip correctly writes the target configuration file again, the control chip pulls down the PROG signal of the first pin connecting the control chip and the programmable chip within a preset time period, and after the programmable chip recognizes the PROG signal after being pulled down, it reads the target configuration file from the storage chip again, and after successfully loading the target configuration file, the programmable chip pulls up the DONE signal of the second pin connecting the control chip and the programmable chip to inform the control chip that the programmable chip has been successfully upgraded.
[0100] In an optional implementation manner, the operation of writing the target configuration file in the data buffer area into the storage chip in the above step S402 may specifically be:
[0101] The historical configuration file in the storage chip is erased, and after the historical configuration file is completely erased, the target configuration file in the data cache area is written into the storage chip according to the bus timing of the storage chip.
[0102] Optionally, the historical configuration file is used to indicate the configuration file originally stored in the storage chip, and erasing the historical configuration file in the storage chip refers to formatting the historical configuration file from the storage chip. When the historical configuration file in the storage chip is completely deleted, the control chip starts to write the target configuration file in the data cache area into the storage chip. The historical configuration file specifically refers to the target configuration file required for the last upgrade operation of the programmable chip.
[0103] Optionally, the bus timing refers to the timing of the storage chip receiving data sent by the control chip via the serial data bus SPI. The bus timing can ensure the transmission rate and accuracy of the data transmitted on the serial data bus SPI.
[0104] Optionally, when the historical configuration files in the control chip are completely erased, the control chip writes the target configuration files cached in the data cache area of the control chip into the storage chip in sequence according to the bus timing of the storage chip.
[0105] In an optional embodiment, see Figure 6 In the above step S403, the operation of comparing the target configuration file and the configuration file to be verified to determine whether the target configuration file matches the configuration to be verified may specifically be:
[0106] S601: If the verification code in the configuration file to be verified is consistent with the verification code in the target configuration file, and the configuration data in the configuration file to be verified is consistent with the configuration data in the target configuration file, it is determined that the target configuration file matches the configuration to be verified.
[0107] Optionally, when the verification code of the configuration file to be verified read back by the control chip is the same as the verification code of the target configuration file cached in the data buffer of the control chip, and the configuration data contained in the configuration file to be verified read back by the control chip is also the same as the configuration data contained in the target configuration file cached in the data buffer area of the control chip, then it is determined that the target configuration file cached in the data buffer area of the control chip is the same as the configuration file to be verified actually stored in the storage chip, and the storage chip successfully writes the target configuration file.
[0108] S602: Otherwise, determine that the target configuration file does not match the configuration to be verified.
[0109] Optionally, when the verification code of the configuration file to be verified read back by the control chip is different from the verification code of the target configuration file cached in the data buffer of the control chip, and / or the configuration data contained in the configuration file to be verified read back by the control chip is different from the configuration data contained in the target configuration file cached in the data buffer area of the control chip, it is determined that the target configuration file cached in the data buffer area of the control chip does not match the configuration file to be verified actually stored in the storage chip, and the storage chip fails to write the target configuration file, that is, the configuration file to be verified actually stored in the storage chip is different from the target configuration file cached in the data buffer area of the control chip.
[0110] In an optional embodiment, see Figure 7 After determining whether to perform an upgrade operation on the programmable chip according to the operation instruction in the above step S401, the method further includes:
[0111] S701. Determine an upgrade operation type of a programmable chip according to an operation instruction. The upgrade operation type includes: local upgrade or remote upgrade.
[0112] Optionally, the upgrade operation type refers to the upgrade type of the programmable chip, the remote upgrade refers to the signal upgrade between internal logic blocks of the programmable chip, and the local upgrade refers to the signal upgrade between the programmable chip and an external circuit.
[0113] Optionally, the control chip determines the type of upgrade operation of the programmable chip according to the content indicated by the operation instruction sent by the host computer.
[0114] S702: Determine a target transmission mode of a target configuration file according to the upgrade operation type.
[0115] Optionally, the target transmission mode refers to a data transmission mode for the control chip to obtain the target configuration file, and the control chip selects the mode for obtaining the target configuration file according to the upgrade type of the programmable chip.
[0116] Optionally, if the upgrade operation type of the programmable chip is local upgrade, the control chip can copy the target configuration file to the data cache area of the control chip by moving a USB flash drive; if the upgrade operation type of the programmable chip is remote upgrade, the control chip downloads the target configuration file to the data cache area of the control chip through the network.
[0117] In an optional embodiment, see Figure 8 The operation of step S701 may specifically be:
[0118] S801: If the operation instruction indicates to perform signal upgrade between logic blocks in the programmable chip, determine that the upgrade operation type of the programmable chip is near-end upgrade.
[0119] Optionally, when the upper computer sends an operation instruction to the control chip indicating that a signal upgrade is required between the logic blocks inside the programmable chip, the upgrade type of the programmable chip is a proximal upgrade, and the control chip can copy the target configuration file to the data cache area of the control chip by moving a USB flash drive.
[0120] S802: If the operation instruction indicates to perform signal upgrade between the programmable chip and the external circuit, determine that the upgrade operation type of the programmable chip is remote upgrade.
[0121] Optionally, when the host computer sends an operation instruction to the control chip indicating that signal upgrade is required between the logic blocks inside the programmable chip, the upgrade type of the programmable chip is proximal upgrade, and the control chip downloads the target configuration file to the data cache area of the control chip through the network.
[0122] Fig. 9 For the operation flow chart of a control chip provided in this application, see Fig. 9,The specific operation logic of the control chip in the board system is as follows: the control chip receives the ,operation command sent by the host computer, and ,determines whether to upgrade the programmable chip in the board system according to the ,received operation command, and determines whether the upgrade operation type of the ,programmable chip is to be upgraded or to be remote upgrade; if the programmable chip needs to be upgraded, the transmission method for obtaining the target ,configuration file to be updated is selected according to the type of the upgrade operation of the ,programmable chip; after caching the target configuration file to be updated in the data cache area of the ,control chip erases the historical configuration file in the storage chip FLASH via the serial data bus, and after the entire ,storage chip is erased, the control chip writes the target configuration file cached in the data cache area of the ,control chip into the storage chip via the serial data bus SPI; when the target configuration file is completely written into the storage chip, the control chip performs a ,read data operation, and the control chip reads back the configuration file to be verified ,actually stored in the storage chip. And according to the comparison result of the configuration file to be verified and the target configuration file, it is determined whether the storage chip has correctly written the target configuration file; if so, the control chip pulls down the PROG signal of the first pin connecting the control chip and the programmable chip, and waits for the DONE signal of the second pin connecting the control chip and the programmable chip to be pulled high by the programmable chip, until the DONE signal is pulled high, the programmable chip upgrade is completed; if not, the control chip determines that the storage chip has not correctly written the target configuration file, the control chip re-executes the upgrade operation, and rewrites the target configuration file in the data cache area of the control chip into the storage chip until the configuration file to be verified actually stored in the storage chip matches the target configuration file cached in the data cache area of the control chip; if the DONE signal of the second pin connecting the control chip and the programmable chip is not pulled high, the programmable chip has not successfully loaded the target configuration file in the storage chip, and the control chip still needs to re-execute the upgrade operation.
[0123] Fig.10 For a loading timing diagram of an FPGA loading target configuration file provided in this application, see Fig.10, PROGRAM_B is used to indicate the PROG signal of the first pin connecting the control chip to the programmable chip; T_program_b is used to indicate the duration of the control chip pulling the PROG signal low, that is, T_program_b is used to indicate the preset time period; INIT_B is used to indicate the INIT signal of the third pin connecting the control chip to the programmable chip; T_init_b is used to indicate the preparation time for the control chip to pull the INIT signal high; CCLK is used to indicate the bus timing of the memory chip; T_dk is used to indicate a time period in the bus timing of the memory chip; T_cl is used to indicate the falling edge in the bus timing of the memory chip, that is, the time to stop writing or reading data; T_ch is used to indicate the rising edge in the bus timing of the memory chip, that is, the time to start writing or reading data; DIN is used to indicate the signal transmitted by the DIN connector, which is a standard interface; DONE is used to indicate the DONE signal of the second pin connecting the control chip to the programmable chip.
[0124] Fig.11 A schematic diagram of the structure of an electronic device provided in this application, see Fig.11 The electronic device 20 provided in the embodiment of the present application is equipped with the above-mentioned board system 10, and the electronic device 20 implements the upgrade of FPGA via the board system 10. The function of the board system 10 is consistent with the above-mentioned method embodiment, and the present application will not elaborate on it here.
[0125] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.
[0126] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A method for upgrading a programmable chip, characterized in that: The method is applied to a board system, the board system comprising: a control chip, and a programmable chip and a storage chip that are communicatively connected to the control chip, and the method comprises: The control chip obtains an operation instruction issued by the host computer, and determines whether to perform an upgrade operation on the programmable chip according to the operation instruction; If yes, the control chip loads the target configuration file into the data buffer area of the control chip, and writes the target configuration file in the data buffer area into the storage chip; The control chip reads the configuration file to be verified actually stored in the storage chip back to the control chip, and compares the target configuration file with the configuration file to be verified to determine whether the target configuration file matches the configuration file to be verified; If so, the control chip pulls down the signal of the first pin connecting the control chip and the programmable chip within a preset time period; After the programmable chip recognizes the signal of the first pin being pulled low, the programmable chip automatically loads the target configuration file in the storage chip.
2. The method for upgrading a programmable chip according to claim 1, characterized in that: After the programmable chip automatically loads the target configuration file in the storage chip, the method further includes: If the target configuration file is loaded successfully, the programmable chip pulls up the signal of the second pin connecting the control chip and the programmable chip; After the control chip recognizes the signal of the second pin after being pulled high, the upgrade process ends and waits for a new upgrade instruction.
3. The method for upgrading a programmable chip according to claim 1, characterized in that: After the programmable chip automatically loads the target configuration file in the storage chip, the method further includes: If a data error occurs when the programmable chip automatically loads the target configuration file, the programmable chip pulls down the signal of the third pin connecting the control chip to the programmable chip so that the signal of the second pin connecting the control chip to the programmable chip will not be pulled high.
4. The method for upgrading a programmable chip according to claim 3, characterized in that: The method further comprises: The control chip pulls up the signal of the first pin and the signal of the third pin, reloads the target configuration file into the data cache area of the control chip, and writes the target configuration file in the data cache area into the storage chip.
5. The method for upgrading a programmable chip according to claim 1, characterized in that: Writing the target configuration file in the data buffer area into the storage chip includes: The historical configuration file in the storage chip is erased, and after the historical configuration file is completely erased, the target configuration file in the data cache area is written into the storage chip according to the bus timing of the storage chip.
6. The method for upgrading a programmable chip according to claim 1, characterized in that: The comparing the target configuration file and the configuration file to be verified to determine whether the target configuration file matches the configuration file to be verified includes: If the verification code in the configuration file to be verified is consistent with the verification code in the target configuration file, and the configuration data in the configuration file to be verified is consistent with the configuration data in the target configuration file, it is determined that the target configuration file matches the configuration to be verified; Otherwise, it is determined that the target configuration file does not match the configuration to be verified.
7. The method for upgrading a programmable chip according to claim 1, characterized in that: After determining whether to perform an upgrade operation on the programmable chip according to the operation instruction, the method further includes: Determining, according to the operation instruction, an upgrade operation type of the programmable chip, the upgrade operation type including: proximal upgrade or remote upgrade; According to the upgrade operation type, a target transmission mode of the target configuration file is determined.
8. The method for upgrading a programmable chip according to claim 7, characterized in that: The step of determining the upgrade operation type of the programmable chip according to the operation instruction includes: If the operation instruction instructs to perform signal upgrade between logic blocks in the programmable chip, determining that the upgrade operation type of the programmable chip is near-end upgrade; If the operation instruction indicates to perform signal upgrade between the programmable chip and the external circuit, it is determined that the upgrade operation type of the programmable chip is remote upgrade.
9. A board system, characterized in that: The board system includes: a control chip, and a programmable chip and a storage chip that are communicatively connected to the control chip; The board system is used to execute the steps of the method for upgrading a programmable chip as described in any one of claims 1-8.
10. An electronic device, characterized in that: The board system according to claim 9 is deployed in the electronic device.