Instruction selection method and device and storage medium

Abstract

The invention discloses an instruction selection method and device and a storage medium, and belongs to the field of computers.The method comprises the steps that queue ready information in a reservation station is sorted according to priorities, a ready queue of the reservation station and a mask of a queue pointer are obtained, and the all-one part of the mask is an area where the highest priority is located; carrying out AND on the ready queue and the mask, carrying out AND on the inverse codes of the ready queue and the mask, and obtaining a queue bit corresponding to a ready instruction in an AND result through a priority encoder; when the obtained queue bit exists in the mask phase and result, selecting a ready instruction in the mask phase and result; otherwise, a ready instruction in the inverse phase and the result is selected. The method is used for solving the problems of high energy consumption and high calculation cost when the processor selects the current highest priority ready instruction.

Description

Technical Field

[0001] The present invention relates to the field of computers, and in particular to a method, device and storage medium for selecting instructions. Background Art

[0002] A superscalar processor is a high-performance processor technology that improves the throughput and performance of the processor by executing multiple instructions concurrently and out-of-order execution technology. The advantage of a superscalar processor is that it can significantly improve the throughput and performance of the processor. By executing multiple instructions concurrently and out-of-order execution technology, a superscalar processor can more effectively utilize the processor's resources and improve the parallelism of instructions. This makes the superscalar processor more efficient when processing complex computing tasks.

[0003] However, the design of superscalar processors also faces some challenges. For example, how to achieve accurate branch prediction, how to handle the correlation check between load / store instructions, and how to balance hardware complexity and power consumption are all important factors that need to be considered in the design of superscalar processors.

[0004] The issue unit is the basic unit responsible for scheduling instructions. In each clock cycle, the superscalar processor needs to select idle reservation stations and fill these reservation stations with instructions waiting to be assigned. In addition, the processor also needs to identify the oldest ready instructions in the reservation station and issue several instructions to the execution unit. The number of instructions issued usually depends on the number of execution units.

[0005] These processes require the arbiter to have the ability to quickly select, but the reservation station of the circular queue selects the oldest ready instruction by shifting. This mechanism does not physically move the instruction, but logically selects the next instruction to be executed by updating the pointer or index. In order to select the oldest ready instruction, the processor needs to constantly check the status of the instructions in the queue and adjust the order of the instructions in the queue accordingly. This adjustment usually involves a shift operation to ensure that the oldest ready instruction is at the front of the queue for fast access by the processor.

[0006] The existing solution is that the computer processor uses the ALU to execute shift instructions for calculation. The shift here refers to selecting a position. The calculation process requires a data selector to be equipped with each bit output, which has a high calculation cost. The data selector is a multiplexer that can select an output from multiple input signals. During the execution of the shift instruction, the data selector can be used to select the bit to be moved and output it to the specified position.

[0007] The existing solutions not only have high hardware resource requirements, but more importantly, they will cause large delays, thus becoming a significant bottleneck for improving processor performance. Summary of the invention

[0008] To overcome the above-mentioned deficiencies of the prior art, the present invention provides a method, device and storage medium for selecting instructions, so as to solve the problem that the processor selects the oldest ready instruction at present with high energy consumption and high computational cost.

[0009] In order to solve the above technical problems, the present invention is implemented by adopting the following technical solutions:

[0010] In a first aspect, the present invention provides a method for selecting an instruction, comprising:

[0011] S1: sorting the queue ready information in the reservation station by priority, obtaining the ready queue and queue pointer mask of the reservation station, wherein the mask includes an all-1 part where all bits are 1, and the all-1 part is the area where the highest priority is located;

[0012] S2: perform AND operation on the ready queue obtained in step S1 and the mask, and perform AND operation on the ready queue obtained in step S1 and the inverse of the mask to obtain an AND operation result;

[0013] S3: Obtain the ready queue bit corresponding to the ready instruction in the result of step S2 through the priority encoder;

[0014] S4: When the ready queue bit obtained in step S3 exists in the mask phase AND result, select the ready instruction corresponding to the ready queue bit in the mask phase AND result;

[0015] When the ready queue bit only exists in the inverted AND result in step S3, the ready instruction corresponding to the ready queue bit in the inverted AND result is selected.

[0016] In the above method for selecting instructions, the queue pointer is a binary number. In step S1, the mask generation method includes:

[0017] L1: Obtain an input binary number, and determine the number of bits of the mask according to the number of bits of the binary number;

[0018] L2: Convert the binary number obtained in step L1 into decimal;

[0019] L3: Set the bits of the decimal number in step L2 in the mask bit of step L1 to 0, and set the remaining bits to 1;

[0020] L4: Loop through steps L1 to L3 to create a truth table for the binary output mask of the bit number in step L1;

[0021] L5: Obtain the logical expression of each bit of the mask according to the truth table established in step L4;

[0022] L6: Use the Karnaugh map to simplify the logical expression of step L5;

[0023] L7: Based on the simplified logic expression in step L6, the circuit structure is designed using gate-level circuits;

[0024] L8: Generate a mask using the circuit structure designed in step L7.

[0025] The above-mentioned method for selecting an instruction, in step L1, determining the number of bits of the mask according to the number of bits of the binary number includes: the number of bits of the mask is a binary number state number, when the number of bits of the binary number is n, the number of bits of the mask is 2 n , n is a positive integer.

[0026] In the aforementioned method for selecting instructions, step L1 also includes: determining one end of the mask as the starting end; step L3 includes: according to the decimal number obtained in step L2, starting from the starting bit of the mask starting end determined in step L1, setting the mask bits of the decimal number to 0 and the remaining mask bits to 1.

[0027] In the aforementioned method for selecting an instruction, step L7 comprises:

[0028] L71: traverse the logical expressions simplified in step L6, and obtain common items composed of binary bits, where the common items refer to the same logical parts existing in two or more logical expressions;

[0029] L72: Loop through step L71 to get all common items;

[0030] L73: sort the common items obtained in step L72 from small to large according to the number of bits constituting the common items;

[0031] L74: Design the circuit structure using gate-level circuits starting from the common items consisting of 2 bits according to the order of step L73.

[0032] In the aforementioned method for selecting instructions, when the circuit structure is used to generate the aforementioned mask, the start bit at one end of the mask is connected to a high level.

[0033] In the aforementioned method of selecting instructions, when the three bits of the input binary number A are A2A1A0 respectively, and the generated mask Y bits are Y7 / Y6 / Y5 / Y4 / Y3 / Y2 / Y1 / Y0 respectively, and Y0 is the starting end, the logical expression of each bit of the mask Y after simplification in step L6 is:

[0034] = ;

[0035] = ;

[0036] = ;

[0037] = ;

[0038] = ;

[0039] = ;

[0040] = ;

[0041] = 1.

[0042] In the aforementioned method for selecting an instruction, the circuit structure of step L7 includes: a first OR gate, a second OR gate, a third OR gate, a fourth OR gate, a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a first NOT gate, a second NOT gate, a third NOT gate, a fourth NOT gate, a fifth NOT gate, a sixth NOT gate and a seventh NOT gate;

[0043] The construction process of the circuit structure includes:

[0044] A1 and A0 are connected to the two input terminals of the first OR gate respectively;

[0045] A1 and A0 are connected to two input terminals of the first AND gate respectively;

[0046] According to the logical expression of Y0, the output end of the first OR gate is connected to one input end of the second OR gate, the other input end of the second OR gate is connected to A2, the output end of the second OR gate is connected to the input end of the first NOT gate, and the output end of the first NOT gate is connected to Y0;

[0047] According to the logical expression of Y1, A2 and A1 are respectively connected to the two input terminals of the third OR gate, the output terminal of the third OR gate is connected to the input terminal of the second NOT gate, and the output terminal of the second NOT gate is connected to Y1;

[0048] According to the logic expression of Y2, the output end of the first AND gate is connected to one input end of the fourth OR gate, the other input end of the fourth OR gate is connected to A2, the output end of the fourth OR gate is connected to the input end of the third NOT gate, and the output end of the third NOT gate is connected to Y2;

[0049] According to the logical expression of Y3, A2 is connected to the input of the fourth NOT gate, and the output of the fourth NOT gate is connected to Y3;

[0050] According to the logic expression of Y4, A2 is connected to one input terminal of the second AND gate, the output terminal of the first OR gate is connected to the other input terminal of the second AND gate, the output terminal of the second AND gate is connected to the input terminal of the fifth NOT gate, and the output terminal of the fifth NOT gate is connected to Y4;

[0051] According to the logic expression of Y5, A2 and A1 are respectively connected to the two input terminals of the third AND gate, the output terminal of the third AND gate is connected to the input terminal of the sixth NOT gate, and the output terminal of the sixth NOT gate is connected to Y5;

[0052] According to the logic expression of Y6, A2 is connected to one input terminal of the fourth AND gate, the output terminal of the first AND gate is connected to the other input terminal of the fourth AND gate, the output terminal of the fourth AND gate is connected to the input terminal of the seventh NOT gate, and the output terminal of the seventh NOT gate is connected to Y6;

[0053] According to the logical expression of Y7, Y7 is connected to a high level.

[0054] In a second aspect, the present invention provides a device for selecting instructions, comprising: a preprocessing module, a calculation module, an acquisition module and a selection module;

[0055] The selection module is used to sort the queue ready information in the reservation station according to the priority, and obtain the ready queue and queue pointer mask of the reservation station, wherein the mask includes an all-1 part in which all bits are 1, and the all-1 part is the area where the highest priority is located;

[0056] The operation module is used to perform AND operation on the ready queue obtained by the selection module and the mask, and perform AND operation on the ready queue obtained by the selection module and the inverse of the mask to obtain an AND operation result;

[0057] The acquisition module is used to acquire the ready queue bit corresponding to the ready instruction in the result of the operation module through the priority encoder;

[0058] The selection module is used for selecting the ready instruction corresponding to the ready queue bit in the mask phase and result when the ready queue bit obtained by the acquisition module exists in the mask phase and result;

[0059] When the ready queue bit in the acquisition module exists only in the inverted phase AND result, the ready instruction corresponding to the ready queue bit in the inverted phase AND result is selected.

[0060] In a third aspect, a computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of any one of the methods described in the first aspect.

[0061] Compared with the prior art, the present invention has the following beneficial effects:

[0062] The present invention adopts a mask to replace a shift operation when selecting the highest priority ready instruction in a reservation station. The present invention does not need shifting. When the mask is not all 1s, the ready instructions are searched for in two blocks at the same time, and the ready instructions in the area where the highest priority is located are output preferentially. Complex shift operations are not required, thereby speeding up the calculation speed of the instruction selection process, reducing energy consumption and calculation costs. When the highest priority is set to the oldest, the present invention can be used to solve the problem of high energy consumption and high calculation cost when the processor selects the current oldest ready instruction.

[0063] In order to further reduce the energy consumption and computing cost of generating masks, the present invention adopts specially designed gate-level circuits to generate masks. Compared with the traditional shift calculation method, the mask generation process composed of simple gate-level circuits consumes fewer resources, has simpler circuits, lower costs and energy consumption, and faster computing speed.

[0064] The method and circuit structure for generating a mask of the present invention can be flexibly adjusted according to the number of bits of an input binary number, and can adaptively generate a corresponding mask for application in a wider range of application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] Figure 1 1 is a structural block diagram of a three-bit binary number generation mask according to Embodiment 2 of the present invention;

[0066] Figure 2 It is a schematic diagram of a circuit structure for generating a mask according to Embodiment 2 of the present invention. DETAILED DESCRIPTION

[0067] The technical solution of the present invention is described in detail below through the accompanying drawings and specific embodiments. It should be understood that the embodiments of the present application and the specific features in the embodiments are detailed descriptions of the technical solution of the present application, rather than limitations on the technical solution of the present application. In the absence of conflict, the embodiments of the present application and the technical features in the embodiments can be combined with each other.

[0068] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0069] The term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0070] Embodiment 1:

[0071] This embodiment provides a method for selecting an instruction, for selecting a ready instruction with the highest priority in a reservation station, comprising:

[0072] S1: sorting the queue ready information in the reservation station by priority, obtaining the ready queue and queue pointer mask of the reservation station, wherein the mask includes an all-1 part in which all bits are 1, and the all-1 part is the area where the highest priority is located; the queue pointer is a binary number, and in this embodiment, the highest priority of the ready queue is on the left side of the queue, and the left side of the mask is the all-1 part;

[0073] S2: perform AND operation on the ready queue obtained in step S1 and the mask, and perform AND operation on the ready queue obtained in step S1 and the inverse of the mask to obtain an AND operation result;

[0074] When all the mask bits are 1, only the ready queue obtained in step S1 is ANDed with the mask; when not all the mask bits are 1, step S2 divides the ready queue into two parts by the mask;

[0075] S3: Obtain the ready queue bit corresponding to the ready instruction in the result of step S2 through the priority encoder;

[0076] When the mask bits are not all 1, step S3 searches in parallel for the ready queue bits where the ready instructions are located in the two parts of the ready queue divided by the mask;

[0077] S4: When the ready queue bit obtained in step S3 exists in the mask phase AND result, select the ready instruction corresponding to the ready queue bit in the mask phase AND result;

[0078] When the ready queue bit only exists in the inverted AND result in step S3, the ready instruction corresponding to the ready queue bit in the inverted AND result is selected.

[0079] In the ready queue bit where the ready instruction is located, if there is a ready instruction in the area where the highest priority is located (in the mask phase and result), the ready instruction in this area is selected; if the ready instruction only exists in the inverse phase and result, the ready instruction in this area is selected.

[0080] Compared with the original operation of shifting first and then selecting the ready instructions, the present invention does not require shifting. When the mask is not all 1s, the ready instructions are searched for simultaneously in two blocks, and the ready instructions in the area with the highest priority are output preferentially. No complicated shifting operation is required, which speeds up the calculation speed of the instruction selection process and reduces energy consumption and calculation cost.

[0081] The queue pointer is a binary number. In step S1, the mask generation method includes:

[0082] L1: Obtain an input binary number, and determine the number of bits of the mask according to the number of bits of the binary number;

[0083] L2: Convert the binary number obtained in step L1 into decimal;

[0084] L3: Set the bits of the decimal number in step L2 in the mask bit of step L1 to 0, and set the remaining bits to 1;

[0085] L4: Loop through steps L1 to L3 to create a truth table for the binary output mask of the bit number in step L1;

[0086] L5: Obtain the logical expression of each bit of the mask according to the truth table established in step L4;

[0087] L6: Use the Karnaugh map to simplify the logical expression of step L5; using the Karnaugh map to simplify can get the simplest logical expression;

[0088] L7: Based on the simplified logic expression in step L6, the circuit structure is designed using gate-level circuits;

[0089] L8: Generate a mask using the circuit structure designed in step L7.

[0090] In step L1, determining the number of bits of the mask according to the number of bits of the binary number includes: the number of bits of the mask is a binary number state number, when the number of bits of the binary number is n, the number of bits of the mask is 2 n , n is a positive integer. In this embodiment, the number of bits of the input binary number is 3, and the number of bits of the generated mask is 2 3 =8.

[0091] Step L1 also includes determining one end of the mask as the starting end;

[0092] Step L3 includes setting the mask bits of the decimal number obtained in step L2 to 0, and setting the remaining mask bits to 1, starting from the starting bit of the mask start end determined in step L1.

[0093] In the 8-bit mask Y of this embodiment, the mask bits can be defined from left to right as: Y7 / Y6 / Y5 / Y4 / Y3 / Y2 / Y1 / Y0 or Y0 / Y1 / Y2 / Y3 / Y4 / Y5 / Y6 / Y7, and the starting bit at one end of the mask is Y0 or Y7. When the mask bits from left to right are: Y7 / Y6 / Y5 / Y4 / Y3 / Y2 / Y1 / Y0, the leftmost end of the mask is the starting end, and the obtained decimal is 5, 5 mask bits are set to 0 and 3 mask bits are set to 1, specifically: mask bits Y4 / Y3 / Y2 / Y1 / Y0 are set to 0, and the remaining mask bits Y7 / Y6 / Y5 are set to 1.

[0094] Step L7 includes:

[0095] L71: traverse the logical expressions simplified in step L6, and obtain common items composed of binary bits, where the common items refer to the same logical parts existing in two or more logical expressions;

[0096] L72: Loop through step L71 to get all common items;

[0097] L73: sort the common items obtained in step L72 from small to large according to the number of bits constituting the common items;

[0098] L74: Design the circuit structure using gate-level circuits starting from the common items consisting of 2 bits according to the order of step L73.

[0099] Embodiment 2

[0100] This embodiment provides a circuit structure design based on the embodiment 1. The circuit structure design process includes:

[0101] C1: Determine the logic function as follows: convert the input binary number into a plurality of high and low levels, the high and low levels constitute a mask, wherein the total number of high and low levels is the binary state number, and the number of low levels is the decimal number converted from the binary number;

[0102] C2: Establish a truth table of the binary number output mask according to the logic function of step C1;

[0103] C3: Obtain the logical expression of each bit of the mask according to the truth table established in step C2;

[0104] C4: Use the Karnaugh map to simplify the logical expression of step C3;

[0105] C5: Based on the simplified logic expression in step C4, the circuit structure is designed using gate-level circuits;

[0106] In the circuit structure for generating the mask, the start bit at one end of the mask is connected to a high level.

[0107] In step C1, if Figure 1 As shown in the structural block diagram of the generation mask, the circuit structure of this embodiment inputs a 3-bit binary number, and the total number of states of the binary number is 2 3 =8, that is, three binary numbers can generate eight-bit masks, its input is three binary numbers A2A1A0, and its output is eight high and low level signals Y0~Y7. The high level logic is 1, and the low level logic is 0.

[0108] In step C2, the truth table of the output mask of the input three-bit binary number is shown in Table 1 below.

[0109]

[0110] According to the truth table shown in Table 1, the corresponding logical expression is written. It can be seen that the output Y0~Y7 is the minimum term accumulation of the three input variables A2A1A0.

[0111] In steps C3 and C4, the logic expression of each bit of the mask is obtained according to the truth table established in step C2, and then the logic expression of step C3 can be simplified by the Karnaugh map. The logic expression is simplified to the following formula:

[0112] = =

[0113] = ' =

[0114] = =

[0115] = =

[0116] = =

[0117] = =

[0118] = =

[0119] = 1 =

[0120] By analogy, when the input is more than 3 bits, the same method can be used to obtain the logical expression of each bit of the mask.

[0121] Step C5 includes:

[0122] C51: traverse the logical expressions simplified in step C4, and obtain common items composed of binary bits, where the common items refer to the same logical parts existing in two or more logical expressions;

[0123] C52: loop through step C51 to obtain all common items; in this embodiment, the common items include: A2+A1; A1+A0; A2; A1; A0; ;

[0124] C53: sort the common items obtained in step C52 from small to large according to the number of bits constituting the common items; in this embodiment, the common items are sorted as follows: A2; A1; A0; A2+A1; A1+A0; ;

[0125] C54: Design the circuit structure using gate-level circuits starting from the common item consisting of 2 bits according to the order in step C53. In this embodiment, the common item consisting of 2 bits is: A2+A1; A1+A0; ; Among them, A2+A1; A1+A0 are common items with the same bit number (composed of 2 bits), the same operation method (all are OR operations), and the same bit (the same bit is A1), so choose one of the common items to start the subsequent circuit design. ; For common items with the same bit number (composed of 2 bits), the same operation method (all AND operations), and the same bit (the same bit is A1), one of the common items is selected to start the subsequent circuit design. In this embodiment, there is no common item composed of more than 2 bits. When there is a common item composed of more than 2 bits, after the common item composed of 2 bits is designed, the common item composed of 3 bits is designed, and so on.

[0126] This embodiment uses A1+A0 and Start subsequent circuit design, such as Figure 2 As shown, the circuit structure includes: a first OR gate, a second OR gate, a third OR gate, a fourth OR gate, a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a first NOT gate, a second NOT gate, a third NOT gate, a fourth NOT gate, a fifth NOT gate, a sixth NOT gate and a seventh NOT gate;

[0127] The specific construction process is:

[0128] According to A1+A0, add the first OR gate, A1 and A0 are connected to the two input terminals of the first OR gate respectively; according to Add the first AND gate, and connect A1 and A0 to the two input terminals of the first AND gate respectively;

[0129] According to the logical expression of Y0, add a second OR gate, and connect the output of the first OR gate to one input of the second OR gate; the other input of the second OR gate is connected to A2; add a first NOT gate; the output of the second OR gate is connected to the input of the first NOT gate, and the output of the first NOT gate is connected to Y0; thus, the circuit structure of the binary number A2A1A0 output mask bit Y0 is completed.

[0130] According to the logical expression of Y1, add a third OR gate, and connect A2 and A1 to the two input terminals of the third OR gate respectively; add a second NOT gate, and connect the output terminal of the third OR gate to the input terminal of the second NOT gate; the output terminal of the second NOT gate is connected to Y1; thus, the circuit structure of the binary number A2A1A0 output mask bit Y1 is completed.

[0131] According to the logical expression of Y2, add a fourth OR gate, the output end of the first AND gate is connected to one input end of the fourth OR gate, and the other input end of the fourth OR gate is connected to A2; add a third NOT gate, the output end of the fourth OR gate is connected to the input end of the third NOT gate, and the output end of the third NOT gate is connected to Y2; thus, the circuit structure of the binary number A2A1A0 output mask bit Y2 is completed;

[0132] According to the logical expression of Y3, add the fourth NOT gate, A2 is connected to the input end of the fourth NOT gate, and the output end of the fourth NOT gate is connected to Y3; thus, the circuit structure of the binary number A2A1A0 output mask bit Y3 is completed;

[0133] According to the logic expression of Y4, add a second AND gate, A2 is connected to one input of the second AND gate, and the output of the first OR gate is connected to the other input of the second AND gate; add a fifth NOT gate, the output of the second AND gate is connected to the input of the fifth NOT gate, and the output of the fifth NOT gate is connected to Y4; thus, the circuit structure of the binary number A2A1A0 output mask bit Y4 is completed;

[0134] According to the logical expression of Y5, add a third AND gate, A2 and A1 are connected to the two input ends of the third AND gate respectively; add a sixth NOT gate, the output end of the third AND gate is connected to the input end of the sixth NOT gate, and the output end of the sixth NOT gate is connected to Y5; thus, the circuit structure of the binary number A2A1A0 output mask bit Y5 is completed;

[0135] According to the logic expression of Y6, add a fourth AND gate, A2 is connected to one input of the fourth AND gate, and the output of the first AND gate is connected to the other input of the fourth AND gate; add a seventh NOT gate, the output of the fourth AND gate is connected to the input of the seventh NOT gate, and the output of the seventh NOT gate is connected to Y6; thus, the circuit structure of the binary number A2A1A0 output mask bit Y6 is completed;

[0136] According to the logic expression of Y7, Y7 is connected to a high level, thus completing the circuit structure of the binary number A2A1A0 output mask bit Y7;

[0137] In summary, the circuit structure of outputting three-bit binary numbers into eight-bit masks is completed.

[0138] For example, 101 => 1110 0000. Taking the generation of eight bits from three binary numbers as an example, unlike the existing solution that uses ALU to perform shift operations and equips each bit output with an eight-to-one data selector, the circuit structure of the present invention can obtain the output bit through only three gate-level circuits at most (when outputting Y0 / Y2 / Y4 / Y6), and only one gate-level circuit at least (when outputting Y7). The mask generation process consumes fewer resources, the circuit is simpler, the cost and energy consumption are lower, and the operation speed is faster.

[0139] By analogy, when the number of binary digits input is not 3, the same design process can be used to obtain the circuit structure for generating the mask.

[0140] Embodiment three:

[0141] This embodiment provides a device for selecting instructions, including: a preprocessing module, a calculation module, an acquisition module and a selection module;

[0142] The selection module is used to sort the queue ready information in the reservation station according to the priority, and obtain the ready queue and queue pointer mask of the reservation station, wherein the mask includes an all-1 part in which all bits are 1, and the all-1 part is the area where the highest priority is located;

[0143] The operation module is used to perform AND operation on the ready queue obtained by the selection module and the mask, and perform AND operation on the ready queue obtained by the selection module and the inverse of the mask to obtain an AND operation result;

[0144] The acquisition module is used to acquire the ready queue bit corresponding to the ready instruction in the result of the operation module through the priority encoder;

[0145] The selection module is used for selecting the ready instruction corresponding to the ready queue bit in the mask phase and result when the ready queue bit obtained by the acquisition module exists in the mask phase and result;

[0146] When the ready queue bit in the acquisition module exists only in the inverted phase AND result, the ready instruction corresponding to the ready queue bit in the inverted phase AND result is selected.

[0147] Embodiment 4:

[0148] This embodiment introduces a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the steps of the method described in the embodiment 1 or 2 of the claim are implemented.

[0149] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0150] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0151] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0152] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0153] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for selecting an instruction, characterized in that: include: S1: sorting the queue ready information in the reservation station by priority, obtaining the ready queue and queue pointer mask of the reservation station, wherein the mask includes an all-1 part where all bits are 1, and the all-1 part is the area where the highest priority is located; S2: perform AND operation on the ready queue obtained in step S1 and the mask, and perform AND operation on the ready queue obtained in step S1 and the inverse of the mask to obtain an AND operation result; S3: Obtain the ready queue bit corresponding to the ready instruction in the result of step S2 through the priority encoder; S4: When the ready queue bit obtained in step S3 exists in the mask phase AND result, select the ready instruction corresponding to the ready queue bit in the mask phase AND result; When the ready queue bit only exists in the inverted AND result in step S3, the ready instruction corresponding to the ready queue bit in the inverted AND result is selected.

2. The method for selecting an instruction according to claim 1, characterized in that: The queue pointer is a binary number. In step S1, the mask generation method includes: L1: Obtain an input binary number, and determine the number of bits of the mask according to the number of bits of the binary number; L2: Convert the binary number obtained in step L1 into decimal; L3: Set the bits of the decimal number in step L2 in the mask bit of step L1 to 0, and set the remaining bits to 1; L4: Loop through steps L1 to L3 to create a truth table for the binary output mask of the bit number in step L1; L5: Obtain the logical expression of each bit of the mask according to the truth table established in step L4; L6: Use the Karnaugh map to simplify the logical expression of step L5; L7: Based on the simplified logic expression in step L6, the circuit structure is designed using gate-level circuits; L8: Generate a mask using the circuit structure designed in step L7.

3. The method for selecting an instruction according to claim 2, characterized in that: In step L1, determining the number of bits of the mask according to the number of bits of the binary number includes: the number of bits of the mask is the binary number state number, when the number of bits of the binary number is n, the number of bits of the mask is 2 n , n is a positive integer.

4. The method for selecting an instruction according to claim 3, characterized in that: Step L1 also includes: determining one end of the mask as the starting end; Step L3 includes: according to the decimal number obtained in step L2, starting from the starting bit of the mask starting end determined in step L1, setting the mask bits of the decimal number to 0, and setting the remaining mask bits to 1.

5. The method for selecting an instruction according to claim 2, characterized in that: Step L7 includes: L71: traverse the logical expressions simplified in step L6, and obtain common items composed of binary bits, where the common items refer to the same logical parts existing in two or more logical expressions; L72: Loop through step L71 to get all common items; L73: sort the common items obtained in step L72 from small to large according to the number of bits constituting the common items; L74: Design the circuit structure using gate-level circuits starting from the common items consisting of 2 bits according to the order of step L73.

6. The method for selecting an instruction according to claim 4, characterized in that: When the mask is generated by using a circuit structure, the start bit at one end of the mask is connected to a high level.

7. The method for selecting an instruction according to claim 4, characterized in that: When the input three-bit binary number A bits are A2A1A0 respectively, the generated mask Y bits are Y7 / Y6 / Y5 / Y4 / Y3 / Y2 / Y1 / Y0 respectively, and Y0 is the starting end, the logical expression of each bit of the mask Y after simplification in step L6 is: = ； = ； = ； = ； = ； = ； = ； = 1。 8. The method for selecting an instruction according to claim 7, characterized in that: The circuit structure of step L7 includes: a first OR gate, a second OR gate, a third OR gate, a fourth OR gate, a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a first NOT gate, a second NOT gate, a third NOT gate, a fourth NOT gate, a fifth NOT gate, a sixth NOT gate and a seventh NOT gate; The construction process of the circuit structure includes: A1 and A0 are connected to the two input terminals of the first OR gate respectively; A1 and A0 are connected to two input terminals of the first AND gate respectively; According to the logical expression of Y0, the output end of the first OR gate is connected to one input end of the second OR gate, the other input end of the second OR gate is connected to A2, the output end of the second OR gate is connected to the input end of the first NOT gate, and the output end of the first NOT gate is connected to Y0; According to the logical expression of Y1, A2 and A1 are respectively connected to the two input terminals of the third OR gate, the output terminal of the third OR gate is connected to the input terminal of the second NOT gate, and the output terminal of the second NOT gate is connected to Y1; According to the logic expression of Y2, the output end of the first AND gate is connected to one input end of the fourth OR gate, the other input end of the fourth OR gate is connected to A2, the output end of the fourth OR gate is connected to the input end of the third NOT gate, and the output end of the third NOT gate is connected to Y2; According to the logical expression of Y3, A2 is connected to the input of the fourth NOT gate, and the output of the fourth NOT gate is connected to Y3; According to the logic expression of Y4, A2 is connected to one input terminal of the second AND gate, the output terminal of the first OR gate is connected to the other input terminal of the second AND gate, the output terminal of the second AND gate is connected to the input terminal of the fifth NOT gate, and the output terminal of the fifth NOT gate is connected to Y4; According to the logic expression of Y5, A2 and A1 are respectively connected to the two input terminals of the third AND gate, the output terminal of the third AND gate is connected to the input terminal of the sixth NOT gate, and the output terminal of the sixth NOT gate is connected to Y5; According to the logic expression of Y6, A2 is connected to one input terminal of the fourth AND gate, the output terminal of the first AND gate is connected to the other input terminal of the fourth AND gate, the output terminal of the fourth AND gate is connected to the input terminal of the seventh NOT gate, and the output terminal of the seventh NOT gate is connected to Y6; According to the logical expression of Y7, Y7 is connected to a high level.

9. A device for selecting an instruction, characterized in that: include: Preprocessing module, operation module, acquisition module and selection module; The selection module is used to sort the queue ready information in the reservation station according to the priority, and obtain the mask of the ready queue and queue pointer of the reservation station, wherein the mask includes an all-1 part in which all bits are 1, and the all-1 part is the area where the highest priority is located; The operation module is used to perform AND operation on the ready queue obtained by the selection module and the mask, and perform AND operation on the ready queue obtained by the selection module and the inverse of the mask to obtain an AND operation result; The acquisition module is used to acquire the ready queue bit corresponding to the ready instruction in the result of the operation module through the priority encoder; The selection module is used for selecting the ready instruction corresponding to the ready queue bit in the mask phase and result when the ready queue bit obtained by the acquisition module exists in the mask phase and result; When the ready queue bit in the acquisition module exists only in the inverted phase AND result, the ready instruction corresponding to the ready queue bit in the inverted phase AND result is selected.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps of the method according to any one of claims 1 to 8 are implemented.

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