A method, apparatus and storage medium for selecting an instruction

Abstract

The application discloses a method, device and storage medium for selecting instructions, and belongs to the computer field. The method comprises the following steps: sorting queue ready information in a reservation station according to priorities, obtaining a ready queue and a mask of a queue pointer of the reservation station, and the all-1 part of the mask being a highest priority area; performing an AND operation on the ready queue and the mask, and performing an AND operation on the ready queue and the inverse code of the mask, obtaining and acquiring queue bits corresponding to ready instructions in the AND operation result through a priority encoder; when the acquired queue bits exist in the mask AND operation result, selecting the ready instructions in the mask AND operation result; otherwise, selecting the ready instructions in the inverse code AND operation result. The application aims at solving the problems of high energy consumption and high calculation cost of a processor in selecting currently highest priority ready instructions.

Description

Technical Field

[0001] The present invention relates to the field of computers, and in particular to a method, device and storage medium for selecting instructions. Background Art

[0002] A superscalar processor is a high-performance processor technology that improves processor throughput and performance by executing multiple instructions concurrently and using out-of-order execution techniques. The advantage of superscalar processors is that they can significantly improve processor throughput and performance. By executing multiple instructions concurrently and using out-of-order execution techniques, superscalar processors can more efficiently utilize processor resources and increase instruction parallelism. This makes superscalar processors more efficient when handling complex computing tasks.

[0003] However, superscalar processor design also faces some challenges. For example, how to achieve accurate branch prediction, how to handle dependency checks between load / store instructions, and how to balance hardware complexity and power consumption are all important factors that need to be considered in superscalar processor design.

[0004] The issue unit is the fundamental unit responsible for scheduling instructions. Every clock cycle, a superscalar processor must select an idle reservation station and fill it with instructions awaiting dispatch. Furthermore, the processor must identify the oldest ready instruction in the reservation station and issue a number of these instructions to the execution units. The number of instructions issued typically depends on the number of execution units.

[0005] These processes require the arbiter to have the ability to quickly select, but the reservation station of the circular queue selects the oldest ready instruction by shifting. This mechanism does not physically move the instruction, but logically selects the next instruction to be executed by updating the pointer or index. In order to select the oldest ready instruction, the processor needs to constantly check the status of the instructions in the queue and adjust the order of the instructions in the queue accordingly. This adjustment usually involves a shift operation to ensure that the oldest ready instruction is at the front of the queue for fast access by the processor.

[0006] The existing solution is for computer processors to use the ALU to perform calculations using shift instructions. Shifting here refers to selecting a position. This calculation requires a data selector for each bit output, which is computationally expensive. A data selector is a multiplexer that selects an output from multiple input signals. During the execution of a shift instruction, the data selector selects the bit to be shifted and outputs it to the specified position.

[0007] The existing solutions not only have high hardware resource requirements, but more importantly, they will cause large delays, thus becoming a significant bottleneck for improving processor performance. Summary of the Invention

[0008] To overcome the above-mentioned deficiencies of the prior art, the present invention provides a method, device and storage medium for selecting instructions, so as to solve the problem of high energy consumption and high computational cost when a processor selects the oldest ready instruction.

[0009] In order to solve the above technical problems, the present invention is implemented by adopting the following technical solutions:

[0010] In a first aspect, the present invention provides a method for selecting an instruction, comprising:

[0011] S1: Sort the queue ready information in the reservation station by priority, obtain the ready queue and queue pointer mask of the reservation station, the mask includes an all-1 part where all bits are 1, and the all-1 part is the area with the highest priority;

[0012] S2: AND the ready queue obtained in step S1 with the mask, and AND the ready queue obtained in step S1 with the inverse of the mask to obtain the AND result;

[0013] S3: Obtain the ready queue bit corresponding to the ready instruction in the result of step S2 through the priority encoder;

[0014] S4: When the ready queue bit obtained in step S3 exists in the mask phase AND result, select the ready instruction corresponding to the ready queue bit in the mask phase AND result;

[0015] When the ready queue bit exists only in the inverted AND result in step S3, the ready instruction corresponding to the ready queue bit in the inverted AND result is selected.

[0016] In the aforementioned method for selecting instructions, the queue pointer is a binary number. In step S1, the mask generation method includes:

[0017] L1: Obtain an input binary number and determine the number of bits of the mask according to the number of bits of the binary number;

[0018] L2: Convert the binary number obtained in step L1 into decimal;

[0019] L3: Set the bits corresponding to the decimal number in step L2 in the mask bits of step L1 to 0, and set the remaining bits to 1;

[0020] L4: Loop through steps L1 to L3 to create a truth table for the binary output mask of the bit number in step L1.

[0021] L5: Obtain the logical expression of each bit of the mask according to the truth table established in step L4;

[0022] L6: Use the Karnaugh map to simplify the logical expression of step L5;

[0023] L7: Based on the simplified logic expression in step L6, design the circuit structure using gate-level circuits;

[0024] L8: Generate a mask using the circuit structure designed in step L7.

[0025] The above-mentioned method for selecting an instruction, in step L1, determining the number of bits of the mask according to the number of bits of the binary number includes: the number of bits of the mask is a binary number state number, when the number of bits of the binary number is n, the number of bits of the mask is 2 n , n is a positive integer.

[0026] In the aforementioned method for selecting instructions, step L1 also includes: determining one end of the mask as the starting end; step L3 includes: according to the decimal number obtained in step L2, starting from the starting bit of the mask starting end determined in step L1, setting the mask bits of the decimal number to 0 and the remaining mask bits to 1.

[0027] In the aforementioned method for selecting an instruction, step L7 includes:

[0028] L71: Traverse the logical expressions simplified in step L6 to obtain common items composed of binary bits. The common items refer to the same logical parts existing in two or more logical expressions;

[0029] L72: Loop through step L71 to get all common items;

[0030] L73: Sort the common items obtained in step L72 from least to most in terms of the number of bits that make up the common items;

[0031] L74: Design the circuit structure using gate-level circuits starting from the common items consisting of 2 bits according to the order in step L73.

[0032] In the aforementioned method for selecting an instruction, when a circuit structure is used to generate the aforementioned mask, the start bit at one end of the mask is connected to a high level.

[0033] In the aforementioned method for selecting instructions, when the three bits of the input binary number A are A2A1A0, and the generated mask Y bits are Y7 / Y6 / Y5 / Y4 / Y3 / Y2 / Y1 / Y0, with Y0 being the starting point, the logical expression of each bit of the mask Y after simplification in step L6 is:

[0034] = ;

[0035] = ;

[0036] = ;

[0037] = ;

[0038] = ;

[0039] = ;

[0040] = ;

[0041] = 1.

[0042] In the aforementioned method for selecting an instruction, the circuit structure of step L7 includes: a first OR gate, a second OR gate, a third OR gate, a fourth OR gate, a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a first NOT gate, a second NOT gate, a third NOT gate, a fourth NOT gate, a fifth NOT gate, a sixth NOT gate, and a seventh NOT gate;

[0043] The construction process of the circuit structure includes:

[0044] A1 and A0 are connected to the two input terminals of the first OR gate respectively;

[0045] A1 and A0 are connected to the two input terminals of the first AND gate respectively;

[0046] According to the logical expression of Y0, the output of the first OR gate is connected to one input of the second OR gate, the other input of the second OR gate is connected to A2, the output of the second OR gate is connected to the input of the first NOT gate, and the output of the first NOT gate is connected to Y0;

[0047] According to the logical expression of Y1, A2 and A1 are connected to the two input terminals of the third OR gate respectively, the output terminal of the third OR gate is connected to the input terminal of the second NOT gate, and the output terminal of the second NOT gate is connected to Y1;

[0048] According to the logical expression of Y2, the output of the first AND gate is connected to one input of the fourth OR gate, the other input of the fourth OR gate is connected to A2, the output of the fourth OR gate is connected to the input of the third NOT gate, and the output of the third NOT gate is connected to Y2;

[0049] According to the logical expression of Y3, A2 is connected to the input of the fourth NOT gate, and the output of the fourth NOT gate is connected to Y3;

[0050] According to the logic expression of Y4, A2 is connected to one input of the second AND gate, the output of the first OR gate is connected to the other input of the second AND gate, the output of the second AND gate is connected to the input of the fifth NOT gate, and the output of the fifth NOT gate is connected to Y4;

[0051] According to the logical expression of Y5, A2 and A1 are connected to the two input terminals of the third AND gate respectively, the output terminal of the third AND gate is connected to the input terminal of the sixth NOT gate, and the output terminal of the sixth NOT gate is connected to Y5;

[0052] According to the logic expression of Y6, A2 is connected to one input of the fourth AND gate, the output of the first AND gate is connected to the other input of the fourth AND gate, the output of the fourth AND gate is connected to the input of the seventh NOT gate, and the output of the seventh NOT gate is connected to Y6;

[0053] According to the logic expression of Y7, Y7 is connected to a high level.

[0054] In a second aspect, the present invention provides a device for selecting an instruction, comprising: a preprocessing module, a calculation module, an acquisition module, and a selection module;

[0055] The selection module is used to sort the queue ready information in the reservation station according to priority, obtain the ready queue and queue pointer mask of the reservation station, the mask includes an all-1 part where all bits are 1, and the all-1 part is the area with the highest priority;

[0056] The operation module is used to perform an AND operation on the ready queue obtained by the selection module and the mask, and perform an AND operation on the ready queue obtained by the selection module and the inverse of the mask to obtain an AND result;

[0057] The acquisition module is used to acquire the ready queue bit corresponding to the ready instruction in the result of the operation module through the priority encoder;

[0058] The selection module is used for selecting the ready instruction corresponding to the ready queue bit in the mask phase AND result when the ready queue bit obtained by the acquisition module exists in the mask phase AND result;

[0059] When the ready queue bit in the acquisition module exists only in the inverted phase AND result, the ready instruction corresponding to the ready queue bit in the inverted phase AND result is selected.

[0060] In a third aspect, a computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of any one of the methods described in the first aspect.

[0061] Compared with the prior art, the present invention has the following beneficial effects:

[0062] The present invention adopts a mask instead of a shift operation when selecting the highest priority ready instruction in a reservation station. The present invention does not require shifting. When the mask is not all 1s, the ready instructions are searched for simultaneously in two blocks, and the ready instructions in the area where the highest priority is located are output preferentially. Complex shift operations are not required, thereby accelerating the calculation speed of the instruction selection process and reducing energy consumption and calculation costs. When the highest priority is set to the oldest, the present invention can be used to solve the problem of high energy consumption and high calculation cost when the processor selects the currently oldest ready instruction.

[0063] In order to further reduce the energy consumption and computational cost of mask generation, the present invention uses specially designed gate-level circuits to generate masks. Compared with traditional shift calculation methods, the mask generation process composed of simple gate-level circuits consumes fewer resources, has simpler circuits, lower costs and energy consumption, and faster computing speed.

[0064] The method and circuit structure for generating a mask of the present invention can be flexibly adjusted according to the number of bits of an input binary number, and can adaptively generate corresponding masks for application in a wider range of application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] Figure 1 This is a structural block diagram of a three-bit binary number generation mask according to embodiment 2 of the present invention;

[0066] Figure 2 This is a schematic diagram of a circuit structure for generating a mask according to embodiment 2 of the present invention. DETAILED DESCRIPTION

[0067] The technical solution of the present invention is described in detail below through the accompanying drawings and specific embodiments. It should be understood that the embodiments of the present application and the specific features in the embodiments are detailed descriptions of the technical solution of the present application, rather than limitations on the technical solution of the present application. Unless there is a conflict, the embodiments of the present application and the technical features in the embodiments can be combined with each other.

[0068] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integral connections; mechanical connections, electrical connections, or mutual communication; direct connections or indirect connections through an intermediate medium; and internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0069] The term "and / or" in this document simply describes a relationship between related objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, or B exists alone. Additionally, the character " / " in this document generally indicates an "or" relationship between the related objects.

[0070] Example 1:

[0071] This embodiment provides a method for selecting an instruction, for selecting a highest priority ready instruction in a reservation station, comprising:

[0072] S1: Sort the queue readiness information in the reservation station by priority, and obtain the ready queue and queue pointer mask of the reservation station. The mask includes an all-1 portion where all bits are 1. The all-1 portion is the area where the highest priority is located. The queue pointer is a binary number. In this embodiment, the highest priority ready queue is on the left side of the queue, so the left side of the mask is the all-1 portion.

[0073] S2: AND the ready queue obtained in step S1 with the mask, and AND the ready queue obtained in step S1 with the inverse of the mask to obtain the AND result;

[0074] When all the mask bits are 1, only the ready queue obtained in step S1 is ANDed with the mask; when not all the mask bits are 1, step S2 divides the ready queue into two parts by the mask;

[0075] S3: Obtain the ready queue bit corresponding to the ready instruction in the result of step S2 through the priority encoder;

[0076] When the mask bits are not all 1, step S3 searches for the ready queue bits where the ready instructions are located in parallel in the two parts of the ready queue divided by the mask;

[0077] S4: When the ready queue bit obtained in step S3 exists in the masked AND result, select the ready instruction corresponding to the ready queue bit in the masked AND result;

[0078] When the ready queue bit exists only in the inverted AND result in step S3, the ready instruction corresponding to the ready queue bit in the inverted AND result is selected.

[0079] In the ready queue bit where the ready instruction is located, if there is a ready instruction in the area where the highest priority is located (in the mask phase and result), the ready instruction in this area is selected; if the ready instruction only exists in the inverse phase and result, the ready instruction in this area is selected.

[0080] Compared with the original operation of shifting and selecting the ready instruction, the application does not need to shift, when the mask is not all 1, searches the ready instruction in two blocks at the same time, preferentially outputs the ready instruction in the area where the highest priority is located, does not need complex shift operation, speeds up the calculation speed of the instruction selection process, and reduces energy consumption and calculation cost.

[0081] The queue pointer is a binary number, and the generation method of the mask in step S1 includes:

[0082] L1: obtaining an input binary number, and determining the number of mask bits according to the number of bits of the binary number;

[0083] L2: converting the binary number obtained in step L1 into a decimal number;

[0084] L3: setting the bits of the mask bits in step L1 corresponding to the number of bits of the decimal number obtained in step L2 to 0, and setting the remaining mask bits to 1;

[0085] L4: cyclically executing steps L1 to L3 to establish a truth table of the binary number of the number of bits in step L1 output mask;

[0086] L5: obtaining a logic expression of each bit of the mask according to the truth table established in step L4;

[0087] L6: simplifying the logic expression in step L5 by using a Karnaugh map; the Karnaugh map simplification can obtain the simplest logic expression;

[0088] L7: designing a circuit structure by using a gate-level circuit according to the simplified logic expression in step L6;

[0089] L8: generating the mask by using the circuit structure designed in step L7.

[0090] In step L1, determining the number of mask bits according to the number of bits of the binary number includes that the number of mask bits is the number of binary states, and when the number of bits of the binary number is n, the number of mask bits is 2 n n, n is a positive integer. In this embodiment, the number of bits of the input binary number is 3, and the number of bits of the generated mask is 2 3 =8.

[0091] Step L1 further includes determining that one end of the mask is a starting end;

[0092] Step L3 includes starting from the starting bit of the starting end of the mask determined in step L1, setting the mask bits corresponding to the number of bits of the decimal number obtained in step L2 to 0, and setting the remaining mask bits to 1.

[0093] In the 8-bit mask Y of this embodiment, the mask bits can be defined from left to right as: Y7 / Y6 / Y5 / Y4 / Y3 / Y2 / Y1 / Y0 or Y0 / Y1 / Y2 / Y3 / Y4 / Y5 / Y6 / Y7, and the starting bit at one end of the mask is Y0 or Y7. When the mask bits from left to right are: Y7 / Y6 / Y5 / Y4 / Y3 / Y2 / Y1 / Y0, the leftmost end of the mask is the starting end, and the obtained decimal value is 5, 5 mask bits are set to 0 and 3 mask bits are set to 1. Specifically, mask bits Y4 / Y3 / Y2 / Y1 / Y0 are set to 0, and the remaining mask bits Y7 / Y6 / Y5 are set to 1.

[0094] Step L7 includes:

[0095] L71: Traverse the logical expressions simplified in step L6 to obtain common items composed of binary bits. The common items refer to the same logical parts existing in two or more logical expressions;

[0096] L72: Loop through step L71 to get all common items;

[0097] L73: Sort the common items obtained in step L72 from least to most by the number of bits that make up the common items;

[0098] L74: Design the circuit structure using gate-level circuits starting from the common items consisting of 2 bits according to the order in step L73.

[0099] Example 2

[0100] This embodiment provides a circuit structure design based on the first embodiment. The circuit structure design process includes:

[0101] C1: Determine the logical function as follows: convert the input binary number into multiple high and low levels, which form a mask, where the total number of high and low levels is the number of binary state states, and the number of low levels is the decimal number converted from the binary number;

[0102] C2: Create a truth table for the binary output mask based on the logic function of step C1;

[0103] C3: Obtain the logical expression of each bit of the mask according to the truth table established in step C2;

[0104] C4: Use the Karnaugh map to simplify the logical expression of step C3;

[0105] C5: Based on the simplified logic expression in step C4, design the circuit structure using gate-level circuits;

[0106] In the circuit structure for generating the mask, the start bit at one end of the mask is connected to a high level.

[0107] In step C1, if Figure 1 As shown in the structural block diagram of the generation mask, the circuit structure of this embodiment inputs a 3-bit binary number, and the total number of states of the binary number is 2 3 =8, that is, a three-bit binary number can generate an eight-bit mask. Its input is a three-bit binary number A2A1A0, and its output is an eight-bit high- and low-level signal Y0 to Y7. The high level is logically expressed as 1, and the low level is logically expressed as 0.

[0108] In step C2, the truth table of the output mask of the input three-bit binary number is shown in Table 1 below.

[0109]

[0110] According to the truth table shown in Table 1, the corresponding logic formula can be written. It can be seen that the output Y0~Y7 is the minimum term accumulation of the three input variables A2A1A0.

[0111] In steps C3 and C4, the logical expression of each bit of the mask is obtained according to the truth table established in step C2. Then, the logical expression of step C3 can be simplified by the Karnaugh map. The logical expression is simplified to the following formula:

[0112] = =

[0113] = ' =

[0114] = =

[0115] = =

[0116] = =

[0117] = =

[0118] = =

[0119] = 1 =

[0120] Similarly, when the input is more than 3 bits, the same method can be used to obtain the logical expression of each bit of the mask.

[0121] Step C5 includes:

[0122] C51: Traverse the logical expressions simplified in step C4 to obtain common items composed of binary bits, where the common items refer to the same logical parts existing in two or more logical expressions;

[0123] C52: Loop through step C51 to obtain all common items; in this embodiment, the common items include: A2+A1; A1+A0; A2; A1; A0; ;

[0124] C53: Sort the common items obtained in step C52 from least to most by the number of bits that make up the common items. In this embodiment, the order of the common items is: A2; A1; A0; A2+A1; A1+A0; ;

[0125] C54: Based on the order in step C53, the circuit structure is designed using gate-level circuits starting from the common item consisting of 2 bits. In this embodiment, the common item consisting of 2 bits is: A2+A1; A1+A0; ; Among them, A2+A1; A1+A0 are common items with the same number of bits (composed of 2 bits), the same operation method (both are OR operations), and the same bit (the same bit is A1). Then select one of the common items to start the subsequent circuit design. ; For common items with the same bit number (2 bits), the same operation method (all AND operations), and the same bit (the same bit is A1), select one of the common items to begin subsequent circuit design. This embodiment does not have common items with more than 2 bits. When common items with more than 2 bits are present, after designing the common items with 2 bits, design the common items with 3 bits, and so on.

[0126] This embodiment uses A1+A0 and Start subsequent circuit design, such as Figure 2 As shown, the circuit structure includes: a first OR gate, a second OR gate, a third OR gate, a fourth OR gate, a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a first NOT gate, a second NOT gate, a third NOT gate, a fourth NOT gate, a fifth NOT gate, a sixth NOT gate and a seventh NOT gate;

[0127] The specific construction process is:

[0128] Add the first OR gate according to A1+A0, and connect A1 and A0 to the two input terminals of the first OR gate respectively; Add the first AND gate, and connect A1 and A0 to the two input terminals of the first AND gate respectively;

[0129] According to the logical expression of Y0, add a second OR gate, connect the output of the first OR gate to one input of the second OR gate; connect the other input of the second OR gate to A2; add a first NOT gate; connect the output of the second OR gate to the input of the first NOT gate, and connect the output of the first NOT gate to Y0; thus, the circuit structure of the binary number A2A1A0 output mask bit Y0 is completed.

[0130] According to the logical expression of Y1, add a third OR gate, connect A2 and A1 to its two input terminals respectively; add a second NOT gate, connect the output terminal of the third OR gate to the input terminal of the second NOT gate; connect the output terminal of the second NOT gate to Y1; thus, the circuit structure of the binary number A2A1A0 output mask bit Y1 is completed.

[0131] According to the logical expression of Y2, add a fourth OR gate. Connect the output of the first AND gate to one input of the fourth OR gate, and the other input of the fourth OR gate to A2. Add a third NOT gate. Connect the output of the fourth OR gate to the input of the third NOT gate, and the output of the third NOT gate to Y2. This completes the circuit structure for outputting the mask bit Y2 of the binary number A2A1A0.

[0132] According to the logical expression of Y3, add a fourth NOT gate, connect A2 to the input of the fourth NOT gate, and connect the output of the fourth NOT gate to Y3. This completes the circuit structure of the binary number A2A1A0 output mask bit Y3.

[0133] Based on the logical expression of Y4, add a second AND gate, connect A2 to one input of the second AND gate, and connect the output of the first OR gate to the other input of the second AND gate. Add a fifth NOT gate, connect the output of the second AND gate to the input of the fifth NOT gate, and connect the output of the fifth NOT gate to Y4. This completes the circuit structure for outputting the binary number A2A1A0 as the mask bit Y4.

[0134] According to the logical expression of Y5, add a third AND gate, connecting A2 and A1 to its two inputs respectively. Add a sixth NOT gate, connecting the output of the third AND gate to the input of the sixth NOT gate, and the output of the sixth NOT gate to Y5. This completes the circuit structure for outputting the binary number A2A1A0 mask bit Y5.

[0135] Based on the logical expression of Y6, add a fourth AND gate, connect A2 to one input of the fourth AND gate, and connect the output of the first AND gate to the other input of the fourth AND gate. Add a seventh NOT gate, connect the output of the fourth AND gate to the input of the seventh NOT gate, and connect the output of the seventh NOT gate to Y6. This completes the circuit structure for outputting the mask bit Y6 of the binary number A2A1A0.

[0136] According to the logic expression of Y7, Y7 is connected to a high level, thus completing the circuit structure of the binary number A2A1A0 output mask bit Y7;

[0137] In summary, the circuit structure of outputting three-bit binary numbers into an eight-bit mask is completed.

[0138] For example, 101 => 1110 0000. Taking the generation of eight bits from a three-bit binary number as an example, unlike existing solutions that use an ALU to perform shift operations and equip each output with an eight-to-one data selector, the circuit structure of the present invention can obtain the output bit using only three gate-level circuits at most (when outputting Y0 / Y2 / Y4 / Y6) and only one gate-level circuit at least (when outputting Y7). This mask generation process consumes fewer resources, has a simpler circuit, reduces cost and energy consumption, and achieves faster operation speeds.

[0139] Similarly, when the number of binary digits input is not 3, the same design process can be used to obtain the circuit structure for generating the mask.

[0140] Example 3:

[0141] This embodiment provides a device for selecting an instruction, comprising: a preprocessing module, a calculation module, an acquisition module, and a selection module;

[0142] The selection module is used to sort the queue ready information in the reservation station according to priority, obtain the ready queue and queue pointer mask of the reservation station, the mask includes an all-1 part where all bits are 1, and the all-1 part is the area with the highest priority;

[0143] The operation module is used to perform an AND operation on the ready queue obtained by the selection module and the mask, and perform an AND operation on the ready queue obtained by the selection module and the inverse of the mask to obtain an AND operation result;

[0144] The acquisition module is used to acquire the ready queue bit corresponding to the ready instruction in the result of the operation module through the priority encoder;

[0145] The selection module is used for selecting the ready instruction corresponding to the ready queue bit in the mask phase AND result when the ready queue bit obtained by the acquisition module exists in the mask phase AND result;

[0146] When the ready queue bit in the acquisition module exists only in the inverted phase AND result, the ready instruction corresponding to the ready queue bit in the inverted phase AND result is selected.

[0147] Example 4:

[0148] This embodiment introduces a computer-readable storage medium having a computer program stored thereon, which implements the steps of the method described in claim embodiment 1 or 2 when executed by a processor.

[0149] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0150] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0151] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0152] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0153] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for selecting an instruction, characterized in that: include: S1: Sort the queue ready information in the reservation station by priority, obtain the ready queue and queue pointer mask of the reservation station, the mask includes an all-1 part where all bits are 1, and the all-1 part is the area with the highest priority; S2: AND the ready queue obtained in step S1 with the mask, and AND the ready queue obtained in step S1 with the inverse of the mask to obtain the AND result; S3: Obtain the ready queue bit corresponding to the ready instruction in the result of step S2 through the priority encoder; S4: When the ready queue bit obtained in step S3 exists in the mask phase AND result, select the ready instruction corresponding to the ready queue bit in the mask phase AND result; When the ready queue bit in step S3 exists only in the inverted AND result, select the ready instruction corresponding to the ready queue bit in the inverted AND result; In step S1, the mask generation method includes: L1: Obtain an input binary number and determine the number of bits of the mask according to the number of bits of the binary number; L2: Convert the binary number obtained in step L1 into decimal; L3: Set the bits corresponding to the decimal number in step L2 in the mask bit of step L1 to 0, and set the remaining bits to 1; L4: Loop through steps L1 to L3 to create a truth table for the binary output mask of the bit number in step L1. L5: Obtain the logical expression of each bit of the mask according to the truth table established in step L4; L6: Use the Karnaugh map to simplify the logical expression of step L5; L7: Based on the simplified logic expression in step L6, design the circuit structure using gate-level circuits; L8: Generate a mask using the circuit structure designed in step L7; Step L7 includes: L71: Traverse the logical expressions simplified in step L6 to obtain common items composed of binary bits. The common items refer to the same logical parts existing in two or more logical expressions; L72: Loop through step L71 to get all common items; L73: Sort the common items obtained in step L72 from least to most by the number of bits that make up the common items; L74: Designing a circuit structure using gate-level circuits starting from the common item consisting of 2 bits according to the order in step L73; When the bits of the input three-bit binary number A are A2 / A1 / A0 respectively, and the generated mask Y bits are Y7 / Y6 / Y5 / Y4 / Y3 / Y2 / Y1 / Y0 respectively, and Y0 is the starting end, the logical expression of each bit of the mask Y after simplification in step L6 is: = ； = ； = ； = ； = ； = ； = ； = 1； The circuit structure of step L7 includes: a first OR gate, a second OR gate, a third OR gate, a fourth OR gate, a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a first NOT gate, a second NOT gate, a third NOT gate, a fourth NOT gate, a fifth NOT gate, a sixth NOT gate, and a seventh NOT gate; The construction process of the circuit structure includes: A1 and A0 are connected to the two input terminals of the first OR gate respectively; A1 and A0 are connected to the two input terminals of the first AND gate respectively; According to the logical expression of Y0, the output of the first OR gate is connected to one input of the second OR gate, the other input of the second OR gate is connected to A2, the output of the second OR gate is connected to the input of the first NOT gate, and the output of the first NOT gate is connected to Y0; According to the logical expression of Y1, A2 and A1 are connected to the two input terminals of the third OR gate respectively, the output terminal of the third OR gate is connected to the input terminal of the second NOT gate, and the output terminal of the second NOT gate is connected to Y1; According to the logical expression of Y2, the output of the first AND gate is connected to one input of the fourth OR gate, the other input of the fourth OR gate is connected to A2, the output of the fourth OR gate is connected to the input of the third NOT gate, and the output of the third NOT gate is connected to Y2; According to the logical expression of Y3, A2 is connected to the input of the fourth NOT gate, and the output of the fourth NOT gate is connected to Y3; According to the logic expression of Y4, A2 is connected to one input of the second AND gate, the output of the first OR gate is connected to the other input of the second AND gate, the output of the second AND gate is connected to the input of the fifth NOT gate, and the output of the fifth NOT gate is connected to Y4; According to the logical expression of Y5, A2 and A1 are connected to the two input terminals of the third AND gate respectively, the output terminal of the third AND gate is connected to the input terminal of the sixth NOT gate, and the output terminal of the sixth NOT gate is connected to Y5; According to the logic expression of Y6, A2 is connected to one input of the fourth AND gate, the output of the first AND gate is connected to the other input of the fourth AND gate, the output of the fourth AND gate is connected to the input of the seventh NOT gate, and the output of the seventh NOT gate is connected to Y6; According to the logic expression of Y7, Y7 is connected to a high level.

2. The method for selecting an instruction according to claim 1, wherein: In step L1, the number of bits of the mask is determined according to the number of bits of the binary number, which includes: the number of bits of the mask is the binary number state number, and when the number of bits of the binary number is n, the number of bits of the mask is 2. n , n is a positive integer.

3. The method for selecting an instruction according to claim 2, wherein: Step L1 further includes: determining one end of the mask as the starting end; Step L3 includes: according to the decimal number obtained in step L2, starting from the starting bit of the mask starting end determined in step L1, setting the mask bits of the decimal number to 0, and setting the remaining mask bits to 1.

4. The method for selecting an instruction according to claim 1, wherein: When the mask is generated by adopting a circuit structure, the start bit at one end of the mask is connected to a high level.

5. A device for selecting an instruction, characterized in that: The method for executing the selection instruction of claim 1 comprises: a pre-processing module, a calculation module, an acquisition module and a selection module; The selection module is used to sort the queue ready information in the reservation station according to priority, obtain the ready queue and queue pointer mask of the reservation station, the mask includes an all-1 part where all bits are 1, and the all-1 part is the area with the highest priority; The operation module is used to perform an AND operation on the ready queue obtained by the selection module and the mask, and perform an AND operation on the ready queue obtained by the selection module and the inverse of the mask to obtain an AND operation result; The acquisition module is used to acquire the ready queue bit corresponding to the ready instruction in the result of the operation module through the priority encoder; The selection module is used for selecting the ready instruction corresponding to the ready queue bit in the mask phase AND result when the ready queue bit obtained by the acquisition module exists in the mask phase AND result; When the ready queue bit in the acquisition module exists only in the inverted phase AND result, the ready instruction corresponding to the ready queue bit in the inverted phase AND result is selected.

6. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps of the method according to any one of claims 1 to 4 are implemented.

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