Detection circuit and detection device

Abstract

The embodiment of the invention provides a detection circuit and a detection device. The detection circuit comprises a first interface, a control module, a switch module, a first detection module and a data transmission module. The control module is used for detecting whether the solid-state disk is inserted into the first interface; when it is detected that the solid state disk is inserted into the first interface, a first power supply signal is output; when it is detected that the solid state disk is not inserted into the first interface, outputting a first power-off signal; and when the first power consumption data output by the first detection module is received, the first power consumption data is uploaded to the data transmission module. The switch module is used for supplying power to the first interface when receiving the first power supply signal; and when the first power-off signal is received, power supply to the first interface is cut off. The first detection module is used for detecting the current output to the first interface by the switch module in real time and generating first power consumption data. And the data transmission module is used for providing the first power consumption data to the user side when receiving the first power consumption data from the control module so as to improve the detection efficiency.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of electronic circuits, and in particular to a detection circuit and a detection device. Background Art

[0002] When you need to plug or unplug an SSD (Solid State Drive), you need to power off the entire machine. You must first shut down all running software and operating systems. This process may require waiting for some running programs to save data, shut down background processes, etc. Frequent shutdown and startup operations bring inconvenience to users. Summary of the invention

[0003] The embodiments of the present application provide a detection circuit and a detection device, which can realize hot plugging of a solid-state hard disk and detect the power consumption of the solid-state hard disk, thereby improving the test efficiency.

[0004] In a first aspect, an embodiment of the present application provides a detection circuit, the detection circuit comprising: a first interface, a control module, a switch module, a first detection module, and a data transmission module; the first interface is connected to the control module and the switch module respectively, the control module is also connected to the switch module, the first detection module, and the data transmission module respectively, and the switch module is also connected to the first detection module and a first power supply respectively; the control module is used to detect whether the first interface is inserted into a solid-state hard disk; and when it is detected that the first interface is inserted into the solid-state hard disk, it outputs a first power supply signal; when it is detected that the first interface is not inserted into the solid-state hard disk, it outputs a first power-off signal; when receiving the first power consumption data output by the first detection module, the first power consumption data is uploaded to the data transmission module; the switch module is used to supply power to the first interface when receiving the first power supply signal; when receiving the first power-off signal, the power supply to the first interface is disconnected; the first detection module is used to detect the current output by the switch module to the first interface in real time, and generate the first power consumption data; the data transmission module is used to provide the first power consumption data to the user end when receiving the first power consumption data from the control module.

[0005] In some embodiments, the detection circuit also includes a second interface and a second detection module; the second interface is connected to the control module and the switch module respectively, the second detection module is also connected to the switch module, and the control module is also connected to the second detection module; the control module is also used to detect whether the second interface is inserted into a solid-state hard disk; and when it is detected that the second interface is inserted into the solid-state hard disk, a second power supply signal is output; when it is detected that the second interface is not inserted into the solid-state hard disk, a second power-off signal is output; when the second power consumption data output by the second detection module is received, the second power consumption data is uploaded to the data transmission module; the switch module is also used to supply power to the second interface when the second power supply signal is received; when the second power-off signal is received, the power supply to the second interface is disconnected; the second detection module is used to detect the current output by the switch module to the second interface in real time, and generate the second power consumption data; the data transmission module is also used to provide the second power consumption data to the user end when the second power consumption data is received from the control module.

[0006] In some embodiments, the switch module includes a chip U45, a capacitor C899, a capacitor XC77, a resistor XR469, a resistor XR540, and a resistor XR447;

[0007] The VIN1 pin of the chip U45 and the VIN2 pin of the chip U45 are both connected to the first power supply, the ON1 pin of the chip U45 is connected to the control module through the resistor XR469, the VBIAS pin of the chip U45 is connected to the second power supply, the CT1 pin of the chip U45 is grounded through the capacitor C899, the GND1 pin of the chip U45 and the GND2 pin of the chip U45 are both grounded, the VOUT1 pin of the chip U45 and the VOUT2 pin of the chip U45 are connected, the VOUT1 pin of the chip U45 is also connected to the first end of the capacitor XC77 and the first end of the resistor XR540, the second end of the capacitor XC77 is grounded, the second end of the resistor XR540 is connected to the first end of the resistor XR447 and the first detection module, and the second end of the resistor XR447 is connected to the first interface and the first detection module.

[0008] In some embodiments, the switch module also includes a switch tube PQ980 and a resistor XR375; the control end of the switch tube PQ980 is connected to the control module, the first end of the switch tube PQ980 is connected to the VOUT1 pin of the chip U45 and the first end of the resistor XR540, the second end of the switch tube PQ980 is connected to the first end of the resistor XR375 and the first detection module, and the second end of the resistor XR375 is connected to the second end of the resistor XR447, the first interface and the first detection module.

[0009] In some embodiments, the switch module also includes capacitor C900, capacitor XC80, resistor XR470, resistor XR541, and resistor XR449; the VIN3 pin of the chip U45 and the VIN4 pin of the chip U45 are both connected to the first power supply, the ON2 pin of the chip U45 is connected to the control module through the resistor XR470, the CT2 pin of the chip U45 is grounded through the capacitor C900, the VOUT3 pin of the chip U45 is connected to the VOUT4 pin of the chip U45, the VOUT3 pin of the chip U45 is also connected to the first end of the capacitor XC80 and the first end of the resistor XR541, the second end of the capacitor XC80 is grounded, the second end of the resistor XR541 is connected to the first end of the resistor XR449 and the second detection module, and the second end of the resistor XR449 is connected to the second interface and the second detection module.

[0010] In some embodiments, the switch module also includes a switch tube PQ981 and a resistor XR442; the control end of the switch tube PQ981 is connected to the control module, the first end of the switch tube PQ981 is connected to the VOUT3 pin of the chip U45 and the first end of the resistor XR541, the second end of the switch tube PQ981 is connected to the first end of the resistor XR442 and the second detection module, and the second end of the resistor XR442 is connected to the second end of the resistor XR449, the second interface and the second detection module.

[0011] In some embodiments, the first detection module includes a first low current detection unit and a first high current detection unit; the first low current detection unit includes a chip CU1, a resistor R598, a resistor R599, a resistor R601, a resistor R629, and a resistor R600; wherein the A1 pin of the chip CU1, the A0 pin of the chip CU1, and the GND pin of the chip CU1 are all grounded, the SDA pin of the chip CU1 is connected to the control module through the resistor R598, the SCL pin of the chip CU1 is connected to the control module through the resistor R599, the IN+ pin of the chip CU1 is connected to the switch module through the resistor R601, the IN- pin of the chip CU1 is connected to the switch module through the resistor R629, the VBUS pin of the chip CU1 is connected to the switch module through the resistor R600, and the chip The VS pin of chip CU1 is connected to the third power supply; the first high current detection unit includes chip CU7, resistor R649, resistor R650, resistor R646, resistor R648, and resistor R647; wherein, the A1 pin of the chip CU7 and the GND pin of the chip CU7 are grounded respectively, the A0 pin of the chip CU7 and the VS pin of the chip CU7 are connected to the third power supply respectively, the SDA pin of the chip CU7 is connected to the control module through the resistor R649, the SCL pin of the chip CU7 is connected to the control module through the resistor R650, the IN+ pin of the chip CU7 is connected to the switch module through the resistor R646, the IN- pin of the chip CU7 is connected to the switch module through the resistor R648, and the VBUS pin of the chip CU7 is connected to the switch module through the resistor R647.

[0012] In some embodiments, the second detection module includes a second low current detection unit and a second high current detection unit; the second low current detection unit includes a chip CU2, a resistor R606, a resistor R607, a resistor R632, a resistor R633, and a resistor R604; wherein the A1 pin of the chip CU2, the A0 pin of the chip CU2, and the GND pin of the chip CU2 are all grounded, the SDA pin of the chip CU2 is connected to the control module through the resistor R606, the SCL pin of the chip CU2 is connected to the control module through the resistor R607, the IN+ pin of the chip CU2 is connected to the switch module through the resistor R632, the IN- pin of the chip CU2 is connected to the switch module through the resistor R633, the VBUS pin of the chip CU2 is connected to the switch module through the resistor R604, and the chip The VS pin of chip CU2 is connected to the third power supply; the second high current detection unit includes chip CU9, resistor R659, resistor R660, resistor R656, resistor R658, and resistor R657; wherein, the A1 pin of the chip CU9 and the GND pin of the chip CU9 are grounded respectively, the A0 pin of the chip CU9 and the VS pin of the chip CU9 are connected to the third power supply respectively, the SDA pin of the chip CU9 is connected to the control module through the resistor R659, the SCL pin of the chip CU9 is connected to the control module through the resistor R660, the IN+ pin of the chip CU9 is connected to the switch module through the resistor R656, the IN- pin of the chip CU9 is connected to the switch module through the resistor R658, and the VBUS pin of the chip CU9 is connected to the switch module through the resistor R657.

[0013] In some embodiments, the first interface includes interface JSSD1, resistor XR379, and resistor XR478; the GND_14 pin of the interface JSSD1 is respectively connected to the first end of the resistor XR379 and the first end of the resistor XR478, the second end of the resistor XR379 is connected to the third power supply, the second end of the resistor XR478 is connected to the control module, and the 3P3V_1 pin of the interface JSSD1, the 3P3V_2 pin of the interface JSSD1, the 3P3V_3 pin of the interface JSSD1, the 3P3V_4 pin of the interface JSSD1, the 3P3V_5 pin of the interface JSSD1, the 3P3V_6 pin of the interface JSSD1, the 3P3V_7 pin of the interface JSSD1, the 3P3V_8 pin of the interface JSSD1, and the 3P3V_9 pin of the interface JSSD1 are all connected to the switch module.

[0014] In a second aspect, an embodiment of the present application further provides a detection device, which includes the detection circuit as described above.

[0015] Different from the solutions of the prior art, the embodiments of the present application provide a detection circuit and a detection device. The detection circuit includes: a first interface, a control module, a switch module, a first detection module, and a data transmission module; the first interface is connected to the control module and the switch module respectively, the control module is also connected to the switch module, the first detection module, and the data transmission module respectively, and the switch module is also connected to the first detection module and the first power supply respectively; the control module is used to detect whether the first interface is inserted into a solid state drive; and when it is detected that the first interface is inserted into the solid state drive, it outputs a first power supply signal; when it is detected that the first interface is not inserted into the solid state drive, it outputs a first power-off signal; when receiving the first power consumption data output by the first detection module, the first power consumption data is uploaded to the data transmission module; the switch module is used to supply power to the first interface when receiving the first power supply signal; when receiving the first power-off signal, the power supply to the first interface is disconnected; the first detection module is used to detect the current output by the switch module to the first interface in real time, and generate the first power consumption data; the data transmission module is used to provide the first power consumption data to the user end when receiving the first power consumption data from the control module. The embodiments of the present application provide a detection circuit and a detection device. Compared with the traditional method of plugging and unplugging the SSD by powering off the entire machine, the user does not need to shut down the running system and software, avoiding frequent shutdown and startup operations, and realizing hot plugging of the SSD. In addition, the power consumption data of the SSD is detected in real time by the first detection module and transmitted to the user end, so that the user can intuitively understand the energy consumption of the SSD, thereby improving the test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] One or more embodiments are exemplarily described by corresponding drawings, which do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and the figures in the drawings do not constitute proportional limitations unless otherwise stated.

[0017] Figure 1 is a structural block diagram of a detection circuit provided in an embodiment of the present application;

[0018] Figure 2 is a schematic diagram of the circuit structure of a first interface provided in an embodiment of the present application;

[0019] Figure 3 is a schematic diagram of the circuit structure of a switch module provided in an embodiment of the present application;

[0020] Figure 4is a circuit structure diagram of a first low current detection unit provided in an embodiment of the present application;

[0021] Figure 5 is a schematic diagram of the circuit structure of a first high current detection unit provided in an embodiment of the present application;

[0022] Figure 6 is a structural block diagram of a detection circuit provided by another embodiment of the present application;

[0023] Figure 7 is a schematic diagram of the circuit structure of the second interface provided in one embodiment of the present application;

[0024] Figure 8 is a schematic diagram of a circuit structure of a switch module provided in another embodiment of the present application;

[0025] Fig. 9 is a circuit structure diagram of a switch module provided in another embodiment of the present application;

[0026] Fig.10 is a circuit structure diagram of a second low current detection unit provided in an embodiment of the present application;

[0027] Fig.11 Schematic diagram of the circuit structure of the second high current detection unit provided in one embodiment of the present application. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be described clearly and in detail in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0029] The technical features involved in the various embodiments of the present application described below do not conflict with each other and can be combined with each other.

[0030] When an element is referred to as being “connected to” another element, it can be directly connected to the other element, or one or more intervening elements may be present therebetween.

[0031] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more.

[0032] See also Figure 1 , Figure 1 1 is a structural block diagram of a detection circuit 100 provided in an embodiment of the present application.

[0033] The embodiment of the present application provides a detection circuit 100 , which includes: a first interface 10 , a control module 20 , a switch module 30 , a first detection module 40 , and a data transmission module 50 .

[0034] Among them, the first interface 10 is connected to the control module 20 and the switch module 30 respectively, the control module 20 is also connected to the switch module 30, the first detection module 40, and the data transmission module 50 respectively, and the switch module 30 is also connected to the first detection module 40 and the first power supply 200 respectively.

[0035] Specifically, the control module 20 is used to detect whether the first interface 10 is inserted into a solid-state hard disk (not shown); and when it is detected that the first interface 10 is inserted into a solid-state hard disk, it outputs a first power supply signal; when it is detected that the first interface 10 is not inserted into a solid-state hard disk, it outputs a first power-off signal; when receiving the first power consumption data output by the first detection module 40, it uploads the first power consumption data to the data transmission module 50. The switch module 30 is used to supply power to the first interface 10 when receiving the first power supply signal; when receiving the first power-off signal, it disconnects the power supply to the first interface 10. The first detection module 40 is used to detect the current output by the switch module 30 to the first interface 10 in real time, and generate the first power consumption data. The data transmission module 50 is used to provide the first power consumption data to the user end (not shown) when receiving the first power consumption data from the control module 20.

[0036] The first power supply 200 is used to provide power to the solid state drive (SSD). For example, the first power supply 200 can be a stable DC power supply (such as a +3.3V DC power supply) inside the computer, which provides the power required for the solid state drive connected to the first interface 10. When the switch module 30 receives the first power supply signal sent by the control module 20, it transmits the power of the first power supply 200 to the first interface 10, thereby powering the solid state drive.

[0037] Among them, the first power supply signal is an electrical signal sent by the control module 20, which is used to control the state of the switch module 30. It is essentially a command signal, indicating that the solid-state hard disk has been inserted into the first interface 10 and needs to be powered. This signal can be a signal with a specific voltage value or logic level. For example, in a digital circuit, if a low level is used to represent a valid signal, then when the control module 20 detects that the solid-state hard disk is inserted into the first interface 10, it may output a low-level signal (such as 0V) as the first power supply signal. After this signal is received by the switch module 30, it will trigger the switch inside the switch module 30 to close (if it is an electronic switch, such as MOSFET), so that the first power supply 200 can power the first interface 10 through the switch module 30.

[0038] Among them, the first power-off signal is also an electrical signal sent by the control module 20, which is used to instruct the switch module 30 to disconnect the power supply to the first interface 10. When the control module 20 detects that there is no solid-state hard disk inserted in the first interface 10, this signal will be sent. Corresponding to the first power supply signal, it is also a command signal with a specific meaning. For example, it may be a high-level signal (such as 3.3V). When the switch module 30 receives this high-level first power-off signal, it will control the internal switch to disconnect, thereby stopping the first power supply 200 from supplying power to the first interface 10, so as to avoid wasting electricity or causing potential circuit failures when there is no solid-state hard disk inserted.

[0039] Among them, the first power consumption data is the data generated by the first detection module 40 after real-time detection of the current output from the switch module 30 to the first interface 10. It reflects the power consumption of the solid-state hard disk connected to the first interface 10. Specifically, the first detection module 40 generates the first power consumption data by detecting the magnitude of the current flowing through, and combining the power supply voltage of the first interface 10 (usually a fixed voltage provided by the first power supply 200), using the power calculation formula (power = voltage × current). For example, if the first detection module 40 detects that the current flowing through the first interface 10 is 0.5A, and the power supply voltage of the first interface 10 is 5V, then the calculated first power consumption data is 2.5W. The first power consumption data can help users understand the energy consumption of the solid-state hard disk, for example, for evaluating the performance of the solid-state hard disk, detecting whether there is abnormal power consumption, etc.

[0040] In some embodiments, the control module 20 may be an EC (Embedded Controller) or other control device. EC is an embedded microcontroller that plays a vital role in electronic devices (especially laptops and other devices). It is like a small intelligent management unit inside the device, responsible for managing and monitoring various underlying hardware functions of the device. In this embodiment, the control module 20 can detect whether the solid-state drive (SSD) has been correctly inserted into the device through a specific circuit connection or interface signal. This is similar to the function of a sensor, which determines the in-place status of the SSD by detecting changes in physical connections or electrical signals. For example, when the SSD is inserted into the first interface 10, it will cause level changes or signal pulses on certain pins on the interface circuit. EC can capture these changes to determine whether the SSD is in place. EC can also control the power supply of the SSD. It is like a power manager that decides whether to provide power to the SSD based on the in-place status of the SSD and the needs of the system. For example, when the device is started, if it is detected that the SSD is inserted into the first interface 10, the EC will send a signal to turn on the power of the SSD so that it can start and work normally; when it is detected that the SSD is not inserted into the first interface 10, the EC will turn off the power of the SSD to save power and protect data security. The EC can receive data from the first detection module 40. Then, the EC will upload this data to the data transmission module 50, which plays the role of a data transfer station, so that other key components of the device (such as the CPU, etc.) can obtain the power consumption data of the SSD.

[0041] In some embodiments, the data transmission module 50 is a PCH (Platform Controller Hub) or other data transmission device. PCH is a key component in the Intel chipset architecture. It is mainly responsible for connecting low-speed devices in the computer system, and plays an important role in many aspects such as power management and system clock control. It is an important bridge connecting the CPU and various peripheral devices. In this embodiment, after the control module 20 (such as EC) uploads the power consumption data of the SSD to the data transmission module 50 (such as PCH), the data transmission module 50 can further process the data. For example, PCH can pass this data to the CPU or other system management software for system performance analysis, power management strategy adjustment, etc.

[0042] In practical applications, the detection circuit 100 provided in the embodiment of the present application includes the hot-swap principle of a solid-state hard disk and the power consumption data detection and transmission principle.

[0043] Combination Figure 1 , the hot-swap principle of the solid-state drive (SSD) of the detection circuit 100 is as follows:

[0044] First, the control module 20 continuously detects the state of the first interface 10. It determines whether the SSD is inserted through the level change of a specific pin on the first interface 10 or the signal feedback mechanism. For example, some interface designs will ground a pin or pull up the level when the device is inserted, and the control module 20 can identify this level change. Then, once it is detected that the SSD is inserted into the first interface 10, the control module 20 will output a first power supply signal. This power supply signal is a control instruction and is sent to the switch module 30. After receiving the first power supply signal, the switch module 30 will close its internal switch element (such as MOSFET), thereby connecting the first power supply 200 to the first interface 10 and starting to supply power to the SSD. On the contrary, when the control module 20 detects that the first interface 10 is not inserted with the SSD, it will output a first power-off signal. After receiving this signal, the switch module 30 will disconnect the internal switch, so that the first power supply 200 can no longer supply power to the first interface 10, thereby avoiding power waste and potential circuit safety hazards when the device is not inserted. Therefore, the detection circuit 100 provided in the embodiment of the present application realizes powering the SSD when the SSD is inserted into the first interface 10, and cutting off power supply when the SSD is not inserted into the first interface 10, that is, realizing hot plugging of the solid state drive (SSD).

[0045] Combination Figure 1 , the power consumption data detection and transmission principle of the detection circuit 100 is as follows:

[0046] When the SSD is operating normally and being powered, the first detection module 40 starts to play a role. It detects the current output from the switch module 30 to the first interface 10 in real time. The first detection module 40 may detect the current size by connecting a current detection resistor in series in the power supply line, using Ohm's law (calculating the current according to the voltage across the resistor) or using a Hall effect sensor. Then, the first detection module 40 generates the first power consumption data based on the detected current and the known power supply voltage (provided by the first power supply 200) using the power calculation formula (power = voltage × current). For example, if the current is detected to be I ampere and the power supply voltage is V volts, then the first power consumption data is P = V × I watts. Then, the generated first power consumption data will be sent to the control module 20. After receiving the first power consumption data, the control module 20 will upload it to the data transmission module 50. The data transmission module 50 can provide the first power consumption data to the user end through the I2C interface or other communication methods (such as USB, SPI). Among them, the user end can be monitoring software on a computer. After receiving the power consumption data, it can display (using a UI interface), analyze or record it so that the user can understand the power consumption of the SSD, such as for performance evaluation, fault detection and other purposes.

[0047] The detection circuit 100 provided in the embodiment of the present application allows the solid-state drive (SSD) to be inserted or removed when the device is powered on. Compared with the traditional method of plugging and removing the SSD by powering off the entire device, the user does not need to shut down the running system and software, thus avoiding frequent shutdown and startup operations. In addition, the power consumption data of the SSD is detected in real time by the first detection module and transmitted to the user end, so that the user can intuitively understand the energy consumption of the SSD.

[0048] See also Figure 2 , Figure 2 It is a schematic diagram of the circuit structure of the first interface 10 provided in one embodiment of the present application.

[0049] In some embodiments, the first interface 10 includes an interface JSSD1 , a resistor XR379 , and a resistor XR478 .

[0050] The GND_14 pin of the interface JSSD1 is connected to the first end of the resistor XR379 and the first end of the resistor XR478 respectively, and the second end of the resistor XR379 is connected to the third power supply (such as Figure 2 +3.3V_MAIN) in the interface, the second end of the resistor XR478 is connected to the control module 20, and the 3P3V_1 pin of the interface JSSD1, the 3P3V_2 pin of the interface JSSD1, the 3P3V_3 pin of the interface JSSD1, the 3P3V_4 pin of the interface JSSD1, the 3P3V_5 pin of the interface JSSD1, the 3P3V_6 pin of the interface JSSD1, the 3P3V_7 pin of the interface JSSD1, the 3P3V_8 pin of the interface JSSD1, and the 3P3V_9 pin of the interface JSSD1 are all connected to the switch module 30.

[0051] The third power source may be a stable DC power source (such as a +3.3V DC power source) inside the computer, which provides the first interface 10 with the power required for operation.

[0052] Specifically, interface JSSD1 is an M.2 SSD device interface, which is an interface standard for connecting solid-state drives.

[0053] In practical applications, such as Figure 2 As shown, when the interface JSSD1 is inserted into the solid state drive, the GND_14 pin of the interface JSSD1 outputs a low level. When the interface JSSD1 is not inserted into the solid state drive, the third power supply (+3.3V_MAIN) pulls up the GND_14 pin of the interface JSSD1 to a high level.

[0054] The control module 20 (e.g., EC) is connected to the resistor XR478. When the control module 20 detects that the pin connected to the resistor XR478 is a low-level signal, the control module 20 detects that a solid-state hard disk is inserted into the first interface 10. When the control module 20 detects that the pin connected to the resistor XR478 is a high-level signal, the control module 20 detects that no solid-state hard disk is inserted into the first interface 10.

[0055] See also Figure 3 , Figure 3 Schematic diagram of the circuit structure of the switch module 30 provided in one embodiment of the present application.

[0056] In some embodiments, the switch module 30 includes a chip U45, a capacitor C899, a capacitor XC77, a resistor XR469, a resistor XR540, and a resistor XR447.

[0057] Among them, the VIN1 pin of chip U45 and the VIN2 pin of chip U45 are both connected to the first power supply 200, the ON1 pin of chip U45 is connected to the control module 20 through the resistor XR469, the VBIAS pin of chip U45 is connected to the second power supply (+5V_MAIN), the CT1 pin of chip U45 is grounded through the capacitor C899, the GND1 pin of chip U45 and the GND2 pin of chip U45 are both grounded, the VOUT1 pin of chip U45 is connected to the VOUT2 pin of chip U45, the VOUT1 pin of chip U45 is also connected to the first end of capacitor XC77 and the first end of resistor XR540, the second end of capacitor XC77 is grounded, the second end of resistor XR540 is connected to the first end of resistor XR447 and the first detection module 40, and the second end of resistor XR447 is connected to the first interface 10 and the first detection module 40.

[0058] The chip U45 may be a chip of model APL3528, or other power switch chips (such as a chip of model G2898KD1U, a chip of model WS4666DAB-14 / TR, etc.) The second power supply may be a stable DC power supply (such as a +5V DC power supply) inside the computer.

[0059] In this embodiment, when the control module 20 detects that the first interface 10 is plugged into a solid state drive, the control module 20 Figure 3 The SSD1_PWR_EN terminal transmits a first power supply signal (eg, a high level signal) to the switch module 30. At this time, the switch tube inside the chip U45 is turned on, and the VOUT1 pin and the VOUT2 pin of the chip U45 output voltages to supply power to the first interface 10.

[0060] When the control module 20 detects that the first interface 10 is not plugged into the solid state hard disk, the control module 20 Figure 3 The SSD1_PWR_EN terminal transmits a first power-off signal (eg, a low level signal) to the switch module 30. At this time, the switch tube inside the chip U45 is disconnected, and the VOUT1 pin and the VOUT2 pin of the chip U45 do not output voltage to disconnect the power supply to the first interface 10.

[0061] In an embodiment, the first detection module 40 can generate the first power consumption data by detecting the voltage across the resistor XR447. Specifically, the first detection module 40 detects the voltage across the resistor XR447 and uses the current calculation formula (current = voltage / resistance) to calculate the current flowing through the resistor XR447. Combined with the power supply voltage of the first interface 10 (usually a fixed voltage provided by the first power supply 200, such as 3.3V), the power calculation formula (power = voltage × current) is used to generate the first power consumption data.

[0062] It should be noted that the switch module 30 in the above embodiment is only exemplarily shown to be connected to the first interface 10, and the switch module 30 is used to supply power to the first interface 10 or disconnect the power supply to the first interface 10. In other embodiments, the switch module 30 can be connected to multiple interfaces (such as multiple M.2 SSD device interfaces) at the same time to supply power to and disconnect the multiple interfaces at the same time, and the specific structure of the switch module 30 can be adjusted according to actual needs.

[0063] In some embodiments, the switch module 30 further includes a switch tube PQ980 and a resistor XR375. The control end of the switch tube PQ980 is connected to the control module 20, the first end of the switch tube PQ980 is connected to the VOUT1 pin of the chip U45 and the first end of the resistor XR540, the second end of the switch tube PQ980 is connected to the first end of the resistor XR375 and the first detection module 40, and the second end of the resistor XR375 is connected to the second end of the resistor XR447, the first interface 10 and the first detection module 40.

[0064] It should be noted that the resistance value of the resistor XR375 is smaller than the resistance value of the resistor XR447. For example, the resistance value of the resistor XR375 is 10 m ohms, and the resistance value of the resistor XR447 is 10 ohms.

[0065] In an embodiment, when the control module 20 detects that the voltage across the resistor XR447 is too small (for example, less than a preset current threshold), that is, the current of the resistor XR447 is too small, the control module 20 may provide a control terminal ( Figure 3The control module 20 controls the first detection module 40 to detect the voltage across the resistor XR375. The first detection module 40 can generate the first power consumption data by detecting the voltage across the resistor XR375. Specifically, the first detection module 40 detects the voltage across the resistor XR375 and uses the current calculation formula (current = voltage / resistance) to calculate the current flowing through the resistor XR375. Combined with the power supply voltage of the first interface 10 (usually a fixed voltage provided by the first power supply 200, such as 3.3V), the power calculation formula (power = voltage × current) is used to generate the first power consumption data.

[0066] When the current output by the switch module 30 to the first interface 10 is too small, the first detection module 40 may not be able to accurately collect the current and may not accurately generate the first power consumption data. Figure 3 The first detection module 40 detects the voltage across the resistor XR375 to generate accurate first power consumption data, thereby improving the accuracy of detection.

[0067] See also Figure 4 , Figure 4 4 is a schematic diagram of the circuit structure of the first low current detection unit 41 provided in an embodiment of the present application.

[0068] In some embodiments, the first detection module 40 includes a first low current detection unit 41 .

[0069] The first low current detection unit 41 includes a chip CU1, a resistor R598, a resistor R599, a resistor R601, a resistor R629, and a resistor R600.

[0070] Specifically, the A1 pin of chip CU1, the A0 pin of chip CU1, and the GND pin of chip CU1 are all grounded, the SDA pin of chip CU1 is connected to the control module 20 through resistor R598, the SCL pin of chip CU1 is connected to the control module 20 through resistor R599, the IN+ pin of chip CU1 is connected to the switch module 30 through resistor R601, the IN- pin of chip CU1 is connected to the switch module 30 through resistor R629, the VBUS pin of chip CU1 is connected to the switch module 30 through resistor R600, and the VS pin of chip CU1 is connected to the third power supply (+3.3V_MAIN).

[0071] Specifically, the chip CU1 is a INA226 model, or a sampling chip of other models. The SDL (Serial Data Line) and SCL (Serial Clock Line) pins are important components of the I2C (Inter-Integrated Circuit) bus interface.

[0072] In this embodiment, when the control module 20 detects Figure 3 When the voltage across the resistor XR447 in the chip is too small (for example, less than the preset current threshold), the control module 20 controls the first low current detection unit 41 to work through the SDA pin and SCL pin of the chip CU1. At this time, the first low current detection unit 41 collects the current through its IN+ pin and IN- pin. Figure 3 The voltage across the resistor XR375 in the chip CU1 is obtained by calculating the current flowing through the resistor XR375 using the current calculation formula (current = voltage / resistance). Combined with the power supply voltage of the first interface 10 (usually a fixed voltage provided by the first power supply 200, such as 3.3V), the power calculation formula (power = voltage × current) is used to generate the first power consumption data. Finally, the first power consumption data is fed back to the control module 20 through the SDA pin and the SCL pin of the chip CU1.

[0073] The preset current threshold can be set according to actual needs and is not specifically limited here.

[0074] When the current output from the switch module 30 to the first interface 10 is too small, the first high current detection unit 42 in the first detection module 40 may not be able to accurately collect the current, and may not accurately generate the first power consumption data. At this time, the control module 20 controls the switch tube PQ980 to be turned on. In addition, the control module 20 controls the first low current detection unit 41 to detect the voltage across the resistor XR375, so as to generate accurate first power consumption data, which can improve the accuracy of the detection.

[0075] See also Figure 5 , Figure 5 Schematic diagram of the circuit structure of the first high current detection unit 42 provided in one embodiment of the present application.

[0076] In some embodiments, the first detection module 40 further includes a first high current detection unit 42 .

[0077] The first high current detection unit 42 includes a chip CU7, a resistor R649, a resistor R650, a resistor R646, a resistor R648, and a resistor R647.

[0078] Specifically, the A1 pin of chip CU7 and the GND pin of chip CU7 are grounded respectively, the A0 pin of chip CU7 and the VS pin of chip CU7 are connected to the third power supply (+3.3V_MAIN) respectively, the SDA pin of chip CU7 is connected to the control module 20 through resistor R649, the SCL pin of chip CU7 is connected to the control module 20 through resistor R650, the IN+ pin of chip CU7 is connected to the switch module 30 through resistor R646, the IN- pin of chip CU7 is connected to the switch module 30 through resistor R648, and the VBUS pin of chip CU7 is connected to the switch module 30 through resistor R647.

[0079] Specifically, the chip CU7 is a INA226 model, or a sampling chip of other models.

[0080] In this embodiment, when the control module 20 needs to obtain the power consumption data of the first interface 10, the control module 20 controls the first high current detection unit 42 to work through the SDA pin and the SCL pin of the chip CU7. At this time, the first high current detection unit 42 collects the power consumption data of the first interface 10 through its IN+ pin and IN- pin. Figure 3 The voltage across the resistor XR447 in the circuit is obtained by calculating the current flowing through the resistor XR447 using the current calculation formula (current = voltage / resistance). Combined with the power supply voltage of the first interface 10 (usually a fixed voltage provided by the first power supply 200, such as 3.3V), the power calculation formula (power = voltage × current) is used to generate the first power consumption data. Finally, the first power consumption data is fed back to the control module 20 through the SDA pin and the SCL pin of the chip CU7. Thus, the first power consumption data output by the switch module 30 to the first interface 10 is detected in real time.

[0081] The embodiment of the present application provides a detection circuit 100. Compared with the traditional method of plugging and unplugging the SSD by powering off the entire machine, the user does not need to shut down the running system and software, avoiding frequent shutdown and startup operations, and realizing hot plugging of the SSD. In addition, the power consumption data of the SSD is detected in real time by the first detection module and transmitted to the user end, so that the user can intuitively understand the energy consumption of the SSD. At the same time, when the current input to the first interface is small, the power consumption data can still be collected, which improves the accuracy of the detection.

[0082] See also Figure 6 , Figure 6 It is a structural block diagram of a detection circuit 100 provided in another embodiment of the present application.

[0083] In some embodiments, the detection circuit 100 further includes a second interface 60 and a second detection module 70 .

[0084] The second interface 60 is connected to the control module 20 and the switch module 30 respectively, the second detection module 70 is also connected to the switch module 30 , and the control module 20 is also connected to the second detection module 70 .

[0085] Specifically, the control module 20 is also used to detect whether the second interface 60 is inserted into a solid-state hard disk (not shown); and when it is detected that the second interface 60 is inserted into a solid-state hard disk, it outputs a second power supply signal; when it is detected that the second interface 60 is not inserted into a solid-state hard disk, it outputs a second power-off signal; when receiving the second power consumption data output by the second detection module 70, it uploads the second power consumption data to the data transmission module 50. The switch module 30 is also used to supply power to the second interface 60 when receiving the second power supply signal; when receiving the second power-off signal, it disconnects the power supply to the second interface 60. The second detection module 70 is used to detect the current output from the switch module 30 to the second interface 60 in real time, and generate second power consumption data. The data transmission module 50 is also used to provide the second power consumption data to the user end (not shown) when receiving the second power consumption data from the control module 20.

[0086] The second power supply signal is an electrical signal sent by the control module 20 and is used to control the state of the switch module 30. It is essentially a command signal, indicating that the second interface 60 has been inserted into the solid state drive and needs to be powered. This signal can be a signal with a specific voltage value or logic level.

[0087] The second power-off signal is also an electrical signal sent by the control module 20, which is used to instruct the switch module 30 to disconnect the power supply to the second interface 60. The control module 20 sends this signal when it detects that the second interface 60 is not plugged into a solid-state hard disk. Corresponding to the second power supply signal, it is also a command signal with a specific meaning.

[0088] The second power consumption data is data generated by the second detection module 70 after real-time detection of the current output from the switch module 30 to the second interface 60 , and reflects the power consumption of the solid state drive connected to the second interface 60 .

[0089] The detection circuit 100 provided in the embodiment of the present application allows the solid-state drive (SSD) to be inserted or removed when the device is turned on. Compared with the traditional method of plugging and unplugging the SSD, which requires the whole machine to be powered off, the user does not need to shut down the running system and software, avoiding frequent shutdown and startup operations. In addition, the power consumption data of the SSD is detected in real time by the first detection module and transmitted to the user end, so that the user can intuitively understand the energy consumption of the SSD. In addition, the hot-swap operation and power consumption monitoring operation of the two interfaces (the first interface 10 and the second interface 60) can be performed simultaneously.

[0090] See also Figure 7 , Figure 7 Schematic diagram of the circuit structure of the second interface 60 provided in one embodiment of the present application.

[0091] In some embodiments, the second interface 60 includes an interface JSSD4, a resistor XR482, and a resistor XR381.

[0092] The GND_14 pin of the interface JSSD4 is connected to the first end of the resistor XR482 and the first end of the resistor XR381 respectively, and the second end of the resistor XR381 is connected to the third power supply (such as Figure 7 The second end of the resistor XR482 is connected to the control module 20. The 3P3V_1 pin of the interface JSSD4, the 3P3V_2 pin of the interface JSSD4, the 3P3V_3 pin of the interface JSSD4, the 3P3V_4 pin of the interface JSSD4, the 3P3V_5 pin of the interface JSSD4, the 3P3V_6 pin of the interface JSSD4, the 3P3V_7 pin of the interface JSSD4, the 3P3V_8 pin of the interface JSSD4, and the 3P3V_9 pin of the interface JSSD4 are all connected to the switch module 30 for receiving power supply.

[0093] The third power source may be a stable DC power source (such as a +3.3V DC power source) inside the computer, which provides the second interface 60 with the power required for operation.

[0094] Specifically, interface JSSD4 is an M.2 SSD device interface, which is an interface standard for connecting solid-state drives.

[0095] In practical applications, such as Figure 7 As shown, when the interface JSSD4 is inserted into the solid state drive, the GND_14 pin of the interface JSSD4 outputs a low level. When the interface JSSD4 is not inserted into the solid state drive, the third power supply (+3.3V_MAIN) pulls up the GND_14 pin of the interface JSSD4 to a high level.

[0096] It should be noted that the working principle of the second interface 60 is similar to Figure 2 The first interface 10 in the embodiment is similar to that in the embodiment, and the description of the first interface 10 in the embodiment above may be referred to, which will not be repeated here.

[0097] See also Figure 8 , Figure 8 Schematic diagram of the circuit structure of the switch module 30 provided in another embodiment of the present application.

[0098] In some embodiments, the switch module 30 further includes a capacitor C900 , a capacitor XC80 , a resistor XR470 , a resistor XR541 , and a resistor XR449 .

[0099] Among them, the VIN3 pin of chip U45 and the VIN4 pin of chip U45 are both connected to the first power supply 200, the ON2 pin of chip U45 is connected to the control module 20 through the resistor XR470, the CT2 pin of chip U45 is grounded through the capacitor C900, the VOUT3 pin of chip U45 and the VOUT4 pin of chip U45 are connected, the VOUT3 pin of chip U45 is also connected to the first end of capacitor XC80 and the first end of resistor XR541, the second end of capacitor XC80 is grounded, the second end of resistor XR541 is connected to the first end of resistor XR449 and the second detection module 70, and the second end of resistor XR449 is connected to the second interface 60 and the second detection module 70.

[0100] In an embodiment, the second detection module 70 can generate the second power consumption data by detecting the voltage across the resistor XR449. Specifically, the second detection module 70 detects the voltage across the resistor XR449 and uses the current calculation formula (current = voltage / resistance) to calculate the current flowing through the resistor XR449. Combined with the power supply voltage of the second interface 60 (usually a fixed voltage provided by the first power supply 200, such as 3.3V), the power calculation formula (power = voltage × current) is used to generate the second power consumption data.

[0101] In some embodiments, the switch module 30 further includes a switch tube PQ981 and a resistor XR442.

[0102] Among them, the control end of the switch tube PQ981 is connected to the control module 20, the first end of the switch tube PQ981 is connected to the VOUT3 pin of the chip U45 and the first end of the resistor XR541, the second end of the switch tube PQ981 is connected to the first end of the resistor XR442 and the second detection module 70, and the second end of the resistor XR442 is connected to the second end of the resistor XR449, the second interface 60 and the second detection module 70.

[0103] When the current output from the switch module 30 to the second interface 60 is too small, the second detection module 70 may not be able to accurately collect the current and may not accurately generate the second power consumption data. Figure 8 The SSD4_LP_CTRL_R terminal in the circuit breaker outputs a high level signal to control the switch tube PQ981 to be turned on. In addition, the second detection module 70 detects the voltage across the resistor XR442 to generate accurate second power consumption data, thereby improving the accuracy of the detection.

[0104] It should be noted that Figure 8 The working principle of the switch module 30 in Figure 3 The working principle of the switch module 30 is similar and will not be repeated here.

[0105] See also Fig. 9 , Fig. 9 Schematic diagram of the circuit structure of the switch module 30 provided in another embodiment of the present application. Fig. 9 yes Figure 8 and Figure 3 Combined with the circuit diagram of the switch module 30, Fig. 9 The working principle of the switch module 30 in the embodiment can be referred to the above Figure 3 and Figure 8 The description will not be repeated here.

[0106] In one embodiment, the switch tube PQ980 and the switch tube PQ981 are either triodes or field effect tubes.

[0107] Figure 3 , Figure 8 , Fig. 9 The switch tube PQ980 and the switch tube PQ981 are both field effect tubes. The control end of the switch tube PQ980 (switch tube PQ981) is the gate of the field effect tube; the first end of the switch tube PQ980 (switch tube PQ981) is the source of the field effect tube; the second end of the switch tube PQ980 (switch tube PQ981) is the drain of the field effect tube. Fig. 9 As shown, the switch tubes PQ980 and PQ981 are P-type FETs.

[0108] FET (Field Effect Transistor) is a field effect transistor, which is a transistor that uses an electric field to control the conductivity of a semiconductor material channel. Common FET types include MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and JFET (Junction Field Effect Transistor).

[0109] See also Fig.10 , Fig.10 Schematic diagram of the circuit structure of the second low current detection unit 71 provided in one embodiment of the present application.

[0110] In some embodiments, the second detection module 70 includes a second low current detection unit 71 .

[0111] The second low current detection unit 71 includes a chip CU2, a resistor R606, a resistor R607, a resistor R632, a resistor R633, and a resistor R604.

[0112] Specifically, the A1 pin of chip CU2, the A0 pin of chip CU2, and the GND pin of chip CU2 are all grounded, the SDA pin of chip CU2 is connected to the control module 20 through resistor R606, the SCL pin of chip CU2 is connected to the control module 20 through resistor R607, the IN+ pin of chip CU2 is connected to the switch module 30 through resistor R632, the IN- pin of chip CU2 is connected to the switch module 30 through resistor R633, the VBUS pin of chip CU2 is connected to the switch module 30 through resistor R604, and the VS pin of chip CU2 is connected to the third power supply (+3.3V_MAIN).

[0113] Specifically, the chip CU2 is a INA226 model, or other types of sampling chips.

[0114] When the current output from the switch module 30 to the second interface 60 is too small, the second high current detection unit 72 in the second detection module 70 may not be able to accurately collect the current and may not accurately generate the second power consumption data. At this time, the control module 20 controls the switch tube PQ981 to turn on. In addition, the control module 20 controls the second low current detection unit 71 to detect Figure 8 The voltage across the middle resistor XR442 can generate accurate second power consumption data, thereby improving the accuracy of detection.

[0115] It should be noted that the working principle of the second low current detection unit 71 is similar to that of the first low current detection unit 41 , which will not be described in detail herein.

[0116] See also Fig.11 , Fig.11 Schematic diagram of the circuit structure of the second high current detection unit 72 provided in one embodiment of the present application.

[0117] In some embodiments, the second detection module 70 further includes a second high current detection unit 72 .

[0118] The second high current detection unit 72 includes a chip CU9, a resistor R659, a resistor R660, a resistor R656, a resistor R658, and a resistor R657.

[0119] Specifically, the A1 pin of chip CU9 and the GND pin of chip CU9 are grounded respectively, the A0 pin of chip CU9 and the VS pin of chip CU9 are connected to the third power supply (+3.3V_MAIN) respectively, the SDA pin of chip CU9 is connected to the control module 20 through resistor R659, the SCL pin of chip CU9 is connected to the control module 20 through resistor R660, the IN+ pin of chip CU9 is connected to the switch module 30 through resistor R656, the IN- pin of chip CU9 is connected to the switch module 30 through resistor R658, and the VBUS pin of chip CU9 is connected to the switch module 30 through resistor R657.

[0120] Specifically, the chip CU9 is a INA226 model, or a sampling chip of other models.

[0121] In this embodiment, when the control module 20 needs to obtain the power consumption data of the second interface 60, the control module 20 controls the second high current detection unit 72 to work through the SDA pin and the SCL pin of the chip CU9. At this time, the second high current detection unit 72 collects the power consumption data of the second interface 60 through its IN+ pin and IN- pin. Figure 8 The voltage across the resistor XR449 in the circuit is obtained by calculating the current flowing through the resistor XR449 using the current calculation formula (current = voltage / resistance). Combined with the power supply voltage of the second interface 60 (usually a fixed voltage provided by the first power supply 200, such as 3.3V), the power calculation formula (power = voltage × current) is used to generate the second power consumption data. Finally, the second power consumption data is fed back to the control module 20 through the SDA pin and the SCL pin of the chip CU9. Thus, the second power consumption data output by the switch module 30 to the second interface 60 is detected in real time.

[0122] It should be noted that the working principle of the second high current detection unit 72 is similar to that of the second high current detection unit 42 , which will not be described in detail herein.

[0123] The embodiment of the present application provides a detection circuit 100. Compared with the traditional method of plugging and unplugging the SSD, which requires the whole machine to be powered off, the user does not need to shut down the running system and software, avoids frequent shutdown and startup operations, and realizes the hot plug of the SSD. In addition, the power consumption data of the SSD is detected in real time by the first detection module and the second detection module, and it is transmitted to the user end, so that the user can intuitively understand the energy consumption of the SSD. At the same time, when the current input to the first interface and the second interface is small, the power consumption data can still be collected, which improves the accuracy of the detection. In addition, the hot plugging and power consumption detection work of the two interfaces (the first interface 10 and the second interface 60) can be performed simultaneously.

[0124] The embodiment of the present application further provides a detection device, which includes the detection circuit 100 as described above.

[0125] Specifically, the detection device can be an SSD test board, which can record the power consumption performance of all SSDs under test, and realize the hot-swap function of the SSD under test when the test board is turned on, thereby improving the test efficiency.

[0126] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Based on the idea of ​​the present application, the technical features in the above embodiments or different embodiments may also be combined, and there are many other changes in different aspects of the present application as described above, which are not provided in detail for the sake of simplicity. Although the present application has been described in detail with reference to the aforementioned embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A detection circuit, characterized in that: The detection circuit includes: a first interface, a control module, a switch module, a first detection module, and a data transmission module; The first interface is connected to the control module and the switch module respectively, the control module is also connected to the switch module, the first detection module, and the data transmission module respectively, and the switch module is also connected to the first detection module and the first power supply respectively; The control module is used to detect whether the first interface is inserted into a solid-state hard disk; and when detecting that the first interface is inserted into the solid-state hard disk, output a first power supply signal; when detecting that the first interface is not inserted into the solid-state hard disk, output a first power-off signal; and when receiving the first power consumption data output by the first detection module, upload the first power consumption data to the data transmission module; The switch module is used to supply power to the first interface when receiving the first power supply signal; and disconnect the power supply to the first interface when receiving the first power-off signal; The first detection module is used to detect the current output by the switch module to the first interface in real time and generate the first power consumption data; The data transmission module is configured to provide the first power consumption data to a user end when receiving the first power consumption data from the control module.

2. The detection circuit according to claim 1, characterized in that: The detection circuit also includes a second interface and a second detection module; The second interface is connected to the control module and the switch module respectively, the second detection module is also connected to the switch module, and the control module is also connected to the second detection module; The control module is also used to detect whether the second interface is inserted into a solid-state hard disk; and output a second power supply signal when it is detected that the second interface is inserted into the solid-state hard disk; output a second power-off signal when it is detected that the second interface is not inserted into the solid-state hard disk; and upload the second power consumption data to the data transmission module when receiving the second power consumption data output by the second detection module; The switch module is further configured to supply power to the second interface upon receiving the second power supply signal; and disconnect power to the second interface upon receiving the second power-off signal; The second detection module is used to detect the current output by the switch module to the second interface in real time and generate the second power consumption data; The data transmission module is further configured to provide the second power consumption data to a user end when receiving the second power consumption data from the control module.

3. The detection circuit according to claim 2, characterized in that: The switch module includes a chip U45, a capacitor C899, a capacitor XC77, a resistor XR469, a resistor XR540, and a resistor XR447; The VIN1 pin of the chip U45 and the VIN2 pin of the chip U45 are both connected to the first power supply, the ON1 pin of the chip U45 is connected to the control module through the resistor XR469, the VBIAS pin of the chip U45 is connected to the second power supply, the CT1 pin of the chip U45 is grounded through the capacitor C899, the GND1 pin of the chip U45 and the GND2 pin of the chip U45 are both grounded, the VOUT1 pin of the chip U45 and the VOUT2 pin of the chip U45 are connected, the VOUT1 pin of the chip U45 is also connected to the first end of the capacitor XC77 and the first end of the resistor XR540, the second end of the capacitor XC77 is grounded, the second end of the resistor XR540 is connected to the first end of the resistor XR447 and the first detection module, and the second end of the resistor XR447 is connected to the first interface and the first detection module.

4. The detection circuit according to claim 3, characterized in that: The switch module also includes a switch tube PQ980 and a resistor XR375; The control end of the switch tube PQ980 is connected to the control module, the first end of the switch tube PQ980 is connected to the VOUT1 pin of the chip U45 and the first end of the resistor XR540, the second end of the switch tube PQ980 is connected to the first end of the resistor XR375 and the first detection module, and the second end of the resistor XR375 is connected to the second end of the resistor XR447, the first interface and the first detection module.

5. The detection circuit according to claim 4, characterized in that: The switch module also includes a capacitor C900, a capacitor XC80, a resistor XR470, a resistor XR541, and a resistor XR449; The VIN3 pin of the chip U45 and the VIN4 pin of the chip U45 are both connected to the first power supply, the ON2 pin of the chip U45 is connected to the control module through the resistor XR470, the CT2 pin of the chip U45 is grounded through the capacitor C900, the VOUT3 pin of the chip U45 is connected to the VOUT4 pin of the chip U45, the VOUT3 pin of the chip U45 is also connected to the first end of the capacitor XC80 and the first end of the resistor XR541, the second end of the capacitor XC80 is grounded, the second end of the resistor XR541 is connected to the first end of the resistor XR449 and the second detection module, and the second end of the resistor XR449 is connected to the second interface and the second detection module.

6. The detection circuit according to claim 5, characterized in that: The switch module also includes a switch tube PQ981 and a resistor XR442; The control end of the switch tube PQ981 is connected to the control module, the first end of the switch tube PQ981 is connected to the VOUT3 pin of the chip U45 and the first end of the resistor XR541, the second end of the switch tube PQ981 is connected to the first end of the resistor XR442 and the second detection module, and the second end of the resistor XR442 is connected to the second end of the resistor XR449, the second interface and the second detection module.

7. The detection circuit according to claim 1, characterized in that: The first detection module includes a first low current detection unit and a first high current detection unit; The first low current detection unit includes a chip CU1, a resistor R598, a resistor R599, a resistor R601, a resistor R629, and a resistor R600; wherein the A1 pin of the chip CU1, the A0 pin of the chip CU1, and the GND pin of the chip CU1 are all grounded, the SDA pin of the chip CU1 is connected to the control module through the resistor R598, the SCL pin of the chip CU1 is connected to the control module through the resistor R599, the IN+ pin of the chip CU1 is connected to the switch module through the resistor R601, the IN- pin of the chip CU1 is connected to the switch module through the resistor R629, the VBUS pin of the chip CU1 is connected to the switch module through the resistor R600, and the VS pin of the chip CU1 is connected to a third power supply; The first high current detection unit includes chip CU7, resistor R649, resistor R650, resistor R646, resistor R648, and resistor R647; wherein, the A1 pin of the chip CU7 and the GND pin of the chip CU7 are grounded respectively, the A0 pin of the chip CU7 and the VS pin of the chip CU7 are connected to the third power supply respectively, the SDA pin of the chip CU7 is connected to the control module through the resistor R649, the SCL pin of the chip CU7 is connected to the control module through the resistor R650, the IN+ pin of the chip CU7 is connected to the switch module through the resistor R646, the IN- pin of the chip CU7 is connected to the switch module through the resistor R648, and the VBUS pin of the chip CU7 is connected to the switch module through the resistor R647.

8. The detection circuit according to claim 2, characterized in that: The second detection module includes a second low current detection unit and a second high current detection unit; The second low current detection unit includes a chip CU2, a resistor R606, a resistor R607, a resistor R632, a resistor R633, and a resistor R604; wherein the A1 pin of the chip CU2, the A0 pin of the chip CU2, and the GND pin of the chip CU2 are all grounded, the SDA pin of the chip CU2 is connected to the control module through the resistor R606, the SCL pin of the chip CU2 is connected to the control module through the resistor R607, the IN+ pin of the chip CU2 is connected to the switch module through the resistor R632, the IN- pin of the chip CU2 is connected to the switch module through the resistor R633, the VBUS pin of the chip CU2 is connected to the switch module through the resistor R604, and the VS pin of the chip CU2 is connected to a third power supply; The second high current detection unit includes chip CU9, resistor R659, resistor R660, resistor R656, resistor R658, and resistor R657; wherein, the A1 pin of the chip CU9 and the GND pin of the chip CU9 are grounded respectively, the A0 pin of the chip CU9 and the VS pin of the chip CU9 are connected to the third power supply respectively, the SDA pin of the chip CU9 is connected to the control module through the resistor R659, the SCL pin of the chip CU9 is connected to the control module through the resistor R660, the IN+ pin of the chip CU9 is connected to the switch module through the resistor R656, the IN- pin of the chip CU9 is connected to the switch module through the resistor R658, and the VBUS pin of the chip CU9 is connected to the switch module through the resistor R657.

9. The detection circuit according to claim 1, characterized in that: The first interface includes an interface JSSD1, a resistor XR379, and a resistor XR478; The GND_14 pin of the interface JSSD1 is respectively connected to the first end of the resistor XR379 and the first end of the resistor XR478, the second end of the resistor XR379 is connected to the third power supply, the second end of the resistor XR478 is connected to the control module, the 3P3V_1 pin of the interface JSSD1, the 3P3V_2 pin of the interface JSSD1, the 3P3V_3 pin of the interface JSSD1, the 3P3V_4 pin of the interface JSSD1, the 3P3V_5 pin of the interface JSSD1, the 3P3V_6 pin of the interface JSSD1, the 3P3V_7 pin of the interface JSSD1, the 3P3V_8 pin of the interface JSSD1, and the 3P3V_9 pin of the interface JSSD1 are all connected to the switch module.

10. A detection device, characterized in that: The detection device comprises the detection circuit according to any one of claims 1 to 9.

Images