Chip testing method and device and storage medium

Abstract

The embodiment of the invention discloses a chip testing method and device and a storage medium, a target test item and a target configuration parameter corresponding to the target test item sent by an upper computer are received, and the target configuration parameter is used for enabling a test board card of a lower computer to execute the target test item before executing the target test item and / or to execute the target test item; after the target test item is executed, the server is in a required target test state; based on the target configuration parameter and the target test item, testing the to-be-tested object to obtain target test data corresponding to the target test item; and sending the target test data to the upper computer, so that the upper computer performs data processing on the target test data to obtain the target test result, thereby facilitating expansion of multiple test scenes and improvement of test diversity.

Description

Technical Field

[0001] The present disclosure relates to chip testing technology, and in particular to a chip testing method, device and storage medium. Background Art

[0002] Chip testing is the process of controlling the test system hardware to test various parameters of the chip under test, which is used to determine whether the chip under test can reach or exceed the pre-defined design indicators.

[0003] Before testing a chip, multiple test items are pre-set to test different types of chip parameters or to test the same type of parameters multiple times. However, there may be test items that need to be coupled among the multiple test items. For example, the execution of one test item depends on the execution result of another test item, that is, it needs to be executed after the execution of another test item is completed. The test process of multiple test items has certain limitations and is not easy to adjust and expand. Summary of the invention

[0004] The embodiments of the present disclosure provide a chip testing method, device and storage medium to solve the above technical problems to a certain extent.

[0005] One aspect of an embodiment of the present disclosure provides a chip testing method for a lower computer, including:

[0006] Receiving a target test item and a target configuration parameter corresponding to the target test item sent by the upper computer, wherein the target configuration parameter is used to make the test board of the lower computer be in a desired target test state before executing the target test item and / or after executing the target test item;

[0007] Based on the target configuration parameters and the target test items, the object to be tested is tested to obtain target test data corresponding to the target test items;

[0008] The target test data is sent to the host computer so that the host computer processes the target test data to obtain a target test result.

[0009] Another aspect of the embodiments of the present disclosure provides a chip testing method for a host computer, including:

[0010] Obtaining a pre-configured target test item and a target configuration parameter corresponding to the target test item;

[0011] Send the target test item and the target configuration parameter to the lower computer, so that the lower computer tests the object to be tested based on the target configuration parameter and the target test item to obtain target test data corresponding to the target test item;

[0012] The target test data sent by the lower computer is received, and data processing is performed on the target test data to obtain a target test result.

[0013] Another aspect of the embodiments of the present disclosure provides a chip testing device for a lower computer, including:

[0014] A parameter receiving module, used for receiving a target test item sent by a host computer and a target configuration parameter corresponding to the target test item, wherein the target configuration parameter is used to make the test board of the slave computer be in a desired target test state before executing the target test item and / or after executing the target test item;

[0015] An object testing module, used to test the object to be tested based on the target configuration parameters and the target test items, and obtain target test data corresponding to the target test items;

[0016] The data sending module is used to send the target test data to the host computer so that the host computer processes the target test data to obtain a target test result.

[0017] Another aspect of the embodiments of the present disclosure provides a chip testing device for a host computer, including:

[0018] A data acquisition module, used to acquire pre-configured target test items and target configuration parameters corresponding to the target test items;

[0019] A parameter sending module, used for sending the target test item and the target configuration parameter to the lower computer, so that the lower computer tests the object to be tested based on the target configuration parameter and the target test item, and obtains the target test data corresponding to the target test item;

[0020] The data receiving module is used to receive the target test data sent by the lower computer, perform data processing on the target test data, and obtain a target test result.

[0021] Another aspect of the embodiments of the present disclosure provides an electronic device, comprising: a memory for storing a computer program; a processor for executing the computer program stored in the memory, and when the computer program is executed, the chip testing method described in any of the above embodiments is implemented.

[0022] Another aspect of the embodiments of the present disclosure provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the chip testing method described in any of the above embodiments is implemented.

[0023] Another aspect of the embodiments of the present disclosure provides a computer program product, including a computer program, which, when executed by a processor, implements the chip testing method described in any of the above embodiments.

[0024] In the disclosed embodiment, corresponding target configuration parameters are set for target test items used to test the object to be tested. The target configuration parameters can enable the test board in the lower computer to reach the desired target test state before executing the target test item and / or after executing the target test item. After the lower computer receives the target test item and the corresponding target configuration parameters, it tests the object to be tested based on the target test item and the target configuration parameters to obtain target test data, and sends the target test data to the upper computer so that the upper computer obtains the target test result based on the target test data. By setting the target configuration parameters, the test board used to test the object to be tested can quickly reach the target test state required before or after the test, thereby reducing the debugging process and helping to improve the test efficiency.

[0025] In addition, for some test scenarios that need to meet special conditions, such as test item coupling scenarios, by setting the target configuration parameters, the test board can automatically adjust to the corresponding target test state based on the target configuration parameters during the test process to meet special conditions. The test items that need to be coupled can be decoupled, which helps to expand various test scenarios and improve test diversity.

[0026] The technical solution of the present disclosure is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings, which constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0028] The present disclosure may be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0029] Figure 1 is a structural schematic diagram of a testing device provided by an exemplary embodiment of the present disclosure;

[0030] Figure 2 is a flow chart of a chip testing method provided by an exemplary embodiment of the present disclosure;

[0031] Figure 3 is a flow chart of a chip testing method provided by another exemplary embodiment of the present disclosure;

[0032] Figure 4 is a flow chart of a chip testing method provided by another exemplary embodiment of the present disclosure;

[0033] Figure 5is a schematic diagram of module interaction of a testing tool provided by an exemplary embodiment of the present disclosure;

[0034] Figure 6 is a flowchart of a test process executed by a test tool provided by an exemplary embodiment of the present disclosure;

[0035] Figure 7 is a schematic structural diagram of a chip testing device provided by an exemplary embodiment of the present disclosure;

[0036] Figure 8 is a schematic structural diagram of a chip testing device provided by another exemplary embodiment of the present disclosure;

[0037] Fig. 9 It is a schematic diagram of the structure of an electronic device provided by an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0038] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless otherwise specifically stated.

[0039] Those skilled in the art can understand that the terms "first" and "second" in the embodiments of the present disclosure are only used to distinguish different steps, devices or modules, etc., and neither represent any specific technical meaning nor indicate the necessary logical order between them.

[0040] It should also be understood that in the embodiments of the present disclosure, “plurality” may refer to two or more than two, and “at least one” may refer to one, two, or more than two.

[0041] It should also be understood that any component, data or structure mentioned in the embodiments of the present disclosure can generally be understood as one or more, unless explicitly limited or otherwise indicated in the context.

[0042] In addition, the term "and / or" in the present disclosure is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in the present disclosure generally indicates that the associated objects before and after are in an "or" relationship.

[0043] It should also be understood that the description of the various embodiments in the present disclosure focuses on the differences between the various embodiments, and the same or similar aspects thereof can be referenced to each other, and for the sake of brevity, they will not be described one by one.

[0044] At the same time, it should be understood that for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0045] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present disclosure, its application, or uses.

[0046] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0047] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0048] The disclosed embodiments can be applied to electronic devices such as terminal devices, computer systems, servers, etc., which can operate with many other general or special computing system environments or configurations. Examples of well-known terminal devices, computing systems, environments and / or configurations suitable for use with electronic devices such as terminal devices, computer systems, servers, etc. include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network personal computers, small computer systems, large computer systems, and distributed cloud computing technology environments including any of the above systems, etc.

[0049] Electronic devices such as terminal devices, computer systems, servers, etc. can be described in the general context of computer system executable instructions (such as program modules) executed by computer systems. Generally, program modules can include routines, programs, object programs, components, logic, data structures, etc., which perform specific tasks or implement specific abstract data types. Computer systems / servers can be implemented in a distributed cloud computing environment, where tasks are performed by remote processing devices linked through a communication network. In a distributed cloud computing environment, program modules can be located on local or remote computing system storage media including storage devices.

[0050] The chip test process includes verifying the chip's power supply rules, digital signal level rules, logic rules, and timing rules. During the test verification process, the test vector (Pattern), timing, drive level, comparison voltage and other parameters of the automatic test equipment (ATE) need to be set. The ATE test board can output the corresponding waveform to the chip under test according to the set parameters. When the waveform is output from the chip, the test board can capture the level at the corresponding moment according to the set trigger time. After that, it can be determined whether the level captured by the test board is consistent with the preset expected waveform, and the test result of the chip under test can be determined, which includes test pass (Pass) and test fail (Fail) results.

[0051] In each process of chip testing, different test items (such as test items for testing chip current, voltage, frequency, etc.) may require different special test conditions. In the embodiment of the present disclosure, a chip testing method is provided. In the process of testing the object to be tested, the test can be performed based on the target test item and the target configuration parameters corresponding to the target test item to meet the required special test conditions and enable the test board to reach the required target test state, which is conducive to the expansion of different special test scenarios and to improving test efficiency.

[0052] like Figure 1 As shown, it shows a schematic diagram of a test device provided by an exemplary embodiment of the present disclosure. The test device includes an upper computer 11 and a lower computer 12, and the lower computer 12 includes a test board 121. The test device can be used to perform semiconductor testing on an object to be tested, and the object to be tested may include a wafer, a chip, etc. The upper computer 11 and the lower computer 12 of the test device interact to complete the test process of the object to be tested.

[0053] In an exemplary embodiment, test items for testing the object to be tested and configuration parameters corresponding to each test item may be preconfigured, wherein the configuration parameters corresponding to each test item are used to make the test board 121 in the test state required by the test item before executing the target test item and / or after executing the target test item. The host computer 11 may obtain the preconfigured target test item and the target configuration parameters corresponding to the target test item, send the target test item and the target configuration parameters to the lower computer 12, the lower computer 12 receives the target test item and the target configuration parameters sent by the host computer 11, test the object to be tested based on the target configuration parameters and the target test item, obtain the target test data corresponding to the target test item, send the target test data to the host computer 11, the host computer 11 receives the target test data sent by the lower computer 12, and perform data processing on the target test data to obtain the target test result.

[0054] like Figure 2As shown, it shows a flowchart of a chip testing method provided by an exemplary embodiment of the present disclosure, which can be used for the lower computer 12 described in the above embodiment, and the method includes:

[0055] Step 201, receiving a target test item and a target configuration parameter corresponding to the target test item sent by a host computer, wherein the target configuration parameter is used to make the test board of the slave computer in a desired target test state before executing the target test item and / or after executing the target test item.

[0056] When testing the object to be tested, test items for testing the object to be tested may be pre-configured to implement testing of different aspects of the object to be tested. For example, the test items for testing the object to be tested may include different types of test items, such as test items for parameter testing, functional testing, performance testing, etc., and may also include multiple different test items of the same type, for example, including multiple test items for testing frequency.

[0057] For different test items, the configuration parameters corresponding to the test items can be pre-configured, and the configuration parameters are used to adjust the test status of the test board. The corresponding target configuration parameters are set for the target test items, so that the test board can reach the target test status before testing the object to be tested based on the target test items, and / or after testing the object to be tested based on the target test items.

[0058] Step 202: Test the object to be tested based on the target configuration parameters and the target test items to obtain target test data corresponding to the target test items.

[0059] In a possible implementation, before the control test board tests the object to be tested based on the target test items, and / or after the object to be tested, the test board can be debugged based on the target configuration parameters to reach the target test state.

[0060] When the target configuration parameters include parameters for enabling the test board of the lower computer to reach the required target test state before executing the target test items, the test board can be debugged based on the target configuration parameters. After the debugging is completed, the test board is controlled to test the object to be tested based on the target test items to obtain the target test data corresponding to the target test items.

[0061] When the target configuration parameters include parameters for enabling the test board of the lower computer to reach the desired target test state after executing the target test items, the test board can be controlled to test the object to be tested to obtain target test data. After the test, the test board is debugged based on the target configuration parameters to achieve the desired target test state.

[0062] Schematically, the target test item may be an input current test (such as an IIL test) in a direct current (DC) test. When performing an IIL test, first apply VDDmax to the power supply end, apply a high level (VIH) to the input pin, and pre-process it to a logic 1 state. Then, connect the input pin to the pin to be tested of the object to be tested, drive a low level input, measure the current of the pin to be tested, and compare it with the expected IIL boundary to obtain the test process of the pin to be tested. After completion, switch to another pin to be tested. The pre-processing operation needs to be repeated continuously during this process. In a possible implementation, the corresponding target configuration parameters may be pre-set so that the lower computer can debug the input pin of the test board according to the target configuration parameters to apply VIH and process it to a logic 1 state, so that the test board reaches the required test state before the input current test is performed to meet the input current test requirements. By setting the target configuration parameters, repeated pre-processing operations can be reduced and test efficiency can be improved.

[0063] Step 203: Send the target test data to the host computer so that the host computer processes the target test data to obtain the target test result.

[0064] After the lower computer test obtains the target test data corresponding to the target test item, the target test data can be processed to obtain the target test result. In schematic form, the level captured by the test board can be processed, and the processed waveform can be compared with the expected waveform to obtain the corresponding test result.

[0065] In the disclosed embodiment, corresponding target configuration parameters are set for target test items used to test the object to be tested. The target configuration parameters can enable the test board in the lower computer to reach the desired target test state before executing the target test item and / or after executing the target test item. After the lower computer receives the target test item and the corresponding target configuration parameters, it tests the object to be tested based on the target test item and the target configuration parameters to obtain target test data, and sends the target test data to the upper computer so that the upper computer obtains the target test result based on the target test data. By setting the target configuration parameters, the test board used to test the object to be tested can reach the target test state required before or after the test, thereby reducing the debugging process and helping to improve the test efficiency.

[0066] In addition, for some test scenarios that need to meet special conditions, such as test item coupling scenarios, by setting the target configuration parameters, the test board can automatically adjust to the corresponding target test state based on the target configuration parameters during the test process to meet special conditions. The test items that need to be coupled can be decoupled, which helps to expand various test scenarios and improve test diversity.

[0067] In one possible implementation, the target configuration parameters include at least one of a pre-configuration parameter and a post-configuration parameter, the pre-configuration parameter being used to put the test board in a pre-test state before executing the target test item, and the post-configuration parameter being used to put the test board in a post-test state after executing the target test item.

[0068] The pre-test state is the target test state that the test board needs to reach before testing the target test item, and the post-test state is the target test state that the test board needs to reach after testing the object to be tested based on the target test item. In a possible implementation, the test board can be debugged based on the pre-configuration parameters and / or the post-configuration parameters to enable the test board to reach the pre-test state and / or the post-test state.

[0069] Optionally, the pre-configuration parameters may include parameters for initializing the test board and at least one of the test parameters, wherein the parameters for initializing the test board are used to put the test board in a normal test state, and the test parameters are used to debug parameters such as voltage and current of the test board to ensure the smooth execution of the target test item. The post-configuration parameters may include board reset parameters, which are used to reset the test board after executing the target test item.

[0070] When the target configuration parameters include pre-configuration parameters, in the process of testing the object to be tested based on the target configuration parameters and the target test items, the test board can be configured based on the pre-configuration parameters so that the test board is in a pre-test state, and the test board in the pre-test state can be controlled based on the target test items to test the object to be tested. After receiving the pre-configuration parameters and the target test items, the lower computer first uses the pre-configuration parameters to debug the test board, and then uses the debugged test board to test the object to be tested.

[0071] In schematic form, in combination with the above example, when the target test item is a test item corresponding to the input current test, the pre-configuration parameters can be set so that the test board reaches the required pre-test state before the input current test, that is, VIH is applied to the input pin of the test board and processed as a logic 1 state.

[0072] When the target configuration parameters include post-configuration parameters, in the process of testing the object to be tested based on the target configuration parameters and the target test items, the test board can be controlled to test the object to be tested based on the target test items, and the test board after executing the target test items can be configured based on the post-configuration parameters so that the test board is in a post-test state. After the lower computer receives the target test items and the corresponding post-configuration parameters, it tests the object to be tested based on the target test items, and after the test, the test board is debugged based on the post-configuration parameters.

[0073] When the target configuration parameters include pre-configuration parameters and post-configuration parameters, in the process of testing the object to be tested based on the target configuration parameters and the target test items, the test board can be configured based on the pre-configuration parameters so that the test board is in a pre-test state, and based on the target test items, the test board in the pre-test state can be controlled to test the object to be tested. After the test, the test board after executing the target test items can be configured based on the post-configuration parameters so that the test board is in a post-test state.

[0074] In the embodiment of the present disclosure, by setting at least one of the pre-configuration parameters and the post-configuration parameters, the test board can be automatically debugged based on at least one of the pre-configuration parameters and the post-configuration parameters during the test process, so that the test board satisfies at least one of the pre-test state and the post-test state, which helps to improve test efficiency and helps to expand different types of special test scenarios.

[0075] In an exemplary embodiment, the post-configuration parameters may include a delayed power-on parameter, and the delayed power-on parameter includes a delay time (Waiting time) for the power board to be powered on again after being powered off. The test board includes a power board, and the power board is used to supply power to the object to be tested. During the test, the relay in the power board needs to be repeatedly closed and opened. When the relay is opened when there is current passing through, or when there is current passing through the moment of closing the relay, hot switching will cause damage to the relay and reduce the service life of the relay. In a possible implementation, the post-configuration parameters including the delayed power-on parameter can be configured, and the delayed power-on parameter can be used to control the interval between powering off and powering on again after the power board is powered off, thereby avoiding hot switching.

[0076] After receiving the post-configuration parameters including the delayed power-on parameter, the lower computer configures the power-on and power-off states of the power board in the test board after executing the target test item based on the delayed power-on parameter. In a possible implementation, the lower computer controls the power-on and power-off states of the power board according to the delay time included in the delayed power-on parameter. After the test board completes the test based on the target test item, the power board is first controlled to power off. When the power-off time reaches the delay time, the power board is controlled to power on again to supply power to the chip to be tested. Specifically, the lower computer can configure the power-on and power-off states of the power pins (pins) in the power board for powering the object to be tested based on the delayed power-on parameter.

[0077] Indicatively, the delay time may be 200ms. When the power-off time reaches 200ms, the power board may be controlled to power on again.

[0078] In the embodiment of the present disclosure, by configuring the delayed power-on parameters, the relay in the power board can be powered on with a delay after power off, thereby avoiding hot switching operations of the relay. In addition, the power board can be prevented from overheating due to the delayed power-on operation, which can effectively avoid damage to the board.

[0079] In a possible implementation, the target configuration parameters include control configuration parameters, and the control configuration parameters are used to indicate whether to start a configuration operation based on the target configuration parameters. For a target test item, there may be a situation where the target configuration parameters do not need to be used. The control configuration parameters used to control the configuration operation based on the target configuration parameters can be pre-set, and the lower computer can determine whether to use the target configuration parameters according to the control configuration parameters.

[0080] Optionally, the control configuration parameters include a first control parameter for starting the configuration operation and a second control parameter for closing the configuration operation. Exemplarily, the first control parameter may be on, and the second control parameter may be off.

[0081] After receiving the target configuration parameters including the control configuration parameters, the lower computer starts the configuration operation in response to the control configuration parameter instruction, tests the object to be tested based on the target configuration parameters and the target test items, and obtains the target test data corresponding to the target test items.

[0082] When the control configuration parameter is the first control parameter, the lower computer determines to start the configuration operation, and can test the object to be tested based on the target configuration parameter and the target test item to obtain the target test data corresponding to the target test item. When the control configuration parameter is the second control parameter, the lower computer can directly control the test board to test the object to be tested based on the target test item without configuring the test board.

[0083] When the target configuration parameter includes a control configuration parameter and a pre-configuration parameter, if the control configuration parameter is a first control parameter, the lower computer can debug the test board based on the pre-configuration parameter, and control the debugged test board to test the object to be tested based on the target test item. If the control configuration parameter is a second control parameter, the lower computer can control the test board to test the object to be tested based on the target test item.

[0084] When the target configuration parameter includes a control configuration parameter and a post-configuration parameter, if the control configuration parameter is a first control parameter, the lower computer can control the test board to test the object to be tested based on the target test item, and debug the test board after the test based on the post-configuration parameter. If the control configuration parameter is a second control parameter, the lower computer can control the test board to test the object to be tested based on the target test item, and there is no need to debug the test board based on the post-configuration parameter after the test.

[0085] In a possible implementation, a first control configuration parameter may be set for a pre-configuration parameter, and a second control configuration parameter may be set for a post-configuration parameter, wherein the first control configuration parameter and the second control configuration parameter are respectively used to control whether to start the configuration operation of the test board before the test and the configuration parameters of the test board after the test. When the target configuration parameter includes a pre-configuration parameter, a post-configuration parameter, a first control configuration parameter, and a second control configuration parameter, if the first control configuration parameter and the second control configuration parameter are the first control parameter, the lower computer may debug the test board based on the pre-configuration parameter, control the debugged test board to test the object to be tested based on the target test item, and debug the post-test test board based on the post-configuration parameter after the test is completed.

[0086] In a possible implementation, the target configuration parameters include execution mode parameters, and the execution mode parameters are used to execute the execution mode of the configuration operation based on the target configuration parameters, and the execution modes include a periodic execution mode and a full-range execution mode. In a possible case, testing the object to be tested based on the target test items includes multiple test processes, and the multiple test processes may include multiple test processes based on the same parameters, and may also include multiple test processes based on different parameters, such as during the current test process, inputting different currents to the object to be tested and performing multiple tests. For the case of multiple tests, the execution model parameters for the configuration parameters can be pre-configured to instruct the lower computer to execute the execution mode of the configuration operation based on the target configuration parameters.

[0087] When the lower computer receives the target configuration parameter including the execution mode parameter, in response to the execution mode parameter indicating that the execution mode is the periodic execution mode, the interval test number corresponding to the execution cycle is determined. When the number of tests reaches the interval test number, the test board is configured based on the target configuration parameter to put the test board in the target test state, and the number of tests is the number of tests performed on the object to be tested based on the target test item.

[0088] In an exemplary embodiment, when the execution mode parameter indicates that the execution model is a periodic execution mode, if the target configuration parameter includes a pre-configuration parameter, then whenever the number of tests reaches the interval test number, the test board is configured based on the pre-configuration parameter so that the test board is in a pre-test state, and then the test board in the pre-test state is controlled to test the object to be tested based on the target test item. If the target configuration parameter is a post-configuration parameter, then whenever the number of tests reaches the interval test number, the test board is debugged based on the post-configuration parameter so that the test board is in a post-test state.

[0089] Indicatively, the number of interval tests can be 1. If the target configuration parameters include pre-configuration parameters, before each test, the test board is configured based on the pre-configuration parameters so that the test board is in a pre-test state, and the test board in the pre-test state is controlled to test the object to be tested based on the target test items. After the test is completed, the test board is configured again based on the pre-configuration parameters so that the test board is in a pre-test state, and the next test is performed. If the target configuration parameters include post-configuration parameters, after each test board tests the object to be tested based on the target test items, the test board is debugged based on the post-configuration parameters so that the test board is in a post-test state.

[0090] When the lower computer receives the target configuration parameters including the execution mode parameters, in response to the execution mode parameters indicating that the execution mode is the full-range execution mode, based on the target configuration parameters, the test board is configured to put the test board in the target test state, and based on the target test items, m tests are performed on the object to be tested, where m is a preset integer not less than 1.

[0091] In one example, if the target configuration parameter includes a pre-configuration parameter, the test board is configured based on the pre-configuration parameter so that the test board is in a pre-test state, and then the test board in the pre-test state is controlled to perform m tests on the object to be tested based on the target test item. If the target configuration parameter is a post-configuration parameter, after the test board performs m tests on the object to be tested based on the target test item, the test board is debugged based on the post-configuration parameter so that the test board is in a post-test state.

[0092] Schematically, m can be 100, and the target configuration parameters include pre-configuration parameters and post-configuration parameters. Before the test starts, the test board is configured based on the pre-configuration parameters to put the test board in a pre-test state. Afterwards, the test board in the pre-test state is controlled to perform 100 tests on the object to be tested based on the target test items. After 100 tests, the test board can be debugged based on the post-configuration parameters to put the test board in a post-test state.

[0093] In an illustrative example, as shown in Table 1, the target configuration parameters include the test item name, pre-configuration parameters, and post-configuration parameters of the corresponding target test item. The post-configuration parameters specifically include delayed power-on parameters. The delayed power-on parameters include control configuration parameters (off) and execution mode parameters (full range execution mode parameters (All) / periodic execution model parameters (Point)), a set of power-on and power-off pins (Pins) to be controlled, and a delay time for powering on again after powering off.

[0094] Table 1

[0095]

[0096]

[0097] In the disclosed embodiment, the control configuration parameters can be set for the target configuration parameters, so that the lower computer automatically determines whether to execute the configuration operation according to the control configuration parameters, so as to meet the test requirements in different scenarios, which is conducive to the expansion of diversified test scenarios. In addition, the target configuration parameters can also include execution mode parameters, which can configure the execution mode, so that the lower computer controls the execution mode of the configuration operation based on the execution module parameters, so as to meet the test requirements in different scenarios, which is conducive to the expansion of diversified test scenarios.

[0098] like Figure 3 As shown, it shows a flowchart of a chip testing method provided by an exemplary embodiment of the present disclosure. The method can be used for the host computer 11 described in the above embodiment. The method includes:

[0099] Step 301: Obtain pre-configured target test items and target configuration parameters corresponding to the target test items.

[0100] In a possible implementation, the host computer may sequentially obtain different pre-configured test items and configuration parameters corresponding to each test item according to the execution order of the test items.

[0101] Step 302 : Send the target test items and target configuration parameters to the lower computer, so that the lower computer tests the object to be tested based on the target configuration parameters and the target test items, and obtains target test data corresponding to the target test items.

[0102] When the target test items and the corresponding target configuration parameters are obtained, the target configuration parameters and target test items can be sent to the lower computer. The lower computer debugs the test board based on the target configuration parameters to put it in the required target test state, and controls the test board to test the object to be tested based on the target test items to obtain the target test data corresponding to the target test items.

[0103] Step 303: receiving the target test data sent by the lower computer, performing data processing on the target test data, and obtaining the target test result.

[0104] After the lower computer obtains the target test data, it sends the target test data to the upper computer, and the upper computer determines the corresponding target test result.

[0105] In an exemplary embodiment, Figure 4As shown, during the chip testing process, the upper computer can obtain the target test items and target configuration parameters, and then execute the parameter preloading process, including loading the parameters corresponding to the target test items and the target configuration parameters. After the preloading is completed, the test item execution command can be sent to the lower computer, which includes the target test items and the target configuration parameters. After that, the lower computer can control the test board to execute the test process on the object to be tested based on the target test items and the target configuration parameters, obtain the target test data, and send the target test data to the upper computer. The upper computer can process the target test data, obtain the target test results, and display the target test results.

[0106] After the target test result is determined, the host computer displays the target test result. In one possible implementation, a custom graphics rendering framework is used to display the test result graph. Schematically, the test result graph is displayed in the form of a Plot graph, wherein the display unit, the coordinate axis, and the canvas used to display the results in the custom graphics rendering framework are independent of each other, wherein the canvas and the coordinate axis are interactive units, and the user can adjust the displayed results in the canvas through interactive operations such as dragging and zooming to view different test results. Schematically, the canvas can support the drawing of the maximum amount of data for displaying a single-station site, such as supporting the drawing of 1024*1024 test result data. By dragging and zooming the canvas, different test result data drawn can be displayed in the display unit.

[0107] Through independent display units, coordinate axes and a canvas for displaying results, a large amount of test result data can be drawn in the canvas to avoid the limitation of the data that can be displayed by the display unit on the data that can be drawn on the canvas, so that it supports the display of a large amount of data.

[0108] In an exemplary embodiment, a test tool (such as ShmooPlot tool) can be used to control the execution of test items and display test results. Figure 5 As shown, it shows a schematic diagram of the calling relationship between each module of the test tool during the test item execution process. First, perform interface initialization and data initialization process, in the data initialization process, obtain test item data and configuration parameter data, in the interface initialization process, the menu bar module, toolbar and status bar displayed can be initialized, wherein, the menu bar module includes interactive controls for controlling the execution of test items and stopping test items, in response to the operation of the interactive control for executing the test items, the execution test item command can be sent to make the lower computer execute the test, and the test data obtained based on the test of the lower computer is determined, and the test result is displayed in the form of a Plot diagram, and the test result can also be exported (export), and the tool can also receive the test item result (Import) input, such as importing the stored test item result, etc. In response to the operation of the interactive control for stopping the test item, a stop test command can be sent to make the lower computer stop the test.

[0109] In the disclosed embodiment, corresponding target configuration parameters are set for target test items used to test the object to be tested. The target configuration parameters can enable the test board in the lower computer to reach the desired target test state before executing the target test items and / or after executing the target test items. The upper computer can send the target test items and the corresponding target configuration parameters to the lower computer. The lower computer tests the object to be tested based on the target test items and the target configuration parameters to obtain target test data, and sends the target test data to the upper computer so that the upper computer obtains the target test results based on the target test data. By setting the target configuration parameters, the test board used to test the object to be tested can reach the target test state required before or after the test, thereby reducing the debugging process and helping to improve the test efficiency.

[0110] In addition, for some test scenarios that need to meet special conditions, such as test item coupling scenarios, by setting the target configuration parameters, the test board can automatically adjust to the corresponding target test state based on the target configuration parameters during the test process to meet special conditions. The test items that need to be coupled can be decoupled, which helps to expand various test scenarios and improve test diversity.

[0111] In a possible implementation, during the test process based on the target test item, the target configuration parameters can also be modified in real time. In response to the modification operation on the target configuration parameters, the upper computer obtains the modified configuration parameters; and sends the modified configuration parameters to the lower computer, so that the lower computer tests the object to be tested based on the modified configuration parameters and the target test item, and obtains the target test data corresponding to the target test item.

[0112] In a possible implementation, Figure 6 As shown, the test tool can obtain data after startup, including test items and configuration parameters. In the process of executing the test items, parameter verification is first performed to determine whether the parameters included in the test items and the configuration parameters meet the use conditions. After that, it is determined whether there is a test item being executed. If not, the next test item is selected, and it is determined whether the configuration parameters are modified. It can be determined whether the configuration parameters need to be modified based on the re-acquired test items. If they need to be modified, the configuration parameters are modified. After that, an execution command can be sent, which includes the selected test items and the corresponding configuration parameters. In the process of stopping the test items, it is determined whether there is a test item being executed. If so, in response to the stop command, a stop command can be sent to the lower computer. After obtaining the target test results, the test results can be displayed. The test results can be displayed in the form of a Plot graph, and the test results support switching stations. In response to the station switching operation, the test result data corresponding to the switched station is obtained, and based on the test result data corresponding to the switched station, the display results are refreshed.

[0113] like Figure 7As shown, it shows a schematic diagram of the structure of a chip testing device provided by an exemplary embodiment of the present disclosure, the device comprising:

[0114] The parameter receiving module 701 is used to receive the target test item sent by the upper computer and the target configuration parameters corresponding to the target test item, wherein the target configuration parameters are used to make the test board of the lower computer be in the required target test state before executing the target test item and / or after executing the target test item;

[0115] An object testing module 702 is used to test the object to be tested based on the target configuration parameters and the target test items, and obtain target test data corresponding to the target test items;

[0116] The data sending module 703 is used to send the target test data to the host computer, so that the host computer processes the target test data to obtain a target test result.

[0117] In an exemplary embodiment, the target configuration parameter includes at least one of a pre-configuration parameter and a post-configuration parameter, wherein the pre-configuration parameter is used to put the test board in a pre-test state before executing the target test item, and the post-configuration parameter is used to put the test board in a post-test state after executing the target test item;

[0118] The object testing module 702 is further used for:

[0119] Based on the pre-configuration parameters, configure the test board to put the test board in the pre-test state, and based on the target test items, control the test board in the pre-test state to test the object to be tested;

[0120] and / or,

[0121] Based on the target test item, the test board is controlled to test the object to be tested, and based on the post-configuration parameters, the test board is configured after executing the target test item so that the test board is in the post-test state.

[0122] In an exemplary embodiment, the post-configuration parameter includes a power-on delay parameter, and the power-on delay parameter includes a delay time for the power board to be powered on again after being powered off;

[0123] The object testing module 702 is further used for:

[0124] Based on the delayed power-on parameter, the power-on and power-off states of the power board in the test board after executing the target test item are configured, and the power board is used to supply power to the object to be tested.

[0125] In an exemplary embodiment, the target configuration parameters include control configuration parameters, and the control configuration parameters are used to indicate whether to start a configuration operation based on the target configuration parameters;

[0126] The object testing module 702 is further used for:

[0127] In response to the control configuration parameter indicating the start of the configuration operation, the object to be tested is tested based on the target configuration parameter and the target test item to obtain target test data corresponding to the target test item.

[0128] In an exemplary embodiment, the target configuration parameter includes an execution mode parameter, the execution mode parameter is used to execute an execution mode of a configuration operation based on the target configuration parameter, the execution mode includes a periodic execution mode and a full-range execution mode;

[0129] The object testing module 702 is further used for:

[0130] In response to the execution mode parameter indicating that the execution mode is the periodic execution mode, determining the number of interval tests corresponding to the execution cycle;

[0131] When the number of tests reaches the interval test number, the test board is configured based on the target configuration parameters to put the test board in the target test state, and the number of tests is the number of tests performed on the object to be tested based on the target test item.

[0132] In response to the execution mode parameter indicating that the execution mode is the full-range execution mode, based on the target configuration parameters, the test board is configured so that the test board is in the target test state, and the object to be tested is tested m times based on the target test items, wherein m is a preset integer not less than 1.

[0133] like Figure 8 As shown, it shows a schematic structural diagram of a chip testing device provided by another exemplary embodiment of the present disclosure, the device comprising:

[0134] The data acquisition module 801 is used to acquire pre-configured target test items and target configuration parameters corresponding to the target test items;

[0135] A parameter sending module 802 is used to send the target test item and the target configuration parameter to the lower computer, so that the lower computer tests the object to be tested based on the target configuration parameter and the target test item to obtain target test data corresponding to the target test item;

[0136] The data receiving module 803 is used to receive the target test data sent by the lower computer, perform data processing on the target test data, and obtain a target test result.

[0137] In an exemplary embodiment, the data acquisition module 801 is further configured to acquire a modified configuration parameter in response to a modification operation on the target configuration parameter;

[0138] The parameter sending module 802 is further used to send the modified configuration parameters to the lower computer, so that the lower computer tests the object to be tested based on the modified configuration parameters and the target test items to obtain target test data corresponding to the target test items.

[0139] The chip testing device in the embodiment of the present disclosure corresponds to the embodiment of the chip testing method in the present disclosure, and the relevant contents can be referenced to each other, which will not be repeated here. The beneficial technical effects corresponding to the chip testing device in the embodiment of the present disclosure can refer to the corresponding beneficial technical effects of the corresponding exemplary method part above, which will not be repeated here.

[0140] In addition, an embodiment of the present disclosure further provides an electronic device, including:

[0141] Memory for storing computer programs;

[0142] The processor is used to execute the computer program stored in the memory, and when the computer program is executed, the chip testing method described in any of the above embodiments of the present disclosure is implemented.

[0143] Fig. 9 is a schematic diagram of the structure of an electronic device provided by an exemplary embodiment of the present disclosure, such as Fig. 9 As shown, the electronic device includes one or more processors and memory.

[0144] The processor may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device to perform desired functions.

[0145] The memory may store one or more computer program products, and the memory may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, a random access memory (RAM) and / or a cache memory (cache), etc. The non-volatile memory may include, for example, a read-only memory (ROM), a hard disk, a flash memory, etc. One or more computer program products may be stored on the computer-readable storage medium, and the processor may run the computer program product to implement the chip testing method of each embodiment of the present disclosure described above and / or other desired functions.

[0146] In one example, the electronic device may further include: an input device and an output device, and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0147] In addition, the input device may also include, for example, a keyboard, a mouse, and the like.

[0148] The output device can output various information to the outside, including determined distance information, direction information, etc. The output device can include, for example, a display, a speaker, a printer, a communication network and a remote output device connected thereto, and the like.

[0149] Of course, to simplify, Fig. 9 Only some of the components related to the present disclosure in the electronic device are shown, and components such as a bus, an input / output interface, etc. are omitted. In addition, according to specific application situations, the electronic device may further include any other appropriate components.

[0150] In addition to the above-mentioned methods and devices, an embodiment of the present disclosure may also be a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the chip testing method according to various embodiments of the present disclosure described in the above part of this specification.

[0151] The computer program product may be written in any combination of one or more programming languages ​​to write program code for performing the operations of the disclosed embodiments, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0152] In addition, an embodiment of the present disclosure may also be a computer-readable storage medium having computer program instructions stored thereon, which, when executed by a processor, enables the processor to execute the steps of the chip testing method according to various embodiments of the present disclosure described in the above part of this specification.

[0153] The computer readable storage medium can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium can include, for example, but is not limited to, a system, device or device of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0154] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present disclosure. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, and are not limitations. The above details do not limit the present disclosure to the necessity of adopting the above specific details to be implemented.

[0155] Each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the system embodiment, since it basically corresponds to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0156] The block diagrams of the devices, apparatuses, equipment, and systems involved in this disclosure are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including," "comprising," "having," and the like are open words, referring to "including but not limited to," and can be used interchangeably therewith. The words "or" and "and" used herein refer to the words "and / or," and can be used interchangeably therewith, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to," and can be used interchangeably therewith.

[0157] The method and apparatus of the present disclosure may be implemented in many ways. For example, the method and apparatus of the present disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above order of steps for the method is for illustration only, and the steps of the method of the present disclosure are not limited to the order specifically described above, unless otherwise specifically stated. In addition, in some embodiments, the present disclosure may also be implemented as a program recorded in a recording medium, which includes machine-readable instructions for implementing the method according to the present disclosure. Therefore, the present disclosure also covers a recording medium storing a program for executing the method according to the present disclosure.

[0158] It should also be noted that in the apparatus, device and method of the present disclosure, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as equivalent solutions of the present disclosure.

[0159] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0160] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present disclosure to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. A chip testing method, characterized in that: The method is used for a lower computer, and the method comprises: Receiving a target test item and a target configuration parameter corresponding to the target test item sent by the upper computer, wherein the target configuration parameter is used to make the test board of the lower computer be in a desired target test state before executing the target test item and / or after executing the target test item; Based on the target configuration parameters and the target test items, the object to be tested is tested to obtain target test data corresponding to the target test items; The target test data is sent to the host computer so that the host computer processes the target test data to obtain a target test result.

2. The method according to claim 1, characterized in that The target configuration parameters include at least one of a pre-configuration parameter and a post-configuration parameter, wherein the pre-configuration parameter is used to put the test board in a pre-test state before executing the target test item, and the post-configuration parameter is used to put the test board in a post-test state after executing the target test item; The testing of the object to be tested based on the target configuration parameters and the target test items includes: Based on the pre-configuration parameters, configure the test board to put the test board in the pre-test state, and based on the target test items, control the test board in the pre-test state to test the object to be tested; and / or, Based on the target test item, the test board is controlled to test the object to be tested, and based on the post-configuration parameters, the test board is configured after executing the target test item so that the test board is in the post-test state.

3. The method according to claim 2, characterized in that The post-configuration parameters include a power-on delay parameter, and the power-on delay parameter includes a delay time for the power board to be powered on again after being powered off; The configuring the test board after executing the target test item so that the test board is in the post-test state includes: Based on the delayed power-on parameter, the power-on and power-off states of the power board in the test board after executing the target test item are configured, and the power board is used to supply power to the object to be tested.

4. The method according to any one of claims 1 to 3, characterized in that: The target configuration parameters include control configuration parameters, and the control configuration parameters are used to indicate whether to start a configuration operation based on the target configuration parameters; The step of testing the object to be tested based on the target configuration parameter and the target test item to obtain target test data corresponding to the target test item includes: In response to the control configuration parameter indicating the start of the configuration operation, the object to be tested is tested based on the target configuration parameter and the target test item to obtain target test data corresponding to the target test item.

5. The method according to any one of claims 1 to 3, characterized in that: The target configuration parameters include execution mode parameters, and the execution mode parameters are used to execute an execution mode of a configuration operation based on the target configuration parameters, and the execution mode includes a periodic execution mode and a full-range execution mode; The step of testing the object to be tested based on the target configuration parameter and the target test item to obtain target test data corresponding to the target test item includes: In response to the execution mode parameter indicating that the execution mode is the periodic execution mode, determining the number of interval tests corresponding to the execution cycle; When the number of tests reaches the interval test number, the test board is configured based on the target configuration parameters to put the test board in the target test state, and the number of tests is the number of tests performed on the object to be tested based on the target test item.

6. The method according to claim 5, characterized in that The step of testing the object to be tested based on the target configuration parameter and the target test item to obtain target test data corresponding to the target test item includes: In response to the execution mode parameter indicating that the execution mode is the full-range execution mode, based on the target configuration parameters, the test board is configured so that the test board is in the target test state, and the object to be tested is tested m times based on the target test items, wherein m is a preset integer not less than 1.

7. A chip testing method, characterized in that: The method is used for a host computer, and the method comprises: Obtaining a pre-configured target test item and a target configuration parameter corresponding to the target test item; Send the target test item and the target configuration parameter to the lower computer, so that the lower computer tests the object to be tested based on the target configuration parameter and the target test item to obtain target test data corresponding to the target test item; The target test data sent by the lower computer is received, and data processing is performed on the target test data to obtain a target test result.

8. The method according to claim 7, characterized in that The method further comprises: In response to a modification operation on the target configuration parameter, obtaining a modified configuration parameter; The modified configuration parameters are sent to the lower computer, so that the lower computer tests the object to be tested based on the modified configuration parameters and the target test items, and obtains target test data corresponding to the target test items.

9. An electronic device, characterized in that: include: Memory for storing computer programs; A processor is used to execute a computer program stored in the memory, and when the computer program is executed, the chip testing method described in any one of claims 1 to 6 is implemented, or the chip testing method described in any one of claims 7 to 8 is implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, it implements the chip testing method described in any one of claims 1 to 6, or implements the chip testing method described in any one of claims 7 to 8.

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