Simulation test method and device for equipment bandwidth, equipment and storage medium

Abstract

The invention relates to the technical field of computers, and discloses an equipment bandwidth simulation test method and device, equipment and a storage medium, and the method comprises the steps: configuring a preset transmission bandwidth for master equipment after the master equipment establishes a communication connection with slave equipment, starting a simulation test, and in the simulation test, setting a preset transmission bandwidth for the slave equipment; the master device transmits the first data to the slave device according to a preset transmission bandwidth; at the end of the simulation test, acquiring at least one transmission parameter value of the master device, and acquiring second data received by the slave device; judging whether the first data is consistent with the second data; and if not, testing to obtain that the actual transmission bandwidth of the main equipment is smaller than the preset transmission bandwidth, and determining the reason that the actual transmission bandwidth is smaller than the preset transmission bandwidth based on the at least one transmission parameter value. The method can solve the problems that whether the bandwidth value of the main equipment can reach the highest bandwidth or not and the efficiency and the accuracy rate are low when the bandwidth value of the main equipment does not reach the highest bandwidth.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a method, device, equipment and storage medium for simulating and testing device bandwidth. Background Art

[0002] With the gradual promotion of the application of Universal Serial Bus (USB) technology, more and more electronic products use USB interface functions, which are usually implemented by integrating USB devices in integrated circuits. When USB devices between integrated circuits communicate, for example, when a USB HOST device communicates with multiple USB DEVICE devices in real time, bandwidth requirements need to be met. For a USB HOST device, it is necessary to meet the demand for real-time communication with multiple USB DEVICE devices, and its bandwidth is usually required to be higher, and it needs to be designed with the maximum value specified in the USB protocol standard, while a USB DEVICE only needs to be designed with the highest bandwidth that matches it according to actual applications.

[0003] In actual applications, after the USB HOST device communicates with multiple USB DEVICE devices in real time, it is usually necessary to manually determine whether the bandwidth value designed by the USB HOST device can reach the maximum bandwidth, and it is necessary to manually determine the reason why the maximum bandwidth is not reached. This method is inefficient and has poor accuracy; at the same time, it will cause data transmission delays, data loss or errors, consumption of additional system resources, and poor system stability when the USB HOST device communicates with multiple USB DEVICE devices in real time. Summary of the invention

[0004] In view of this, the present invention provides a device bandwidth simulation test method, apparatus, device and storage medium to solve the problem of low efficiency and poor accuracy in determining whether the bandwidth value of the main device can reach the maximum bandwidth and the reason for not reaching the maximum bandwidth.

[0005] In a first aspect, the present invention provides a simulation test method for device bandwidth, which is applied to a simulation test device, wherein the simulation test device is connected to a master device and a slave device respectively; the master device is connected to a first double data rate (DDR) memory, and the slave device is connected to a second memory; the method comprises: after the master device and the slave device establish a communication connection, configuring a preset transmission bandwidth for the master device, and starting a simulation test, in which the master device transmits first data stored in a first memory to the slave device according to the preset transmission bandwidth, and the slave device receives the data transmitted by the master device and stores it in a second memory; at the end of the simulation test, obtaining at least one transmission parameter value of the master device, and obtaining second data received by the slave device stored in the second memory, wherein at least one transmission parameter value is a parameter value of at least one component associated with the master device; determining whether the first data is consistent with the second data; if not, testing that the actual transmission bandwidth of the master device is less than the preset transmission bandwidth, and determining the reason why the actual transmission bandwidth is less than the preset transmission bandwidth based on at least one transmission parameter value.

[0006] Based on the method of the first aspect above, under the premise of configuring a preset transmission bandwidth for the master device, the above simulation test is to send the first data to the slave device through the master device, compare the first data before the master device sends and the second data received by the slave device, if the second data is inconsistent with the first data, it indicates that abnormal conditions such as packet loss or error occur in the transmission process, and further indicates that the actual transmission bandwidth of the master device during the first data transmission process does not reach the preset transmission bandwidth value. In addition, since at least one transmission parameter value of the master device is obtained, and at least one output parameter value is the parameter value of at least one component associated with the master device, it is possible to determine which component of the components associated with the master device causes the actual transmission bandwidth of the master device to not reach the preset transmission bandwidth based on at least one transmission parameter value, and then determine the reason why the actual transmission bandwidth is less than the preset transmission bandwidth, thereby improving the efficiency of troubleshooting.

[0007] Through simulation testing, the actual transmission bandwidth of the master device can be tested in advance, and it can be accurately determined whether the actual transmission bandwidth of the master device is less than the preset transmission bandwidth, and the reason why the actual transmission bandwidth is less than the preset transmission bandwidth, thereby improving efficiency and avoiding data transmission delays, data loss or errors, consumption of additional system resources, poor system stability and other problems caused by real-time communication between the master device and the slave device.

[0008] In an optional embodiment, before the master device and the slave device establish a communication connection, the method also includes: after the master device is powered on, configuring the initialization parameters of the master device; controlling the master device and the slave device to perform an enumeration process to obtain the slave device information of the slave device, the device information including the transmission data type and the transmission data length; configuring the slave device information for the master device to establish a communication connection between the master device and the slave device.

[0009] Based on the above method, the communication connection between the master device and the slave device can be established by configuring the initialization parameters of the master device and controlling the master device and the slave device to complete the enumeration process, so as to prepare for the subsequent simulation test.

[0010] In an optional embodiment, the master device is a device included in a first integrated circuit, and the first integrated circuit also includes a first central processing unit (CPU); at the end of the simulation test, at least one transmission parameter value of the master device is obtained, including: obtaining the number of transmission instructions issued by the first central processing unit within a preset time period, the transmission instruction is used to instruct the master device to transmit the first data to the slave device according to the preset transmission bandwidth; obtaining the single transmission amount of data read from the first memory and transmitted to the slave device at a time after the master device receives the transmission instruction once; obtaining the read-write signal record corresponding to the memory of the master device, the read-write signal record is a record generated when the master device transmits the first data, reads the data included in the first data from the first memory and writes it into the memory, and then transmits it from the memory to the slave device.

[0011] Based on the above method, after the simulation test is completed, the transmission parameter values ​​of multiple components associated with the main device during the simulation process can be obtained, so as to facilitate the subsequent determination of the reason why the actual transmission bandwidth of the main device is less than the preset transmission bandwidth based on at least one transmission parameter value.

[0012] In an optional implementation, the main device is connected to the first central processor via an internal interconnection bus; based on at least one transmission parameter value, determining the reason why the actual transmission bandwidth is less than the preset transmission bandwidth includes: judging whether the number of transmission times is less than the preset number of transmission times, the preset number of transmission times being the minimum number of transmission instructions that need to be sent by the first central processor within a preset time period under the preset transmission bandwidth.

[0013] If the number of sends is less than the preset number of sends, the reason is determined to be that the operating frequency of the first central processing unit is insufficient; if the number of sends is greater than or equal to the preset number of sends, it is determined whether the single output amount is less than the preset single transmission amount. The preset single transmission amount is the minimum transmission amount of data read from the first memory and transmitted to the slave device at a single time under the preset transmission bandwidth.

[0014] If the single transmission amount is less than the preset single transmission amount, it is determined that the cause is insufficient operating clock frequency of the first memory; if the number of sends is greater than or equal to the preset number of sends, and the single transmission amount is greater than or equal to the preset single transmission amount, then it is determined whether the bus width of the internal interconnection bus reaches the maximum bus width, and whether the bus operating frequency of the internal interconnection bus reaches the maximum bus operating frequency; if both are reached, then it is determined whether the read and write signal records include a full flag or a read empty flag; if so, it is determined that the cause is insufficient memory of the master device.

[0015] Based on the above method, the reason why the actual transmission bandwidth of the master device is less than the preset transmission bandwidth can be determined based on at least one transmission parameter value, thereby improving the efficiency of troubleshooting.

[0016] In an optional implementation, if the first data is consistent with the second data, the actual transmission bandwidth of the master device obtained through testing satisfies the preset transmission bandwidth.

[0017] Based on the above method, when the first data is consistent with the second data, it means that during the data transmission process of the master device, the first data is completely transmitted to the slave device, which further indicates that the actual transmission bandwidth of the master device is consistent with the preset transmission bandwidth, that is, the actual transmission bandwidth of the master device meets the preset transmission bandwidth.

[0018] In an optional implementation, the master device and the slave device are controlled to perform an enumeration process to obtain the slave device information of the slave device, including: controlling the master device to send a reset signal to the slave device to put the slave device into a default state; controlling the master device to send a standard request to obtain a device descriptor of the slave device, the device descriptor represents the slave device information, and the slave device information includes the slave device's manufacturer identification, device identification, device type, transmission data type and transmission data length.

[0019] Based on the above method, the slave device information of the slave device can be obtained by controlling the master device and the slave device to perform the enumeration process, so as to facilitate the subsequent establishment of a communication connection between the master device and the slave device.

[0020] In an optional implementation, a second simulation test is started. In the second simulation test, the slave device transmits the third data stored in the second memory to the master device. The master device receives the data transmitted by the slave device according to the preset transmission bandwidth and stores the data in the first memory. At the end of the second simulation test, the fourth data sent by the slave device and received and stored in the first memory is obtained. It is determined whether the third data is consistent with the fourth data. If not, the test shows that the actual transmission bandwidth of the master device is less than the preset transmission bandwidth.

[0021] Based on the above method, in the above second simulation test, the master device receives the third data sent by the slave device, and compares the fourth data received by the master device with the third data sent by the slave device. If the fourth data is inconsistent with the third data, it indicates that abnormal conditions such as packet loss or errors occur during the transmission process, which further indicates that the actual transmission bandwidth of the master device during the first data transmission process does not reach the preset transmission bandwidth value. Similarly, if the fourth data is consistent with the third data, it indicates that the third data is completely received during the data reception process of the master device, which further indicates that the actual transmission bandwidth of the master device is consistent with the preset transmission bandwidth, that is, the actual transmission bandwidth of the master device meets the preset transmission bandwidth.

[0022] In a second aspect, the present invention provides a device bandwidth simulation test apparatus, the device bandwidth simulation test apparatus is connected to a master device and a slave device respectively; the master device is connected to a first double data rate memory, and the slave device is connected to a second memory.

[0023] A processing module is used to configure a preset transmission bandwidth for the master device and start a simulation test after the master device and the slave device establish a communication connection. In the simulation test, the master device transmits the first data stored in the first memory to the slave device according to the preset transmission bandwidth, and the slave device receives the data transmitted by the master device and stores it in the second memory; a transceiver module is used to obtain at least one transmission parameter value of the master device at the end of the simulation test, and obtain the second data received by the slave device stored in the second memory, at least one transmission parameter value is a parameter value of at least one component associated with the master device; the processing module is also used to determine whether the first data is consistent with the second data; the processing module is also used to test and obtain the actual transmission bandwidth of the master device is less than the preset transmission bandwidth if they are inconsistent, and determine the reason why the actual transmission bandwidth is less than the preset transmission bandwidth based on at least one transmission parameter value.

[0024] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the device bandwidth simulation test method of the first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0025] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the device bandwidth simulation test method of the first aspect or any corresponding embodiment thereof.

[0026] In a fifth aspect, the present invention provides a computer program product, including computer instructions, where the computer instructions are used to enable a computer to execute the device bandwidth simulation test method of the first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0028] Figure 1 is a topology diagram of a simulation test system for device bandwidth according to an embodiment of the present invention;

[0029] Figure 2is a diagram of the internal structure of a first integrated circuit according to an embodiment of the present invention;

[0030] Figure 3 A schematic diagram of a flow chart of a method for simulating and testing device bandwidth according to an embodiment of the present invention;

[0031] Figure 4 is a structural block diagram of a simulation test device for device bandwidth according to an embodiment of the present invention;

[0032] Figure 5 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0034] The embodiment of the present invention provides a device bandwidth simulation test method, which is applied to integrated circuits integrated with USB devices. As described in the background technology, the method of manually judging whether the bandwidth value designed by the USB HOST device can reach the maximum bandwidth and manually determining the reason for not reaching the maximum bandwidth is inefficient and has poor accuracy; and it will cause data transmission delay, data loss or error, consumption of additional system resources, poor system stability and other problems.

[0035] In order to solve the above technical problems, an embodiment of the present invention provides a simulation test method for device bandwidth. Through simulation testing, the actual transmission bandwidth of the main device is tested in advance to improve the accuracy and efficiency of determining whether the actual transmission bandwidth of the main device is less than the preset transmission bandwidth, and the reason why the actual transmission bandwidth is less than the preset transmission bandwidth.

[0036] Below Figure 1 Taking the device bandwidth simulation test system 10 as an example, the method provided by the embodiment of the present invention is described. Figure 1 It is only a schematic diagram and does not constitute a limitation on the applicable scenarios of the technical solution provided in this application.

[0037] like Figure 1 As shown, Figure 1 4 is a topology diagram of a simulation test system for device bandwidth according to an embodiment of the present invention. Figure 1In the embodiment, the device bandwidth simulation test system 10 may include a device bandwidth simulation test apparatus 101, a master device 102, a slave device 103, a first DDR memory 104, and a second DDR memory 105. Optionally, the device bandwidth simulation test system 10 may also include a first CPU 106, a second CPU 107, a first DDR controller 108, and a second DDR controller 109.

[0038] In the embodiment of the present invention, the device bandwidth simulation test device 101 (referred to as the simulation test device) can be any device with computing and communication functions. For example, the simulation test device can be a server, a cloud server, and the like.

[0039] In the embodiment of the present invention, the host device 102, also referred to as a USB HOST device, can be any device having a computing function and capable of performing data transmission via a USB protocol. For example, the USB HOST device can be a personal computer, a smart phone, a tablet computer, and an embedded system. The USB HOST device is responsible for managing the connection, enumeration, data transmission, and power management with the slave device.

[0040] Specifically, the host device 102 also includes a USB controller and a USB physical layer (USB Physical Layer, USBPHY) interface. The USB controller includes a random access memory (Random Access Memory, RAM) memory and registers. The USB controller is also called a USB 3.0 & 2.0 controller, which means that the USB controller can transmit data through the USB 3.0PHY interface and can also transmit data through the USB 2.0PHY interface.

[0041] In the embodiment of the present invention, the slave device 103, also called a USB DEVICE device, may refer to a peripheral device connected to and controlled by a USB HOST device in a USB system. For example, a USB DEVICE device is usually various types of external hardware, such as a keyboard, a mouse, a printer, a storage device, a camera, etc. These devices communicate with the USB HOST device through a USB interface and are managed and controlled by the host.

[0042] In the embodiment of the present invention, the first DDR memory 104 (ie, the first memory) or the second DDR memory (ie, the second memory) 105 can be any type of DDR memory.

[0043] In the embodiment of the present invention, the first CPU 106 or the second CPU 107 may be any central processing unit.

[0044] In the embodiment of the present invention, the first DDR controller 108 or the second DDR controller 109 may be used to control the reading and writing of data in the first DDR memory or the second DDR memory.

[0045] The first CPU 106 and the host device 102 are integrated on a first integrated circuit; the first integrated circuit also integrates a first DDR controller. Figure 2 As shown, Figure 2 is a diagram of the internal structure of a first integrated circuit according to an embodiment of the present invention. Figure 2 In the embodiment, the first CPU is connected to the USB controller and the first DDR controller through an internal interconnect bus. The first DDR controller is connected to the first DDR memory. The USB controller is connected to the USB 3.0 PHY interface and the USB 2.0 PHY interface. The USB 3.0 PHY interface and the USB 2.0 PHY interface are connected to other slave devices through USB cables.

[0046] The first CPU 106 implements the control function of the USB 3.0 & 2.0 controller and the first DDR controller through the internal interconnection bus.

[0047] The internal interconnection bus realizes the control data transmission of the first CPU to each module inside the first integrated circuit, and the data transmission between each internal functional module.

[0048] USB 3.0PHY connects to USB 3.0&2.0 controller through PIPE interface to realize data transmission of USB 3.0 protocol.

[0049] USB 2.0PHY connects to USB 3.0&2.0 controller through UTMI interface to realize data transmission of USB 2.0 protocol;

[0050] The first CPU reads and writes internal registers of the USB 3.0 PHY and the USB 2.0 PHY through the control bus, and controls the working state of the USB PHY.

[0051] The first DDR controller implements timing control of the first DDR memory, and realizes the data access function of transferring data in the first integrated circuit to the DDR particles.

[0052] It is understandable that the second CPU 107 and the slave device 103 are integrated on the second integrated circuit. The second integrated circuit is also integrated with a second DDR controller. The second integrated circuit is similar to the first integrated circuit and is not described in detail here. The connection between the host device 102 and the slave device is achieved by connecting the USB 2.0 PHY of the USB HOST to the USB 2.0 PHY of the USB DEVICE; or, connecting the USB 3.0 PHY of the USB HOST to the USB 3.0 PHY of the USB DEVICE.

[0053] It can be understood that when the master device 102 and the slave device 103 communicate and transmit, there are usually four data transmission scenarios, including: control transmission, interrupt transmission, batch transmission, and synchronous transmission.

[0054] Figure 1 The device bandwidth simulation test system 10 shown is only used as an example and is not used to limit the technical solution of the present application. Those skilled in the art should understand that in the specific implementation process, the device bandwidth simulation test system 10 can also include other devices, and the number of slave devices and masters can also be determined according to specific needs without limitation.

[0055] According to an embodiment of the present invention, an embodiment of a simulation test method for device bandwidth is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0056] In this embodiment, a device bandwidth simulation test method is provided, which can be used in the above-mentioned simulation test device. Figure 3 is a flow chart of a simulation test method for device bandwidth according to an embodiment of the present invention. Figure 3 As shown, the process includes the following steps:

[0057] S301: After the master device establishes a communication connection with the slave device, a preset transmission bandwidth is configured for the master device, and a simulation test is started.

[0058] In the simulation test, the master device transmits the first data stored in the first DDR memory to the slave device according to the preset transmission bandwidth, and the slave device receives the data transmitted by the master device and stores it in the second DDR memory. It can be understood that the simulation test simulates the process of batch transmission between the master device and the slave device.

[0059] Specifically: in the simulation test, the USB HOST device reads the first data stored in the first DDR memory, and groups the first data into multiple data packets according to the USB protocol, and transmits the multiple data packets to the USB DEVICE device through the USB PHY interface according to the preset transmission bandwidth.

[0060] In the embodiment of the present invention, the preset transmission bandwidth is related to the USB protocol used by the master device when transmitting data. The USB protocol used by the master device when transmitting data is related to the connected slave device. If the connected slave device is a device that needs to transmit data through the USB 3.0 protocol, the preset transmission bandwidth is the highest transmission bandwidth corresponding to the USB 3.0 protocol. If the connected slave device is a device that needs to transmit data through the USB 2.0 protocol, the preset transmission bandwidth is the highest transmission bandwidth corresponding to the USB 2.0 protocol.

[0061] The maximum transmission bandwidth of bulk transfer in USB 2.0 protocol: In the simulation test, the maximum packet byte number of bulk transfer is 512 bytes, and each microframe (125us) can perform 13 transmissions. The calculated maximum transmission bandwidth of bulk transfer in USB 2.0 protocol is: 13*512 / 125us=53.248MB / s.

[0062] The maximum transmission bandwidth of bulk transfer in the USB 3.0 protocol: In the simulation test, the maximum packet byte number of bulk transfer is 1024 bytes, each microframe (125us) can be transmitted 3 times, the number of bursts is 16, and the calculated maximum transmission bandwidth of bulk transfer in the USB 3.0 protocol is: 3*16*1024 / 125us=393.216MB / s.

[0063] Exemplarily, after the master device establishes a communication connection with the slave device, the simulation test apparatus configures a preset transmission bandwidth for the registers in the master device including a USB controller, and starts a batch OUT transmission simulation test.

[0064] In some optional embodiments, before the master device and the slave device establish a communication connection, the simulation test device can also configure the initialization parameters of the master device after the master device is powered on; control the master device and the slave device to perform an enumeration process to obtain the slave device information of the slave device; configure the slave device information for the master device to establish a communication connection between the master device and the slave device.

[0065] The device information includes the transmission data type and the transmission data length. The transmission data type includes the data type transmitted based on the USB 3.0 protocol or the data type transmitted based on the USB 2.0 protocol. The transmission data length is used to indicate the transmission bandwidth configured by the slave device, which is usually consistent with the preset transmission bandwidth of the master device.

[0066] In some optional implementations, the master device is controlled to send a reset signal to the slave device to put the slave device into a default state; the master device is controlled to send a standard request to obtain a device descriptor of the slave device, the device descriptor represents the slave device information, and the slave device information includes the slave device's manufacturer identification, device identification, device type, the transmission data type and the transmission data length.

[0067] Exemplarily, after the host device is powered on, the simulation test apparatus sets the port status and control register, command ring control register, configuration register, device content base address pointer, USB command register, and interrupt management register of the USB HOST device through the first CPU to configure the initialization parameters in the USB HOST device register.

[0068] The simulation test device controls the USB HOST device to send a reset signal to the slave device, so that the slave device enters the default state; sends a standard request to obtain the device descriptor of the slave device, and performs insertion detection, power supply, device identification, address setting, etc. on the USB DEVICE device, performs an enumeration process on the USB DEVICE, and obtains the slave device information of the slave device.

[0069] The simulation test device configures the USB DEVICE endpoint content in the register of the USB HOST device through the first CPU, and sets the slave device information of the slave device. After that, the simulation test device controls the USB HOST device to send a token packet to the USB DEVICE device, and the USB DEVICE device returns an ACK handshake packet to the USB HOST device after receiving the token packet. At this point, the communication connection between the master device and the slave device is established.

[0070] The simulation test device sets the doorbell register corresponding to the USB DEVICE endpoint through the first CPU, and sends a signal to inform the USB controller that the first data to be sent is ready, and the first data can be sent to the USB DEVICE device to start the simulation test.

[0071] Optionally, after the slave device is powered on, the simulation test apparatus configures the data transmission speed level, the number of endpoints, the endpoint type, and the event buffer address information in the USB DEVICE register through the first CPU.

[0072] S302: When the simulation test ends, obtain at least one transmission parameter value of the master device, and obtain second data received from the slave device and stored in the second memory.

[0073] Among them, at least one transmission parameter value is a parameter value of at least one component associated with the master device. For example, at least one transmission parameter can be the number of transmission instructions issued by the simulation test device through the first CPU within a preset time period, the single transmission amount of data read from the first DDR memory and transmitted to the slave device by the simulation test device at a single time, or the read and write signal record corresponding to the memory of the master device.

[0074] In some optional embodiments, the simulation test device obtains the number of transmission instructions issued by the first CPU within a preset time period, the transmission instructions are used to instruct the master device to transmit the first data to the slave device according to the preset transmission bandwidth; obtains the single transmission amount of data read from the first DDR memory and transmitted to the slave device after the master device receives the transmission instruction once; obtains the read and write signal records corresponding to the memory of the master device, the read and write signal records are records generated when the master device transmits the first data, reads the data included in the first data from the first DDR memory and writes it into the memory, and then transmits it from the memory to the slave device.

[0075] S303: Determine whether the first data is consistent with the second data.

[0076] In one example, if the data volume of the first data is consistent with the data volume of the second data, and each data value in the first data is the same as each corresponding data value in the second data, the simulation test device determines that the first data is consistent with the second data. If the data volume of the first data is less than the data volume of the second data, or there is data with different data values ​​in the first data and the second data, the simulation test device determines that the first data is inconsistent with the second data.

[0077] S304: If they are inconsistent, the actual transmission bandwidth of the master device is tested to be smaller than the preset transmission bandwidth, and the reason why the actual transmission bandwidth is smaller than the preset transmission bandwidth is determined based on at least one transmission parameter value.

[0078] In some optional embodiments, the simulation test device determines whether the number of transmissions is less than the preset number of transmissions; if the number of transmissions is less than the preset number of transmissions, it is determined that the cause is insufficient CPU operating frequency of the first CPU; if the number of transmissions is greater than or equal to the preset number of transmissions, it is determined whether the single output amount is less than the preset single transmission amount; if the single transmission amount is less than the preset single transmission amount, it is determined that the cause is insufficient operating clock frequency of the first DDR memory; if the number of transmissions is greater than or equal to the preset number of transmissions, and the single transmission amount is greater than or equal to the preset single transmission amount, it is determined whether the bus width of the internal interconnection bus reaches the maximum bus width, and whether the bus operating frequency of the internal interconnection bus reaches the maximum bus operating frequency; if both are reached, it is determined whether the read and write signal records include a full flag or a read empty flag; if so, it is determined that the cause is insufficient memory of the master device.

[0079] The preset number of times of sending is the minimum number of times that the transmission instruction needs to be sent by the first CPU within a preset time period under the preset transmission bandwidth. For example, if the preset transmission bandwidth is the highest transmission bandwidth corresponding to the USB 3.0 protocol, the preset number of times of sending can be 3 times; if the preset transmission bandwidth is the highest transmission bandwidth corresponding to the USB 2.0 protocol, the preset number of times of sending can be 13 times. It can be understood that the preset number of times of sending can also be set according to actual needs. For example, the preset number of times of sending is set to a value greater than the minimum number of times of sending transmission instructions without restriction.

[0080] It is understandable that the preset time period may be any time period without limitation. For example, the preset time period may be each microframe time period (125 us).

[0081] In the embodiment of the present invention, the preset single transmission amount is the minimum transmission amount of data read from the first DDR memory and transmitted to the slave device at a single time under the preset transmission bandwidth. For example, if the preset transmission bandwidth is the highest transmission bandwidth corresponding to the USB 3.0 protocol, the preset single transmission amount is 1024 bytes; if the preset transmission bandwidth is the highest transmission bandwidth corresponding to the USB 2.0 protocol, the preset single transmission amount is 512 bytes. It can be understood that the preset single transmission amount can also be set according to actual needs. For example, the preset single transmission amount is set to a value larger than the minimum transmission amount without restriction.

[0082] In one example, if the simulation test device determines that the bus width of the internal interconnection bus does not reach the maximum bus width, or the bus operating frequency of the internal interconnection bus does not reach the maximum bus operating frequency, the bus width of the internal interconnection bus can be increased, or the bus operating frequency of the internal interconnection bus can be increased. After that, the simulation test device starts the simulation test again to obtain the test result; if the test result indicates that the first data and the second data are still inconsistent, it continues to determine whether the read / write signal record includes a full mark or a read empty mark; if so, it is determined that the cause is insufficient memory of the master device.

[0083] In some optional implementations, if the first data is consistent with the second data, the simulation test device tests that the actual transmission bandwidth of the master device meets the preset transmission bandwidth.

[0084] Furthermore, the simulation test device can start a second simulation test. In the second simulation test, the slave device transmits the third data stored in the second DDR memory to the master device. The master device receives the data transmitted by the slave device according to the preset transmission bandwidth and stores it in the first DDR memory. At the end of the second simulation test, the fourth data sent by the slave device and received and stored in the first DDR memory is obtained. It is determined whether the third data is consistent with the fourth data. If they are inconsistent, the test shows that the actual transmission bandwidth of the master device is less than the preset transmission bandwidth.

[0085] It can be understood that the second simulation test is to simulate the process of synchronous transmission between the master device and the slave device.

[0086] Therefore, based on the second simulation test, it is equivalent to simulating the batch transmission test and synchronous transmission test between the master device and the slave device. The priority of batch transmission and the maximum communication bandwidth that can be achieved by synchronous transmission are higher than those of other transmissions. That is, the maximum communication bandwidth of batch transmission can be achieved, which means that when other communication transmission scenarios are carried out between the master device and the slave device, the maximum communication bandwidth requirements can also be met.

[0087] Based on the above-mentioned method S301-S304, the simulation test device configures a preset transmission bandwidth for the master device, and the above-mentioned simulation test is performed by sending the first data from the master device to the slave device, comparing the first data before the master device sends the data and the second data received by the slave device. If the second data is inconsistent with the first data, it indicates that an abnormal situation such as packet loss or error occurs in the transmission process, and further indicates that the actual transmission bandwidth of the master device during the first data transmission process does not reach the preset transmission bandwidth value. In addition, since at least one transmission parameter value of the master device is obtained, and at least one output parameter value is a parameter value of at least one component associated with the master device, it is possible to determine which component of the components associated with the master device causes the actual transmission bandwidth of the master device to not reach the preset transmission bandwidth based on at least one transmission parameter value, and then determine the reason why the actual transmission bandwidth is less than the preset transmission bandwidth, thereby improving the efficiency of troubleshooting.

[0088] Through simulation testing, the actual transmission bandwidth of the master device can be tested in advance, and it can be accurately determined whether the actual transmission bandwidth of the master device is less than the preset transmission bandwidth, and the reason why the actual transmission bandwidth is less than the preset transmission bandwidth, thereby improving efficiency and avoiding data transmission delays, data loss or errors, consumption of additional system resources, poor system stability and other problems caused by real-time communication between the master device and the slave device.

[0089] In this embodiment, a simulation test device for device bandwidth is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0090] This embodiment provides a device bandwidth simulation test device, such as Figure 4 As shown, Figure 41 is a structural block diagram of a device bandwidth simulation test device according to an embodiment of the present invention; the device bandwidth simulation test device is connected to a master device and a slave device respectively; the master device is connected to a first memory, and the slave device is connected to a second memory; and includes:

[0091] The processing module 401 is used to configure a preset transmission bandwidth for the master device and start a simulation test after the master device and the slave device establish a communication connection. In the simulation test, the master device transmits the first data stored in the first memory to the slave device according to the preset transmission bandwidth, and the slave device receives the data transmitted by the master device and stores it in the second memory.

[0092] The transceiver module 402 is used to obtain at least one transmission parameter value of the master device and the second data received from the slave device stored in the second memory when the simulation test ends. The at least one transmission parameter value is a parameter value of at least one component associated with the master device.

[0093] The processing module 401 is further used to determine whether the first data is consistent with the second data.

[0094] The processing module 401 is further configured to, if inconsistent, test to obtain that the actual transmission bandwidth of the master device is less than the preset transmission bandwidth, and determine the reason why the actual transmission bandwidth is less than the preset transmission bandwidth based on at least one transmission parameter value.

[0095] In some optional embodiments, before the master device and the slave device establish a communication connection, the processing module 401 is also used to configure the initialization parameters of the master device after the master device is powered on; the processing module 401 is also used to control the enumeration process of the master device and the slave device to obtain the slave device information of the slave device, and the device information includes the transmission data type and the transmission data length; the processing module 401 is also used to configure the slave device information for the master device and establish a communication connection between the master device and the slave device.

[0096] In some optional embodiments, the master device is a device included in the first integrated circuit, and the first integrated circuit also includes a first central processing unit; the transceiver module 402 is specifically used to obtain the number of transmission instructions issued by the first central processing unit within a preset time period, and the transmission instruction is used to instruct the master device to transmit the first data to the slave device according to the preset transmission bandwidth; the transceiver module 402 is also specifically used to obtain the single transmission amount of data read from the first memory and transmitted to the slave device at a time after the master device receives the transmission instruction once; the transceiver module 402 is also specifically used to obtain the read-write signal record corresponding to the memory of the master device, and the read-write signal record is a record generated when the master device transmits the first data, reads the data included in the first data from the first memory and writes it into the memory, and then transmits it from the memory to the slave device.

[0097] In some optional implementations, the main device and the first central processor are connected via an internal interconnection bus; the processing module 401 is further specifically used to determine whether the number of transmission times is less than a preset number of transmission times, where the preset number of transmission times is the minimum number of transmission instructions that need to be transmitted by the first central processor within a preset time period under a preset transmission bandwidth; if the number of transmission times is less than the preset number of transmission times, it is determined that the cause is that the operating frequency of the first central processor is insufficient; if the number of transmission times is greater than or equal to the preset number of transmission times, it is determined whether the single output amount is less than the preset single transmission amount, where the preset single transmission amount is the number of transmission instructions that can be transmitted under the preset transmission bandwidth. The minimum transmission amount of data read from the first memory and transmitted to the slave device at a single time under the preset width; if the single transmission amount is less than the preset single transmission amount, it is determined that the cause is that the operating clock frequency of the first memory is insufficient; if the number of times sent is greater than or equal to the preset number of times sent, and the single transmission amount is greater than or equal to the preset single transmission amount, then it is determined whether the bus width of the internal interconnection bus reaches the maximum bus width, and whether the bus operating frequency of the internal interconnection bus reaches the maximum bus operating frequency; if both are reached, then it is determined whether the read and write signal records include a full mark or a read empty mark; if so, it is determined that the cause is insufficient memory of the master device.

[0098] In some optional implementations, the processing module 401 is further configured to test and determine whether the actual transmission bandwidth of the master device satisfies the preset transmission bandwidth if the first data is consistent with the second data.

[0099] In some optional implementations, the processing module 401 is further specifically used to control the master device to send a reset signal to the slave device so that the slave device enters a default state; the processing module 401 is further specifically used to control the master device to send a standard request to obtain a device descriptor of the slave device, the device descriptor represents the slave device information, and the slave device information includes the slave device's manufacturer identification, device identification, device type, transmission data type and transmission data length.

[0100] In some optional embodiments, the processing module 401 is also used to start a second simulation test. In the second simulation test, the slave device transmits the third data stored in the second memory to the master device. The master device receives the data transmitted by the slave device according to the preset transmission bandwidth and stores it in the first memory; the transceiver module 402 is also used to obtain the fourth data sent by the slave device and received and stored in the first memory at the end of the second simulation test; the processing module 401 is also used to determine whether the third data is consistent with the fourth data; the processing module 401 is also used to test that if they are inconsistent, the actual transmission bandwidth of the master device is less than the preset transmission bandwidth.

[0101] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0102] The device bandwidth simulation test apparatus in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0103] The embodiment of the present invention also provides a computer device having the above Figure 4 Simulation test setup of the device bandwidth shown.

[0104] See also Figure 5 , Figure 5 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Figure 5 As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 5 A processor 10 is taken as an example.

[0105] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0106] The memory 20 stores instructions executable by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0107] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0108] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0109] The computer device further comprises a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0110] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0111] Part of the present application may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present application through the operation of the computer. Those skilled in the art should understand that the existence of computer program instructions in computer-readable media includes but is not limited to source files, executable files, installation package files, etc., and accordingly, the way in which computer program instructions are executed by a computer includes but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to the computer.

[0112] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A device bandwidth simulation test method, characterized in that: Applied to a simulation test device, the simulation test device is connected to a master device and a slave device respectively; The master device is connected to a first memory, and the slave device is connected to a second memory; the method comprises: After the master device establishes a communication connection with the slave device, a preset transmission bandwidth is configured for the master device, and a simulation test is started. In the simulation test, the master device transmits the first data stored in the first memory to the slave device according to the preset transmission bandwidth, and the slave device receives the data transmitted by the master device and stores it in the second memory; At the end of the simulation test, obtaining at least one transmission parameter value of the master device and obtaining second data received by the slave device and stored in the second memory, wherein the at least one transmission parameter value is a parameter value of at least one component associated with the master device; Determining whether the first data is consistent with the second data; If they are inconsistent, the test shows that the actual transmission bandwidth of the master device is smaller than the preset transmission bandwidth, and based on the at least one transmission parameter value, the reason why the actual transmission bandwidth is smaller than the preset transmission bandwidth is determined.

2. The method according to claim 1, characterized in that Before the master device establishes a communication connection with the slave device, the method further includes: After the master device is powered on, configuring initialization parameters of the master device; Controlling the master device and the slave device to perform an enumeration process to obtain slave device information of the slave device, wherein the device information includes a transmission data type and a transmission data length; The slave device information is configured for the master device, and the communication connection between the master device and the slave device is established.

3. The method according to claim 1, characterized in that The master device is a device included in a first integrated circuit, and the first integrated circuit also includes a first central processor; when the simulation test ends, obtaining at least one transmission parameter value of the master device includes: Acquire the number of transmission instructions issued by the first central processor within a preset time period, wherein the transmission instruction is used to instruct the master device to transmit the first data to the slave device according to the preset transmission bandwidth; Acquire a single transmission amount of data read from the first memory and transmitted to the slave device once after the master device receives the transmission instruction once; Obtain a read / write signal record corresponding to the memory of the master device, wherein the read / write signal record is a record generated when the master device transmits the first data, reads data included in the first data from the first memory and writes it into the memory, and then transmits it from the memory to the slave device.

4. The method according to claim 3, characterized in that The master device is connected to the first central processor via an internal interconnect bus; and the determining, based on the at least one transmission parameter value, a reason why the actual transmission bandwidth is less than the preset transmission bandwidth includes: Determine whether the sending number is less than a preset sending number, where the preset sending number is the minimum number of times the transmission instruction needs to be sent by the first central processor within the preset time period under the preset transmission bandwidth; If the number of times of sending is less than the preset number of times of sending, it is determined that the reason is that the operating frequency of the first central processing unit is insufficient; If the number of times of sending is greater than or equal to the preset number of times of sending, determining whether the single output amount is less than a preset single transmission amount, the preset single transmission amount being the minimum transmission amount of data read from the first memory and transmitted to the slave device at a single time under the preset transmission bandwidth; If the single transmission amount is less than the preset single transmission amount, determining that the cause is that the operating clock frequency of the first memory is insufficient; If the number of transmissions is greater than or equal to the preset number of transmissions, and the single transmission amount is greater than or equal to the preset single transmission amount, then determining whether the bus width of the internal interconnection bus reaches the maximum bus width, and whether the bus operating frequency of the internal interconnection bus reaches the maximum bus operating frequency; If both are reached, determining whether the read / write signal record includes a full mark or a read empty mark; If so, it is determined that the cause is insufficient memory of the master device.

5. The method according to claim 4, characterized in that The method further comprises: If the first data is consistent with the second data, the actual transmission bandwidth of the master device obtained through testing satisfies the preset transmission bandwidth.

6. The method according to claim 2, characterized in that The controlling the master device and the slave device to perform an enumeration process to obtain slave device information of the slave device includes: Controlling the master device to send a reset signal to the slave device so that the slave device enters a default state; The master device is controlled to send a standard request to obtain a device descriptor of the slave device, wherein the device descriptor represents the slave device information, and the slave device information includes the manufacturer identification, device identification, device type, transmission data type and transmission data length of the slave device.

7. The method according to claim 6, characterized in that The method further comprises: Initiate a second simulation test, in which the slave device transmits the third data stored in the second memory to the master device, and the master device receives the data transmitted by the slave device according to the preset transmission bandwidth and stores the data in the first memory; At the end of the second simulation test, obtaining the fourth data sent by the slave device and received and stored in the first memory; determining whether the third data is consistent with the fourth data; If they are inconsistent, the test shows that the actual transmission bandwidth of the master device is smaller than the preset transmission bandwidth.

8. A device bandwidth simulation test apparatus, characterized in that: The device bandwidth simulation test device is connected to the master device and the slave device respectively; The master device is connected to a first double data rate memory, and the slave device is connected to a second memory; the apparatus comprises: a processing module, configured to configure a preset transmission bandwidth for the master device and start a simulation test after the master device establishes a communication connection with the slave device, in which the master device transmits the first data stored in the first memory to the slave device according to the preset transmission bandwidth, and the slave device receives the data transmitted by the master device and stores it in the second memory; a transceiver module, configured to obtain, at the end of the simulation test, at least one transmission parameter value of the master device and obtain second data received by the slave device and stored in the second memory, wherein the at least one transmission parameter value is a parameter value of at least one component associated with the master device; The processing module is further used to determine whether the first data is consistent with the second data; The processing module is further configured to, if inconsistent, test to obtain that the actual transmission bandwidth of the master device is smaller than the preset transmission bandwidth, and determine the reason why the actual transmission bandwidth is smaller than the preset transmission bandwidth based on the at least one transmission parameter value.

9. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the device bandwidth simulation test method according to any one of claims 1 to 7 by executing the computer instructions.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the device bandwidth simulation test method according to any one of claims 1 to 7.

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