PCIE Preset code pattern switching trigger based on 555 timer

Abstract

The invention provides a PCIE Preset code pattern switching trigger based on a 555 timer, the PCIE Preset code pattern switching trigger comprises a logic control module, a timing module, an electronic switch module and a clock module which are connected, and the logic control module is configured to be in a key triggering mode; in response to a key trigger mode, the logic control module outputs a low-level signal to the timing module, the timing module outputs a high-level signal to the electronic switch module after receiving the low-level signal, the electronic switch module is switched on, a clock signal is output to external equipment through the clock module, and the electronic switch module is switched off after a preset duration. The trigger is composed of the crystal oscillator, the logic gate, the 555 timer, the electronic switch and other core components, a large chip is not needed, power consumption and cost are low, the trigger is extremely high in flexibility, if a nixie tube display function and a key long-pressing function are not needed, after related circuits are deleted, only one crystal oscillator and four chips are needed to complete basic functions, and the trigger is convenient to use. And the occupied space is extremely small.

Description

Technical Field

[0001] The present application belongs to the field of hardware circuit technology, and in particular, relates to a PCIE Preset code switching trigger based on a 555 timer. Background Art

[0002] In the transmitter signal quality test of the standard PCIE protocol, the PCIE device TX channel will output different types of code patterns, and an oscilloscope is used to check whether each type meets the protocol specifications. Every time the RX channel receives a 1ms 100MHz clock signal, the TX channel will switch to the next code pattern. The total number of PCIE code patterns in each generation is different. For example, PCIE 3.0 has 14 types. After switching to the last code pattern, the next switch will start from the first one.

[0003] Most existing products use controllers such as microcontrollers or CPLD to operate clock output, which is costly, requires programming and development, and is complex to operate. Summary of the invention

[0004] In view of this, the present application aims to propose a PCIE Preset pattern switching trigger based on a 555 timer to solve the problem that using a controller to operate the clock output is costly, requires programming development, and has complex operations.

[0005] To achieve the above purpose, the technical solution of this application is implemented as follows: The present application provides a PCIE Preset code switching trigger based on a 555 timer, comprising a connected logic control module, a timing module, an electronic switch module and a clock module, wherein the logic control module is configured as a key trigger mode; In response to the key trigger mode, the logic control module outputs a low-level signal to the timing module. After receiving the low-level signal, the timing module outputs a high-level signal to the electronic switch module. The electronic switch module is turned on, and a clock signal is output to an external device through the clock module, and is turned off after a predetermined period of time.

[0006] Further, the logic control module is composed of a first logic control unit and a second logic control unit; The first pin and the fifth pin of the first logic control unit are connected to the fourth pin and the sixth pin of the single-pole double-throw switch, the third pin, the fourth pin and the thirteenth pin of the first logic control unit are interconnected, and the eighth pin of the first logic control unit is connected to the first pin, the second pin, the tenth pin and the thirteenth pin of the second logic control unit; The third pin of the second logic control unit is connected to its fourth pin, the fifth pin, the eighth pin and the twelfth pin of the second logic control unit are interconnected, and the eleventh pin of the second logic control unit is connected to the timing module.

[0007] Furthermore, it also includes a delay unit, which is composed of a first switch tube and an RC delay circuit; The gate of the first switch tube is connected to the fourth pin of the single-pole double-throw switch, and the source and drain of the first switch tube are connected to the electronic switch module through the RC delay circuit.

[0008] Furthermore, the timing module comprises a timing unit, a second pin of the timing unit is connected to an eleventh pin of the second logic control unit, and a third pin of the timing unit is connected to the electronic switch module.

[0009] Further, the electronic switch module includes a switch unit, a first pin and a fourth pin of the switch unit are connected to a third pin of the timing unit, an eighth pin of the switch unit is connected to a twelfth pin of the first logic control unit, and a tenth pin of the switch unit is connected to the RC delay circuit; The third pin of the switch unit is connected to the first connector through a third resistor, and the sixth pin of the switch unit is connected to the second connector through a fifth resistor.

[0010] Further, the clock module includes a clock unit, a fourth pin of the clock unit is connected to the second pin of the switch unit through a sixth resistor, and a fifth pin of the clock unit is connected to the fifth pin of the switch unit through a fourth resistor.

[0011] Furthermore, the timing unit adopts a monostable 555 timer and is configured to output a high level signal after receiving a trigger signal.

[0012] Furthermore, the logic control module is also configured as a long press mode; In response to the long press module, the logic control module outputs a high level signal to the electronic switch module, and the electronic switch module switch is turned on, so that the square wave generating module outputs a square wave signal to the logic control module. The logic control module outputs a low level signal to the timing module in each cycle of the square wave signal to control the electronic switch module to be turned on, output a clock signal to an external device through the clock module, and turn off after a predetermined period of time.

[0013] Furthermore, the square wave generating module comprises a square wave generating unit, a third pin of the square wave generating unit is connected to the clock module, and a second pin of the square wave generating unit is connected to a sixth pin thereof.

[0014] Furthermore, it also includes a digital tube counting module, which is connected to the timing module and is configured to accumulate counts after receiving a high-level signal and display the current count through a digital tube.

[0015] Compared with the prior art, the PCIE Preset pattern switching trigger based on a 555 timer described in this application has the following beneficial effects: The PCIE Preset code switching trigger based on the 555 timer described in the present application is composed of core components such as a crystal oscillator, a logic gate, a 555 timer and an electronic switch. There is no need to use a large chip, and the power consumption and cost are low. The trigger is extremely flexible. If the digital tube display function and the key long press function are not required, after deleting the relevant circuits, only 1 crystal oscillator and 4 chips are needed to complete the basic functions, and very little space is occupied. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings constituting a part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1 This is a circuit structure diagram of the trigger button trigger mode described in an embodiment of the present application; Figure 2 This is a circuit structure diagram of a trigger long press mode according to an embodiment of the present application; Figure 3 This is a circuit diagram of the logic control module described in the embodiment of the present application; Figure 4 A circuit diagram of a timing module according to an embodiment of the present application; Figure 5 This is a circuit diagram of the electronic switch module and the clock module described in the embodiment of the present application; Figure 6 This is a circuit diagram of the square wave generating module described in the embodiment of the present application; Figure 7 This is a circuit diagram of a digital tube counting module described in an embodiment of the present application. DETAILED DESCRIPTION

[0017] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0018] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be the usual meanings understood by people with ordinary skills in the field to which the present application belongs. The "first", "second" and similar words used in the embodiments of the present application do not represent any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0019] This embodiment provides a PCIE Preset pattern switching trigger based on a 555 timer, comprising a logic control module, a timing module, an electronic switch module and a clock module connected to each other, wherein the logic control module is configured as a key trigger mode; In response to the key trigger mode, the logic control module outputs a low-level signal to the timing module. After receiving the low-level signal, the timing module outputs a high-level signal to the electronic switch module. The electronic switch module is turned on, and a clock signal is output to the external device through the clock module, and is turned off after a predetermined period of time.

[0020] Specifically, in this embodiment, at the moment when the single-pole double-throw button is pressed, the logic control module outputs a low-level signal of several microseconds to tens of microseconds to the timing module. After receiving the signal, the timing module outputs a 1ms high-level signal to the electronic switch module. After receiving the high-level signal, the electronic switch module turns on the switch and outputs the 100MHz clock generated by the clock module to the external device (external connector), and then turns off after 1ms.

[0021] The working principle of the key trigger mode circuit is as follows Figure 1 As shown, the key signal is defibrillated by the RS latch and then input into the AND gate together with the square wave signal. At this time, the long press mode is not entered, the square wave input pin is constantly 1, and the AND gate output signal BR is the same as AQ. The logic module's subsequent circuit consists of a NOT gate, an RS latch, and an AND-NON gate.

[0022] In key trigger mode, the logic circuit can be divided into eight states: The first state: the button is released. At this time, the input AR of the NAND gate latch A is 0, AS is 1, the output AQ is 0, the output BR of the AND gate is 0, the output BS of the NOT gate is 1, the output BQ# of the NAND gate latch B is 1, the input trigger of the 555 timer is 1, and the timer outputs a low level.

[0023] The second state: the button switches from released to suspended state. At this time, AR is set from 0 to 1, AS = 1, and the output AQ of the NAND gate latch A remains 0. The output of the next stage is consistent with the previous state, and the timer outputs a low level.

[0024] The third state: the button is suspended, at this time AR = 1, AS = 1, the output AQ of the NAND latch A remains 0, the output of the next stage is consistent with the previous state, and the timer outputs a low level.

[0025] The fourth state: the button switches from floating to pressed state, at this time AR = 1, AS is set from 1 to 0, the output AQ of the NAND gate latch A is set from 0 to 1, the output signal BR of the AND gate is set from 0 to 1, the output BS of the NOT gate is briefly maintained at 1 due to the discharge of the capacitor, the output BQ# of the NAND gate latch B is briefly maintained at 1, the input trigger of the 555 timer is briefly set to 0, and the timer receives a low-level trigger signal and starts to output a high level for 1ms.

[0026] The fifth state: the button is pressed, at this time AR = 1, AS = 0, NAND gate latch A output AQ = 1, AND gate output signal BR = 1, NOT gate output BS = 0, NAND gate latch B output BQ# = 0, 555 timer input trigger = 1, the timer outputs a high level for 1ms and then remains at a low level.

[0027] The sixth state: the button switches from being pressed to being suspended. At this time, AR = 1, AS is set from 0 to 1, the output AQ of the NAND latch A remains 1, the output of the next stage is consistent with the previous state, and the timer outputs a low level.

[0028] The seventh state: the key is suspended. At this time, AR = 1, AS = 1, the output AQ of the NAND latch A remains 0, the output of the next stage is consistent with the previous state, and the timer outputs a low level.

[0029] The eighth state: the key switches from the suspended state to the released state. At this time, AR is set from 1 to 0, AS = 1, the output AQ of the NAND gate latch A is set from 1 to 0, the output signal BR of the AND gate is set from 1 to 0, and the output BS of the NOT gate is kept at 0 briefly due to the discharge of the capacitor. The NAND gate latch B is in an indeterminate state, and the output BQ# = 1, the input trigger of the 555 timer = 1, and the timer outputs a low level.

[0030] Logical analysis shows that at this time, the logic module only outputs 0 (capacitor discharge time) for a short time when the single-pole double-throw button is connected to AS, and the trigger is 1 at other times; the 555 timer outputs a high level after receiving the trigger signal, and pulls low after timing 1ms; after the electronic switch receives a 1ms high-level signal, it is turned on for 1ms, allowing the crystal oscillator to output a 1ms clock to the external connector.

[0031] In some embodiments, the logic control module is composed of a first logic control unit U2 and a second logic control unit U3; The 1A pin and the 2B pin of the first logic control unit U2 are connected to the 4 pin and the 6 pin of the single-pole double-throw switch SW1, the 1Y pin, the 2A pin and the 4B pin of the first logic control unit U2 are interconnected, and the 3Y pin of the first logic control unit U2 is connected to the 1A pin, the 1B pin, the 3B pin and the 4B pin of the second logic control unit U3; The 1Y pin of the second logic control unit U3 is connected to its 2A pin, the 2B pin, the 3Y pin, and the 4A pin of the second logic control unit U3 are interconnected, and the 4Y pin of the second logic control unit U3 is connected to the timing module; It also includes a delay unit, which is composed of a first switch tube Q1 and an RC delay circuit (composed of a resistor R17 and a capacitor C6); The gate of the first switch tube Q1 is connected to the 4th pin of the single-pole double-throw switch SW1, and the source and drain of the first switch tube Q1 are connected to the electronic switch module through an RC delay circuit.

[0032] Specifically, in this embodiment, Figure 3 This is the circuit schematic diagram of the logic control module, which consists of 8 NAND gates, 2 RS latches, 1 AND gate, a NOT gate, and a NAND gate to meet the logic requirements; the delay part is composed of NMOS tubes and RC delay circuits. When the button is long pressed, the SW_hold signal is delayed by about 300ms and pulled up to 2V.

[0033] Specifically, a single press sends a 1ms clock, and a long press of about 300ms enters the continuous sending mode, sending once every 390ms. Each trigger outputs a low level of about 2us, and the button is pressed for about 300ms to output a high level.

[0034] This application uses simple devices to output single or periodic pulse signals as low as nanoseconds. The logic control module only needs to adjust the capacitance of capacitor C5 to adjust the pulse width of the output trigger signal. The minimum can be adjusted to tens of nanoseconds, and can be used in more scenarios in conjunction with other circuits.

[0035] In some embodiments, the timing module includes a timing unit U4, which uses a monostable 555 timer. The pin is connected to the 4Y pin of the second logic control unit, and the Output pin of the timing unit U4 is connected to the electronic switch module.

[0036] Specifically, in this embodiment, Figure 4 This is the schematic diagram of the timing module circuit. After receiving the trigger signal, the monostable 555 timer outputs 1.1×R×C, that is, a 1ms high-level signal.

[0037] In some embodiments, the electronic switch module includes a switch unit U1, wherein the 1OE pin and the 2OE pin of the switch unit U1 are connected to the Output pin of the timing unit U4, the 3B pin of the switch unit U1 is connected to the 4A pin of the first logic control unit U2, and the 3OE pin of the switch unit U1 is connected to the RC delay circuit; The 1B pin of the switch unit U1 is connected to the first connector J1 through the resistor R3, and the 2B pin of the switch unit U1 is connected to the second connector J2 through the resistor R5; The clock module includes a clock unit Y1, an OUT+ pin of the clock unit Y1 is connected to a 1A pin of the switch unit U1 through a resistor R6, and an OUT- pin of the clock unit Y1 is connected to a 2A pin of the switch unit U1 through a resistor R4.

[0038] Specifically, in this embodiment, Figure 5 This is the circuit schematic diagram of the electronic switch and clock module. After receiving the timing module signal, the electronic switch channels 1 and 2 are turned on for 1ms and output the clock to the connector. Channel 3 is turned on after the SW_hold signal is pulled high and outputs the square wave to the logic control module.

[0039] In some embodiments, the logic control module is further configured to be in a long press mode; In response to the long press module, the logic control module outputs a high-level signal to the electronic switch module, and the electronic switch module switch is turned on, so that the square wave generating module outputs a square wave signal to the logic control module. The logic control module outputs a low-level signal to the timing module in each cycle of the square wave signal to control the electronic switch module to be turned on, output a clock signal to the external device through the clock module, and turn off after a predetermined period of time.

[0040] Specifically, in this embodiment, when the single-pole double-throw button is pressed, the delay part circuit of the logic control module is started. After several hundred milliseconds, if the button is still pressed, it enters the long press mode and outputs a high-level signal to the electronic switch module; after the electronic switch module receives the signal, the switch is turned on, so that the square wave signal output by the square wave generating module is given to the logic control module; after receiving the square wave signal, the logic control module outputs a low-level signal of several microseconds to tens of microseconds to the timing module once in each cycle of the square wave signal, and the subsequent process is as described in the button trigger mode.

[0041] How long press mode works: When the button is in hold state five, AS = 0, MOS tube Q1 is turned off, and capacitor C6 starts to charge. After a period of time, capacitor C6 is charged to the threshold, SW_hold outputs a high level, the electronic switch is turned on, and the square wave output by the square wave generating module is given to the AND gate input signal SW_hold_out, and the circuit enters the long press mode. The working principle of the circuit is as follows: Figure 2 As shown. At this time, AQ remains at 1, the square wave signal is output to the AND gate, and BR changes with the square wave cycle; in one square wave cycle, the trigger signal will experience a jump from state 1 to 8, and output a low level equivalent to the capacitor discharge time; the timer will receive a level trigger signal in each cycle, control the electronic switch to turn on for 1ms, and output a 1ms clock.

[0042] In some embodiments, the square wave generating module includes a square wave generating unit, a third pin of the square wave generating unit is connected to the clock module, and a second pin of the square wave generating unit is connected to a sixth pin thereof.

[0043] Specifically, in this embodiment, Figure 6 This is the circuit schematic of the square wave generator module. The astable 555 timer periodically outputs high and low signals, and the high level time is 0.693×(R A +R B )×C, low level time is 0.693×R B ×C, the period can be adjusted according to demand, currently it is 390ms.

[0044] In some embodiments, a digital tube counting module (composed of a counting unit, a level conversion unit, a count clearing unit, and two digital tube display units) is also included. The digital tube counting module is connected to the timing module and is configured to accumulate counts after receiving a high-level signal and display the current count through the digital tube.

[0045] Specifically, in this embodiment, Figure 7 This is the circuit schematic diagram of the digital tube counting module. The timer module outputs signals to a 2-digit decimal counter, and the digital tube displays the current count.

[0046] The trigger described in the present application is easy to operate, and the user only needs to control one button to complete all functions. The digital tube display allows the user to more intuitively view the current clock count being sent.

[0047] The trigger described in this application mainly includes core components such as crystal oscillators, logic gates, 555 timers and electronic switches. There is no need to use large chips, and the power consumption and cost are low. The trigger is extremely flexible. If the digital tube display function and the key long press function are not required, after deleting the relevant circuits, only 1 crystal oscillator and 4 chips are needed to complete the basic functions, and it takes up very little space.

[0048] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. These modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention, and they should all be included in the scope of the claims and specification of the present invention.

[0049] The embodiments of the present application are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of the present application.

Claims

1. A PCIE Preset pattern switching trigger based on a 555 timer, characterized in that: It includes a logic control module, a timing module, an electronic switch module and a clock module connected to each other, wherein the logic control module is configured as a key trigger mode; In response to the key trigger mode, the logic control module outputs a low-level signal to the timing module. After receiving the low-level signal, the timing module outputs a high-level signal to the electronic switch module. The electronic switch module is turned on, and a clock signal is output to an external device through the clock module, and is turned off after a predetermined period of time.

2. The PCIE Preset pattern switching trigger based on a 555 timer according to claim 1, characterized in that: The logic control module is composed of a first logic control unit and a second logic control unit; The first pin and the fifth pin of the first logic control unit are connected to the fourth pin and the sixth pin of the single-pole double-throw switch, the third pin, the fourth pin and the thirteenth pin of the first logic control unit are interconnected, and the eighth pin of the first logic control unit is connected to the first pin, the second pin, the tenth pin and the thirteenth pin of the second logic control unit; The third pin of the second logic control unit is connected to its fourth pin, the fifth pin, the eighth pin and the twelfth pin of the second logic control unit are interconnected, and the eleventh pin of the second logic control unit is connected to the timing module.

3. The PCIE Preset code switching trigger based on a 555 timer according to claim 2, characterized in that: It also includes a delay unit, which is composed of a first switch tube and an RC delay circuit; The gate of the first switch tube is connected to the fourth pin of the single-pole double-throw switch, and the source and drain of the first switch tube are connected to the electronic switch module through the RC delay circuit.

4. The PCIE Preset code switching trigger based on a 555 timer according to claim 3, characterized in that: The timing module comprises a timing unit, a second pin of the timing unit is connected to an eleventh pin of the second logic control unit, and a third pin of the timing unit is connected to the electronic switch module.

5. The PCIE Preset code switching trigger based on a 555 timer according to claim 4, characterized in that: The electronic switch module comprises a switch unit, wherein the first pin and the fourth pin of the switch unit are connected to the third pin of the timing unit, the eighth pin of the switch unit is connected to the twelfth pin of the first logic control unit, and the tenth pin of the switch unit is connected to the RC delay circuit; The third pin of the switch unit is connected to the first connector through a third resistor, and the sixth pin of the switch unit is connected to the second connector through a fifth resistor.

6. The PCIE Preset pattern switching trigger based on a 555 timer according to claim 5, characterized in that: The clock module comprises a clock unit, a fourth pin of the clock unit is connected to the second pin of the switch unit via a sixth resistor, and a fifth pin of the clock unit is connected to the fifth pin of the switch unit via a fourth resistor.

7. The PCIE Preset code switching trigger based on a 555 timer according to claim 4, characterized in that: The timing unit adopts a monostable 555 timer and is configured to output a high level signal after receiving a trigger signal.

8. The PCIE Preset code switching trigger based on a 555 timer according to claim 1, characterized in that: The logic control module is also configured as a long press mode; In response to the long press module, the logic control module outputs a high level signal to the electronic switch module, and the electronic switch module switch is turned on, so that the square wave generating module outputs a square wave signal to the logic control module. The logic control module outputs a low level signal to the timing module in each cycle of the square wave signal to control the electronic switch module to be turned on, output a clock signal to an external device through the clock module, and turn off after a predetermined period of time.

9. The PCIE Preset code switching trigger based on a 555 timer according to claim 8, characterized in that: The square wave generating module comprises a square wave generating unit, a third pin of the square wave generating unit is connected to the clock module, and a second pin of the square wave generating unit is connected to a sixth pin thereof.

10. The PCIE Preset code switching trigger based on a 555 timer according to claim 8, characterized in that: It also includes a digital tube counting module, which is connected to the timing module and is configured to accumulate counts after receiving a high-level signal and display the current count through a digital tube.

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