A PCIE Preset Pattern Switching Trigger Based on 555 Timer

Abstract

The present application provides a PCIE Preset pattern switching trigger based on a 555 timer, which includes a logically controlled module, a timing module, an electronic switch module, and a clock module connected to each other. The logically controlled module is configured in a key trigger mode; in response to the key trigger mode, the logically controlled module outputs a low-level signal to the timing module. After receiving the low-level signal, the timing module outputs a high-level signal to the electronic switch module, and the electronic switch module is turned on, and a clock signal is output to an external device through the clock module and is turned off after a predetermined duration. The trigger described in the present application is composed of core components such as a crystal oscillator, logic gates, a 555 timer, and an electronic switch, without the need to use large chips, with low power consumption and cost. The trigger has extremely high flexibility. If the digital tube display function and the long-press function of the key are not required, after deleting the relevant circuits, only 1 crystal oscillator and 4 chips are needed to complete the basic functions, occupying very little space.

Description

Technical Field

[0001] This application belongs to the technical field of hardware circuits, and particularly relates to a PCIE Preset pattern switching trigger based on a 555 timer. Background Art

[0002] In the transmitter signal quality test of the standard PCIE protocol, the TX channel of the PCIE device outputs different types of patterns, and an oscilloscope is used to check whether each one meets the protocol specifications. Whenever the RX channel receives a 1ms 100MHz clock signal, the TX channel switches to the next pattern. The total number of patterns for each generation of PCIE is different. For example, there are 14 patterns for PCIE 3.0. After switching to the last pattern, continuing to switch will start from the first one.

[0003] Most existing products use controllers such as single-chip microcomputers or CPLDs to operate the clock output, which has a high cost and requires programming development, and the operation is complex. Summary of the Invention

[0004] In view of this, this application aims to propose a PCIE Preset pattern switching trigger based on a 555 timer to solve the problems of high cost, programming development requirement, and complex operation in using a controller to operate the clock output.

[0005] To achieve the above object, the technical solution of this application is realized as follows:

[0006] This application provides a PCIE Preset pattern switching trigger based on a 555 timer, including a logically controlled module, a timing module, an electronic switch module, and a clock module connected to each other. The logically controlled module is configured in a key trigger mode;

[0007] In response to the key trigger mode, the logically controlled module outputs a low-level signal to the timing module. After receiving the low-level signal, the timing module outputs a high-level signal to the electronic switch module. The electronic switch module is turned on, and a clock signal is output to an external device through the clock module and is turned off after a predetermined duration.

[0008] Further, the logically controlled module is composed of a first logically controlled unit and a second logically controlled unit;

[0009] The first pin and the fifth pin of the first logically controlled unit are connected to the fourth pin and the sixth pin of a single-pole double-throw switch. The third pin, the fourth pin, and the thirteenth pin of the first logically controlled unit are interconnected. The eighth pin of the first logically controlled unit is connected to the first pin, the second pin, the tenth pin, and the thirteenth pin of the second logically controlled unit;

[0010] The third pin of the second logic control unit is connected to its fourth pin, the fifth pin, eighth pin, and twelfth pin of the second logic control unit are interconnected, and the eleventh pin of the second logic control unit is connected to the timing module.

[0011] Further, it further includes a delay unit, which is composed of a first switching transistor and an RC delay circuit;

[0012] The gate of the first switching transistor is connected to the fourth pin of the single-pole double-throw switch, and between the source and drain of the first switching transistor is connected to the electronic switch module through the RC delay circuit.

[0013] Further, the timing module includes a timing unit, the second pin of the timing unit is connected to the eleventh pin of the second logic control unit, and the third pin of the timing unit is connected to the electronic switch module.

[0014] Further, the electronic switch module includes a switch unit, the first pin and fourth pin of the switch unit are connected to the third pin of the timing unit, the eighth pin of the switch unit is connected to the twelfth pin of the first logic control unit, and the tenth pin of the switch unit is connected to the RC delay circuit;

[0015] The third pin of the switch unit is connected to the first connector through a third resistor, and the sixth pin of the switch unit is connected to the second connector through a fifth resistor.

[0016] Further, the clock module includes a clock unit, the fourth pin of the clock unit is connected to the second pin of the switch unit through a sixth resistor, and the fifth pin of the clock unit is connected to the fifth pin of the switch unit through a fourth resistor.

[0017] Further, the timing unit uses a monostable 555 timer and is configured to output a high-level signal after receiving a trigger signal.

[0018] Further, the logic control module is also configured for a long-press mode;

[0019] In response to the long-press module, the logic control module outputs a high-level signal to the electronic switch module, the electronic switch module is turned on, so that the square-wave generation module outputs a square-wave signal to the logic control module, the logic control module outputs a low-level signal to the timing module within each cycle of the square-wave signal to control the electronic switch module to be turned on, outputs a clock signal to an external device through the clock module, and turns off after a predetermined duration.

[0020] Further, the square wave generating module includes a square wave generating unit. The third pin of the square wave generating unit is connected to the clock module, and the second pin of the square wave generating unit is connected to its sixth pin.

[0021] Further, a digital tube counting module is also included. The digital tube counting module is connected to the timing module and is configured to increment the count after receiving a high-level signal and display the current count through the digital tube.

[0022] Compared with the prior art, the PCIE Preset pattern switching trigger based on a 555 timer described in this application has the following beneficial effects:

[0023] The PCIE Preset pattern switching trigger based on a 555 timer described in this application is composed of core components such as a crystal oscillator, logic gates, a 555 timer, and an electronic switch. It does not require the use of large chips, has low power consumption and cost, and has extremely high flexibility. If the digital tube display function and the long-press function of the button are not required, after deleting the relevant circuits, only 1 crystal oscillator and 4 chips are needed to complete the basic functions, occupying very little space. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The drawings forming a part of this application are used to provide a further understanding of this application. The schematic embodiments and descriptions thereof of this application are used to explain this application and do not constitute an improper limitation to this application. In the drawings:

[0025] Figure 1 is the circuit structure diagram of the trigger button trigger mode described in the embodiment of this application;

[0026] Figure 2 is the circuit structure diagram of the trigger long-press mode described in the embodiment of this application;

[0027] Figure 3 is the circuit diagram of the logic control module described in the embodiment of this application;

[0028] Figure 4 is the circuit diagram of the timing module described in the embodiment of this application;

[0029] Figure 5 is the circuit diagram of the electronic switch module and the clock module described in the embodiment of this application;

[0030] Figure 6 is the circuit diagram of the square wave generating module described in the embodiment of this application;

[0031] Figure 7 is the circuit diagram of the digital tube counting module described in the embodiment of this application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0032] To make the objectives, technical solutions, and advantages of this application more clear and understandable, the following further elaborates on this application in detail with reference to specific embodiments and the accompanying drawings.

[0033] It should be noted that unless otherwise defined, the technical terms or scientific terms used in the embodiments of this application should have the ordinary meanings understood by those with ordinary skills in the field to which this application belongs. The "first", "second", and similar terms used in the embodiments of this application do not denote any order, quantity, or importance, but are only used to distinguish different components. Words such as "including" or "comprising" mean that the elements or objects appearing before this word cover the elements or objects listed after this word and their equivalents, without excluding other elements or objects. Words such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper", "lower", "left", "right", etc. are only used to represent relative position relationships, and when the absolute position of the object being described changes, the relative position relationship may also change accordingly.

[0034] This embodiment provides a PCIE Preset pattern switching trigger based on a 555 timer, which includes a logically controlled module, a timing module, an electronic switch module, and a clock module connected to each other. The logically controlled module is configured in a key-triggered mode;

[0035] In response to the key-triggered mode, the logically controlled module outputs a low-level signal to the timing module. After receiving the low-level signal, the timing module outputs a high-level signal to the electronic switch module. The electronic switch module is turned on, and a clock signal is output to an external device through the clock module and is turned off after a predetermined duration.

[0036] Specifically, in this embodiment, at the moment when the single-pole double-throw key is pressed, the logically controlled module outputs a low-level signal of several microseconds to dozens of microseconds to the timing module once. After receiving the signal, the timing module outputs a 1 ms high-level signal to the electronic switch module. After receiving the high-level signal, the electronic switch module is turned on, and the 100 MHz clock generated by the clock module is output to an external device (external connector) and is turned off after 1 ms.

[0037] The working principle of the key-triggered mode circuit is as Figure 1 shown. The key signal is debounced by an RS latch and then input to an AND gate together with a square wave signal. At this time, the long-press mode is not entered, and the square wave input pin is constantly 1. The output signal BR of the AND gate is the same as AQ. The subsequent circuit of the logic module consists of an inverter, an RS latch, and a NAND gate.

[0038] In the key-triggered mode, the logic circuit can be divided into eight states:

[0039] First state: The key is released. At this time, for NAND latch A, the input AR = 0, AS = 1, the output AQ = 0, the output of the AND gate BR = 0, the output of the NOT gate BS = 1, for NAND latch B, the output BQ# = 1, the input trigger of the 555 timer = 1, and the timer outputs a low level.

[0040] Second state: The key switches from the released state to the floating state. At this time, AR is set from 0 to 1, AS = 1, the output AQ of NAND latch A remains 0, the subsequent output is the same as the previous state, and the timer outputs a low level.

[0041] Third state: The key is in the floating state. At this time, AR = 1, AS = 1, the output AQ of NAND latch A remains 0, the subsequent output is the same as the previous state, and the timer outputs a low level.

[0042] Fourth state: The key switches from the floating state to the pressed state. At this time, AR = 1, AS is set from 1 to 0, the output AQ of NAND latch A is set from 0 to 1, the output signal BR of the AND gate is set from 0 to 1, the output BS of the NOT gate briefly remains 1 due to the capacitor discharging, the output BQ# of NAND latch B briefly remains 1, the input trigger of the 555 timer is briefly set to 0, and the timer starts to output a 1ms high level when it receives the low-level trigger signal.

[0043] Fifth state: The key is pressed. At this time, AR = 1, AS = 0, the output AQ of NAND latch A = 1, the output signal BR of the AND gate = 1, the output BS of the NOT gate = 0, the output BQ# of NAND latch B = 0, the input trigger of the 555 timer = 1, and the timer remains low after outputting the 1ms high level.

[0044] Sixth state: The key switches from the pressed state to the floating state. At this time, AR = 1, AS is set from 0 to 1, the output AQ of NAND latch A remains 1, the subsequent output is the same as the previous state, and the timer outputs a low level.

[0045] Seventh state: The key is in the floating state. At this time, AR = 1, AS = 1, the output AQ of NAND latch A remains 0, the subsequent output is the same as the previous state, and the timer outputs a low level.

[0046] Eighth state: The key switches from the floating state to the released state. At this time, AR is set from 1 to 0, AS = 1, the output AQ of NAND latch A is set from 1 to 0, the output signal BR of the AND gate is set from 1 to 0, the output BS of the NOT gate briefly remains 0 due to the capacitor discharging, NAND latch B is in an indeterminate state, the output BQ# = 1, the input trigger of the 555 timer = 1, and the timer outputs a low level.

[0047] Through logical analysis, it can be known that at this time, the logic module only has a short trigger output of 0 (capacitor discharge time) when the single-pole double-throw button is connected to AS, and the trigger is 1 at other times; after receiving the trigger signal, the 555 timer outputs a high level and pulls it low after 1 ms; after receiving the 1 ms high-level signal, the electronic switch conducts for 1 ms, enabling the crystal oscillator to output a 1 ms clock to the external connector.

[0048] In some embodiments, the logic control module is composed of a first logic control unit U2 and a second logic control unit U3;

[0049] The 1A pin and 2B pin of the first logic control unit U2 are connected to the 4 pin and 6 pin of the single-pole double-throw switch SW1. The 1Y pin, 2A pin, and 4B pin of the first logic control unit U2 are interconnected. The 3Y pin of the first logic control unit U2 is connected to the 1A pin, 1B pin, 3B pin, and 4B pin of the second logic control unit U3;

[0050] The 1Y pin of the second logic control unit U3 is connected to its 2A pin. The 2B pin, 3Y pin, and 4A pin of the second logic control unit U3 are interconnected. The 4Y pin of the second logic control unit U3 is connected to the timing module;

[0051] It further includes a delay unit, which is composed of a first switching transistor Q1 and an RC delay circuit (formed by a resistor R17 and a capacitor C6);

[0052] The gate of the first switching transistor Q1 is connected to the 4 pin of the single-pole double-throw switch SW1. Between the source and drain of the first switching transistor Q1 is connected to the electronic switch module through the RC delay circuit.

[0053] Specifically, in this embodiment, Figure 3 is the circuit schematic diagram of the logic control module, which consists of 8 NAND gates to form 2 RS latches, 1 AND gate, 1 NOT gate, and 1 NAND gate to meet the logical requirements; the delay part is composed of an NMOS transistor and an RC delay circuit. When the button is pressed for a long time, the SW_hold signal is delayed by about 300 ms and pulled high to 2V.

[0054] Specifically speaking, pressing once sends a 1 ms clock once. Pressing and holding for about 300 ms enters the continuous sending mode, sending once every 390 ms. Each trigger outputs a low level of about 2 us, and the button outputs a high level after being pressed for about 300 ms.

[0055] This application uses simple devices to output single or periodic pulse signals as low as the nanosecond level. The logic control module only needs to adjust the capacitance value of the capacitor C5 to adjust the pulse width of the output trigger signal, which can be adjusted to a minimum of dozens of nanoseconds, and can be applied in more scenarios in combination with other circuits.

[0056] In some embodiments, the timing module includes a timing unit U4. The timing unit U4 uses a monostable 555 timer. The pin of the timing unit U4 is connected to the 4Y pin of the second logic control unit, and the Output pin of the timing unit U4 is connected to the electronic switch module.

[0057] Specifically, in this embodiment, Figure 4 is the circuit schematic diagram of the timing module. After receiving the trigger signal, the monostable 555 timer outputs 1.1×R×C, that is, a 1ms high-level signal.

[0058] In some embodiments, the electronic switch module includes a switch unit U1. The 1OE pin and 2OE pin of the switch unit U1 are connected to the Output pin of the timing unit U4. The 3B pin of the switch unit U1 is connected to the 4A pin of the first logic control unit U2, and the 3OE pin of the switch unit U1 is connected to the RC delay circuit;

[0059] The 1B pin of the switch unit U1 is connected to the first connector J1 through the resistor R3, and the 2B pin of the switch unit U1 is connected to the second connector J2 through the resistor R5;

[0060] The clock module includes a clock unit Y1. The OUT+ pin of the clock unit Y1 is connected to the 1A pin of the switch unit U1 through the resistor R6, and the OUT- pin of the clock unit Y1 is connected to the 2A pin of the switch unit U1 through the resistor R4.

[0061] Specifically, in this embodiment, Figure 5 is the circuit schematic diagram of the electronic switch and the clock module. After receiving the signal from the timing module, the electronic switch channels 1 and 2 are turned on for 1ms to output the clock to the connector. Channel 3 is turned on after the SW_hold signal is pulled high to output the square wave to the logic control module.

[0062] In some embodiments, the logic control module is further configured for a long-press mode;

[0063] In response to the long-press module, the logic control module outputs a high-level signal to the electronic switch module, and the electronic switch module is turned on, so that the square wave generation module outputs a square wave signal to the logic control module. The logic control module outputs a low-level signal to the timing module within each cycle of the square wave signal to control the electronic switch module to be turned on, output the clock signal to the external device through the clock module, and turn off after a predetermined duration.

[0064] Specifically, in this embodiment, when the single-pole double-throw button is pressed, the delay part circuit of the logic control module is activated. After several hundred milliseconds, if the button is still pressed, it enters the long-press mode and outputs a high-level signal to the electronic switch module. After receiving the signal, the electronic switch module conducts, enabling the square-wave signal output by the square-wave generation module to be sent to the logic control module. After receiving the square-wave signal, the logic control module outputs a low-level signal of several microseconds to dozens of microseconds once per cycle of the square-wave signal to the timing module, and the subsequent process is as described in the button trigger mode.

[0065] Working principle of the long-press mode:

[0066] When the button maintains state five, AS = 0, the MOS transistor Q1 is cut off, and the capacitor C6 starts to charge. After a period of time, when the capacitor C6 is charged to the threshold, SW_hold outputs a high level, the electronic switch conducts, and the square wave output by the square-wave generation module is given to the AND gate input signal SW_hold_out, and the circuit enters the long-press mode. The circuit working principle is as Figure 2 shown. At this time, AQ remains 1, the square-wave signal is output to the AND gate, and BR changes with the square-wave period; within one square-wave cycle, the trigger signal will experience state transitions from 1 to 8, and a low level equivalent to the capacitor discharge time is output once; the timer will receive a level trigger signal in each cycle to control the electronic switch to conduct for 1 ms and output a 1 ms clock.

[0067] In some embodiments, the square-wave generation module includes a square-wave generation unit. The third pin of the square-wave generation unit is connected to the clock module, and the second pin of the square-wave generation unit is connected to its sixth pin.

[0068] Specifically, in this embodiment, Figure 6 is the circuit schematic diagram of the square-wave generation module. The astable 555 timer periodically outputs high and low signals. The high-level time is 0.693×(R A +R B )×C, and the low-level time is 0.693×R B ×C. The period can be adjusted according to requirements and is currently 390 ms.

[0069] In some embodiments, it further includes a digital tube counting module (composed of a counting unit, a level conversion unit, a counting clear unit, and two digital tube display units). The digital tube counting module is connected to the timing module and is configured to increment the count after receiving a high-level signal and display the current count through the digital tube.

[0070] Specifically, in this embodiment, Figure 7 is the circuit schematic diagram of the digital tube counting module. The timer module outputs a signal to a 2-digit decimal counter, and the current count is displayed by the digital tube.

[0071] The flip-flop described in this application is easy to operate. Users only need to control one button to complete all functions, and the digital tube display enables users to more intuitively view the current number of clock transmissions.

[0072] The flip-flop described in this application mainly includes core components such as crystal oscillators, logic gates, 555 timers, and electronic switches. It does not require the use of large chips, has low power consumption and cost, and has extremely high flexibility. If the digital tube display function and the long-press function of the button are not required, after deleting the relevant circuits, only 1 crystal oscillator and 4 chips are needed to complete the basic functions, occupying very little space.

[0073] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention, and they should all be covered by the scope of the claims and the description of the present invention.

[0074] The embodiments of this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the embodiments of this application shall be included within the protection scope of this application.

Claims

1. A PCIE Preset pattern switching trigger based on a 555 timer, characterized in that: It includes a logically controlled module, a timing module, an electronic switch module, and a clock module that are connected. The logically controlled module is configured in a key trigger mode; In response to the key trigger mode, the logically controlled module outputs a low-level signal to the timing module. After receiving the low-level signal, the timing module outputs a high-level signal to the electronic switch module. The electronic switch module is turned on, and a clock signal is output to an external device through the clock module and is turned off after a predetermined duration; The logically controlled module is also configured in a long-press mode; In response to the long-press module, the logically controlled module outputs a high-level signal to the electronic switch module. The electronic switch module is turned on, so that a square-wave generating module outputs a square-wave signal to the logically controlled module. The logically controlled module outputs a low-level signal to the timing module within each cycle of the square-wave signal to control the electronic switch module to be turned on, and a clock signal is output to an external device through the clock module and is turned off after a predetermined duration.

2. The PCIE Preset pattern switching trigger based on a 555 timer according to claim 1, characterized in that: The logically controlled module is composed of a first logically controlled unit and a second logically controlled unit; The first pin and the fifth pin of the first logically controlled unit are connected to the fourth pin and the sixth pin of a single-pole double-throw switch. The third pin, the fourth pin, and the thirteenth pin of the first logically controlled unit are interconnected. The eighth pin of the first logically controlled unit is connected to the first pin, the second pin, the tenth pin, and the thirteenth pin of the second logically controlled unit; The third pin of the second logically controlled unit is connected to its fourth pin. The fifth pin, the eighth pin, and the twelfth pin of the second logically controlled unit are interconnected. The eleventh pin of the second logically controlled unit is connected to the timing module.

3. The PCIE Preset pattern switching trigger based on a 555 timer according to claim 2, characterized in that: It further includes a delay unit, and the delay unit is composed of a first switching tube and an RC delay circuit; The gate of the first switching tube is connected to the fourth pin of the single-pole double-throw switch. Between the source and the drain of the first switching tube, it is connected to the electronic switch module through the RC delay circuit.

4. The PCIE Preset pattern switching trigger based on a 555 timer according to claim 3, characterized in that: The timing module includes a timing unit. The second pin of the timing unit is connected to the eleventh pin of the second logically controlled unit. The third pin of the timing unit is connected to the electronic switch module.

5. The PCIE Preset pattern switching trigger based on a 555 timer according to claim 4, characterized in that: The electronic switch module includes a switch unit. The first pin and the fourth pin of the switch unit are connected to the third pin of the timing unit. The eighth pin of the switch unit is connected to the twelfth pin of the first logic control unit. The tenth pin of the switch unit is connected to the RC delay circuit; The third pin of the switch unit is connected to a first connector through a third resistor. The sixth pin of the switch unit is connected to a second connector through a fifth resistor.

6. A PCIE Preset pattern switching flip-flop based on a 555 timer according to claim 5, characterized in that: The clock module includes a clock unit. The fourth pin of the clock unit is connected to the second pin of the switch unit through a sixth resistor. The fifth pin of the clock unit is connected to the fifth pin of the switch unit through a fourth resistor.

7. A PCIE Preset pattern switching flip-flop based on a 555 timer according to claim 4, characterized in that: The timing unit uses a monostable 555 timer and is configured to output a high-level signal after receiving a trigger signal.

8. A PCIE Preset pattern switching flip-flop based on a 555 timer according to claim 1, characterized in that: The square wave generating module includes a square wave generating unit. The third pin of the square wave generating unit is connected to the clock module. The second pin of the square wave generating unit is connected to its sixth pin.

9. A PCIE Preset pattern switching flip-flop based on a 555 timer according to claim 1, characterized in that: It further includes a digital tube counting module. The digital tube counting module is connected to the timing module and is configured to increment the count after receiving a high-level signal and display the current count through the digital tube.

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