Data prefetching method and device, electronic equipment and storage medium

Abstract

The invention discloses a data pre-fetching method and device, electronic equipment and a storage medium, and relates to the technical field of computers, after memory access information of all currently running processes is obtained, a corresponding data pre-fetching algorithm is independently trained for each process, an algorithm set is formed, and when data pre-fetching is carried out, the data pre-fetching efficiency is improved. And screening a proper algorithm from the algorithm set according to the target process to which the current memory access request belongs, so that the technical problem that in the prior art, a hardware prefetcher depends on a fixed memory access mode, and when the memory access mode is changed due to process switching, the accuracy of a data prefetching result is reduced can be solved; the technical effect of improving the accuracy of the data prefetching result is achieved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a data pre-fetching method, device, electronic device and storage medium. Background Art

[0002] With the improvement of the performance of computing devices such as servers, the storage wall problem has become more and more prominent. The memory access speed lags far behind the processor computing speed, resulting in memory access delays when data is missing. Therefore, how to pre-fetch memory data to reduce memory access delays has become a key research topic.

[0003] In the related art, a hardware prefetcher is usually used for data prefetching. However, the hardware prefetcher relies on a fixed memory access mode. When the memory access mode changes due to process switching, the accuracy of the data prefetching result decreases, wasting the data prefetching resources of the computing device. Summary of the invention

[0004] The present application provides a data pre-fetching method, device, electronic device and storage medium to at least solve the problem in the related art that the accuracy of data pre-fetching results is reduced and the data pre-fetching resources of the computing device are wasted.

[0005] The present application provides a data pre-fetching method, comprising: Get the memory access information of all currently running processes; For any process, according to the memory access information of the process, a data prefetching algorithm corresponding to the process is trained to obtain a data prefetching algorithm set; When the current cache state of the preset cache meets the preset pre-fetch condition, the current memory access request is obtained, and the target process to which the current memory access request belongs is determined; According to the target process, select a target data prefetching algorithm from the data prefetching algorithm set; Based on the target data prefetching algorithm, the target data prefetching strategy is determined according to the memory access address information of the current memory access request.

[0006] The present application also provides a data pre-fetching device, comprising: The acquisition module is used to obtain the memory access information of all currently running processes; A training module is used for training a data prefetching algorithm corresponding to any process according to the memory access information of the process to obtain a data prefetching algorithm set; A determination module, used for obtaining a current memory access request and determining a target process to which the current memory access request belongs when a current cache state of a preset cache satisfies a preset pre-fetch condition; A screening module, used for screening a target data prefetching algorithm in a data prefetching algorithm set according to a target process; The prefetch module is used to determine the target data prefetch strategy based on the target data prefetch algorithm and the memory access address information of the current memory access request.

[0007] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned data pre-fetching methods when executing the computer program.

[0008] The present application also provides a computer-readable storage medium, in which a computer program is stored, wherein when the computer program is executed by a processor, the steps of any of the above-mentioned data prefetching methods are implemented.

[0009] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned data pre-fetching methods when executed by a processor.

[0010] Through the present application, after obtaining the memory access information of all currently running processes, the corresponding data prefetching algorithm is independently trained for each process and an algorithm set is formed. When performing data prefetching, a suitable algorithm is screened from the algorithm set according to the target process to which the current memory access request belongs. Therefore, the technical problem in the prior art that the hardware prefetcher relies on a fixed memory access mode and the accuracy of its data prefetching results is reduced when the process switching causes the memory access mode to change can be solved, thereby achieving the technical effect of improving the accuracy of the data prefetching results. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0012] Figure 1 A schematic diagram of the structure of a data pre-fetching system based on an embodiment of the present application; Figure 2 A schematic diagram of a flow chart of a data pre-fetching method provided in an embodiment of the present application; Figure 3 A schematic diagram of the structure of an exemplary data pre-fetching system provided in an embodiment of the present application; Figure 4 A schematic diagram of a flow chart of an exemplary data pre-fetching method provided in an embodiment of the present application; Figure 5 A schematic diagram of the structure of another exemplary data pre-fetching system provided in an embodiment of the present application; Figure 6 A schematic diagram of the structure of a pre-fetch transmission unit provided in an embodiment of the present application; Figure 7 A schematic diagram of the structure of a data pre-fetching device provided in an embodiment of the present application; Figure 8 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0013] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0014] It should be noted that, in the description of this application, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in this application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0015] In modern multi-core high-performance processors, resources such as storage capacity allocated to cores are very tight, and the memory access speed seriously lags behind the processor's computing speed. The bottleneck effect caused by the "storage wall" problem has become an important factor restricting the development of high-performance processors. The general approach of modern processors is to add a hidden, small-capacity, fast cache between the CPU and the main memory. Although the cache can provide high-speed storage access for the CPU, when the data required by the program is missing in the cache, it is necessary to obtain the data from the lower-level storage structure, which brings dozens of times more access delay, seriously affecting the computing performance.

[0016] Data prefetching technology refers to the process of loading the required data into the cache in advance based on the principle of local memory access of the program before the program accesses the data, by learning the past memory access rules to predict the subsequent memory access, thereby reducing cache misses and hiding memory latency issues. This technology does not necessarily benefit the program, because this prediction based on the data required by the future processor consumes additional storage bandwidth. If data blocks that will not be accessed in the future are prefetched, it will not only cause additional communication pressure, but also may replace useful data blocks in the cache, causing cache pollution and leading to cache misses that would not have occurred otherwise. It is necessary to judge the effectiveness of the data prefetching technology used.

[0017] At present, the technology trend of high-performance processors generally adopts a multi-core multi-threaded structure. The concurrent execution of multiple processes has brought about a complex computing environment and increased computing load. The memory access pattern characteristics and data ranges between different processes may be different, which will affect the locality of program memory access. The current prefetcher often analyzes and prefetches specific memory access patterns. Different applications have different memory access patterns, which are suitable for different types of prefetch algorithms. A single, static prefetch algorithm cannot have excellent prefetch results for each memory access pattern. Existing research combines multiple prefetchers together and issues prefetch addresses according to priority order. For example, the Slim-AMPM prefetcher combines the access mapping pattern matching (AMPM) prefetcher with the Delta-correlation-prefetcher-table (DCPT) prefetcher, giving priority to the prefetch addresses issued by the DCPT prefetcher. The AMPM prefetcher learns the memory access mode that the DCPT prefetcher cannot learn and issues prefetch addresses. However, when a process switch occurs, the memory access mode learned by the hardware prefetcher for the previous process may not be applicable to the new process. In particular, concurrent execution makes it more difficult to determine the memory access mode of the program when the process switches repeatedly. Blindly continuing to use the prefetch training results of different processes will generate a large number of redundant prefetches, wasting the bandwidth and power consumption of the processor to access the on-chip cache.

[0018] In order to solve the above technical problems, the embodiment of the present application provides a data prefetching method, device, electronic device and storage medium, the method comprising: obtaining the memory access information of all currently running processes; for any process, according to the memory access information of the process, training the data prefetching algorithm corresponding to the process to obtain a data prefetching algorithm set; when the current cache state of the preset cache meets the preset prefetching condition, obtaining the current memory access request and determining the target process to which the current memory access request belongs; according to the target process, screening the target data prefetching algorithm in the data prefetching algorithm set; based on the target data prefetching algorithm, determining the target data prefetching strategy according to the memory access address information of the current memory access request. The method provided by the above scheme, after obtaining the memory access information of all currently running processes, independently trains the corresponding data prefetching algorithm for each process and forms an algorithm set, and when performing data prefetching, screens the appropriate algorithm from the algorithm set according to the target process to which the current memory access request belongs, thereby improving the accuracy of the data prefetching result and laying a foundation for the utilization rate of the data prefetching resources of the computing device.

[0019] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0020] In conjunction with the specific application environment architecture or the specific hardware architecture on which the execution of the data prefetching method depends, the specific application environment architecture or the specific hardware architecture is described herein.

[0021] First, the structure of the data pre-fetching system on which this application is based is described: The data pre-fetching method, device, electronic device and storage medium provided in the embodiments of the present application are suitable for pre-fetching data for computing devices such as servers. Figure 1 As shown, it is a structural diagram of the data prefetching system based on the embodiment of the present application, which mainly includes a host end, a cache and a data prefetching device. Among them, the host end is used to read business data from the cache, and the data prefetching device is used to pre-train data prefetching algorithms suitable for different processes. When data prefetching is required, a suitable algorithm is selected according to the target process to which the current memory access request belongs, and data prefetching is performed for the cache based on the selected algorithm, so as to cache the business data that the host end needs to read into the cache before the host end accesses the cache.

[0022] The embodiment of the present application provides a data pre-fetching method for pre-fetching service data to be accessed by a host-side process from a main memory to a buffer, so that the host-side can quickly read the service data from the buffer. The execution subject of the embodiment of the present application is an electronic device, such as a server, a desktop computer, a laptop computer, a tablet computer, and other electronic devices that can be used for data pre-fetching.

[0023] like Figure 2 FIG. 1 is a flow chart of a data pre-fetching method provided in an embodiment of the present application, the method comprising: Step 201, obtaining memory access information of all currently running processes.

[0024] It should be noted that multiple applications are deployed on the host side. When an application is started, several processes related to the current business are created and start running. Among them, the memory access information of the process includes at least the memory access address, time and frequency.

[0025] Step 202: for any process, according to the memory access information of the process, train the data prefetching algorithm corresponding to the process to obtain a data prefetching algorithm set.

[0026] Among them, the data prefetching algorithms include block-based prefetcher (BOP), machine learning-based prefetcher (MLOP), spatial prefetcher (SPP), temporal prefetcher (Temporal), spatio-temporal prefetcher (STeMs), access mapping pattern matching prefetcher (AMPM), delta correlation prediction table prefetcher (Delta Correlation Prediction Table Prefetcher) and triage prefetcher (Triage).

[0027] Step 203: when the current cache state of the preset cache satisfies the preset pre-fetch condition, the current memory access request is obtained, and the target process to which the current memory access request belongs is determined.

[0028] Among them, the preset cache is the above-mentioned cache, which is a pre-set high-speed cache area for storing data, used to reduce the delay of the host CPU accessing the memory, and the current memory access request is a memory data access request initiated by the host to the preset cache.

[0029] Specifically, the state of the preset cache can be continuously monitored. When the cache state meets the preset pre-fetch condition, the memory access request at this time is obtained, and it is determined to which process the request belongs, so as to prepare for the subsequent screening of a suitable pre-fetch algorithm.

[0030] Step 204 , according to the target process, select a target data prefetching algorithm from the data prefetching algorithm set.

[0031] Specifically, according to the target process to which the current memory access request belongs, a target data prefetch algorithm suitable for the process can be selected from the previously trained data prefetch algorithm set to ensure the matching degree between the target data prefetch algorithm and the target process and improve the accuracy of the prefetch result.

[0032] Step 205 : Based on the target data pre-fetching algorithm and the memory access address information of the current memory access request, a target data pre-fetching strategy is determined.

[0033] The target data pre-fetching strategy at least includes a data pre-fetching address.

[0034] Specifically, based on the target data prefetch algorithm, the memory access address information of the memory access request to be subsequently initiated by the target process can be predicted according to the memory access address information of the current memory access request to obtain the data prefetch address, and then determine the target data prefetch strategy.

[0035] Based on the above embodiment, as an implementable manner, in one embodiment, for any process, according to the memory access information of the process, a data prefetching algorithm corresponding to the process is trained to obtain a data prefetching algorithm set, including: Step 2021, obtaining an initial algorithm set; Step 2022, for any process, training each initial algorithm in the initial algorithm set according to the memory access information of the process; Step 2023, when the preset training cycle is reached, the data prefetching algorithm corresponding to the process is determined according to the prefetching accuracy of each trained algorithm; Step 2024: construct a data prefetching algorithm set according to the data prefetching algorithm corresponding to each process.

[0036] It should be noted that the embodiments of the present application implement personalized data prefetching algorithm training and selection for different processes, can fully adapt to the differences in memory access modes of different processes, improve the accuracy and efficiency of data prefetching, reduce invalid prefetching, reduce the system's bandwidth occupancy and cache pollution, and thus improve the overall performance of the system, especially in a multi-core and multi-threaded environment, when different processes run concurrently, it can better meet the memory access requirements of each process and improve the system's response speed and throughput.

[0037] Specifically, for each process running in the system, each algorithm in the initial algorithm set is trained using its memory access information. By inputting the memory access information of the process into the algorithm, the algorithm is allowed to learn the memory access mode and rules of the process, so as to adjust the internal parameters of the algorithm so that the algorithm can better adapt to the memory access behavior of the process. When the training reaches this preset training cycle, the prefetch accuracy of each trained algorithm is evaluated. The prefetch accuracy can be measured by comparing the matching degree between the prefetch address predicted by the algorithm and the address actually accessed by the process. The algorithm with the highest prefetch accuracy is selected as the data prefetch algorithm corresponding to the process to ensure that the most accurate prefetch service can be provided for the process in subsequent operation. Finally, the most suitable data prefetch algorithm determined for each process is collected to form a new set, namely, the data prefetch algorithm set. The data prefetch algorithm set contains the optimal prefetch algorithm for all processes. When performing data prefetching later, the corresponding prefetch algorithm can be quickly found from this algorithm set according to the process to which the current memory access request belongs.

[0038] Specifically, in one embodiment, for any process, the memory access rule of the process can be determined based on the memory access address information represented by the memory access information of the process; according to the memory access rule of the process, each initial algorithm in the initial algorithm set is trained to optimize the configuration parameters of each initial algorithm.

[0039] It should be noted that the memory access information of a process covers various data when the process accesses memory, such as memory access address information, etc. The memory access address information records the specific memory address accessed by the process. The memory address accessed by the process generally does not appear randomly, but contains the inherent rules of the process memory access. For example, when processing an array, the process may access the memory address in the order of the array elements, showing a sequential access rule; or when performing matrix operations, the address may be accessed in a jump manner according to a specific step size.

[0040] Specifically, after the memory access rules of the process are determined, these rules are applied to the training process of the initial algorithm, and the configuration parameters of the algorithm are adjusted so that the algorithm can better adapt to the memory access mode of the process.

[0041] Specifically, in one embodiment, during the training of each initial algorithm in the initial algorithm set, the actual memory access address of the process can be obtained; when the preset training cycle is reached, the training prefetch results of each trained algorithm are obtained; for any trained algorithm, the prefetch accuracy of the trained algorithm is determined based on the difference between the training prefetch result of the trained algorithm and the actual memory access address of the process; the trained algorithm whose prefetch accuracy reaches a preset threshold is used as a candidate algorithm; the candidate algorithm with the highest prefetch accuracy is used as the data prefetch algorithm corresponding to the process.

[0042] Among them, the actual memory access address reflects the real data access requirements of the process.

[0043] Specifically, for each trained algorithm, the prefetch accuracy of the algorithm is determined by comparing the difference between its training prefetch result and the actual memory access address of the process. The trained algorithm will generate multiple data prefetch addresses during the training process, and the prefetch accuracy of the algorithm is determined by comparing the number of matches between these data prefetch addresses and the actual memory access addresses, that is, according to how many data prefetch addresses match (are consistent) with the actual memory access addresses. After determining the prefetch accuracy of multiple trained algorithms, the trained algorithms whose prefetch accuracy reaches a preset threshold are selected as the candidate algorithms, and the one with the highest prefetch accuracy is selected from the candidate algorithms as the data prefetch algorithm corresponding to the process, that is, the data prefetch algorithm of the process is the trained algorithm whose prefetch accuracy reaches the preset threshold and has the highest prefetch accuracy.

[0044] Specifically, in one embodiment, for any process, if all the trained algorithms of the process have been trained for multiple rounds of preset training cycles and the pre-fetching accuracy still does not reach the preset threshold, the process will be regarded as an abandoned process; and the training of the data pre-fetching algorithm of the abandoned process will be abandoned.

[0045] Specifically, during the training of the data prefetching algorithm, the system uses each algorithm in the initial algorithm set for training each process, and evaluates the prefetching accuracy of the trained algorithm when the preset training cycle is reached. When the prefetching accuracy of all the trained algorithms of a process cannot reach the preset threshold even after multiple rounds of training for the preset training cycle, it means that these algorithms are difficult to adapt to the memory access mode of the process, and it is difficult to achieve the desired effect by continuing to train these algorithms. In this case, the process is marked as an abandoned process, and the training of its data prefetching algorithm is stopped, so that computing resources and time will no longer be invested in trying to optimize the prefetching algorithm for the process, which reduces unnecessary training rounds and computing power, allowing the system to complete the training and optimization of data prefetching algorithms for other processes more quickly, and speeding up the construction process of the entire prefetching algorithm set.

[0046] Accordingly, in one embodiment, if the pre-fetching accuracy of a trained algorithm reaches a preset threshold after a short period of training, the training of the algorithm can be terminated, thereby reducing the training cycle of the algorithm.

[0047] Specifically, in one embodiment, when any process enters a preset interrupt state, the process is treated as an interrupt process; the training of the interrupt process is suspended, and the post-trained algorithm set of the interrupt process and the training pre-fetch results generated by each post-trained algorithm in the post-trained algorithm set during the training process are packaged and processed to obtain a training interrupt data packet of the interrupt process; the training interrupt data packet is stored in a preset temporary storage area (process temporary storage area); when any interrupt process enters a preset active state, the training interrupt data packet corresponding to the interrupt process is extracted from the preset temporary storage area; based on the training interrupt data packet, the training of the post-trained algorithm set of the interrupt process continues.

[0048] It should be noted that a process includes multiple states, such as a ready state, a running state, a blocked state, and a completed state, etc. In the embodiment of the present application, a process that enters a completed state (preset interrupt state) can be regarded as an interrupt process. When a process enters a preset interrupt state, the process terminates and the system reclaims the resources occupied by the process.

[0049] Among them, Figure 3As shown, it is a structural schematic diagram of an exemplary data prefetching system provided by an embodiment of the present application. The data prefetching system includes a memory management unit (MMU) and a multi-level cache (preset cache). The memory management unit includes a page table address space and a prefetching configuration unit. A prefetching algorithm unit, a prefetching training unit, a process temporary storage unit and a prefetching emission unit are arranged between the memory management unit and the multi-level cache. Among them, the prefetching algorithm unit is an integrated unit of each data prefetching algorithm, which is used to generate a data prefetching strategy; the prefetching training unit is used to train the initial algorithm in the prefetching algorithm unit according to the memory access information of the process. The prefetch transmission unit is used to send the prefetch instructions corresponding to the data prefetch strategy to the multi-level cache after the algorithm is trained and the data prefetch strategy is determined, so as to obtain the data that may be accessed by the process in advance, thereby improving the access efficiency of the system. The prefetch transmission unit is also used to monitor the cache status and adjust the prefetch degree, and send a request to the multi-level cache according to the received prefetch address; the process temporary storage unit includes two parts: the memory management unit and the lower-level cache (process temporary storage area) in the multi-level cache, which is used to temporarily store unfinished processes (training interruption data packets of interrupted processes), and set up a separate completion space to record the status of completed processes (interrupted processes) for subsequent rapid training; the page table address space is used to convert the page table base address and running status into a virtual page table address; the prefetch configuration unit is used to configure the parameters and rules related to prefetching, such as recording the process information of completed (interrupted process) and not prefetched (abandoned process) and the initial configuration information of the prefetch training unit for the new page table base address. Among them, when any interrupt process enters the preset active state, the initial configuration information of its data prefetching algorithm is determined according to the training interrupt data packet of the interrupt process, so as to continue to train the post-training algorithm set of the interrupt process based on the training interrupt data packet to improve the training efficiency of the algorithm.

[0050] Specifically, in one embodiment, when any process becomes a completed process or a process to be replaced, it is determined that the process enters a preset interrupt state.

[0051] When a new process is generated and the number of parallel processes reaches a preset parallel threshold, the least used process among the original processes is used as the process to be replaced.

[0052] Specifically, when a new process is generated and the number of processes currently running in parallel has reached a preset parallel threshold, which is the maximum number of processes that can run in parallel at the same time set by the system, the system makes a decision to select one from the original processes for replacement to make room for the new process to run. Specifically, the least used process among the original processes can be selected as the process to be replaced to avoid excessive competition for system resources, so that system resources can be more reasonably allocated to each valuable process, thereby improving the overall operation efficiency of the system.

[0053] Specifically, in one embodiment, the page table base address of the interrupt process is obtained in a preset page table base address register; the page table base address is converted into a virtual page table address; wherein the address length of the virtual page table address is less than the address length of the page table base address; the virtual page table address is added to the training interrupt data packet; when the virtual page table address of the new process matches the virtual page table address of any interrupt process, it is determined that the interrupt process enters a preset active state.

[0054] It should be noted that in the computing device operating system, each process has its own page table, which is used to realize the conversion from virtual address to physical address. The page table base address register is a register specifically used to store the process page table base address. When the process enters the preset interrupt state, the system obtains the page table base address of the interrupt process from the pre-set page table base address register. Since the page table base address is long and contains more information, in order to facilitate subsequent processing and storage, the page table base address is converted into a virtual page table address to reduce the amount of data and improve processing efficiency. It is also convenient for storage and transmission in the training interrupt data packet.

[0055] Among them, multi-core and multi-threading may lead to many concurrent processes, and each process may use several page table base addresses. Recording a large number of page table base addresses, operating status and corresponding information on the chip requires a large amount of storage resources. Therefore, the embodiment of the present application sets up a separate page table address space. By introducing an additional level of indirection, any relevant page table base address is converted into a continuous address (virtual page table address) in a new structure that is only visible to the data prefetch device, so that the page table base address can appear in sequence and reduce the bit width, thereby reducing the storage space.

[0056] Specifically, when a new process is generated, the virtual page table address of the new process is compared with the virtual page table address of the previous interrupt process in the training interrupt data packet. If it is found that the virtual page table address of the new process matches the virtual page table address of a certain interrupt process, this means that the new process has a certain correlation with the interrupt process in memory access mode or resource usage, or the new process is a restarted interrupt process. At this time, it is determined that the interrupt process enters the preset active state.

[0057] Based on the above embodiment, as an implementable manner, in one embodiment, the method further includes: Step 301: when a cache hit rate represented by a current cache state of a preset cache is lower than a preset hit rate threshold, it is determined that the current cache state of the preset cache satisfies a preset pre-fetch condition.

[0058] It should be noted that the cache hit rate refers to the ratio of the number of successful data accesses in the preset cache to the total number of data accesses, which reflects the effective utilization of the cache. The preset hit rate threshold is a standard value set according to system performance requirements and expectations. For example, assuming that the preset hit rate threshold is set to 80%, this means that the system expects that, ideally, 80% of data accesses can be obtained directly from the cache without accessing the slower main memory.

[0059] Specifically, when the cache hit rate represented by the current cache state of the preset cache is lower than the preset hit rate threshold, it means that the preset cache fails to effectively meet the data access requirements, and a large amount of data access needs to be obtained from the main memory, resulting in increased access delay and affecting system performance. At this time, the system determines that the current cache state meets the preset pre-fetch condition, that is, it is necessary to start the data pre-fetch operation to replace the original data in the preset cache to improve the cache hit rate.

[0060] Accordingly, in one embodiment, when the remaining cache space represented by the current cache state of the preset cache is not less than a preset remaining cache space threshold, it is determined that the current cache state of the preset cache satisfies the preset pre-fetching condition.

[0061] It should be noted that the preset remaining cache space is not less than the preset remaining cache space threshold, which indicates that the preset cache has sufficient free space to store the pre-fetched data. Therefore, when the current cache state of the preset cache meets the preset pre-fetch condition, data pre-fetching operation is performed in this case. It will not cause the new pre-fetched data to be unable to be stored due to insufficient cache space, nor will cache replacement be frequently triggered due to tight cache space, thereby ensuring the stability and performance of the preset cache.

[0062] Accordingly, in one embodiment, when the current cache state of the preset cache indicates that the current memory access request misses the cache, it is determined that the current cache state of the preset cache satisfies the preset pre-fetch condition.

[0063] It should be noted that if the current memory access request misses the cache, it means that a memory access miss occurs in the preset cache. If the current memory access request misses, it also means that subsequent related data may not be in the cache. If no prefetch measures are taken, subsequent memory accesses may still face high latency problems. Therefore, it is determined that the current cache status meets the preset prefetch conditions to perform data anticipation, making subsequent memory access requests more likely to hit the cache, thereby effectively reducing access latency and improving overall system performance.

[0064] Based on the above embodiment, as an implementable manner, in one embodiment, obtaining a current memory access request and determining a target process to which the current memory access request belongs includes: Step 2031, after obtaining the current memory access request, analyzing the current memory access request to determine the page table base address of the current memory access request; Step 2032, determining the target process to which the current memory access request belongs according to the page table base address.

[0065] It should be noted that in the operating system, each process has an independent page table. The page table base address is a unique identifier and is the key information of a process page table. After obtaining the current memory access request, the page table base address corresponding to the current memory access request can be obtained from the page table base address register. Through the page table base address, the corresponding page table can be found, and this page table belongs to a specific process. After obtaining the page table base address of the current memory access request, the target process corresponding to the page table base address can be found according to the mapping relationship between the page table and the process, that is, the target process to which the current memory access request belongs can be determined.

[0066] Based on the above embodiment, as an implementable manner, in one embodiment, before determining the target data prefetching strategy based on the target data prefetching algorithm and according to the memory access address information of the current memory access request, the method further includes: Step 401 : determining the prefetching degree of the target data prefetching algorithm according to the cache hit rate and the cache replacement rate represented by the current cache state of the preset cache.

[0067] Among them, the target data prefetching algorithm is negatively correlated with both the cache hit rate and the cache replacement rate. The prefetching degree refers to the amount of data prefetched by the target data prefetching algorithm in one prefetching operation. The higher the prefetching degree, the larger the amount of prefetched data; the lower the prefetching degree, the smaller the amount of prefetched data.

[0068] It should be noted that the cache hit rate represents the ratio of the number of times a process successfully obtains data from the preset cache to the total number of data accesses. The higher the cache hit rate, the higher the cache utilization efficiency. The cache replacement rate represents the frequency with which data in the preset cache is replaced per unit time. A higher cache replacement rate means that the data in the preset cache is updated frequently.

[0069] Specifically, when the cache hit rate is high, it means that the current cache is well utilized. At this time, the prefetching degree of the target data prefetching algorithm can be appropriately reduced to reduce unnecessary prefetching operations and avoid wasting system resources. On the contrary, when the cache hit rate is low, it means that there is insufficient data in the cache, and it is necessary to increase the prefetching degree and prefetch more data into the cache to improve the hit rate of subsequent data access. For the cache replacement rate, when the cache replacement rate is high, it means that the data in the cache is frequently updated and there is excessive prefetching. At this time, the prefetching degree should be reduced, the amount of prefetched data should be reduced, and the pressure of frequent replacement of data in the cache should be reduced. When the cache replacement rate is low, the prefetching degree can be appropriately increased and the amount of prefetched data can be increased to make full use of the cache space and improve data access efficiency.

[0070] Based on the above embodiment, as an implementable manner, in one embodiment, based on the target data prefetching algorithm, according to the memory access address information of the current memory access request, the target data prefetching strategy is determined, including: Step 2051, based on the target data prefetch algorithm, according to the memory access address information of the current memory access request, determine a plurality of data prefetch addresses at different look-ahead degrees; Step 2052: determine a target data prefetch strategy according to a plurality of data prefetch addresses at different degrees of foresight.

[0071] The target data prefetch strategy includes at least a plurality of data prefetch addresses under different degrees of foresight and the order in which the data prefetch addresses are issued. The foresight degree indicates the degree of prediction or advance amount of future data access. For example, if the foresight degree is 10, it means that the currently predicted data prefetch address is the memory access address that the host may initiate access to within the next 10 clock cycles, and so on.

[0072] For example, Figure 4 As shown, it is a flow chart of an exemplary data prefetching method provided by an embodiment of the present application. In the case of a memory access request with a cache miss, it is first determined whether the page table address space records the page table base address of the process to which the current memory access request belongs. If not, it is determined that the process is a new process. At this time, the least used entry (process to be replaced) is replaced to the process temporary storage area, and then the software configuration information corresponding to the process is imported. The software configuration information includes memory access address information to characterize the key contents such as the memory access mode of the process for subsequent simulation prefetch operations. If it exists, it is further determined whether the process is in the prefetch training unit. If not, it is determined that the process has previously suspended training as an interrupt process, so the training interrupt data packet is extracted in the process temporary storage area to determine the data prefetch address; if it exists, the previously determined data prefetch address is directly obtained in the prefetch training unit. After obtaining the data prefetch address, the prefetch accuracy is determined by comparing the difference between the training prefetch result (data prefetch address) and the actual memory access address of the process. When it is determined that the prefetch accuracy reaches the preset threshold, different degrees of foresight are adopted to issue prefetch instructions to multiple levels of cache at the same time to obtain data into the cache in advance, so as to improve the efficiency of subsequent data access.

[0073] Among them, when the corresponding process ends, the prefetch training unit will send the page table base address and the selected prefetch result and hit situation to the completion table, and increase or decrease the score of the corresponding prefetch algorithm in the initial configuration register according to the situation, that is, continue to evaluate and maintain the score table, and the initial configuration register can also be adjusted by assigning values ​​to the register through software, and increase the software recommended instructions to adjust the accelerated prefetch algorithm. Among them, the score of the prefetch algorithm is positively correlated with its prefetch accuracy. That is, the method provided in the embodiment of the present application supports the regulation of the prefetcher by software, and the software configuration port is set in the initial configuration register. Because the software layer has a better grasp of the characteristics of the memory access flow, in some cases, the memory access characteristics of the instruction flow can be obtained in advance, so the prefetcher can be configured accordingly, reducing the training cycle and the number of initial hits, thereby quickly prefetching and reducing useless losses.

[0074] Specifically, in one embodiment, data prefetch addresses at multiple different look-ahead levels may be sent to a high-level cache or a low-level cache according to a target data prefetch strategy and a process priority of a current memory access request; Among them, the preset cache is divided into two parts: high-level cache and low-level cache. Specifically, the transmitter can send the prefetch results (target data prefetch strategy) of frequently used processes to the high-level cache (high-level cache) and the less frequently used processes to the low-level cache (bottom-level cache) according to the information in the process temporary storage area and the prefetch training unit, and adjust the prefetch degree accordingly according to the cache hit situation fed back by the monitor. Among them, the more frequently used process, the higher the process priority. Among them, the high-level cache is closer to the host CPU, the data transmission path is short, the access speed is faster, and it can respond to the data request of the host in a very short time; the bottom-level cache is far away from the host CPU, the data transmission time is long, and the access speed is relatively slow, but the cache capacity of the bottom-level cache is larger than the cache capacity of the high-level cache.

[0075] For example, Figure 5As shown, it is a structural schematic diagram of another exemplary data prefetch system provided by an embodiment of the present application, and the prefetch training unit includes sub-units with different degrees of foresight, and each sub-unit includes an address selector, a threshold checker, a prefetch register stack and a status register. Among them, the address selector is used to select the data prefetch address with the best comprehensive accuracy and hit number to send; the threshold checker is used to check whether the relevant parameters reach the preset threshold to determine the rationality of the prefetch operation; the prefetch register stack contains the same number of prefetch registers as the number of algorithms in the prefetch algorithm unit, which are used to record the virtual page table address, prefetch information, and simulated prefetch hits, etc.; the status register records the status information during the prefetch training process, and two counters are set in the status register, one for recording the number of unused times and the other for recording the training cycle. Sub-modules with different degrees of foresight can achieve different degrees of forward-looking prefetch training to adapt to different memory access modes. The prefetch configuration unit includes an untrained queue, a completion table and an initial configuration register. Among them, the untrained queue is used to cache abandoned processes, and the completion table is used to cache interrupted processes. When the same page table base address as the interrupted process is encountered again, the training cycle and the initial hit number are configured accordingly in the initial configuration register to reduce the training cycle of the process. The replacement register is used to replace the process. When the number of parallel page table base addresses is too large to cause insufficient entries in the pre-fetch training unit, the replacement register replaces the least used process to the process temporary storage area according to the unused counter information, and records the correspondence between the virtual page table address and the unit storage address (predicted data pre-fetch address) for subsequent retrieval. The process temporary storage area is configured in the underlying cache of the preset cache so that it has a larger storage space. When the replacement process is used, it is replaced in the pre-fetch training unit.

[0076] Specifically, in one embodiment, the memory access delay of the data prefetch address in the preset cache is obtained; when the memory access delay of the data prefetch address reaches the preset delay condition, the target data prefetch algorithm is updated to replace the target data prefetch algorithm corresponding to the target process to which the current memory access request belongs.

[0077] It should be noted that memory access latency refers to the time from issuing a request to access the data prefetch address to actually obtaining the corresponding data. A large memory access latency means that the expected data address is predicted late, and the host has already initiated a memory access request, but the prefetched data has not yet been successfully prefetched.

[0078] Specifically, when the memory access delay of the data prefetch address reaches the preset delay condition, it indicates that the current target data prefetch algorithm cannot meet the data access requirements well. At this time, the target data prefetch algorithm corresponding to the target process to which the current memory access request belongs can be replaced. Since different prefetch algorithms are suitable for different memory access modes, the algorithm with the second highest prefetch accuracy among the candidate algorithms of the target process can be used as the target data prefetch algorithm. By replacing the algorithm, it is possible to find a prefetch strategy that is more suitable for the memory access characteristics of the current process, thereby reducing the memory access delay and improving the data access efficiency.

[0079] Among them, Figure 6 As shown, it is a structural schematic diagram of the pre-fetch transmission unit provided by an embodiment of the present application, and the pre-fetch transmission unit includes a cache monitor, a pre-fetch degree controller, a pre-fetch address buffer, a transmitter and a transmitted sequence. The data pre-fetch address and related information sent in the pre-fetch training unit are first temporarily stored in the pre-fetch address buffer, and then extracted according to the pre-fetch degree sent by the pre-fetch degree controller, and sent to the transmitter according to the forward-looking degree. The transmitter sends the pre-fetch address of the ongoing process to the high-level cache, the pre-fetch address of the process that has not been carried out for a long time to the low-level cache, and stores the sent pre-fetch address in the transmitted queue. The cache monitor set monitors the hit rate and replacement rate of the cache and feeds back the situation to the pre-fetch degree controller, and the pre-fetch degree controller adaptively adjusts the pre-fetch degree according to the set threshold. The data recorded in the transmitted sequence will be sent to the pre-fetch address buffer and the corresponding flag bit will be set, and the repeated requests for pre-fetch results of different forward-looking will be filtered in the transmitter. At the same time, cache monitoring will also check whether the subsequent memory access request corresponding to the prefetch address has been executed. For delayed memory access requests, the corresponding counter will be increased by 1. When the value is reached, it is determined that the request issued by the prefetcher is generally a delayed request, that is, the memory access delay of the data prefetch address reaches the preset delay condition, and the second best prefetcher is used (the algorithm with the second highest prefetch accuracy in the target process's selected algorithms is used as the target data prefetch algorithm) for subsequent processing, and so on.

[0080] The data prefetching method provided by the embodiment of the present application obtains the memory access information of all currently running processes; for any process, according to the memory access information of the process, trains the data prefetching algorithm corresponding to the process to obtain a data prefetching algorithm set; when the current cache state of the preset cache meets the preset prefetching condition, obtains the current memory access request and determines the target process to which the current memory access request belongs; according to the target process, screens the target data prefetching algorithm in the data prefetching algorithm set; based on the target data prefetching algorithm, determines the target data prefetching strategy according to the memory access address information of the current memory access request. The method provided by the above scheme, after obtaining the memory access information of all currently running processes, independently trains the corresponding data prefetching algorithm for each process and forms an algorithm set, and when performing data prefetching, screens the appropriate algorithm from the algorithm set according to the target process to which the current memory access request belongs, thereby improving the accuracy of the data prefetching result and laying a foundation for the utilization rate of the data prefetching resources of the computing device. In addition, the page table base address is used to distinguish the processes, and prefetching is performed based on the memory access characteristics of the same process, so as to avoid the destruction of the program memory access locality by the complex computing environment under multi-core and multi-threading. The virtual-to-real conversion of page table addresses is used to reduce the storage space occupied by multiple internal tables, so that it can be implemented in the limited space on the chip. The initial situation is configured using software and completed information, and processes that cannot effectively identify memory access patterns are eliminated, which is conducive to speeding up prefetch training and providing more prefetch opportunities. Filtering delayed and low-precision prefetch requests avoids excessive additional costs for bandwidth and alleviates the problem of limited storage bandwidth of shared caches. Multiple prefetch requests are issued to different levels of cache based on different foresights and process usage frequencies, making full use of prefetch opportunities, increasing the probability of subsequent accesses finding prefetched data in the cache, and improving memory access performance.

[0081] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method.

[0082] The embodiments of the present application also provide a data pre-fetching device for executing the data pre-fetching method provided in the above embodiments.

[0083] like Figure 7 , which is a schematic diagram of the structure of a data pre-fetching device provided in an embodiment of the present application. The data pre-fetching device 70 comprises: an acquisition module 701 , a training module 702 , a determination module 703 , a screening module 704 and a pre-fetching module 705 .

[0084] Among them, the acquisition module is used to obtain the memory access information of all currently running processes; the training module is used to train the data prefetch algorithm corresponding to any process according to the memory access information of the process to obtain a data prefetch algorithm set; the determination module is used to obtain the current memory access request and determine the target process to which the current memory access request belongs when the current cache state of the preset cache meets the preset prefetch condition; the screening module is used to screen the target data prefetch algorithm in the data prefetch algorithm set according to the target process; the prefetch module is used to determine the target data prefetch strategy based on the target data prefetch algorithm and the memory access address information of the current memory access request.

[0085] The description of the features in the embodiment corresponding to the data pre-fetching device can refer to the relevant description of the embodiment corresponding to the data pre-fetching method, which will not be repeated here.

[0086] The embodiment of the present application also provides an electronic device, such as Figure 8 As shown, it is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application, including a processor 10 and a memory 20, in which a computer program is stored, and the processor 10 is configured to run the computer program to execute the steps in any of the above-mentioned data pre-fetching method embodiments.

[0087] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above-mentioned data prefetching method embodiments when running.

[0088] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0089] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any of the above data prefetching method embodiments are implemented.

[0090] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above-mentioned data prefetching method embodiments are implemented.

[0091] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0092] The above is a detailed introduction to a data pre-fetching method, device, electronic device and storage medium provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A data pre-fetching method, characterized in that: include: Get the memory access information of all currently running processes; For any of the processes, according to the memory access information of the process, a data prefetching algorithm corresponding to the process is trained to obtain a data prefetching algorithm set; When the current cache state of the preset cache meets the preset pre-fetch condition, obtaining the current memory access request, and determining the target process to which the current memory access request belongs; According to the target process, a target data prefetching algorithm is selected from the data prefetching algorithm set; Based on the target data pre-fetching algorithm, a target data pre-fetching strategy is determined according to the memory access address information of the current memory access request.

2. The data pre-fetching method according to claim 1, characterized in that: The step of training a data prefetching algorithm corresponding to any of the processes according to the memory access information of the process to obtain a data prefetching algorithm set includes: Get the initial algorithm set; For any of the processes, training each initial algorithm in the initial algorithm set according to the memory access information of the process; When the preset training cycle is reached, the data prefetching algorithm corresponding to the process is determined according to the prefetching accuracy of each trained algorithm; According to the data prefetching algorithm corresponding to each process, a data prefetching algorithm set is constructed.

3. The data pre-fetching method according to claim 2, characterized in that: The step of training each initial algorithm in the initial algorithm set according to the memory access information of any of the processes comprises: For any of the processes, determining a memory access rule of the process according to memory access address information represented by memory access information of the process; According to the memory access rule of the process, each initial algorithm in the initial algorithm set is trained to optimize the configuration parameters of each initial algorithm.

4. The data pre-fetching method according to claim 2, characterized in that: When the preset training cycle is reached, the data prefetching algorithm corresponding to the process is determined according to the prefetching accuracy of each trained algorithm, including: In the process of training each initial algorithm in the initial algorithm set, obtaining the actual memory access address of the process; When the preset training cycle is reached, the training pre-fetch results of each post-training algorithm are obtained; For any of the trained algorithms, determining the prefetch accuracy of the trained algorithm according to a difference between a training prefetch result of the trained algorithm and an actual memory access address of the process; The trained algorithm whose pre-fetching accuracy reaches a preset threshold is used as a candidate algorithm; The selected algorithm with the highest pre-fetching accuracy is used as the data pre-fetching algorithm corresponding to the process.

5. The data pre-fetching method according to claim 4, characterized in that: The method further comprises: For any of the processes, if all trained algorithms of the process have been trained for multiple rounds of preset training cycles and the pre-fetching accuracy still does not reach the preset threshold, the process is regarded as an abandoned process; Abandoning the training of the data prefetch algorithm of the abandoned process.

6. The data pre-fetching method according to claim 4, characterized in that: The method further comprises: When any of the processes enters a preset interrupt state, the process is treated as an interrupt process; The training of the interruption process is suspended, and the training algorithm set of the interruption process and the training pre-fetch results generated by each post-trained algorithm in the training algorithm set during the training process are packaged and processed to obtain a training interruption data packet of the interruption process; Storing the training interruption data packet in a preset temporary storage area; When any of the interruption processes enters a preset active state, extracting a training interruption data packet corresponding to the interruption process in the preset temporary storage area; Based on the training interruption data packet, continue to train the post-training algorithm set of the interruption process.

7. The data pre-fetching method according to claim 6, characterized in that: The method further comprises: When any of the processes becomes a completed process or a process to be replaced, determining that the process enters a preset interrupt state; When a new process is generated and the number of parallel processes reaches a preset parallel threshold, the least used process among the original processes is used as the process to be replaced.

8. The data pre-fetching method according to claim 7, characterized in that: The method further comprises: Obtaining a page table base address of the interrupt process in a preset page table base address register; Converting the page table base address into a virtual page table address; wherein the address length of the virtual page table address is smaller than the address length of the page table base address; Adding the virtual page table address to the training interrupt data packet; When the virtual page table address of the new process matches the virtual page table address of any of the interrupted processes, it is determined that the interrupted process enters a preset active state.

9. The data pre-fetching method according to claim 1, characterized in that: The method further comprises: When the cache hit rate represented by the current cache state of the preset cache is lower than a preset hit rate threshold, it is determined that the current cache state of the preset cache meets the preset pre-fetch condition.

10. The data pre-fetching method according to claim 1, characterized in that: The method further comprises: When the remaining cache space represented by the current cache state of the preset cache is not less than a preset remaining cache space threshold, it is determined that the current cache state of the preset cache meets the preset pre-fetch condition.

11. The data pre-fetching method according to claim 1, characterized in that: The method further comprises: When the current cache state of the preset cache indicates that the current memory access request misses the cache, it is determined that the current cache state of the preset cache meets the preset pre-fetch condition.

12. The data pre-fetching method according to claim 1, characterized in that: The obtaining of the current memory access request and determining the target process to which the current memory access request belongs includes: After obtaining the current memory access request, analyzing the current memory access request to determine a page table base address of the current memory access request; The target process to which the current memory access request belongs is determined according to the page table base address.

13. The data pre-fetching method according to claim 1, characterized in that: Before determining the target data prefetching strategy based on the target data prefetching algorithm and according to the memory access address information of the current memory access request, the method further includes: Determining the prefetching degree of the target data prefetching algorithm according to a cache hit rate and a cache replacement rate represented by a current cache state of the preset cache; The target data pre-fetching algorithm is negatively correlated with both the cache hit rate and the cache replacement rate.

14. The data pre-fetching method according to claim 1, characterized in that: The method of determining a target data prefetching strategy based on the target data prefetching algorithm and according to the memory access address information of the current memory access request includes: Based on the target data prefetch algorithm, and according to the memory access address information of the current memory access request, determining a plurality of data prefetch addresses at different degrees of foresight; Determining a target data prefetching strategy according to the data prefetching addresses at the plurality of different foresight levels; The target data pre-fetching strategy at least includes the data pre-fetching addresses at the multiple different foresight levels and the sending order of the data pre-fetching addresses.

15. The data pre-fetching method according to claim 14, characterized in that: The method further comprises: According to the target data prefetching strategy and the process priority of the current memory access request, the data prefetching addresses at the multiple different look-ahead degrees are sent to the high-level cache or the low-level cache; The preset cache is divided into two parts: a high-level cache and a low-level cache.

16. The data pre-fetching method according to claim 15, characterized in that: The method further comprises: Obtaining a memory access delay of a data prefetch address in the preset cache; When the memory access delay of the data prefetch address reaches a preset delay condition, the target data prefetch algorithm is updated to replace the target data prefetch algorithm corresponding to the target process to which the current memory access request belongs.

17. A data pre-fetching device, characterized in that: include: The acquisition module is used to obtain the memory access information of all currently running processes; A training module, used for training a data prefetching algorithm corresponding to any of the processes according to the memory access information of the process, so as to obtain a data prefetching algorithm set; A determination module, configured to obtain a current memory access request and determine a target process to which the current memory access request belongs when a current cache state of the preset cache satisfies a preset pre-fetch condition; A screening module, used for screening a target data prefetching algorithm in the data prefetching algorithm set according to the target process; The pre-fetch module is used to determine a target data pre-fetch strategy based on the target data pre-fetch algorithm and according to the memory access address information of the current memory access request.

18. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the data prefetching method according to any one of claims 1 to 16 when executing the computer program.

19. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the data pre-fetching method according to any one of claims 1 to 16.

20. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the data pre-fetching method according to any one of claims 1 to 16 are implemented.

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