Memory management method and memory management device

Abstract

The invention provides a memory management method and a memory management device. According to the method, an abnormal hot page can be replaced by a non-abnormal cold page or a non-abnormal free page, so that the access frequency of an abnormal memory is reduced, and the memory performance is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of Internet technology, and in particular to a memory management method and a memory management device. Background Art

[0002] At present, the memory of the device may be abnormal, and the existing technology still frequently accesses the abnormal memory, thereby causing a correctable error (CE) storm. In addition, frequent access to the abnormal memory can also trigger an uncorrectable error (UCE) in the memory. This will cause a decrease in memory performance and reduce business performance. Summary of the invention

[0003] The present application provides a memory management method and a memory management device, which can reduce the frequency of access to abnormal memory and improve memory performance and business performance.

[0004] In a possible implementation, an embodiment of the present application provides a memory management method. The method includes: determining a first memory page that is a hot page and an abnormal memory page, wherein the abnormal memory page is used to indicate a memory page that cannot be normally accessed by the mapped physical memory; replacing the second memory resource in the second memory page with the first memory resource in the first memory page, wherein the second physical memory mapped by the second memory page can be normally accessed; updating the second memory page to a hot page; updating the first memory page to a cold page or a free page; mapping the memory resource access range allocated to the application (for example, a memory page in user mode allocated to the application) to the second physical memory.

[0005] Among them, memory pages that are frequently accessed or recently frequently accessed are called hot pages. These memory pages generally contain recently or frequently executed code segments or frequently used data.

[0006] Abnormal memory page, which means the memory page that the mapped physical memory cannot access normally. In some scenarios, CE may be generated when accessing the physical memory mapped by the memory page. In other words, CE is generated when the CPU accesses the physical address of the physical memory mapped by the memory page. There is a memory error at the physical address.

[0007] The memory resources in the memory page (eg, the resources stored in the physical memory mapped by the memory page) may be data resources or code resources, which are not limited here.

[0008] The second memory page is also described as a non-abnormal memory page (or non-abnormal page). In some scenarios, memory pages can be divided into two categories, one is an abnormal memory page and the other is a non-abnormal memory page. Among them, no CE is generated when accessing the physical memory mapped by the non-abnormal memory page. In other words, there is no memory error in the physical address of the physical memory mapped by the non-abnormal memory page.

[0009] Taking the operating system (OS) to execute the method of the present application as an example, when the OS determines that there are abnormal memory pages in the hot pages, it means that the memory pages that need to be frequently accessed will have CE when accessed. When the CE triggered multiple times cannot be corrected, a CE storm may occur; in addition, the inability to correct CE may also cause UCE of the memory. Both scenarios will cause a decrease in memory performance and reduce business performance.

[0010] In an embodiment of the present application, when the OS determines that a frequently accessed hot page has an abnormality (i.e., determines the first memory page), the memory resources of the non-abnormal memory page (the second memory page) can be replaced with the memory resources in the abnormal hot page (the above-mentioned first memory page), and the second memory page can be updated to a hot page. In this way, the code or data (an example of a memory resource) that needs to be frequently accessed is replaced from the abnormal first memory page to the non-abnormal second memory page, and the second memory page is set as a hot page (for example, added to a hot page address list), so that the first memory resource frequently accessed by the application is stored in the second physical memory indicated by the non-abnormal second memory page. Then, when the second memory page is frequently accessed, there will not be a high error frequency as when the first memory page is frequently accessed, thereby reducing the frequency of access to the abnormal memory page and avoiding the generation of CE storms or memory UCEs, thereby improving memory performance, improving business performance, and ensuring the normal operation of the application.

[0011] Among them, regarding the replacement process of the abnormal hot page (the first memory page) and other memory pages, the OS can replace the abnormal hot page with an idle page or a cold page by replacing the two memory pages. For example, the memory resources in the abnormal hot page are replaced with a non-abnormal cold page or a non-abnormal idle page to achieve the effect of reducing the access frequency to the abnormal memory page.

[0012] Alternatively, the OS may also replace memory resources on more than two memory pages to replace the abnormal hot page with an idle page or a cold page. For example, the memory resources in the abnormal hot page are replaced with the non-abnormal cold page, the memory resources originally stored in the non-abnormal cold page are replaced with the non-abnormal idle page, the abnormal hot page is updated from a hot page to an idle page, the non-abnormal cold page is updated from a cold page to a hot page, and the abnormal hot page is updated to an abnormal idle page. In this way, the abnormal hot page is updated from a hot page to an idle page through two data replacements, which can also achieve the effect of reducing the access frequency to the abnormal memory page.

[0013] To ensure that the physical memory accessed by the application is memory that can be accessed normally, the OS can map the memory resource access range (user-mode memory pages) allocated to the application to a second physical memory without abnormalities to correctly access the memory resources required by the application.

[0014] In this embodiment, through the hot page list and cold page list (or free page list) in the kernel state managed by the OS, abnormal hot pages can be replaced with non-abnormal cold pages or free pages to reduce the frequency of access to abnormal memory pages, thereby improving memory performance and business performance.

[0015] In one possible implementation, determining the first memory page that is a hot page includes: obtaining a first physical access range, wherein the physical memory within the first physical access range cannot be accessed normally; determining a page address list of the abnormal memory pages corresponding to the first physical access range; and determining the first memory page that is a hot page in the abnormal memory pages based on the page address list.

[0016] Taking OS as an example, the first physical access range obtained by OS is also expressed as an abnormal physical address list, and the physical addresses in the list are physical addresses of physical memory, and the physical memory is the physical memory that generates CE and cannot be accessed normally.

[0017] There is no limitation on the way in which the OS obtains the first physical access range, and the OS may obtain the first physical access range from BIOS, BMC, or an external device.

[0018] The OS may convert the physical address of the physical memory into the page address of the memory page in the kernel state, thereby converting each physical address in the first physical access range to obtain a page address list of abnormal memory pages.

[0019] In the above implementation, the OS may determine which memory page or pages in the hot pages are the abnormal memory pages (the first memory page here) based on the page address list of the abnormal memory page maintained by the OS.

[0020] In this embodiment, the method can convert the physical address of the memory into a logical address through the first physical access range that the physical memory cannot access normally, so as to obtain a page address list of abnormal memory pages, so that the OS can classify the kernel-state memory pages it manages into abnormal memory pages and non-abnormal memory pages, so as to reduce the access frequency to abnormal memory pages and improve memory performance.

[0021] In some embodiments, the method may update the locally maintained page address list according to the first physical access range obtained each time, so that the page address list can be synchronized with the CE information.

[0022] In some embodiments, the method may determine the first memory page that is an abnormal memory page and a hot page based on the updated page address list each time the page address list is updated, thereby performing processes such as memory resource replacement of the memory page in the above implementation.

[0023] In a possible implementation, determining the first memory page belonging to the hot page further includes: based on the page address list, regularly checking whether there is an abnormal memory page in the hot page list; and using the abnormal memory page in the hot page list as the first memory page.

[0024] In some scenarios, although the above implementation method can update the abnormal hot page to a cold page or an idle page to reduce its access frequency and reduce the access frequency of the abnormal memory page. However, during the program running process, the cold page may also be awakened and accessed by the application, so that the abnormal cold page is updated to a hot page, or the abnormal idle page is allocated to the application and updated to a hot page. Therefore, the abnormal cold page or abnormal idle page can also be dynamically changed to a hot page. Therefore, the method can be based on the page address list of abnormal memory pages maintained by the OS side to regularly check whether there are abnormal memory pages in the hot page address list, so as to regularly recycle the abnormal memory pages in the hot page, and the memory page found that belongs to the hot page and the abnormal memory page is used as the first memory page of the above embodiment to update the abnormal first memory page to a cold page or an idle page to ensure that the abnormal memory page is always in the cold page address list or the idle page address list. Thereby ensuring that the pages (hot pages) accessed by the application are all non-abnormal memory pages.

[0025] In a possible implementation, the determining of the first memory page belonging to the hot page further includes: upon receiving information indicating that the currently accessed memory page is the abnormal memory page, determining the currently accessed memory page as a hot page and a first memory page belonging to the abnormal memory page.

[0026] In this way, when a memory page accessed by the system is an abnormal memory page, since the memory page is the memory page being accessed, the memory page is also a hot page. The OS can also trigger the process of replacing the data in the abnormal memory page with a non-abnormal memory page when accessing the abnormal memory page to reduce the access frequency to the abnormal memory page.

[0027] In a possible implementation, mapping the memory resource access range allocated to the application to the second physical memory includes: switching the physical memory mapped with the memory resource access range allocated to the application from the first physical memory to the second physical memory, wherein the first physical memory is the physical memory mapped with the first memory page.

[0028] When the memory allocated to the application has an abnormality and cannot be accessed normally, the physical memory mapped by the memory resource access (user-mode memory page) accessed by the application needs to be switched from the first physical memory with the abnormality to the second physical memory.

[0029] In the process of replacing the data of the non-abnormal memory page (cold page or free page) in the kernel state with the abnormal hot page in the operating system, the user state is not aware of it, so it is necessary to ensure that the process-oriented memory address space (for example, the memory page in the user state allocated to the application) does not change. Among them, a certain memory page (memory resource access range) in the user state that is accessible to the application is mapped with the above-mentioned abnormal hot page, so that the application can access the first memory resource in the first physical memory mapped with the abnormal hot page through the memory resource access range. However, the data of the abnormal hot page has been replaced with the non-abnormal cold page or free page (the example of the second memory page above), and the physical memory mapped by the second memory page is the second physical memory. Therefore, in order to ensure the accuracy and consistency of the memory data accessed by the application, the OS can switch the physical memory mapped by a certain memory page in the user state from the first physical memory to the second physical memory. Specifically, the OS can map the abnormal hot page (first memory page) with the above-mentioned memory page in the user state, and update it to the mapping between the non-abnormal second memory page and the above-mentioned memory page in the user state. In this way, it can be ensured that when an application frequently accesses a certain user-mode memory page, the memory resources in the kernel-mode memory page mapped by the memory page are still the first memory resources, and the kernel-mode memory page is still a hot page, and the memory data stored in the kernel-mode memory page mapped by the memory page is consistent with the data previously accessed by the application by mapping the first memory page, so as to improve business performance.

[0030] In a possible implementation, the determining of the first memory page belonging to the hot page further includes: determining a first free page currently allocated to the application, wherein the first free page belongs to the abnormal memory page; and determining the first free page as the first memory page belonging to the hot page.

[0031] Among them, when the OS allocates memory to an application, if it is determined that the memory page (free page) allocated to the application is an abnormal memory page (for example, determined based on the page address list of the above-mentioned abnormal memory page), then the abnormal memory page will be updated to a hot page after being allocated to the application, thereby causing the existence of an abnormal page in the hot page to trigger the replacement process of the hot page and the cold page (free page). In order to avoid triggering this process, when the OS allocates memory to the application, if it is determined that the free page allocated by it is an abnormal memory page, the free page can be determined as the first memory page belonging to the hot page.

[0032] In this way, the embodiment of the present application can, when allocating memory pages to an application, replace memory resources with the second memory page by the allocated free page belonging to the abnormal memory page, so that when allocating memory to the application, the abnormal memory page will not be allocated to the application. Since the newly allocated memory page to the application will be updated to a hot page, it can be avoided that the abnormal memory page is allocated to the application when allocating memory, thereby triggering the abnormal hot page to replace memory resources and other processes.

[0033] In a possible implementation, combined with the previous implementation, the first memory page is an abnormal free page, the second memory page is a cold page before being updated to a hot page, and the first memory page is updated to a cold page.

[0034] Then the second memory page that is replaced with the abnormal free page (an example of the first memory page) newly allocated to the application can be a non-abnormal cold page. In other words, the OS can find a non-abnormal cold page in the cold page address list to replace it with the first memory page, so that the memory page newly allocated by the OS to the application is not an abnormal memory page, but a non-abnormal memory page, so as to reduce the frequency of access to the abnormal memory page.

[0035] In a possible implementation, combined with the previous implementation, replacing the second memory resource in the second memory page with the first memory resource in the first memory page includes: transferring the second memory resource in the second memory page to the first memory page.

[0036] In this embodiment, the first memory page is an abnormal free page, the second memory page may be a non-abnormal cold page, and the memory page newly allocated by the OS to the application needs to be a free page. Therefore, the OS may transfer the second memory resource in the non-abnormal cold page to the first memory page. In this way, there will be no memory resources in the non-abnormal cold page, so that it becomes a free page, so that the second memory page newly allocated by the OS to the application is still a free page, so that when allocating memory to the application, the non-abnormal memory page is allocated to the application to reduce the frequency of access to the abnormal memory page.

[0037] In a possible implementation, the method further includes: based on the page address list, when it is determined that the number of free pages (in the free pages) that do not belong to the abnormal memory page is less than a preset threshold, allocating the first free page belonging to the abnormal memory page to the application.

[0038] When the OS allocates memory to an application, it can determine based on the page address list of the abnormal memory page that there are fewer non-abnormal memory pages in the free pages, and then allocate the first free page belonging to the abnormal memory page to the application. This allows the OS to allocate abnormal free pages to the application only when the number of non-abnormal free pages is insufficient, thereby reducing the allocation of abnormal memory pages.

[0039] In a possible implementation, the method further includes: based on the page address list, when it is determined that the number of free pages (in the free pages) that do not belong to the abnormal memory page is greater than or equal to the preset threshold, allocating the free pages that do not belong to the abnormal memory page to the application.

[0040] When the OS allocates memory to an application, it can determine that there are more non-abnormal memory pages in the free pages based on the page address list of abnormal memory pages, and can give priority to allocating free pages that do not belong to abnormal memory pages to the application. When allocating memory to an application, it can give priority to allocating non-abnormal free pages to reduce the allocation of abnormal memory pages.

[0041] In a possible implementation, before replacing the memory resources in the second memory page with the memory resources in the first memory page, the second memory page is a cold page; before updating the second memory page to a hot page, before updating the first memory page to a cold page, the method further includes: replacing the first memory resources in the first memory page with the second memory resources in the second memory page.

[0042] In this embodiment, the OS may select a non-abnormal cold page (an example of the second memory page) from the cold page, and replace the second memory resource in the non-abnormal cold page with the first memory resource in the abnormal hot page (an example of the first memory page), so that the memory resource in the abnormal hot page is replaced from the first memory resource to the second memory resource, and the memory resource in the non-abnormal cold page is replaced from the second memory resource to the first memory resource. By replacing the abnormal hot page with the non-abnormal cold page, the access frequency of the abnormal memory page is reduced.

[0043] In a possible implementation manner, the acquiring the first physical access range includes: acquiring a first physical access range related to a correctable error CE.

[0044] In this embodiment, when the OS obtains the first physical access range that the physical memory cannot access normally, it can obtain the physical access range related to the CE. For example, the first physical access range obtained by the OS can be a physical address list of the physical memory that cannot be accessed normally obtained based on multiple CE reports.

[0045] In a possible implementation manner, the acquiring the first physical access range includes: when a CE is detected, acquiring a first physical access range related to the CE.

[0046] In this embodiment, the timing for the OS to obtain the first physical access range to replace the abnormal hot page may be when the server or electronic device to which the OS belongs detects CE, to obtain the first physical access range related to CE. In this way, when CE occurs, the abnormal memory page can be replaced to reduce the frequency of access to the abnormal memory page.

[0047] In a possible implementation, an embodiment of the present application provides a memory management device. The device includes: a determination module, used to determine a first memory page that is a hot page and an abnormal memory page, wherein the abnormal memory page is used to indicate a memory page that cannot be normally accessed by the mapped physical memory; a first replacement module, used to replace the second memory resource in the second memory page with the first memory resource in the first memory page, wherein the second physical memory mapped by the second memory page can be normally accessed; a first update module, used to update the second memory page to a hot page; a second update module, used to update the first memory page to a cold page or a free page; a switching module, used to map the memory resource access range allocated to the application to the second physical memory.

[0048] In one possible implementation, the determination module is specifically used to: obtain a first physical access range, wherein the physical memory within the first physical access range cannot be accessed normally; determine a page address list of the abnormal memory pages corresponding to the first physical access range; and based on the page address list, determine a first memory page in the abnormal memory pages that is a hot page.

[0049] In a possible implementation, the determination module is further configured to: based on the page address list, periodically check whether there is an abnormal memory page in the hot page list; and use the abnormal memory page in the hot page list as the first memory page.

[0050] In a possible implementation, the determination module is further configured to: upon receiving information indicating that the currently accessed memory page is the abnormal memory page, determine the currently accessed memory page as a hot page and a first memory page that is an abnormal memory page.

[0051] In a possible implementation, the switching module is specifically used to switch the physical memory mapped to the memory resource access range allocated to the application from the first physical memory to the second physical memory, wherein the first physical memory is the physical memory mapped to the first memory page.

[0052] In a possible implementation, the determination module is further used to: determine a first free page currently allocated to the application, wherein the first free page belongs to the abnormal memory page; and determine the first free page as a first memory page belonging to a hot page.

[0053] In a possible implementation manner, the second memory page is a cold page before being updated to a hot page, and the first memory page is updated to a cold page.

[0054] In a possible implementation manner, the first replacement module is specifically configured to transfer the second memory resource in the second memory page to the first memory page.

[0055] In a possible implementation, the device further includes: a first allocation module, configured to allocate the first free page belonging to the abnormal memory page to the application based on the page address list when it is determined that the number of free pages not belonging to the abnormal memory page is less than a preset threshold.

[0056] In a possible implementation, the device further includes: a second allocation module, for allocating free pages that do not belong to the abnormal memory page to the application based on the page address list when it is determined that the number of free pages that do not belong to the abnormal memory page is greater than or equal to the preset threshold.

[0057] In a possible implementation, before replacing the memory resources in the second memory page with the memory resources in the first memory page, the second memory page is a cold page; before updating the second memory page to a hot page, before updating the first memory page to a cold page, the device also includes: a second replacement module, used to replace the first memory resources in the first memory page with the second memory resources in the second memory page.

[0058] In a possible implementation manner, the determining module is specifically configured to: acquire a first physical access range related to the CE.

[0059] In a possible implementation manner, the determining module is specifically configured to: when a CE is detected, acquire a first physical access range related to the CE.

[0060] The effects of the memory management devices of the above-mentioned embodiments are similar to the effects of the memory management methods of the above-mentioned embodiments, and will not be described in detail here.

[0061] In a possible implementation, an embodiment of the present application provides a computing device cluster, including at least one computing device, each computing device including a processor and a memory. The processor of at least one computing device is used to execute instructions stored in the memory of at least one computing device, so that the computing device cluster executes the memory management method in the first aspect or any possible implementation of the first aspect.

[0062] The effect of the computing device cluster of this embodiment is similar to the effect of the memory management method in the above embodiments, and will not be described in detail here.

[0063] In one possible implementation, an embodiment of the present application provides a computer program product including instructions, which, when executed by a computing device cluster, enables the computing device cluster to execute the memory management method in the first aspect or any possible implementation of the first aspect.

[0064] The effect of the computer program product of this embodiment is similar to the effect of the memory management method in the above-mentioned embodiments, and will not be described in detail here.

[0065] In a possible implementation, an embodiment of the present application provides a computer-readable storage medium, including computer program instructions. When the computer program instructions are executed by a computing device cluster, the computing device cluster executes the memory management method in any one of the above implementations.

[0066] The effect of the computer-readable storage medium of this embodiment is similar to the effect of the memory management method in the above-mentioned embodiments, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] Figure 1 is a schematic diagram of the structure of a server shown as an example;

[0068] Figure 2 A schematic diagram of a memory management process is shown as an example;

[0069] Figure 3a A schematic diagram of a memory management process is shown as an example;

[0070] Figure 3b A schematic diagram of a memory management process is shown as an example;

[0071] Figure 4 is a schematic diagram of the structure of a memory management device shown as an example;

[0072] Figure 5 A schematic diagram of the structure of a computing device is shown as an example;

[0073] Figure 6 A schematic diagram of the structure of a computing device is shown as an example;

[0074] Figure 7 The figure is a schematic diagram of the structure of a computing device cluster shown as an example. DETAILED DESCRIPTION

[0075] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0076] The term "and / or" in this article is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0077] The terms "first" and "second" in the description and claims of the embodiments of the present application are used to distinguish different objects rather than to describe a specific order of objects. For example, a first target object and a second target object are used to distinguish different target objects rather than to describe a specific order of target objects.

[0078] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0079] In the description of the embodiments of the present application, unless otherwise specified, the meaning of "multiple" refers to two or more than two. For example, multiple processing units refer to two or more processing units; multiple systems refer to two or more systems.

[0080] Before describing the technical solution of the embodiment of the present application, the background technology involved in the embodiment of the present application is briefly introduced:

[0081] Public cloud is a cloud platform provided by third-party public cloud providers for individuals or enterprises. In the public cloud, the hardware, software and other structures are owned and managed by the third-party public cloud providers.

[0082] The cloud platform, which may also be referred to as a cloud management platform or cloud management platform in the embodiments of the present application, is a software system for cloud technology (also known as cloud computing technology) services provided by a cloud provider, and is used to provide interfaces related to cloud services for tenants to remotely access cloud services. Tenants can log in to the cloud platform on the cloud service access page using a pre-registered account and password, and after a successful login, select and purchase the corresponding cloud service on the cloud service access page, such as object storage services, virtual machine services, container services, etc. Exemplarily, the cloud management platform can provide a unified entrance (also referred to as an operation and maintenance entrance), and users can access the cloud management platform through the unified entrance, and manage the cloud resources (including hardware and software) of the corresponding cloud through the cloud management platform.

[0083] Cloud services include computing services, storage services, virtual machine services, network services, etc. Any device or function that a user device can access on a cloud platform can be considered a service provided by the cloud platform.

[0084] Cloud resources are hardware resources (also referred to as cloud infrastructure or infrastructure) and software resources (also referred to as public cloud services) used to provide services. Among them, the infrastructure includes multiple cloud data centers set up in multiple regions, and each region is equipped with at least one cloud data center. Cloud data centers may include computing nodes, storage nodes, and network nodes. Among them, computing nodes may be computing servers, storage nodes may be storage servers, and network nodes may include network facilities such as switches. For example, the hardware resources corresponding to software resources such as computing services, storage services, or network services include computing resources, storage resources, or network resources. Among them, computing resources can be deployed on computing nodes, storage resources can be deployed on storage nodes, and network resources can be deployed on network nodes.

[0085] Optionally, computing resources may include central processing unit (CPU) resources, memory resources and / or hard disk resources, etc. For example, a user (also referred to as a tenant) purchases a large number of virtual machine resources, and a large number of applications (also referred to as cloud applications) are deployed on the virtual machine resources. In this embodiment, the virtual machine and the applications in the virtual machine are both cloud services (i.e., software resources), and the server and other devices to which the virtual machine belongs are the corresponding hardware resources.

[0086] Dual In-line Memory Module (DIMM): DIMM is a physical form of memory storage. It is a memory stick that is inserted into the computer's memory slot. DIMM can hold multiple memory chips, providing greater storage capacity and higher bandwidth.

[0087] Memory can be divided into multiple physical units at the physical level, namely Cell, Row, Column, Bank, Memory Chip, and Rank.

[0088] Chip (also called memory particle) is a physical concept. Chip is a hardware device that contains a certain number of cells. Usually a chip is an independent integrated circuit that is soldered on the surface of the circuit board of the memory stick.

[0089] Rank is a logical concept of memory, which is usually composed of a group of chips that share address lines (or addresses and commands) and data lines. For example, a group of chips required for 64-bit data lines in a memory bar can be called a rank. For example, if a memory bar can support 128-bit data line bandwidth, the memory bar can include two ranks. A memory bar can have one or more ranks.

[0090] Cell, in a chip of the memory stick, the smallest data storage unit is called a Cell. Each Cell can independently store one or more bits of data.

[0091] Row / Column is the way to access data in a memory chip. The cells in a memory chip are organized into a two-dimensional grid, which consists of rows and columns. A row and column in a memory chip is a cell. When accessing memory, you need to provide the row address and column address to access the memory.

[0092] Bank is a part of the chip of the memory stick. A chip can be divided into multiple banks. Each bank is a cell array. A single chip of the memory stick is physically divided into multiple banks, so that the cell array of each bank can store and access data independently.

[0093] In summary, in the memory system, the above concepts are interrelated. A single cell stores data, and these cells are organized into rows and columns to form a two-dimensional data array. The memory chips composed of these data arrays are combined together to form one or more ranks, and finally integrated on a DIMM. Sometimes, further, the cells in the chip of the DIMM can be divided into relatively independent parts, that is, banks, so that when one part of the memory is operated, it will not affect other parts. This organization allows multiple operations to be performed simultaneously, thereby improving memory performance.

[0094] At present, when an abnormality occurs in the memory of electronic devices, servers, etc., error correction can be performed. In the prior art, memory error correction is mainly performed through the following schemes. When the BMC or BIOS detects an abnormality in a single row of a memory bar or an abnormality in a single cell, it can notify the operating system (OS) to isolate the memory page corresponding to the row or cell.

[0095] Since a single cell of the memory stick maps the data of a memory page and a row maps the data of a small number of memory pages, the OS can perform memory error correction by isolating a small number of memory pages.

[0096] However, when a memory error occurs at the column, chip (also expressed as device), or bank level in the memory bar, since a column, a chip, or a bank of the memory bar can map many memory pages, the OS will isolate many memory pages, which will cause a sharp reduction in the memory of the OS. Therefore, in the above-mentioned memory processing scheme in the prior art, only the memory at the cell and row levels can be isolated, and the memory anomalies at the column, chip, and bank levels cannot be processed. Among them, the error correction algorithm of the memory controller cannot correct some fault modes (also expressed as abnormal modes). Then the multiple reports of correctable errors (Corrected Error, CE) at the column, bank, chip, etc. levels will cause a CE storm; in addition, the error correction algorithm SDDC of the memory controller cannot correct some fault modes, and there is a certain probability that CE will become an uncorrectable error (Uncorrectable Error, UCE). This will cause a decrease in memory performance, reduce business performance, affect the normal operation of applications, and in typical cases, the CPU utilization will increase significantly.

[0097] To this end, the present application provides a memory management method, which can analyze the failure mode of the hardware and combine the memory access mechanism of the OS to reduce the proportion of abnormal memory access, thereby reducing the fault trigger rate, so as to reduce the occurrence rate of CE storms at the column, Bank, and Chip levels, and reduce the impact of memory anomalies at the column, Bank, and Chip levels on business performance.

[0098] The method can be applied to devices such as servers or electronic devices. The server can be a server on the cloud or a server off the cloud, which is not limited here. The electronic device can be a personal computer, a mobile phone, a tablet computer, a smart TV, a wearable device, a smart car, etc.

[0099] The following takes the application of the method to a server as an example to illustrate the implementation process of the method of the present application.

[0100] Please refer to Figure 1 , Figure 1 The schematic diagram of the structure of the server of the present application is shown as an example. It should be understood that Figure 1 The structure of the server shown is only an example, and the server of the present application may have more or fewer components than those shown in the figure, may combine two or more components, or may have a different component configuration. Figure 1 The various components shown in the EMBODIMENTS 2000 may be implemented in hardware, software, or a combination of hardware and software, including one or more signal processing and / or application specific integrated circuits.

[0101] Combination Figure 1 To describe the hierarchical relationship between the physical units of the memory bars (DIMM bars) in the server.

[0102] like Figure 1 As shown, the server may include but is not limited to an operating system (OS), a basic input / output system (BIOS), and a baseboard management controller (BMC). In addition, the server may also be installed with two CPUs, namely CPU0 and CPU1. This application does not limit the number of CPUs installed in the server.

[0103] Optionally, the server may further include a BMC controller (not shown) for controlling CPU0 and CPU1.

[0104] Take CPU0 as an example. Figure 1 As shown, the memory control bus (IMC) of CPU0 has dual channels, namely Channel0 and Channel1. In addition, two memory modules, namely DIMM0 and DIMM1, are installed on the server. CPU0 can interact with DIMM0 and DIMM1 through the dual channels. For the introduction of CPU1, please refer to the introduction of CPU0 above. The principle is the same and will not be repeated here.

[0105] Continue to refer to Figure 1 For a memory stick, take DIMM0 as an example, DIMM0 can be divided into two ranks, namely Rank0 and Rank1. Take Rank0 as an example to explain, Rank1 is the same, and will not be repeated here. Rank0 may include a group of chips, each chip may include one or more banks, each bank includes an array of cells with multiple rows and columns, and each cell can store multiple bits of data, here is 4 bits of data. About Figure 1 The introduction of Rank 1 is the same as that of Rank 0, so I will not go into details here.

[0106] Taking CPU0 as an example, CPU0 can interleave memory access with the memory sticks (DIMM0 and DIMM1) through the memory controller, and the physical memory of the memory stick can be organized as continuous or discontinuous physical addresses on the memory controller. In addition, the physical address of the physical memory can be mapped to the logical address of the memory in the OS kernel state (for example, in the form of a memory page) through the memory controller. The OS can manage the logical address of the memory and allocate the user state memory space to the process. The user state-oriented memory space is the user state logical address of the memory (also in the form of a memory page), so that the kernel state logical address is mapped to the user state logical address. In this way, the physical address of the physical memory can be mapped to the user state logical address through the kernel state logical address.

[0107] In addition, if Figure 1 As shown, OS, BIOS, BMC, CPU0 and CPU1 can interact with each other.

[0108] based on Figure 1 The architecture, Figure 2 For a flowchart of an exemplary memory management method, please refer to Figure 2 , which may include but is not limited to the following steps:

[0109] S101: The CPU module reports memory abnormality information to the BMC or BIOS.

[0110] In one possible implementation, Figure 1 The CPU0 or CPU1 shown (an example of a CPU module) can notify the abnormal interrupt to the Figure 1 The BIOS shown in the figure enables the BIOS to execute the interrupt processing code. During the interrupt processing, the BIOS can collect the abnormal information of the memory controller of CPU0 or CPU1 (an example of the above-mentioned memory abnormal information) and report it to the BMC through a one-block transfer (BT) channel or a high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express) channel.

[0111] The abnormal information may include but is not limited to: the physical address of the faulty memory, the faulty DIMM, the faulty Device, the faulty RANK, the faulty BANK, the faulty Row, the faulty Column, the faulty Cell, the value of the register of the memory controller and other information.

[0112] In one possible implementation, Figure 1The server shown may also include a BMC controller, which can manage CPU0 and CPU1. When the BMC controller determines that the memory is abnormal, the BMC controller can notify the abnormal information to the BMC through the interrupt pin, so that the BMC can actively query the abnormal information through the CPU (CPU0 or CPU1) out-of-band channel. Or the BMC can obtain the abnormal information by regularly polling the CPU (CPU0, CPU1).

[0113] In a possible implementation, when the method is applied to an electronic device (such as a PC), a CPU module in the electronic device may notify the BIOS of abnormal information.

[0114] S201, the BMC or BIOS determines the abnormal mode of the memory based on the above memory abnormality information.

[0115] First, the BMC or BIOS may perform CE data statistics based on the above memory exception information received each time.

[0116] For example, BMC or BIOS can count the CE data or CE errors reported each time (examples of the above memory abnormality information) according to the physical units of DIMM, Device, Rank, Bank, Row, Column, and Cell, and record them. For example, BMC or BIOS can count the physical units at which level each CE occurs, and the number of CE errors that occur in the physical unit. This statistical information is used to determine the abnormal mode of the memory, and this application does not limit the specific content of the statistical information.

[0117] The BMC or BIOS may then analyze the statistical information to determine the abnormal pattern of the memory (also expressed as the level of the physical unit to which the memory abnormality belongs).

[0118] For example, by analyzing the statistical information of CE data, the BMC or BIOS can determine that CE errors occur multiple times in the same physical unit (the above-mentioned DIMM, Device, RANK, BANK, Row, Column, and Cell are physical units of different levels), and then determine that the memory abnormality mode is an abnormality at the physical unit level.

[0119] For example, the BMC or BIOS determines through statistical information that multiple CE errors are caused by a memory module (for example, Figure 1 If an error occurs in the same row and / or the same CELL of DIMM0) as shown in the figure, the abnormal mode is determined to be CE at the row level or the Cell level.

[0120] For another example, the BMC or BIOS determines through statistical records that three rows (not limited to continuous or discontinuous rows) of a memory stick (such as DIMM0) have multiple errors, and the three rows belong to the same bank, then it can be determined that the abnormal mode is the bank-level CE.

[0121] For another example, the BMC or BIOS determines through statistical information that three columns of a memory stick (such as DIMM0) have multiple errors, and the three columns belong to different banks but the same chip. Then, it can be determined that the abnormal mode is CE at the chip (also expressed as device) level.

[0122] For another example, the BMC or BIOS determines through statistical information that several chips of a memory stick (such as DIMM0) have multiple errors, and the chips belong to the same Rank, then the abnormal mode can be determined to be a CE of the Rank level.

[0123] For another example, the BMC or BIOS determines through statistical records that errors occur multiple times in certain ranks of a certain memory stick (eg, DIMM0), and thus it can be determined that the abnormal mode is CE at the DIMM level.

[0124] It should be understood that the implementation scheme of the present application for BMC or BIOS to determine the abnormal mode of the memory is not limited to the above examples, and can be any implementation scheme that can determine the abnormal mode of the memory based on CE or received memory abnormalities.

[0125] S202: The BMC or BIOS determines a physical address list of abnormal memory according to the abnormal mode of the memory.

[0126] The BMC or BIOS may convert the abnormal mode (also expressed as a fault mode) into the address space of the smallest granularity of the memory to determine the physical address list of the memory where the abnormality occurs.

[0127] In a possible implementation, when executing S202, the BIOS may translate the memory address based on the abnormal mode to determine the physical address list of the abnormal memory, specifically:

[0128] BMC can notify BIOS of the counted abnormal patterns (such as CE at any level such as DIMM, Device, Rank, Bank, Row, Column, Cell, etc.), and BIOS can calculate the physical address list corresponding to the abnormal pattern according to the hardware configuration (such as interleave, memory configuration x4, memory stick configuration specifications, etc., which are not limited here).

[0129] For example, if the fault mode is Row-level CE, such as row i, then in the configuration item of interleave mode, a row address may be mapped to 128 discontinuous addresses in the physical address space of the memory bar, and a column address may be mapped to 1KB (byte) discontinuous addresses in the physical address space of the memory bar. Then the BIOS can determine the physical address list corresponding to the fault mode based on interleave, and thus find the list of physical addresses where the memory bar actually has an abnormality.

[0130] In a possible implementation, when the BMC executes S202, the memory address may be translated based on the abnormal mode to determine the physical address list of the abnormal memory. Specifically, the BIOS may report the above hardware configuration to the BMC during initialization, and the BMC may execute an algorithm similar to the BIOS based on the above hardware configuration to calculate the physical address list corresponding to the abnormal mode.

[0131] S203, the BMC or BIOS reports information indicating memory abnormality to the operating system.

[0132] The information indicating the memory abnormality may include an abnormal physical address list, that is, a physical address list of the abnormal memory.

[0133] In a possible implementation, the BIOS may report the physical address list of the abnormal memory to the operating system (OS) through the extended table items of the APCI table items, ACPI, or the exception report table inherited from the APCI. Then the OS kernel may obtain the physical address table items of the memory that sent the exception through ACPI parsing to obtain the physical address list of the abnormal memory.

[0134] In a possible implementation, the BMC may report the physical address list of the abnormal memory to the OS side through the IPMI channel.

[0135] In a possible implementation, in the above S203, the information indicating the memory abnormality reported by the BMC or BIOS to the operating system may also include the above abnormal mode. In this way, the OS can flexibly determine which method to use to manage the abnormal memory according to different abnormal modes to reduce access to the abnormal memory.

[0136] The above S201 to S203 can be implemented by BIOS and BMC together, or can be executed by BMC or BIOS alone. For example, if the server in this embodiment is replaced by an electronic device, such as a PC or a mobile phone, the abnormal physical address list can be obtained by BIOS.

[0137] In other embodiments, the above S201 to S203 can also be performed by Figure 1The external device connected to the server shown is executed so that the external device obtains the abnormal physical address list and passes it to the operating system of the server. There is no limitation on the specific implementation process of the external device obtaining the abnormal physical address list of the memory device of the server.

[0138] The BIOS and / or BMC detects the CE error of the memory, identifies the abnormal mode of the memory, and obtains the physical address list of the memory where the abnormality occurs through reverse calculation of the abnormal mode. Then, the physical address list is notified to the OS kernel side so that the OS kernel can obtain the physical address list of the memory where the abnormality occurs.

[0139] S301, the operating system may obtain an abnormal physical address list based on the received reported information, and determine an abnormal memory page based on the abnormal physical address list.

[0140] In a possible implementation manner, the reported information may include an abnormal mode, such as CE at any level, such as DIMM, Device (ie, Chip), Rank, Bank, Row, Column, Cell, etc.

[0141] In a possible implementation, when the abnormal mode reported by the BMC or BIOS to the operating system is a row-level or Cell-level CE, since the number of memory pages corresponding to the row-level or Cell-level CE is small, the operating system can reduce the access to the abnormal memory by isolating the abnormal memory pages according to the traditional solution. The specific process is not limited here.

[0142] In another possible implementation, when the abnormal mode reported by the BMC or BIOS to the operating system is any one of the levels of CE in DIMM, Device (i.e., Chip), Rank, Bank, and Column, the memory page mapped by the abnormal mode will be more than 4KB. Then, according to the traditional memory page isolation scheme, it is impossible to isolate the above-mentioned large number of memory pages. In this embodiment, the operating system can manage the abnormal memory through S301 to S304 of the present application to reduce access to the abnormal memory.

[0143] In another possible implementation, when the abnormal mode reported by the BMC or BIOS to the operating system is a row-level or Cell-level CE abnormality, the operating system can also manage the abnormal memory through S301 to S304 of the present application to reduce access to the abnormal memory.

[0144] In addition, in some embodiments, the operating system may not refer to various abnormal modes to determine different processing methods for abnormal memory under different abnormal modes. The operating system may determine the management method for abnormal memory according to the number of abnormal memory pages determined by S301. For example, when the operating system determines that the number of abnormal memory pages is small (for example, less than a threshold), the operating system may reduce access to abnormal memory by isolating the memory pages with abnormalities according to the traditional scheme; and when the number of abnormal memory pages is large (for example, greater than or equal to the above threshold), the operating system may manage abnormal memory through S301 to S304 of the present application to reduce access to abnormal memory.

[0145] In the above S301, the OS may perform mapping based on the acquired abnormal physical address list about the memory according to the memory page size managed by the OS to obtain the page address of the mapped memory page (the page address of the abnormal memory page).

[0146] For example, the OS manages memory in 4K pages by default. Then, multiple physical addresses in the abnormal physical address list obtained by the OS may be mapped to the same memory page, so that there may be a many-to-one mapping relationship between the physical addresses in the abnormal physical address list and the memory pages managed by the OS side.

[0147] Among them, the memory page obtained by the above mapping (an example of an abnormal memory page) is the memory logical address of the OS kernel state, and the OS also allocates a memory logical address to the user state process, which is also a memory page, but the memory page is a user state memory page, which is mapped to the kernel state memory page, thereby achieving the effect of allocating physical memory to the process.

[0148] In some embodiments, in the above S301, the OS may obtain the abnormal physical address list through an embedded hardware system such as BIOS or BMC. In other embodiments, the abnormal physical address list may also be obtained through an application, and then the application notifies the OS kernel of the abnormal physical address list. There is no limitation on the way in which the OS obtains the abnormal physical address list.

[0149] In S301, after determining the abnormal memory page in the kernel state (also referred to as an abnormal page), the OS can create an abnormal page address list for the abnormal page to record the page address information of the abnormal memory page, so that the OS kernel can maintain a set of address lists for the abnormal memory page. The list is used to manage the scheduling of the abnormal page to prevent the abnormal page from being frequently accessed because it is a hot page.

[0150] In addition, the OS may also maintain a hot page address list, a cold page address list, and a free page address list related to the memory.

[0151] The hot page address list may record addresses of memory pages (expressed as hot pages) that are frequently or recently accessed in the kernel-state memory.

[0152] The cold page address list may record addresses of memory pages (referred to as cold pages) with low access frequencies in the kernel-mode memory.

[0153] The free page address list may record addresses of free pages in the kernel-mode memory that are not allocated to the process.

[0154] In the following embodiments, non-exceptional pages may also be mentioned, where the non-exceptional pages are memory pages maintained by the OS except for the exceptional memory pages in the exceptional page address list.

[0155] In other embodiments, the exception address list may include a first exception page address list under the hot page address list (used to record page addresses that belong to hot pages and are exception pages (also expressed as exception memory pages)), a second exception page address list under the cold page address list (used to record page addresses that belong to cold pages and are exception pages), and a third exception page address list under the free page address list (used to record page addresses that belong to free pages and are exception pages).

[0156] In other words, the present application does not impose any restrictions on the form of the exception page address list stored on the OS side. The OS side only needs to maintain the exception page address list based on the reported exception physical address list received, and can synchronously update the exception page address list maintained by the OS side based on the reported exception physical address list, so that the OS side can save the address list of the exception pages in the kernel state.

[0157] S302: When the operating system determines that at least one abnormal memory page is a hot page, the operating system replaces data of the abnormal hot page with a non-abnormal cold page.

[0158] In a possible implementation, the operating system may convert the received abnormal physical address list to obtain an abnormal page address list about the memory, and the abnormal page address list may include the page address of each abnormal memory page converted from the abnormal physical address list.

[0159] As mentioned above, the operating system also maintains a hot page address list. For each abnormal memory page in the abnormal page address list, the operating system can traverse the hot page address list to see if there is a hot page with the same page address as the abnormal memory page. If so, it means that the abnormal memory page is a hot page. It can be determined that the abnormal memory page is a memory page that needs to be frequently accessed. However, an abnormality has occurred in the physical memory corresponding to the memory physical address mapped by the abnormal memory page. In order to avoid the OS from frequently accessing the abnormal memory page, the OS can transfer the data in the abnormal memory page (i.e., the above-mentioned abnormal hot page) belonging to the hot page to a non-abnormal cold page.

[0160] The non-abnormal cold page is a non-abnormal page belonging to a cold page. In other words, the non-abnormal cold page is a cold page whose page address in the cold page address list does not belong to the page address of any abnormal memory page in the abnormal page address list.

[0161] Since the abnormal memory pages in the abnormal page address list may include hot pages and cold pages, the operating system of this embodiment can transfer (an example of replacement) the data of the abnormal hot page to the non-abnormal cold page, so that the data frequently accessed by the OS is located in the non-abnormal page rather than in the abnormal page.

[0162] The memory data originally stored in the above-mentioned non-abnormal cold page can be transferred to the above-mentioned abnormal hot page to achieve mutual replacement of data between the abnormal hot page and the non-abnormal cold page.

[0163] In other embodiments, the OS may also replace multiple memory pages (more than two) to achieve the purpose of replacing the abnormal memory page belonging to the hot page with a non-abnormal free page or a non-abnormal cold page, and to achieve the purpose of replacing the data in the abnormal memory page belonging to the hot page with a non-abnormal free page or a non-abnormal cold page, without being limited to the implementation method of replacing the two memory pages of the abnormal memory page belonging to the hot page and the non-abnormal cold page (or non-abnormal free page).

[0164] For example, the OS may replace the memory data of an abnormal memory page belonging to a hot page with a non-abnormal cold page, and the OS may replace the memory data originally stored in the non-abnormal cold page with a non-abnormal free page, so that the table entry of the abnormal memory page is updated to a free page, the table entry of the non-abnormal cold page is updated to a hot page, and the table entry of the non-abnormal free page is updated to a cold page. Thus, the access frequency to the abnormal memory page (which has been updated from a hot page to a free page) can be reduced.

[0165] Taking the example of OS exchanging memory data between abnormal hot pages and non-abnormal cold pages, OS can replace the physical memory pointed to by the memory physical address mapped by the abnormal hot page (for example Figure 1 The memory data in the storage space in DIMM0 and / or DIMM1 shown in the figure and the memory data in the physical address executed by the memory physical address mapped by the non-abnormal cold page are replaced with each other to achieve data replacement between the abnormal hot page and the non-abnormal cold page.

[0166] Then, after S302 , the OS may replace the entry of the abnormal hot page from the hot page to the cold page.

[0167] Optionally, in S303, the operating system replaces the table entries of the cold page and the hot page.

[0168] For example, the operating system may transfer the page address of the non-abnormal cold page from the cold page address list to the hot page address list, so that the non-abnormal cold page is updated to a non-abnormal hot page, and transfer the page address of the abnormal hot page from the hot page address list to the cold page address list, so that the abnormal hot page is updated to an abnormal cold page, so as to reduce the access to abnormal memory pages.

[0169] S304, the operating system adjusts the mapping between the memory logical address in the user state and the abnormal hot page to the mapping between the memory logical address in the user state and the non-abnormal cold page.

[0170] In the process of replacing the cold page and hot page data of the kernel-state memory page by the operating system, the user state is not aware of it, and the memory address space for the process does not change. Then a certain memory page (memory logical address) of the user state accessed by the process is mapped with the above-mentioned abnormal hot page, but the data of the abnormal hot page has been replaced with the non-abnormal cold page. Therefore, in order to ensure the accuracy and consistency of the memory data accessed by the process, the OS can update the mapping between the abnormal hot page and the user-state memory page to the mapping between the non-abnormal cold page and the user-state memory page. In this way, it can be ensured that when the process frequently accesses a certain memory page of the user state, the kernel-state memory page mapped by the memory page is still a hot page (wherein the table entry of the non-abnormal cold page is updated to a hot page), and the memory data stored in the kernel-state memory page mapped by the memory page is consistent with the data previously accessed by the process.

[0171] The present application does not limit the execution order of S303 and S304.

[0172] Combine the following Figure 3a The following is to illustrate the process of replacing the hot page data with the cold page data by the operating system triggered by the update of the abnormal physical address of the memory.

[0173] like Figure 3a As shown, the memory can be divided into three layers, namely the lowest level physical memory (e.g. Figure 1 DIMM0 and DIMM1 shown in the figure), the kernel state memory space of the OS, and the user state memory space for the process.

[0174] Among them, the lowest level physical memory access needs to be accessed through the physical address, and two physical memories of physical address 1 and physical address 2 are shown here.

[0175] The memory space in kernel mode is a memory space managed by the OS and mapped to physical memory, in the form of memory pages. Memory page 2 and memory page 3 are shown here, where page 2 is mapped to the physical memory of physical address 1, and page 3 is mapped to the physical memory of physical address 2.

[0176] The user-state memory space is the memory space allocated by the OS to the process, which is allocated in the form of memory pages. However, the user-state memory pages and the kernel-state memory pages are independent of each other. The user-state process can access the physical memory through mapping.

[0177] like Figure 3a As shown, page 1 that the OS has allocated to a process and page 2 in kernel mode are originally mapped.

[0178] Thus, before implementing the solution of this application, Figure 3a As shown, by accessing page 1, the OS can determine page 2 mapped to page 1 and access physical address 1 corresponding to page 2 to enable the process to access the memory.

[0179] like Figure 3a As shown, for example, page 2 is a hot page, and the physical memory pointed to by the physical address 1 mapped by page 2 has a memory exception, resulting in a CE error. For example, the CE error is determined to be a Bank-level CE through the above method. In order to avoid the memory frequently accessed by the process (such as the above page 2) being abnormal memory, the OS can translate the physical address 1 where the exception occurs into the page address of the memory page, which is the page address of page 2 here, thereby determining the page address of the abnormal memory page (here page 2).

[0180] Then, if Figure 3a As shown, the OS can traverse the page addresses in the hot page address list to find out whether there is a hot page in the hot page address list that has the same page address as the abnormal memory page. Page 2 is taken as an example for explanation as an abnormal hot page. In actual applications, there are usually multiple abnormal memory pages. When there are multiple abnormal memory pages as hot pages, the principle of the processing process is the same as the principle of the related processing process for page 2, which will not be repeated here.

[0181] Among them, the OS can determine that page 2 is not only an abnormal memory page but also a hot page by traversing the hot page address list. Then the OS can find a non-abnormal memory page (here is page 3) in the cold page and replace the data of page 2 with the data of page 3.

[0182] Specifically, the OS kernel can allocate a new temporary page (e.g., page 0) to itself, and then the OS can copy the memory data in page 2 to the temporary page 0. Then, the OS can find a non-abnormal page (here, page 3) in the cold page address list, and copy the memory data in page 3 to the above page 2. Finally, the OS copies the memory data of temporary page 0 to page 3 to complete the memory data replacement between the cold page (page 3) and the hot page (page 2), and after the data replacement, the OS can release the temporary page 0. Among them, the data replacement process between the hot page and the cold page is specifically implemented by replacing the data in the physical memory pointed to by the physical address 1 mapped to page 2 with the data in the physical memory pointed to by the physical address 2 mapped to page 3.

[0183] Then, if Figure 3a As shown, the OS can update page 2 from a hot page to a cold page to mark it as a cold page. Specifically, the page address of page 2 can be added to the cold page address list. However, it can be understood that page 2 is still an abnormal page. Similarly, the OS can update page 3 from a cold page to a hot page to mark it as a hot page. Specifically, the page address of page 3 can be added to the hot page address list. However, it can be understood that page 3 is still a non-abnormal page. This realizes the replacement of page 2 and page 3 in the table entries of cold pages and hot pages.

[0184] Finally, if Figure 3a As shown, in order to ensure that the user state is unaware of the data replacement between the kernel state memory pages, the OS can remap the user state page 1 to its corresponding kernel state memory logical address. Specifically, the user state page 1 was originally mapped to the kernel state page 2. In order to ensure that the user state is unaware that the physical memory address it accesses has changed, the user state address space can be kept unchanged. Then the OS needs to map the kernel state memory logical address of page 1 from Figure 3a Page 2 shown is modified to page 3, so that the physical memory accessed by the process through page 1 is switched from the physical memory pointed to by physical address 1 mapped to page 2 to the physical memory pointed to by physical address 2 mapped to page 3. In this way, the physical memory accessed by the process is changed, so that the memory frequently accessed by the process is not abnormal.

[0185] In the above implementation, each time the OS obtains the abnormal physical address list and converts the abnormal physical address list to obtain the page address of the abnormal memory page through the above S301, the OS can update the existing abnormal page address list based on the page address of the abnormal memory page obtained this time. For example, the original abnormal page address list only includes page 1, page 2, and page 3, and the new abnormal page address list obtained by converting the abnormal physical address list received by the OS again only includes page 1 and page 4. The OS can update the original abnormal page address list based on the new abnormal page address list, so that the updated page address list only includes page 1 and page 4. The update method of the abnormal page address list can be a full update or an incremental update, which is not limited here.

[0186] In addition, the OS can also execute the above S302 to S304 based on the updated abnormal page address list each time it receives the abnormal physical address list, so as to replace the abnormal hot page with the non-abnormal cold page (or free page) each time the abnormal page address list is updated.

[0187] In this embodiment, the OS kernel can determine the memory page corresponding to the physical address list and mark it as an abnormal memory page. Then, when the abnormal memory page is a hot page, the data of the abnormal hot page and the non-abnormal cold page are switched, and the page address of the hot page is replaced into the cold page address list to reduce the frequency of application access to abnormal memory.

[0188] In another possible implementation, the operating system may also periodically check whether there are abnormal pages in the hot pages, and when it is determined that there is at least one abnormal page in the hot pages, the data of the abnormal hot page is replaced with a non-abnormal cold page, so as to trigger the operating system to execute the above S302 to S304, and the process principle is the same, which will not be repeated here.

[0189] Different from the above embodiment, the operating system automatically triggers the processing of abnormal memory pages based on the received abnormal physical address. In this embodiment, considering that the data in the cold page may be awakened during the program running, the cold page is accessed by the process, so that the cold page can be updated to a hot page. There may be abnormal memory pages in the cold page, wherein the abnormal memory page in the cold page may be determined by the above S301, or may exist by replacing the above abnormal hot page with the non-abnormal cold page and resetting the table entry, for example Figure 3a The unusual page 2 shown is marked as a cold page.

[0190] In order to ensure that there are no abnormal pages in the memory pages (such as hot pages) frequently accessed by the process when the memory pages dynamically change between hot pages and cold pages, in this embodiment, the OS can periodically check the hot page address list based on the abnormal page address list to determine whether there are abnormal memory pages in the hot page address list. When there are abnormal memory pages in the hot page address list, the OS can execute the above S302 to S304 for each abnormal hot page. The specific process is not repeated here, so as to replace the data in the abnormal hot page with the non-abnormal cold page, reset the table entries of the hot page and the cold page, and remap the physical memory of the user-mode memory page.

[0191] For example, in the above Figure 3a In the example, the page 2 may be changed from an abnormal cold page to a hot page, so that the page 2 is determined to be an abnormal hot page through regular checks of the OS.

[0192] In another possible implementation, when the operating system accesses a memory page, when the OS receives an indication from the BMC or BIOS that the memory page currently being accessed is an abnormal memory page (for example, there is a CE error), the OS may determine the memory page currently being accessed as an abnormal hot page, and execute the above S302 to S304, and replace the memory data (which may be code or data, without limitation) in the abnormal hot page with a non-abnormal cold page or a non-abnormal free page.

[0193] In this way, when a memory page accessed by the system is an abnormal memory page, since the memory page is the memory page being accessed, the memory page is also a hot page. The OS can also trigger the process of replacing the data in the abnormal memory page with a non-abnormal memory page when accessing the abnormal memory page to reduce the access frequency to the abnormal memory page.

[0194] In one possible implementation, in S302 to S304 above, the OS may perform data replacement, table entry switching, and physical memory remapping of the abnormal hot page with the non-abnormal cold page. In other embodiments, the memory page that exchanges data with the abnormal hot page may also be a non-abnormal free page. The principle of its implementation process is similar to that of S302 to S304 above, and will not be repeated here.

[0195] That is, in the embodiment of the present application, when the memory page used by the application is an abnormal page, the OS of the present application can replace the memory page used by the application from the abnormal memory page to a non-abnormal cold page, and switch the table entry of the abnormal memory page from a hot page to a cold page; or, the OS can replace the memory page used by the application from the abnormal memory page to a non-abnormal free page, thereby switching the table entry of the abnormal memory page from a hot page to a free page, so as to reduce the access frequency to the abnormal memory page.

[0196] In another possible implementation, the OS may further execute the following S401 to S404. The present application does not limit the execution order of the processes S401 to S404 and the above-mentioned processes S301 to S304.

[0197] The following S401 to S404 are for the scenario where the OS allocates memory pages to the process, while the above S301 to S304 are triggered by an abnormality in the physical address of the memory. In addition, the memory switching scheme in which the OS periodically checks whether there is abnormal memory in the hot page address list can be combined not only with the scenario where the OS determines the abnormal physical address list and performs memory switching, but also with the scenario where the memory allocated by the OS to the process is an abnormally free page.

[0198] S401: The operating system determines that a free page allocated to a process is an abnormal memory page.

[0199] In some embodiments, the free memory (free pages) allocated by the OS to the process are preferentially non-exceptional memory pages, that is, free pages that do not belong to the exceptional page address list. However, in cases where the number of non-exceptional memory pages in the free pages is insufficient, the OS will allocate exceptional free pages to the process, thereby triggering S401 to S404.

[0200] S402, the operating system replaces the data of the normal cold page to the free page.

[0201] Among them, when the free page allocated by the OS to the process is an abnormal memory page, the OS can search for a non-abnormal memory page in the cold page address list, wherein the cold page generally stores memory data (which can be code or data, without limitation), then the OS can copy the memory data in the non-abnormal cold page (that is, the non-abnormal memory page found in the cold page address list) to the abnormal free page, so that the non-abnormal cold page can be used as a free page for the process to access.

[0202] When the OS allocates memory to a process, if the OS determines that the free page allocated to the process is an abnormal memory page, it can find a non-abnormal memory page in the cold page and copy the data of the non-abnormal cold page to the free page. Then, the OS can map the user-state memory page to the non-abnormal cold page and allocate the page address of the user-state memory page to the process. In this way, when the OS allocates memory to the process, it can allocate a non-abnormal memory page to the process. This can avoid the OS detecting abnormal pages in hot pages, thereby performing the data switching process between cold pages and hot pages, and can allocate non-abnormal pages to the process when allocating memory.

[0203] S403: The operating system marks the abnormal free page as a cold page.

[0204] Optionally, the operating system may also mark the above-mentioned non-abnormal cold page as a hot page.

[0205] Among them, the memory page accessed by the process may be a hot page, so the OS can transfer the page address of the above-mentioned non-abnormal cold page allocated to the process from the cold page address list to the hot page address list, so that the non-abnormal cold page is updated to a non-abnormal hot page.

[0206] S404: The operating system establishes a mapping between the non-abnormal cold page and the memory logical address in the user state.

[0207] During the process of the operating system replacing the cold page and hot page data of the kernel-state memory page, the user state is not aware of it. When allocating memory to the process, the OS can convert the non-abnormal cold page into a free page and map the user-state memory page to the non-abnormal cold page to allocate the user-state memory page to the process.

[0208] The present application does not limit the execution order of S403 and S404.

[0209] Combine the following Figure 3b This is to illustrate that when allocating memory to a process, when the allocated memory is an abnormal free page, the operating system is triggered to execute the above S402 to S404 to perform the processing of replacing the free page with the cold page.

[0210] Figure 3b The architecture shown is similar to Figure 3a The principles of the architecture shown are the same and will not be repeated here.

[0211] like Figure 3b As shown, since there is less non-abnormal free memory in the physical memory, the OS allocates an abnormal memory to the process, specifically the physical memory with memory abnormality pointed to by physical address 3. The physical address 3 is mapped to page 5 in kernel mode, and page 5 is an abnormal free page, that is, an idle page belonging to an abnormal page. The OS can find a non-abnormal cold page in the cold page address list based on the abnormal page address list, here is page 6, and transfer the data of page 6 to page 5, for example, copy the data in the physical memory pointed to by physical address 4 mapped to page 6 to the physical memory pointed to by physical address 3 mapped to page 5, and delete the data in the physical memory pointed to by physical address 4. This is to achieve data replacement between cold pages and free pages.

[0212] Then, the OS may mark page 5 from an abnormal free page to an abnormal cold page. Optionally, the OS may also mark page 6 from a non-abnormal cold page to a non-abnormal hot page.

[0213] Finally, in order for the OS to Figure 3bPage 6 shown maps the user-mode memory page, here page 4, to allocate page 4 to the process, so that the memory space allocated to the process is the physical memory pointed to by physical address 4. There is no abnormality in the physical memory and it can be accessed normally.

[0214] In the above embodiment, the abnormal page address list can be a first-level page table, and the abnormal page address list does not distinguish between free pages and non-free pages. In some embodiments, the abnormal page address list maintained by the OS side may include a second-level page table of the free page address list. For example, the free page address list may include a second-level page table, which is a page table of abnormal free pages (including page addresses of free pages belonging to abnormal pages) and a page table of non-abnormal free pages (including page addresses of free pages belonging to non-abnormal pages). Then, when the OS allocates memory to the process, it can preferentially select the memory page allocated to the process in the page table of non-abnormal free pages to preferentially allocate reliable free pages, without using the abnormal page address list as a first-level page table and the free page address list to traverse and search, to find non-abnormal free pages to allocate to the process, which can avoid the problem of triggering memory exceptions due to frequent access to abnormal memory pages by the program during program operation.

[0215] In the above-mentioned embodiments of the present application, the OS can replace the data in the abnormal memory page used by the process with a non-abnormal free page or a non-abnormal cold page, so that the memory page used by the process is converted from an unreliable abnormal memory page to a reliable non-abnormal memory page. This can avoid the hot page used by the application being an abnormal memory, and can reduce the frequency of the application accessing the abnormal memory.

[0216] An embodiment of the present application provides a memory management device. Figure 4 The schematic diagram of the structure of the memory management device 800 is shown as an example. Figure 4 The memory management device 800 includes: a determination module 801, used to determine a first memory page that is a hot page and an abnormal memory page, wherein the abnormal memory page is used to indicate a memory page that the mapped physical memory cannot access normally; a first replacement module 802, used to replace the second memory resource in the second memory page with the first memory resource in the first memory page, wherein the second physical memory mapped by the second memory page can be accessed normally; a first update module 803, used to update the second memory page to a hot page; a second update module, used to update the first memory page to a cold page or a free page; a switching module 804, used to map the memory resource access range allocated to the application to the second physical memory.

[0217] In one possible implementation, the determination module 801 is specifically used to: obtain a first physical access range, wherein the physical memory within the first physical access range cannot be accessed normally; determine a page address list of the abnormal memory pages corresponding to the first physical access range; and based on the page address list, determine a first memory page in the abnormal memory pages that is a hot page.

[0218] In a possible implementation, the determination module 801 is further configured to: based on the page address list, periodically check whether there is an abnormal memory page in the hot page list; and use the abnormal memory page in the hot page list as the first memory page.

[0219] In a possible implementation, the determination module 801 is further configured to: upon receiving information indicating that the currently accessed memory page is the abnormal memory page, determine the currently accessed memory page as a hot page and the first memory page that is an abnormal memory page.

[0220] In a possible implementation, the switching module 804 is specifically used to switch the physical memory mapped to the memory resource access range allocated to the application from the first physical memory to the second physical memory, wherein the first physical memory is the physical memory mapped to the first memory page.

[0221] In a possible implementation, the determination module 801 is further used to: determine a first free page currently allocated to the application, wherein the first free page belongs to the abnormal memory page; and determine the first free page as a first memory page belonging to a hot page.

[0222] In a possible implementation manner, the second memory page is a cold page before being updated to a hot page, and the first memory page is updated to a cold page.

[0223] In a possible implementation manner, the first replacement module 802 is specifically configured to transfer the second memory resource in the second memory page to the first memory page.

[0224] In a possible implementation, the device further includes: a first allocation module, configured to allocate the first free page belonging to the abnormal memory page to the application based on the page address list when it is determined that the number of free pages not belonging to the abnormal memory page is less than a preset threshold.

[0225] In a possible implementation, the device further includes: a second allocation module, for allocating free pages that do not belong to the abnormal memory page to the application based on the page address list when it is determined that the number of free pages that do not belong to the abnormal memory page is greater than or equal to the preset threshold.

[0226] In a possible implementation, before replacing the memory resources in the second memory page with the memory resources in the first memory page, the second memory page is a cold page; before updating the second memory page to a hot page, before updating the first memory page to a cold page, the device also includes: a second replacement module, used to replace the first memory resources in the first memory page with the second memory resources in the second memory page.

[0227] In a possible implementation manner, the determining module 801 is specifically configured to: acquire a first physical access range related to the CE.

[0228] In a possible implementation manner, the determining module 801 is specifically configured to: when a CE is detected, acquire a first physical access range related to the CE.

[0229] The effects of the memory management devices of the above-mentioned embodiments are similar to the effects of the memory management methods of the above-mentioned embodiments, and will not be described in detail here.

[0230] Among them, the above modules can all be implemented by software, or can be implemented by hardware. Among them, the module is an example of a software functional unit, and the above module may include code running on a computing instance. Among them, the computing instance may include at least one of a physical host (computing device), a virtual machine, and a container. Further, the above computing instance may be one or more. For example, the determination module 801 may include code running on multiple hosts / virtual machines / containers. It should be noted that the multiple hosts / virtual machines / containers used to run the code may be distributed in the same region (region) or in different regions. Further, the multiple hosts / virtual machines / containers used to run the code may be distributed in the same availability zone (AZ) or in different AZs, each AZ including a data center or multiple data centers with similar geographical locations. Among them, usually a region may include multiple AZs.

[0231] Similarly, multiple hosts / virtual machines / containers used to run the code can be distributed in the same virtual private cloud (VPC) or in multiple VPCs. Usually, a VPC is set up in a region. For cross-region communication between two VPCs in the same region and between VPCs in different regions, a communication gateway needs to be set up in each VPC to achieve interconnection between VPCs through the communication gateway.

[0232] As an example of a hardware functional unit, the module may include at least one computing device, such as a server, etc. Alternatively, the module may also be a device implemented by an application-specific integrated circuit (ASIC) or a programmable logic device (PLD). The PLD may be a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof.

[0233] The multiple computing devices included in the above-mentioned memory management device can be distributed in the same region or in different regions. The multiple computing devices included in the above-mentioned memory management device can be distributed in the same AZ or in different AZs. Similarly, the multiple computing devices included in the above-mentioned memory management device can be distributed in the same VPC or in multiple VPCs. The multiple computing devices can be any combination of computing devices such as servers, ASICs, PLDs, CPLDs, FPGAs, and GALs.

[0234] It should be noted that, in other embodiments, the above modules can be used to execute corresponding steps in the memory management method to realize all functions of the memory management device.

[0235] The present application also provides a computing device 900. Figure 5 As shown, the computing device 900 includes: a bus 902, a processor 904, a memory 906, and a communication interface 909. The processor 904, the memory 906, and the communication interface 909 communicate with each other through the bus 902. The computing device 900 can be a server or a terminal device. It should be understood that the present application does not limit the number of processors and memories in the computing device 900.

[0236] The bus 902 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 5The bus 902 may include a path for transmitting information between various components of the computing device 900 (eg, the memory 906, the processor 904, and the communication interface 909).

[0237] The processor 904 may include any one or more of a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), or a digital signal processor (DSP).

[0238] The memory 906 may include a volatile memory, such as a random access memory (RAM). The processor 904 may also include a non-volatile memory, such as a read-only memory (ROM), a flash memory, a hard disk drive (HDD), or a solid state drive (SSD).

[0239] The memory 906 stores executable program codes, and the processor 904 executes the executable program codes to respectively implement the functions of the aforementioned determination module, the first replacement module, the first update module, and the switching module, thereby implementing the memory management method. That is, the memory 906 stores instructions for executing the memory management method.

[0240] The communication interface 909 uses a transceiver module such as, but not limited to, a network interface card or a transceiver to implement communication between the computing device 900 and other devices or a communication network.

[0241] The embodiment of the present application also provides a computing device cluster. The computing device cluster includes at least one computing device. The computing device can be a server, such as a central server, an edge server, or a local server in a local data center. In some embodiments, the computing device can also be a terminal device such as a desktop computer, a laptop computer, or a smart phone.

[0242] like Figure 6 As shown, the computing device cluster includes at least one computing device 1000. The memory 1006 in one or more computing devices 1000 in the computing device cluster may store the same instructions for executing the memory management method.

[0243] In some possible implementations, the memory 1006 of one or more computing devices 1000 in the computing device cluster may also store some instructions for executing the memory management method. In other words, the combination of one or more computing devices 1000 may jointly execute the instructions for executing the memory management method.

[0244] It should be noted that the memory 1006 in different computing devices 1000 in the computing device cluster can store different instructions, which are respectively used to execute part of the functions of the memory management device. That is, the instructions stored in the memory 1006 in different computing devices 1000 can implement the functions of one or more modules among the determination module, the first replacement module, the first update module, and the switching module.

[0245] In some possible implementations, one or more computing devices in the computing device cluster may be connected via a network, which may be a wide area network or a local area network. Figure 7 A possible implementation is shown. Figure 7 As shown, two computing devices 1100A and 1100B are connected via a network. Specifically, the network is connected via a communication interface in each computing device. In this type of possible implementation, the memory 1106 in the computing device 1100A stores instructions for executing the functions of the determination module, the first replacement module, the first update module, and the switching module. At the same time, the memory 1106 in the computing device 1100B stores instructions for executing the functions of the first allocation module, the second allocation module, and the second replacement module.

[0246] It should be understood that Figure 7 The functions of the computing device 1100A shown in FIG. 1100A may also be completed by multiple computing devices 1100. Similarly, the functions of the computing device 1100B may also be completed by multiple computing devices 1100.

[0247] The present application embodiment also provides another computing device cluster. The connection relationship between the computing devices in the computing device cluster can be similar to that of Figure 5 and Figure 7 The connection mode of the computing device cluster is different in that the memory 1106 in one or more computing devices 1100 in the computing device cluster may store the same instructions for executing the memory management method.

[0248] In some possible implementations, the memory 1106 of one or more computing devices 1100 in the computing device cluster may also store some instructions for executing the memory management method. In other words, the combination of one or more computing devices 1100 may jointly execute the instructions for executing the memory management method.

[0249] It should be noted that the memory 1106 in different computing devices 1100 in the computing device cluster may store different instructions for executing part of the functions of the memory management device. That is, the instructions stored in the memory 1106 in different computing devices 1100 may implement the functions of one or more devices in the memory management device.

[0250] The present application also provides a computer program product including instructions. The computer program product may be software or a program product including instructions that can be run on a computing device or stored in any available medium. When the computer program product is run on at least one computing device, the at least one computing device executes the memory management method in the above embodiment.

[0251] The embodiment of the present application also provides a computer-readable storage medium. The computer-readable storage medium can be any available medium that can be stored by a computing device or a data storage device such as a data center containing one or more available media. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk). The computer-readable storage medium includes instructions that instruct the computing device to execute the memory management method in the above embodiment.

[0252] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the protection scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, characterized in that: The method comprises: Determine a first memory page that is a hot page and an abnormal memory page, wherein the abnormal memory page is used to indicate a memory page that cannot be normally accessed by the mapped physical memory; replacing the second memory resource in the second memory page with the first memory resource in the first memory page, wherein the second physical memory mapped by the second memory page can be accessed normally; Updating the second memory page to a hot page; Updating the first memory page to a cold page or a free page; The memory resource access range allocated to the application is mapped to the second physical memory.

2. The method according to claim 1, characterized in that The determining of the first memory page belonging to the hot page includes: Acquire a first physical access range, wherein the physical memory within the first physical access range cannot be normally accessed; Determine a page address list of the abnormal memory pages corresponding to the first physical access range; Based on the page address list, a first memory page that is a hot page among the abnormal memory pages is determined.

3. The method according to claim 2, characterized in that The step of determining the first memory page that is a hot page also includes: Based on the page address list, regularly check whether there are abnormal memory pages in the hot page list; The abnormal memory page in the hot page list is used as the first memory page.

4. The method according to claim 2 or 3, characterized in that: The step of determining the first memory page that is a hot page also includes: When receiving information indicating that the currently accessed memory page is the abnormal memory page, the currently accessed memory page is determined to be a hot page and a first memory page that is an abnormal memory page.

5. The method according to any one of claims 2 to 4, characterized in that The mapping the memory resource access range allocated to the application to the second physical memory includes: The physical memory mapped to the memory resource access range allocated to the application is switched from the first physical memory to the second physical memory, wherein the first physical memory is the physical memory mapped to the first memory page.

6. The method according to any one of claims 2 to 4, characterized in that The step of determining the first memory page that is a hot page also includes: Determine a first free page currently allocated to the application, wherein the first free page belongs to the abnormal memory page; The first free page is determined as a first memory page belonging to a hot page.

7. The method according to claim 6, characterized in that The second memory page is a cold page before being updated to a hot page, and the first memory page is updated to a cold page.

8. The method according to claim 6 or 7, characterized in that: The replacing the second memory resource in the second memory page with the first memory resource in the first memory page includes: The second memory resource in the second memory page is transferred to the first memory page.

9. The method according to any one of claims 6 to 8, characterized in that The method further comprises: Based on the page address list, when it is determined that the number of free pages that do not belong to the abnormal memory page is less than a preset threshold, the first free page that belongs to the abnormal memory page is allocated to the application.

10. The method according to claim 9, characterized in that The method further comprises: Based on the page address list, when it is determined that the number of free pages that do not belong to the abnormal memory page is greater than or equal to the preset threshold, the free pages that do not belong to the abnormal memory page are allocated to the application.

11. The method according to any one of claims 1 to 10, characterized in that Before the memory resources in the second memory page are replaced with the memory resources in the first memory page, the second memory page is a cold page; Before updating the second memory page to a hot page and before updating the first memory page to a cold page, the method further includes: The first memory resource in the first memory page is replaced with the second memory resource in the second memory page.

12. The method according to any one of claims 2 to 11, characterized in that The obtaining of the first physical access range includes: A first physical access range associated with a correctable error CE is obtained.

13. The method according to claim 12, characterized in that The obtaining of the first physical access range includes: When a CE is detected, a first physical access range associated with the CE is obtained.

14. A memory management device, characterized in that: The device comprises: A determination module, used to determine a first memory page that is a hot page and an abnormal memory page, wherein the abnormal memory page is used to indicate a memory page that cannot be normally accessed by the mapped physical memory; A first replacement module, used to replace a second memory resource in a second memory page with a first memory resource in the first memory page, wherein a second physical memory mapped by the second memory page can be normally accessed; A first update module, used for updating the second memory page to a hot page; A second update module, used for updating the first memory page to a cold page or a free page; The switching module is used to map the memory resource access range allocated to the application to the second physical memory.

15. A computing device cluster, characterized in that: comprising at least one computing device, each computing device comprising a processor and a memory; The processor of the at least one computing device is configured to execute instructions stored in the memory of the at least one computing device, so that the computing device cluster executes the method according to any one of claims 1 to 13.

16. A computer program product comprising instructions, characterized in that When the instructions are executed by a computing device cluster, the computing device cluster is caused to perform the method according to any one of claims 1 to 13.

17. A computer-readable storage medium, characterized in that: The method comprises computer program instructions. When the computer program instructions are executed by a computing device cluster, the computing device cluster performs the method according to any one of claims 1 to 13.

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