An access method and related apparatus

Abstract

Embodiments of the present specification provide an access method applied to a first node in a target system, each first node in the target system comprising a processor and a first memory, when the access method is implemented, if a certain first node (i.e. a local node) initiates an access request for a target address in a remote memory of a remote node, after executing a first operation, a second operation is executed after a target time, the target time is randomly generated by the local node, or the target time corresponds to an associated node (the local node and the remote node), in this way, by delaying the target time after the first operation, the position factor of different local nodes accessing the remote memory in the same remote node is weakened, the problem that the access success rate of the first node to the remote memory of a certain or certain remote node is always low is avoided, and the fairness of atomic operation (i.e. the first operation and the second operation) is improved.

Description

TECHNICAL FIELD

[0001] The present specification relates to the technical field of computer application, in particular, to a memory access technology under a NUMA (Non-Uniform Memory Access) architecture, and more particularly, to an access method and related apparatus. BACKGROUND

[0002] NUMA (Non-Uniform Memory Access) architecture is a kind of multiprocessor architecture, and in the NUMA architecture, there can be multiple nodes, each node including one or a group of processors and its own local memory.

[0003] The memory in each node in the NUMA architecture can have two different and opposite attributes, namely, shareable normal memory (Shareable Normal memory) and non-shareable normal memory (Non-shareable Normal memory), and the shareable normal memory can be accessed by the processors of other nodes in the NUMA architecture. In order to maintain the synchronization of shared data in the shareable normal memory, atomic operations can be introduced to ensure that a thread does not complete the access to the shareable normal memory before being interrupted by other operations, thereby avoiding the situation that multiple threads access the shareable normal memory at the same time.

[0004] However, due to the different distribution areas of different nodes, for the same shared memory, there can be a situation that the access success rate of certain nodes to the shared memory is always low, resulting in unfairness of atomic operations. SUMMARY

[0005] The embodiments of the present specification provide an access method and related apparatus to solve the problem that the access success rate of a first node to the remote memory of a certain or certain remote node is always low, and to improve the fairness of atomic operations.

[0006] To achieve the above technical purposes, the embodiments of the present specification provide the following technical solutions:

[0007] In a first aspect, one embodiment of the present specification provides an access method applied to a first node in a target system, wherein the target system includes a plurality of first nodes, and the first node includes a processor and a first memory; the access method includes:

[0008] In response to an access request for a target address, performing an access operation, wherein the target address is located in a remote memory of a remote node, the remote node includes other first nodes outside a local node, and the remote memory includes a first memory of the remote node; the local node includes the first node performing the access operation;

[0009] The access operation comprises:

[0010] performing a first operation for registering an exclusive access intention for the target address to the remote node, so that the remote node sets an exclusive access mark corresponding to the processor of the local node;

[0011] after delaying a target time, performing a second operation for accessing the target address when there is an exclusive access mark corresponding to the processor of the local node; the target time is randomly generated by the local node, or the target time corresponds to associated nodes including the local node and the remote node.

[0012] In a second aspect, an embodiment of the present specification provides a communication system comprising a plurality of first nodes, the first nodes comprising processors and first memories;

[0013] The first nodes are configured to:

[0014] in response to an access request for a target address, performing an access operation, the target address being located in a remote memory of a remote node, the remote node comprising other first nodes outside the local node, the remote memory comprising the first memory of the remote node; the local node comprising the first node performing the access operation;

[0015] The access operation comprises:

[0016] performing a first operation for registering an exclusive access intention for the target address to the remote node, so that the remote node sets an exclusive access mark corresponding to the processor of the local node;

[0017] after delaying a target time, performing a second operation for accessing the target address when there is an exclusive access mark corresponding to the processor of the local node; the target time is randomly generated by the local node, or the target time corresponds to associated nodes including the local node and the remote node.

[0018] In a third aspect, an embodiment of the present specification also provides a computing device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor implements the access method as described above when executing the computer program.

[0019] In a fourth aspect, an embodiment of the present specification also provides a computer readable storage medium, and the computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the access method described above.

[0020] In a fifth aspect, an embodiment of the present specification provides a computer program product or a computer program, and the computer program product includes a computer program, and the computer program is stored in a computer readable storage medium; the processor of the computer device reads the computer program from the computer readable storage medium, and the processor implements the steps of the access method described above when executing the computer program.

[0021] From the above technical solution, it can be seen that the access method provided by the embodiment of the present specification is applied to the first node in the target system, each first node in the target system includes a processor and a first memory, and when the access method is implemented, if a certain first node (i.e. a local node) initiates an access request for a target address in the remote memory of a remote node, a second operation is executed after a delay of a target time after a first operation, and the target time is randomly generated by the local node, or the target time corresponds to an associated node (the local node and the remote node). In this way, by delaying the target time after the first operation, the position factor of different local nodes accessing the remote memory in the same remote node is weakened, and the problem that the access success rate of the first node to the remote memory of a certain or certain remote node is always low is avoided, and the fairness of atomic operation (i.e. the first operation and the second operation) is improved. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present specification or the prior art, the drawings needed in the embodiment or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only embodiments of the present specification, and those skilled in the art can obtain other drawings according to the provided drawings without creative labor.

[0023] Figure 1 A structural schematic diagram of a communication system provided by an embodiment of the present specification is shown in the figure;

[0024] Figure 2 A flowchart of an access method provided by an embodiment of the present specification is shown in the figure;

[0025] Figure 3 An illustration of different local nodes accessing the same remote node provided by an embodiment of the present specification is shown in the figure;

[0026] Figure 4A first target matrix display mode schematic diagram provided for an embodiment of the present specification;

[0027] Figure 5 A structure schematic diagram of a computing device provided for an embodiment of the present specification. DETAILED DESCRIPTION

[0028] Unless otherwise defined, technical terms or scientific terms used in the embodiments of the present specification shall be understood as having the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments of the present specification belong. The terms "first", "second" and similar words used in the embodiments of the present specification do not represent any order, number or importance, but are only set to avoid confusion of the constituent elements.

[0029] Unless otherwise required by the context, throughout the specification, "a plurality" means "at least two", "includes" is interpreted as an open, inclusive meaning, i.e. "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" and the like are intended to mean that the specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of the specification. The illustrative representation of the above terms does not necessarily mean the same embodiment or example.

[0030] The technical solutions in the embodiments of the present specification will be described clearly and completely in combination with the drawings in the embodiments of the present specification. Obviously, the described embodiments are only part of the embodiments of the present specification, not all. Based on the embodiments in the present specification, all other embodiments obtained by those of ordinary skill in the art without creative labor are within the scope of protection of the present specification.

[0031] SUMMARY

[0032] The traditional SMP (Symmetric Multi-Processor) architecture is a multi-processor architecture, all processors share the same memory and bus resources, and each processor can access the entire system memory space. However, the SMP architecture has poor scalability, and as the number of processors increases, the memory bandwidth may become a bottleneck, resulting in performance degradation. In order to solve this problem, the NUMA architecture with its own local memory for each processor or a group of processors has emerged, when it is necessary to expand the storage capacity or the number of processors, it can be realized by increasing the nodes, and the scalability is strong. Reference Figure 1 , Figure 1 A feasible NUMA architecture is shown, in Figure 1In some embodiments, each of the different first nodes (first node 0 and first node 1) can each include a processor and a first memory (Memory). The number of processors in each of the first nodes can be one or more, and the number of processors in each of the first nodes can be the same or different. The number of processor cores (e.g., CPU0 and CPU1) included in each processor can be one or more, and the number of processor cores included in each processor can be the same or different. The present specification does not limit this.

[0033] In some embodiments, the processor can further include a local monitor, and the first node can further include a network-on-chip (NOC), and the NOC can include a global monitor. As described above, in the NUMA architecture, the first memory in each first node can include shared memory and non-shared memory, where the shared memory can be accessed by the processors in multiple first nodes, and the non-shared memory can be accessed by the processors local to the first node.

[0034] To distinguish the first node that sends an access request and the first node in which the first memory that is requested to be accessed is located, the first node that sends an access request can be referred to as a local node, and the first node that includes the first memory in which the target address that is requested to be accessed is located can be referred to as a remote node. The first memory in the remote node can be referred to as a remote memory.

[0035] If the processor wants to perform exclusive access to the non-shared memory of the local first memory, only the local monitor inside the local processor in the local node (i.e., the first node in which the processor that performs the specific access operation is located) needs to be operated. If the processor wants to access the shared memory of the remote memory in the other first node (i.e., the remote node), in addition to involving the local monitor inside the processor in the local node, since the shared memory can be accessed by the processors in other first nodes in the system, the global monitor also needs to be coordinated.

[0036] In some embodiments, when a processor of a local node accesses a shared memory of a remote node, the processor may call a first operation to access a certain segment of shared memory. At this time, the global monitor will set an exclusive access mark for the processor. When the processor calls a second operation to access the shared memory segment, if the exclusive access mark for the processor still exists, the shared memory can be accessed. After the access is completed, the global monitor will clear the exclusive access marks of all processors that have applied for exclusive use of the shared memory segment. If the exclusive access mark for the processor no longer exists when the processor calls the second operation to access the shared memory segment, it indicates that other processors have already performed access operations on the shared memory segment between the processor calling the first operation and the second operation. At this time, the processor fails to call the second operation to access the shared memory segment, and needs to re-call the first operation to set the exclusive access mark corresponding to the processor for the shared memory segment.

[0037] The first operation mentioned above includes but is not limited to a Load-Linked operation (LL operation for short), and the second operation mentioned above includes but is not limited to a Store-Conditional operation (SC operation for short). The first operation and the second operation together implement atomic operations for shared memory. The LL operation can load a value from memory into a register and mark the corresponding memory location as "linked". The SC operation can attempt to store a value to a memory location previously loaded by the LL operation. If no other write operations have occurred on the memory location since the load, the SC operation succeeds and the memory location will be updated. Otherwise, the SC operation fails and may need to be retried.

[0038] In the NUMA architecture, the processors and first memories in the system are distributed between different first nodes (or areas). Each first node has its own local first memory. If a processor needs to access the remote memory in a remote node, a relatively high delay will occur. When different first nodes initiate access to the remote memory in the same remote node, due to the different distances to the remote memory, the access success rate of the processors in one or some first nodes to the remote memory may remain at a low level, resulting in unfair atomic operations.

[0039] In order to solve this problem, the inventors have found that for a target system including multiple first nodes (for example, Figure 1In the NUMA architecture-based system shown, when a first node (local node) in the target system needs to access a remote memory in another first node (remote node) across nodes, the processor of the local node can delay the execution of a second operation after the execution of a first operation for a target time, which can be randomly generated by the local node. In this way, each first node will delay for a random time before actually accessing the memory, avoiding the situation where the success rate of access to the memory by a certain first node is consistently low, which is conducive to improving the fairness of atomic operations.

[0040] In addition, the target time can also correspond to an associated node, which includes the local node and the remote node. In this way, the target time can be adaptively adjusted according to different associated nodes, so that the access delay of different first nodes to the remote memory of the remote node is basically the same, avoiding the situation where the success rate of access to the memory by a certain first node is consistently low, which is conducive to improving the fairness of atomic operations.

[0041] When the target time corresponds to the associated node, a first target matrix of access parameters including the correspondence between each two first nodes and access delay, and / or a second target matrix including the correspondence between each first node and the success rate of accessing the remote memory can be collected in advance. Based on the associated node, the first target matrix and / or the second target matrix are queried to obtain an access parameter, which can include at least one of a first parameter and a second parameter. The first parameter includes the success rate of the local node accessing the remote memory, and the second parameter includes the access delay of the local node and the remote node. After obtaining the access parameter, a more accurate target time can be determined based on the access parameter to compensate for the access delay of different first nodes to the remote memory, so as to ensure that the access delay of different first nodes to the remote memory is basically consistent.

[0042] Based on the above concept, the embodiments of the present specification provide an access method, which will be exemplarily described below with reference to the accompanying drawings.

[0043] Exemplary method

[0044] For example, the access method provided by the embodiments of the present specification can be applied to a NUMA architecture-based system as shown. Figure 2 Taking the first node shown as an example, the embodiments of the present specification provide an access method, Figure 2 The target system in the access method includes a plurality of first nodes, each first node including a processor and a first memory. The access method includes:

[0045] S201: in response to an access request for a target address, performing an access operation, the target address being located in a remote memory of a remote node, the remote node comprising a first node other than a local node, the remote memory comprising a first memory of the remote node; the local node comprising the first node performing the access operation;

[0046] In the embodiment, the first node that needs to access the target address is referred to as the local node, and the first node where the first memory of the target address is located, or the first node that the local node needs to access, is referred to as the remote node. As described above, when the local node accesses the remote node, there may be a problem that the success rate of access of one or more local nodes to the remote node is low for a long time due to different distances between different local nodes and the remote node, different processor performances in different local nodes, and the like. Therefore, the access method provided in the embodiments of the present specification is dedicated to solving the above problem, and the process of the processor in the first node accessing the local first memory can refer to the process in the related art.

[0047] The access operation comprises:

[0048] S2011: performing a first operation, the first operation being used for registering an exclusive access intention for the target address to the remote node, so as to make the remote node set an exclusive access mark corresponding to the processor of the local node;

[0049] Optionally, as described above, the first operation can comprise an LL operation. Specifically, the LL operation can load a value from the memory into the register and mark the corresponding memory location as "linked", so as to achieve the purpose of registering the exclusive access intention for the target address to the remote node.

[0050] S2022: after delaying a target time, performing a second operation, the second operation being used for accessing the target address when there is an exclusive access mark corresponding to the processor of the local node; the target time being randomly generated by the local node, or the target time corresponding to an associated node, the associated node comprising the local node and the remote node.

[0051] After the first node performs the first operation, the second operation is performed after a delay target time, and optionally, the second operation can include an SC operation. The SC operation can attempt to store a value to a memory location previously loaded by the LL operation, and if no other write operation has occurred on the memory location since the LL operation loaded it, the store operation succeeds and the memory location is updated (the update can be clearing all processor corresponding exclusive access markers). Otherwise, the store operation fails and can need to be retried. In some embodiments, the LL operation can use a LDXR (Load-Exclusive) instruction, and the SC operation can use a STXR (Store-Exclusive) instruction.

[0052] From the above description of the LL operation and the SC operation, it is not difficult to find that, as shown in Figure 3 For the same remote node, if different local nodes (local node 1 and local node 2) initiate access to the remote memory in the remote node at the same time, since the local node 1 is closer to the remote node, the data transmission delay between the local node 1 and the remote node is generally smaller, and thus after the local node 1 and the local node 2 perform the LL operation, when the local node 1 performs the SC operation, the local node 2 can not have started to perform the SC operation (or the instruction of performing the SC operation has not been received by the remote node), at this time, the exclusive access marker corresponding to the processor of the local node 1 in the remote memory loaded by the LL operation of the local node 1 exists, the SC operation is successfully implemented, the access to the target address is achieved, and all exclusive access markers are cleared; then, when the local node 2 performs the SC operation, since the local node 1 has cleared all exclusive access markers, the local node 2 fails to perform the SC operation and needs to perform the LL operation again to load the exclusive access marker corresponding to the processor in the local node 2 to the target address before performing the SC operation. If the access requirements of the local node 1 and the local node 2 for the remote memory are highly consistent, the local node 2 can be unable to access the remote memory for a long time.

[0053] Therefore, in the present embodiment, after the first node performs the first operation, the second operation is performed after a delay target time, and the target time can be randomly generated, so that each first node accesses the memory after a random delay, avoiding the situation that the access success rate of a certain first node to the memory is continuously low, which is beneficial to improve the fairness of atomic operations.

[0054] In addition, the target time can also correspond to an associated node including the local node and the remote node, so that the target time can be adaptively adjusted according to different associated nodes, so that the access delay of different first nodes to the remote memory of the remote node is basically the same, avoiding the case that the access success rate of a certain first node to the memory is continuously low, and being beneficial to improving the fairness of atomic operation.

[0055] When the target time corresponds to the associated node, one embodiment of the present specification provides a process for determining the target time, specifically, the process includes:

[0056] According to the target address, determining the remote node;

[0057] Based on the access parameter corresponding to the associated node, determining the target time, the access parameter including at least one of a first parameter and a second parameter, the first parameter including: the success rate of the local node accessing the remote memory, the second parameter including: the access delay of the local node and the remote node.

[0058] In the present embodiment, in order to accurately determine the target time so that the total delay of different local nodes accessing the same remote node is basically the same, the target time can be determined based on the access parameter corresponding to the associated node, so that the total delay time of each local node to the same remote node after the delay target time is basically the same, ensuring that the access success rate of different local nodes to the remote node is basically the same, avoiding the problem that the access success rate of a certain or certain local node to a certain remote node is continuously low.

[0059] The following is an exemplary description of how to determine the target time when the access parameter includes different parameter types.

[0060] For example, in one embodiment, the access parameter includes the second parameter;

[0061] The determination of the target time based on the access parameter corresponding to the associated node includes:

[0062] Based on the associated node, querying a first target matrix to obtain the second parameter;

[0063] Based on the second parameter, determining the target time;

[0064] The first target matrix includes the corresponding relationship between each two first nodes and access delay.

[0065] In the present embodiment, the first target matrix as shown in Figure 4 can be obtained by collecting the corresponding relationship between each two first nodes and access delay.Figure 4 In [1], Numa0-n represents the 0th to nth first nodes, and Delay (ns) represents the access delay (in nanoseconds) between each two first nodes. The access delay can refer to the delay caused by transmitting instructions or information through a communication link of a certain length, or the time required for instructions or information to be transmitted between different first nodes. The first target matrix can be obtained by testing each pair of first nodes using a memory delay test tool.

[0066] In actual application, the first target matrix can be queried based on the associated node to obtain the second parameters corresponding to the local node and the remote node. Specifically, assuming that the local node is Numa0 and the remote node is Numa1, the second parameter corresponding to when Numa0 accesses Numa1 can be obtained by looking up the table in the first target matrix.

[0067] After obtaining the second parameter, the second parameter may be determined as the target time, or the target time may be obtained after processing the second parameter. This specification does not limit this, and the specific method depends on the actual situation.

[0068] In this embodiment, the second parameter is obtained by looking up a table, and the target time is determined based on the second parameter. This allows the determined target time to be associated with the second parameter, which is beneficial for compensating for the delay caused by the distance difference between different first nodes and remote nodes, and is beneficial for ensuring that the access success rate of different first nodes to the same remote node is basically the same.

[0069] Also for example, in another embodiment, the access parameter includes the first parameter;

[0070] The determining the target time based on the access parameter corresponding to the associated node includes:

[0071] Based on the associated node, query a second target matrix to obtain the first parameter;

[0072] determining the target time based on the first parameter, wherein the target time is positively correlated with a success rate of accessing the remote storage;

[0073] The second target matrix includes a correspondence between each of the first nodes and a success rate of accessing the remote memory.

[0074] Similarly, in this embodiment, the second target matrix can be obtained by collecting the success rates of each first node accessing the same remote storage. Referring to Table 1, Table 1 shows a feasible representation of the second target matrix.

[0075] Table 1 Second target matrix

[0076] Numa0 Numa1 Numa2 …… Numan Numa0 Rate (%) Rate (%) Rate (%) Rate (%) Numa1 Rate (%) Rate (%) Rate (%) Rate (%) Numa2 Rate (%) Rate (%) Rate (%) Rate (%) …… Rate (%) Rate (%) Rate (%) Rate (%) Numan Rate (%) Rate (%) Rate (%) Rate (%)

[0077] In Table 1, Numa0-n represents the 0th- nth first node, Rate(%) represents the success rate of one first node accessing another first node (expressed in %), wherein the first node in the first row is taken as the local node, and the first node in the first column is taken as the remote node, for example, for the second row and the third column, the Rate(%) therein represents the success rate of Numa1 accessing Numa0. The success rate can be equal to the proportion of the successfully implemented second operations in the total number of second operations, for example, assuming that in a period of time, the total number of second operations implemented by Numa1 accessing the remote memory in Numa0 is 100, and the number of successfully implemented second operations is 30, then the success rate of Numa1 accessing Numa0 can be calculated as 30 / 100 = 30%. The second target matrix can be obtained by collecting historical data or by testing in the manner of a testing tool.

[0078] In actual application, the second target matrix can be queried based on the associated nodes to obtain the first parameter corresponding to the local node and the remote node, specifically, assuming that the local node is Numa0 and the remote node is Numa1, the first parameter corresponding to Numa0 accessing Numa1 can be obtained by table lookup in the second target matrix.

[0079] After obtaining the first parameter, the target time positively correlated with the first parameter can be determined based on the first parameter, specifically, assuming that the success rates of Numa1 and Numa2 accessing Numa0 are 30% and 90% respectively, the target time of Numa1 accessing Numa0 can be positively correlated with 30%, for example, it can be 30ns, and the target time of Numa2 accessing Numa0 can be positively correlated with 90%, for example, it can be 90ns, in this way, by adding a longer delay time (90ns) for Numa2 accessing Numa0 and a shorter delay time (30ns) for Numa1 accessing Numa0, the success rates of Numa2 and Numa1 accessing Numa0 can be pulled to a substantially same level, thereby avoiding the situation that Numa1 cannot successfully access Numa0 for a long time when Numa2 and Numa1 access Numa0 at the same time.

[0080] For another example, in yet another embodiment, a method for determining the target time by comprehensively considering the first parameter and the second parameter is given, specifically, the determining the target time based on the access parameter corresponding to the associated node comprises:

[0081] obtaining a first time corresponding to the first parameter based on the first parameter;

[0082] Based on the second parameter, obtaining a second time corresponding to the second parameter;

[0083] The target time is obtained based on the first time, the second time, the weights corresponding to the first parameter and the second parameter.

[0084] In this embodiment, after obtaining the first parameter and the second parameter, the first time and the second time can be obtained based on the first parameter and the second parameter, respectively. The first parameter and the second parameter can also each be assigned different weights. Subsequently, the target time can be obtained by performing a weighted summation based on the first time, the second time, and the weights corresponding to the first parameter and the second parameter. In this way, different weights can be assigned to the first parameter and the second parameter, respectively, so that the target time can be determined by comprehensively considering the first parameter and the second parameter.

[0085] For example, assuming that the weights corresponding to the first parameter and the second parameter are 0.3 and 0.7 respectively, and the first time and the second time are 30ns and 20ns respectively, the target time obtained by weighted summation may be equal to 0.3×30ns+0.7×20ns=23ns.

[0086] In one embodiment, a feasible method for delaying a target time is provided. Specifically, the delaying a target time includes:

[0087] Determining an execution duration based on a target parameter of a processor of the local node, where the execution duration includes a duration required for the processor of the local node to execute a single target instruction;

[0088] Determining a target number of instructions based on the target time and the execution duration;

[0089] Based on the determined number of target instructions, a plurality of the target instructions are executed, wherein the target instructions correspond to no operations.

[0090] In the embodiment, the execution duration is determined by the target parameter of the processor of the local node, which includes but is not limited to the processor frequency, so that the accurate execution duration can be determined based on the specific situation of each processor, and then the target instruction quantity to be executed for delaying the target time is determined based on the accurate execution duration, so that the purpose of accurately delaying the target time duration can be achieved by executing a plurality of target instructions. The target instruction includes but is not limited to the NOP (No Operation, No Operation or Empty Operation) instruction, and the target instruction can be executed to delay the unit time (i.e. the execution duration) without affecting the instructions of other normal tasks of the processor. For example, assuming that the execution duration of the target instruction of the processor A is 2ns, when the target time duration is 30ns, 15 target instructions need to be executed to delay 30ns. For the processor B, assuming that the execution duration of the target instruction is 3ns, when the target time duration is 30ns, 10 target instructions need to be executed to delay 30ns.

[0091] Exemplary apparatus

[0092] In one example embodiment of the present specification, an access device is also provided, which is applied to a first node in a target system, the target system including a plurality of first nodes, the first node including a processor and a first memory; the access device includes:

[0093] an operation delay module, configured to execute an access operation in response to an access request for a target address, the target address being located in a remote memory of a remote node, the remote node including other first nodes outside the local node, and the remote memory including a first memory of the remote node; the local node including the first node executing the access operation;

[0094] The access operation includes:

[0095] performing a first operation, the first operation being configured to register an exclusive access intention for the target address to the remote node, so that the remote node sets an exclusive access mark corresponding to the processor of the local node;

[0096] after delaying a target time, performing a second operation, the second operation being configured to access the target address when there is an exclusive access mark corresponding to the processor of the local node; the target time is randomly generated by the local node, or the target time corresponds to an associated node, the associated node including the local node and the remote node.

[0097] The specific limitation of the access device can refer to the limitation of the access method in the foregoing, which will not be repeated here. Each module in the access device described above can be implemented by software, hardware, and a combination thereof, in whole or in part. The above-mentioned modules can be embedded in or independent of the processor in the computer device in hardware form, or can be stored in the memory in the computer device in software form, so that the processor calls and executes the operations corresponding to each of the above modules.

[0098] Exemplary device

[0099] One embodiment of the present specification also provides a communication system, which refers to Figure 1 , comprising a plurality of first nodes, the first nodes comprising a processor and a first memory;

[0100] The first node is configured to:

[0101] In response to an access request for a target address, perform an access operation, the target address being located in a remote memory of a remote node, the remote node comprising other first nodes outside a local node, and the remote memory comprising a first memory of the remote node; the local node comprising the first node performing the access operation;

[0102] The access operation comprises:

[0103] Performing a first operation, the first operation being used to register an exclusive access intention for the target address to the remote node, so that the remote node sets an exclusive access mark corresponding to the processor of the local node;

[0104] After a target time, performing a second operation, the second operation being used to access the target address when there is an exclusive access mark corresponding to the processor of the local node; the target time being randomly generated by the local node, or the target time corresponding to an associated node, the associated node comprising the local node and the remote node.

[0105] Optionally, the first node further comprises a global monitor;

[0106] The global monitor is configured to: in response to the first operation, set a corresponding exclusive access mark for the processor performing the first operation; and in response to the access operation for the target address, clear the exclusive access mark of all the processors for the target address.

[0107] The related limitation of the access method implemented by the first node in the communication system can refer to the related description in the foregoing, which will not be repeated here.

[0108] Another embodiment of the present application also proposes a computing device, which refers toFigure 5 As shown, one of the example embodiments of the present specification also provides a computing device, comprising: a memory and a processor, the memory storing a computer program, and the processor executing the computer program to perform the steps in the access method according to various embodiments of the present specification described in the above embodiments of the present specification.

[0109] The internal structure of the computing device can be as shown in Figure 5 As shown, the computing device comprises a processor, a memory, a network interface and an input device connected through a system bus. Among them, the processor of the computing device is used to provide computing and control capabilities. The memory of the computing device comprises a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operating system and the computer program in the non-volatile storage medium to run. The network interface of the computing device is used to communicate with the external terminal through the network connection. The computer program is executed by the processor to perform the steps in the access method according to various embodiments of the present specification described in the above embodiments of the present specification.

[0110] The processor can include a main processor, and can also include a baseband chip, a modem, etc.

[0111] The memory stores programs for executing the technical solutions of the present application, and can also store operating systems and other key services. Specifically, the program can include program code, and the program code includes computer operation instructions. More specifically, the memory can include read-only memory (ROM), other types of static storage devices that can store static information and instructions, random access memory (RAM), other types of dynamic storage devices that can store information and instructions, disk storage, flash, etc.

[0112] The processor can be a general-purpose processor, such as a general-purpose central processing unit (CPU), a microprocessor, etc., or an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of programs of the present application. It can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a ready-to-use programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component.

[0113] The input device can include devices that receive data and information input by the user, such as a keyboard, a mouse, a camera, a scanner, a light pen, a voice input device, a touch screen, a pedometer or a gravity sensor, etc.

[0114] The output device can include any device that allows output of information such as displays, printers, speakers, etc.

[0115] The communication interface can include any device that uses a transceiver to communicate with other devices or communication networks such as Ethernet, Radio Access Network (RAN), Wireless Local Area Network (WLAN), etc.

[0116] The processor executes the program stored in the memory and invokes other devices, which can be used to implement each step of any access method provided by the embodiments of the present application.

[0117] The computing device can also include a display component and a voice component, the display component can be a liquid crystal display or an electronic ink display, and the input device of the computing device can be a touch layer overlaid on the display component, or can be a key, trackball or touchpad arranged on the housing of the computing device, or can be an external keyboard, touchpad or mouse, etc.

[0118] Those skilled in the art can understand that, Figure 5 The structure shown in the figure is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the computing device to which the scheme of the present application is applied. A specific computing device can include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0119] Exemplary computer program product and storage medium

[0120] In addition to the above method and device, the access method provided by the embodiments of the present application can also be a computer program product, which includes computer program instructions, and the computer program instructions make the processor execute the steps of the access method according to various embodiments of the present application described in the above "Exemplary Method" part of the present application when the processor runs.

[0121] The computer program product can be written in any combination of one or more programming languages to perform the operations of the embodiments of the present application, including object-oriented programming languages such as Java, C++, etc., and conventional procedural programming languages such as "C" language or similar programming languages. The program code can be executed entirely on the user computing device, partially on the user device, as an independent software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0122] In addition, the embodiment of the present specification also provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to perform the steps in the access method according to various embodiments of the present specification described in the above "exemplary method" part.

[0123] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing related hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when the computer program is executed, the processes of the above-mentioned embodiments of each method can be included. Any reference to memory, storage, database or other medium used in each embodiment provided by the present specification can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0124] Any combination of the technical features of the above embodiments can be made. In order to make the description simple, all possible combinations of each technical feature in the above embodiments are not described, however, as long as the combination of these technical features does not exist, it should be considered as the scope of the present specification.

[0125] The above embodiments only express several implementation manners of the present specification, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the solutions provided by the embodiments of the present specification. It should be noted that for those skilled in the art, without departing from the concept of the present specification, a number of modifications and improvements can be made, which are within the scope of protection of the present specification. Therefore, the protection scope of the present specification patent should be subject to the appended claims.

Claims

1. An access method, characterized in that: The method is applied to a first node in a target system, wherein the target system includes a plurality of first nodes, and the first node includes a processor and a first memory; the access method includes: In response to an access request for a target address, performing an access operation, wherein the target address is located in a remote memory of a remote node, the remote node includes a first node other than the local node, the remote memory includes a first memory of the remote node, and the local node includes the first node performing the access operation; The access operation includes: performing a first operation, the first operation being configured to register an exclusive access intention for the target address with the remote node, so that the remote node sets an exclusive access flag corresponding to the processor of the local node; After delaying the target time, a second operation is performed, wherein the second operation is used to access the target address when there is an exclusive access tag corresponding to the processor of the local node; the target time is randomly generated by the local node, or the target time corresponds to an associated node, and the associated node includes the local node and the remote node.

2. The method according to claim 1, characterized in that The process of determining the target time includes: Determining the remote node according to the target address; The target time is determined based on the access parameters corresponding to the associated node, where the access parameters include at least one of a first parameter and a second parameter, the first parameter including: a success rate of the local node accessing the remote memory, and the second parameter including: an access delay between the local node and the remote node.

3. The method according to claim 2, wherein: The access parameters include the second parameter; The determining the target time based on the access parameter corresponding to the associated node includes: Based on the associated node, query the first target matrix to obtain the second parameter; determining the target time based on the second parameter; The first target matrix includes a correspondence between every two of the first nodes and access delays.

4. The method according to claim 2, characterized in that The access parameters include the first parameter; The determining the target time based on the access parameter corresponding to the associated node includes: Based on the associated node, query a second target matrix to obtain the first parameter; determining the target time based on the first parameter, wherein the target time is positively correlated with a success rate of accessing the remote storage; The second target matrix includes a correspondence between each of the first nodes and a success rate of accessing the remote memory.

5. The method according to claim 2, characterized in that The determining the target time based on the access parameter corresponding to the associated node includes: Based on the first parameter, obtaining a first time corresponding to the first parameter; Based on the second parameter, obtaining a second time corresponding to the second parameter; The target time is obtained based on the first time, the second time, the weights corresponding to the first parameter and the second parameter.

6. The method according to any one of claims 1 to 5, characterized in that The target delay time includes: Determining an execution duration based on a target parameter of a processor of the local node, where the execution duration includes a duration required for the processor of the local node to execute a single target instruction; Determining a target number of instructions based on the target time and the execution duration; Based on the determined number of target instructions, a plurality of the target instructions are executed, wherein the target instructions correspond to no operations.

7. A communication system, characterized in that: comprising a plurality of first nodes, each of the first nodes comprising a processor and a first memory; The first node is configured to: In response to an access request for a target address, performing an access operation, wherein the target address is located in a remote memory of a remote node, the remote node includes a first node other than the local node, and the remote memory includes a first memory of the remote node; The local node includes a first node that performs the access operation; The access operation includes: performing a first operation, the first operation being configured to register an exclusive access intention for the target address with the remote node, so that the remote node sets an exclusive access flag corresponding to the processor of the local node; After delaying the target time, a second operation is performed, wherein the second operation is used to access the target address when there is an exclusive access tag corresponding to the processor of the local node; the target time is randomly generated by the local node, or the target time corresponds to an associated node, and the associated node includes the local node and the remote node.

8. The system according to claim 7, characterized in that The first node further includes: a global monitor; The global monitor is configured to: in response to the first operation, set a corresponding exclusive access flag for the processor executing the first operation; in response to an access operation to the target address, clear the exclusive access flags of all the processors to the target address.

9. A computing device, characterized in that The invention comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the access method according to any one of claims 1 to 6 when executing the computer program.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the access method according to any one of claims 1 to 6 is implemented.

Images