Signal processing chip with distance measurement, speed measurement and angle measurement functions

Abstract

The invention provides a signal processing chip with distance measurement, speed measurement and angle measurement functions, which can be applied to the technical field of information processing. The signal processing chip comprises a data input interface used for receiving to-be-processed data, a clock and a control signal; the data output interface is used for sending result data and verification information; the digital signal processing sub-module array is used for processing large-scale digital signal data in parallel; the instruction state machine is used for scheduling data transmission and operation resources on the chip; the preprocessing circuit is used for converting the format of the input digital signal; the algorithm data processing circuit is used for converting the data format of the input data information; the input data cache is used for storing input digital signal data; the data memory is used for storing operation data; the system bus is used for data transmission in the chip; the phase-locked loop is used for generating a main frequency clock for working of the chip. The chip can perform a high-speed parallel digital signal processing flow through programming.

Description

Technical Field

[0001] The present invention relates to the field of information processing technology, and in particular to a signal processing chip with distance measurement, speed measurement and angle measurement functions. Background Art

[0002] Currently, digital signal processing technology is developing at an unprecedented speed, especially in the field of calculating the distance, speed and angle of the detected target. Its core development needs focus on achieving faster calculation speed, expanding a wider detection range, and pursuing higher detection accuracy. In order to meet these urgent application needs, the research and development of signal processing chips with strong real-time performance and the ability to process massive data, and which must have the functions of distance measurement, speed measurement and angle measurement, has become the focus of industry research.

[0003] At present, most of these digital signal processing systems rely on field programmable gate arrays (FPGAs) or commercial digital signal processors (DSP) platforms. However, they are still unable to meet the above requirements. Limited by area, power consumption and resource allocation, these platforms have encountered many challenges in implementing digital signal processing algorithms for large amounts of data, making it difficult to deploy and implement them efficiently. In contrast, dedicated digital signal processing chips stand out with their large-scale, reconfigurable arrays of digital signal processing sub-modules. It can not only support large-scale processing tasks, but also show extremely high flexibility, providing a strong guarantee for coping with complex and changing signal processing needs. Summary of the invention

[0004] 1. Technical issues to be resolved

[0005] In order to solve the above-mentioned problems existing in the digital signal processing technology for calculating distance, speed and angle in the prior art, an embodiment of the present invention provides a signal processing chip with distance measurement, speed measurement and angle measurement functions. Through a parallel processing architecture based on a single instruction multiple data stream processing method, data is processed in the form of calling large-scale digital signal processing sub-modules, thereby effectively improving the support for large-scale processing tasks, and improving flexibility through reconfigurable digital signal processing sub-modules to support more types of signal processing algorithms.

[0006] (II) Technical solution

[0007] In view of the above problems, an embodiment of the present invention provides a signal processing chip with distance measurement, speed measurement and angle measurement functions.

[0008] According to a first aspect of the present invention, there is provided a signal processing chip with distance measurement, speed measurement and angle measurement functions, comprising: a data input interface, a data output interface, a digital signal processing submodule array, an instruction state machine, a preprocessing circuit, an algorithm data processing circuit, an input data cache, a data storage device, a system bus and a phase-locked loop, wherein the data input interface is used to receive digital signal data and algorithm data to be processed, a master clock and a control signal; the data output interface is used to send operation result data, operation intermediate data and state machine verification information; the digital signal processing submodule array is used to program parallel processing of large-scale digital signal data; the instruction state machine is used to execute input instruction codes, schedule The on-chip data transmission links and computing resources complete the corresponding processing tasks; the preprocessing circuit is used to convert the input digital signal into a data format that can be processed; the algorithm data processing circuit is used to convert the input data information into a data format that can be processed and stored by the system bus, wherein the data information includes algorithm parameters; the input data cache is used to store the input digital signal data processed by the preprocessing circuit; the data storage device is used to store the intermediate data of the operation, the result data of the operation, the algorithm parameters and the instruction code; the system bus is used for data transmission inside the chip, connecting the digital signal processing sub-module array and the data storage device; and the phase-locked loop is used to generate the main frequency clock of the chip according to the instruction configuration.

[0009] In some exemplary embodiments, the data input interface includes a digital signal interface, an algorithm data interface, a control signal interface and a master clock interface, wherein the digital signal interface is used to receive digital signals from the front end; the algorithm data interface is used to receive digital signal processing algorithm parameters, state machine instructions and intermediate data from external storage of the chip; and the control signal interface is used to control the chip global reset and state machine check selection.

[0010] In some exemplary embodiments, digital signal data is input from a digital signal interface, processed by a preprocessing circuit, and stored in an input data cache; algorithm parameters are input from an algorithm data interface, processed by an algorithm data processing circuit, and stored in a data storage device; and digital signal data and algorithm parameters are processed by a digital signal processing sub-module array to obtain processing results, which are stored in a data storage device and finally output to a host computer through an output interface via a system bus.

[0011] In some exemplary embodiments, the digital signal processing sub-module array includes: a frequency reduction and extraction filtering module, a pulse compression module, a Fourier transform module, a constant false alarm rate detection module and an angle detection module, wherein the frequency reduction and extraction filtering module is used to perform orthogonal down-conversion, finite impulse response and extraction filtering operations on the digital signal sequence; the pulse compression module is used to perform frequency domain related operations on the digital signal; the Fourier transform module is used to perform Fourier transform on the digital signal; the constant false alarm rate detection module is used to perform constant false alarm rate detection on the two-dimensional digital signal graph to remove false alarm points; the angle detection module is used to perform target angle information detection on the digital signal.

[0012] In some exemplary embodiments, the digital signal processing sub-module array includes multiple parallel digital signal processing sub-modules, each of which can independently process different computing tasks according to the control of the instruction state machine; and multiple digital signal processing sub-modules can perform collaborative calculations.

[0013] In some exemplary embodiments, the operation process of the digital signal processing sub-module array includes: repeatedly running the frequency reduction extraction filter module and the pulse compression module to obtain two-dimensional signal data; running the Fourier transform module and the constant false alarm rate detection module to obtain the distance and speed information of the target; and running the angle detection module to obtain the angle information of the target.

[0014] In some exemplary embodiments, the data storage device includes: a one-dimensional signal data storage for caching the results of the frequency reduction extraction filter; a two-dimensional signal data storage for accumulating the one-dimensional signal data after pulse compression processing; an algorithm parameter storage for storing the parameters required by each digital signal processing sub-module; and an instruction parameter storage for storing the algorithm instructions of the instruction state machine.

[0015] In some exemplary embodiments, the preprocessing circuit performs real-time preprocessing operations on the input digital signal within a single receiving cycle and writes it into the input data cache; at the beginning of the next receiving cycle, the frequency reduction and extraction filtering module in the digital signal processing sub-module array reads the data cache and writes the result into the one-dimensional signal data storage; the pulse compression module reads the one-dimensional signal data storage and writes the result into the two-dimensional signal data storage.

[0016] In some exemplary embodiments, at least one of the features is included: the preprocessing circuit converts the input digital signal into a data format that can be processed, including merging and accumulating the digital signals input by the digital signal interface, and converting the accumulated signals into a data format that can be processed; the algorithm data processing circuit converts the input data information into a data format that can be processed and stored by the system bus, including accumulating and rearranging the data information input by the algorithm data interface, and converting it into a data format that can be transmitted and stored by the system bus; in the data storage device, each type of data has an independent storage space.

[0017] In some exemplary embodiments, the instruction state machine implements a digital signal processing algorithm using a custom reduced instruction set, wherein the custom reduced instruction set includes computing instructions, data handling instructions, and instruction flow control instructions; and the custom reduced instruction set is stored in a data memory.

[0018] (III) Beneficial effects

[0019] It can be seen from the above technical solutions that the signal processing chip with distance measurement, speed measurement and angle measurement functions provided by the embodiments of the present invention has at least one of the following beneficial effects:

[0020] (1) The order and content of operations can be adjusted through instruction programming, allowing the hardware design to be reused in a flexible manner.

[0021] (2) Use a separate digital signal processing sub-module design to increase the amount of supported data while reducing chip power consumption.

[0022] (3) Storage for different purposes is independent of each other, which improves memory access speed and data throughput.

[0023] (4) The digital signal processing sub-module array processes different computing tasks separately in units of digital signal processing sub-modules, and multiple modules can perform collaborative computing. The supported data size to be processed is increased by increasing the number of sub-module computing units, and the flexibility is improved through the reconfigurable digital signal processing sub-module hardware design. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above contents and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0025] Figure 1 A schematic diagram of the structure of a signal processing chip with distance measurement, speed measurement and angle measurement functions according to an embodiment of the present invention is shown;

[0026] Figure 2A schematic diagram schematically shows the structural relationship between the digital signal processing submodule array and the data storage according to an embodiment of the present invention;

[0027] Figure 3 A schematic diagram schematically showing the operation sequence of the digital signal processing submodule according to an embodiment of the present invention; and

[0028] Figure 4 The diagram schematically shows the memory access relationship among modules in a digital signal receiving and processing cycle according to an embodiment of the present invention. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical scheme and advantages of the present invention more clearly understood, the present invention is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0030] Figure 1 The structure diagram of a signal processing chip with distance measurement, speed measurement and angle measurement functions according to an embodiment of the present invention is schematically shown.

[0031] like Figure 1As shown, a signal processing chip with distance measurement, speed measurement and angle measurement functions according to an embodiment of the present invention includes: a data input interface 10, a data output interface 20, a digital signal processing submodule array 30, an instruction state machine 40, a preprocessing circuit 50, an algorithm data processing circuit 60, an input data cache 70, a data storage device 80, a system bus 90 and a phase-locked loop 100, wherein the data input interface 10 is used to receive digital signal data and algorithm data to be processed, a master clock and a control signal; the data output interface 20 is used to send operation result data, operation intermediate data and state machine verification information; the digital signal processing submodule array 30 is used to program parallel processing of large-scale digital signal data; the instruction state machine 40 is used to execute input instruction codes, The data transmission links and computing resources on the scheduling chip complete the corresponding processing tasks; the preprocessing circuit 50 is used to convert the input digital signal into a data format that can be processed; the algorithm data processing circuit 60 is used to convert the input data information into a data format that can be processed and stored by the system bus 90, wherein the data information includes algorithm parameters; the input data cache 70 is used to store the input digital signal data processed by the preprocessing circuit 50; the data storage device 80 is used to store the intermediate data of the operation, the result data of the operation, the algorithm parameters and the instruction code; the system bus 90 is used for data transmission inside the chip, connecting the digital signal processing sub-module array 30 and the data storage device 80; and the phase-locked loop 100 is used to generate the main frequency clock of the chip according to the instruction configuration.

[0032] In the embodiment of the present invention, the data input interface 10 includes M digital signal interfaces 110, N algorithm data interfaces 120, P control signal interfaces 130 and 1 master clock interface 140, wherein M, N and P are all positive integers greater than 0. The digital signal interface 110 is used to receive digital signals from the front end; the algorithm data interface 120 is used to receive digital signal processing algorithm parameters, state machine instructions and intermediate data stored outside the chip; and the control signal interface 130 is used to control the chip global reset and state machine check selection.

[0033] In the embodiment of the present invention, the instruction state machine 40 uses a custom reduced instruction set to implement a digital signal processing algorithm, wherein the custom reduced instruction set includes calculation instructions, data handling instructions, and instruction flow control instructions; and the custom reduced instruction set is stored in the data memory 80. The operation order and content can be adjusted by instruction programming, and the hardware design can be reused in a flexible form.

[0034] In the embodiment of the present invention, the preprocessing circuit 50 converts the input digital signal into a processable data format, including merging and accumulating the digital signals input from the digital signal interface, and converting the accumulated signals into a processable data format; the algorithm data processing circuit 60 converts the input data information into a data format that can be processed and stored by the system bus 90, including accumulating and rearranging the data information input from the algorithm data interface, and converting it into a data format that can be transmitted and stored by the system bus 90; in the data storage 80, each type of data has an independent storage space. The storage for different purposes is independent of each other, which improves the memory access speed and data throughput.

[0035] In the embodiment of the present invention, digital signal data is input from the digital signal interface, processed by the preprocessing circuit 50 and stored in the input data cache 70, and algorithm parameters are input from the algorithm data interface, processed by the algorithm data processing circuit 60 and stored in the data storage. The digital signal data and algorithm parameters are processed by the digital signal processing submodule array 30 to obtain processing results, which are stored in the data storage 80 and finally output to the host computer through the output interface via the system bus 90.

[0036] Figure 2 The structure diagram schematically shows the interactive relationship between the digital signal processing sub-module array 30 and the data storage 80 according to an embodiment of the present invention.

[0037] like Figure 2 As shown, according to an embodiment of the present invention, the digital signal processing submodule array 30 includes: a frequency reduction extraction filter module 310, a pulse compression module 320, a Fourier transform module 330, a constant false alarm rate detection module 340 and an angle detection module 350, wherein the frequency reduction extraction filter module 310 is used to perform orthogonal down-conversion, finite impulse response and extraction filtering operations on the digital signal sequence; the pulse compression module 320 is used to perform frequency domain related operations on the digital signal; the Fourier transform module 330 is used to perform Fourier transform on the digital signal; the constant false alarm rate detection module 340 is used to perform constant false alarm rate detection on the two-dimensional digital signal diagram to remove false alarm points; the angle detection module 350 is used to perform target angle information detection on the digital signal.

[0038] In the embodiment of the present invention, the digital signal processing submodule array 30 includes a plurality of parallel digital signal processing submodules, each of which can independently process different computing tasks; and a plurality of digital signal processing submodules can coordinate computing. The use of a separate digital signal processing submodule design can increase the amount of supported data while reducing chip power consumption.

[0039] Figure 3 The schematic diagram schematically shows the operation sequence of the digital signal processing submodule according to an embodiment of the present invention.

[0040] like Figure 3 As shown, the operation sequence of the digital signal processing submodule according to an embodiment of the present invention includes repeatedly running the frequency reduction extraction filter module 310 and the pulse compression module 320 to obtain two-dimensional signal data; running the Fourier transform module 330 and the constant false alarm rate detection module 340 to obtain the distance and speed information of the target; and running the angle detection module to obtain the angle information of the target.

[0041] like Figure 2 As shown, the data storage device 80 according to the embodiment of the present invention includes: a one-dimensional signal data storage 810, which is used to cache the results of the frequency reduction extraction filtering; a two-dimensional signal data storage 820, which is used to accumulate the obtained one-dimensional signal data; an algorithm parameter storage 830, which is used to store the parameters required by each digital signal processing sub-module; and an instruction parameter storage 840, which is used to store the algorithm instructions of the instruction state machine 40.

[0042] Figure 4 The diagram schematically shows the memory access relationship among modules in a digital signal receiving and processing cycle according to an embodiment of the present invention.

[0043] like Figure 4 As shown, the memory access relationship of each module in the digital signal receiving and processing cycle according to an embodiment of the present invention includes: the preprocessing circuit 50 performs real-time preprocessing operations on the input digital signal in a single receiving cycle and writes it into the input data cache 70; at the beginning of the next receiving cycle, the down-conversion extraction filter module 310 in the digital signal processing sub-module array 30 reads the data cache and writes the result into the one-dimensional signal data storage 810; the pulse compression module 320 reads the one-dimensional signal data storage 810, and writes the result into the two-dimensional signal data storage 820.

[0044] The embodiments of the present invention are described above. However, these embodiments are only for the purpose of illustration, and are not intended to limit the scope of the present invention. Although each embodiment is described above, it does not mean that the measures in each embodiment cannot be used in combination advantageously. Without departing from the scope of the present invention, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A signal processing chip with distance measurement, speed measurement and angle measurement functions, characterized in that: include: Data input interface, data output interface, digital signal processing submodule array, instruction state machine, preprocessing circuit, algorithm data processing circuit, input data cache, data storage, system bus and phase-locked loop, Wherein, the data input interface is used to receive digital signal data and algorithm data to be processed, master clock and control signal; The data output interface is used to send operation result data, operation intermediate data and state machine verification information; The digital signal processing submodule array is used for programming and parallel processing of large-scale digital signal data; The instruction state machine is used to execute the input instruction code and schedule the data transmission link and computing resources on the chip to complete the corresponding processing task; The preprocessing circuit is used to convert the input digital signal into a data format that can be processed; The algorithm data processing circuit is used to convert input data information into a data format that can be processed and stored by the system bus, wherein the data information includes algorithm parameters; The input data cache is used to store the input digital signal data processed by the preprocessing circuit; The data memory is used to store intermediate calculation data, calculation result data, algorithm parameters and instruction codes; A system bus, used for data transmission within the chip, connecting the digital signal processing submodule array and the data storage; and The phase-locked loop is used to generate the main frequency clock for the chip according to the instruction configuration.

2. The signal processing chip according to claim 1, characterized in that: The data input interface includes a digital signal interface, an algorithm data interface, a control signal interface and a master clock interface. Wherein, the digital signal interface is used to receive a digital signal from the front end; The algorithm data interface is used to receive digital signal processing algorithm parameters, state machine instructions and intermediate data from off-chip storage; and The control signal interface is used to control chip global reset and state machine check selection.

3. The signal processing chip according to claim 2, characterized in that: The digital signal data is input from the digital signal interface and stored in the input data buffer after being processed by the preprocessing circuit; The algorithm parameters are input from the algorithm data interface and stored in the data memory after being processed by the algorithm data processing circuit; as well as The digital signal data and algorithm parameters are processed by the digital signal processing submodule array to obtain the processing results, which are stored in the data memory and finally output to the host computer through the output interface via the system bus.

4. The signal processing chip according to claim 1, characterized in that: The digital signal processing submodule array includes: a frequency reduction and extraction filter module, a pulse compression module, a Fourier transform module, a constant false alarm rate detection module and an angle detection module. Wherein, the frequency reduction and decimation filtering module is used to perform orthogonal down-conversion, finite impulse response and decimation filtering operations on the digital signal sequence; The pulse compression module is used to perform frequency domain related operations on the digital signal; The Fourier transform module is used to perform Fourier transform on the digital signal; The constant false alarm rate detection module is used to perform constant false alarm rate detection on the two-dimensional digital signal graph to remove false alarm points; The angle detection module is used to perform target angle information detection on the digital signal.

5. The signal processing chip according to claim 4, characterized in that: The digital signal processing submodule array includes a plurality of parallel signal processing submodules. According to the control of the instruction state machine, each digital signal processing submodule can independently process different computing tasks; and the plurality of digital signal processing submodules can coordinate computing.

6. The signal processing chip according to claim 4, characterized in that: The operation process of the digital signal processing submodule array includes: repeatedly running the frequency reduction extraction filter module and the pulse compression module to obtain two-dimensional signal data; Running the Fourier transform module and the constant false alarm rate detection module to obtain the distance and speed information of the target; and Run the angle detection module to obtain the angle information of the target.

7. The signal processing chip according to claim 4, characterized in that: The data storage device comprises: One-dimensional signal data storage, used to cache the results of down-conversion decimation filtering; Two-dimensional signal data storage, used to accumulate one-dimensional signal data after pulse compression processing; Algorithm parameter storage, used to store the parameters required by each digital signal processing submodule; and Instruction parameter storage, used to store algorithm instructions of the instruction state machine.

8. The signal processing chip according to claim 7, characterized in that: The preprocessing circuit performs real-time preprocessing operations on the input digital signal in a single receiving cycle and writes the input data into the buffer; At the beginning of the next receiving cycle, the frequency reduction and decimation filter module in the digital signal processing submodule array reads the data cache and writes the result into the one-dimensional signal data storage; The pulse compression module reads the one-dimensional signal data store and writes the result to the two-dimensional signal data store.

9. The signal processing chip according to claim 1, characterized in that: Contains at least one of the following characteristics: The preprocessing circuit converts the input digital signal into a processable data format, including merging and accumulating the digital signals input from the digital signal interface, and converting the accumulated signals into a processable data format; The algorithm data processing circuit converts the input data information into a data format that can be processed and stored by the system bus, including accumulating and rearranging the data information input by the algorithm data interface and converting it into a data format that can be transmitted and stored by the system bus; In the data storage device, each type of data has an independent storage space.

10. The signal processing chip according to claim 1, characterized in that: The instruction state machine uses a custom reduced instruction set to implement a digital signal processing algorithm. The user-defined reduced instruction set includes computing instructions, data handling instructions, and instruction flow control instructions; and The customized reduced instruction set is stored in a data memory.

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