Processors, methods, systems, and instructions for atomically storing data wider than a natively supported data width to memory

Abstract

The processor includes a widest set of data registers corresponding to a given logical processor. Each of the data registers of the widest set has a first width in bits. A decode unit corresponding to the given logical processor is to decode instructions specifying data registers of the widest set and is to decode an atomic store to memory instruction. The atomic store to memory instruction is to indicate data to have a second width in bits that is wider than the first width in bits. The atomic store to memory instruction is to indicate memory address information associated with a memory location. An execution unit is coupled with the decode unit. The execution unit, in response to the atomic store to memory instruction, is to atomically store the indicated data to the memory location.

Description

TECHNICAL FIELD

[0001] Embodiments described herein generally relate to processors. In particular, embodiments described herein generally relate to guaranteeing memory atomicity in a processor. BACKGROUND

[0002] Many processors have single instruction multiple data (SIMD) architectures. In a SIMD architecture, packed data instructions, vector instructions, or SIMD instructions can operate on multiple data elements or pairs of data elements simultaneously or in parallel. Processors can have parallel execution hardware responsive to packed data instructions to perform multiple operations simultaneously or in parallel.

[0003] Multiple data elements can be packed within a register as packed data or vector data. In packed data, bits of other storage locations or registers can be logically divided into a sequence of data elements. For example, a 128-bit wide packed data register can have two 64-bit wide data elements, four 32-bit data elements, eight 16-bit data elements, or sixteen 8-bit data elements. Each of the data elements can represent a separate independent piece of data (e.g., a pixel color, a component of a complex number, etc.) that can be operated on individually and / or independently of the remaining data elements. BRIEF DESCRIPTION OF DRAWINGS

[0004] The application can best be understood by referring to the following description and accompanying drawings that are used to illustrate embodiments. In the drawings:

[0005] Figure 1 is a block diagram of an embodiment of a processor that operates to execute an embodiment of an atomic store to memory instruction to atomically store data wider than a natively supported data width to memory.

[0006] Figure 2 is a block flow diagram of an embodiment of a method of executing an embodiment of an atomic store to memory instruction to atomically store data wider than a natively supported data width to memory.

[0007] Figure 3 is a block diagram of another embodiment of a processor that operates to execute an embodiment of an atomic store to memory instruction to atomically store data wider than a natively supported data width to memory.

[0008] Figure 4 is a block flow diagram of a more detailed example embodiment of a method of executing an example embodiment of an atomic store to memory instruction.

[0009] Figure 5 is a block diagram of an embodiment of a logical processor having a first detailed example embodiment of an execution unit that includes a hierarchical buffer and a write-combining buffer.

[0010] Figure 6 is a block diagram of an embodiment of a logic processor having a more particular second detailed example embodiment of an execution unit including a hierarchical buffer and a write-combining buffer.

[0011] Figure 7A is a block diagram illustrating an embodiment of an in-order pipeline and an embodiment of a register renaming out-of-order issue / execution pipeline.

[0012] Figure 7B is a block diagram of an embodiment of a processor core including a front-end unit coupled to execution engine units and both coupled to a memory unit.

[0013] Figure 8A is a block diagram of an embodiment of a single processor core along with its connection to an on-chip interconnect network and along with its local subset of level 2 (L2) cache.

[0014] Figure 8B is a block diagram of an embodiment of an expanded view of a portion of the processor core of Figure 8A

[0015] Figure 9 is a block diagram of an embodiment of a processor that can have more than one core, that can have an integrated memory controller, and that can have integrated graphics.

[0016] Figure 10 is a block diagram of a first embodiment of a computer architecture.

[0017] Figure 11 is a block diagram of a second embodiment of a computer architecture.

[0018] Figure 12 is a block diagram of a third embodiment of a computer architecture.

[0019] Figure 13 is a block diagram of an embodiment of a system-on-a-chip architecture.

[0020] Figure 14 is a block diagram of using a software instruction translator to convert binary instructions in a source instruction set to binary instructions in a target instruction set in accordance with an embodiment of the present invention. DETAILED DESCRIPTION

[0021] ​Disclosed herein are instructions for atomically storing data wider than a natively supported data width to memory, processors for executing the instructions, methods performed by the processors when processing or executing the instructions, and systems incorporating one or more processors to process or execute the instructions. In some embodiments, the processors can have a decode unit or other logic to receive and / or decode the instructions and an execution unit or other logic to execute or otherwise perform the instructions. In the following description, numerous specific details are set forth (e.g., particular instruction operations, data formats, processor configurations, microarchitectural details, sequences of operations, etc.). However, embodiments can be practiced without these specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail in order not to obscure the understanding of this description.

[0022] Figure 1 is a block diagram of an embodiment of a processor 100 that operates to execute an embodiment of an atomic store to memory instruction 108 to atomically store data wider than a natively supported data width to memory 125. In some embodiments, the processor can be a general purpose processor (e.g., a general purpose microprocessor or central processing unit (CPU) of the type used in desktop, laptop, or other computers). Alternatively, the processor can be a special purpose processor. Examples of suitable special purpose processors include, but are not limited to, network processors, communications processors, cryptographic processors, graphics processors, coprocessors, embedded processors, digital signal processors (DSPs), and controllers (e.g., microcontrollers).

[0023] The processor 100 includes at least one logic processor 101. A logic processor can also be referred to as a processor element. Examples of suitable logic processors include, but are not limited to, cores, hardware threads, thread units, and thread slots, as well as other logic processors or processor elements having a dedicated context or architectural state including a program counter or instruction pointer. The term core is often used to refer to logic located on an integrated circuit capable of maintaining independent architectural state (e.g., an execution state), and where the architectural state is associated with exclusive execution and certain other resources. In contrast, the term hardware thread is often used to refer to logic located on an integrated circuit capable of maintaining independent architectural state, and where the architectural state shares access to the execution or certain other resources. The line between such uses of the terms core and hardware thread can tend to be less distinct when two or more architectural states share some execution and / or other resources, and other execution or other resources are dedicated to an architectural state. However, cores, hardware threads, thread units, and thread slots, as well as other logic processors or processor elements, are generally treated as independent logic processors or processor elements by software. Generally, a software thread, process, or workload can be scheduled and independently associated with each of cores, hardware threads, thread units, and thread slots, as well as other logic processors or processor elements.

[0024] The logic processor 101 has an instruction set architecture (ISA). The ISA represents the architecture of the logic processor that is relevant to programming, and typically includes the instructions that the logic processor natively supports, architectural registers, data types, addressing modes, memory architecture, etc. The ISA is distinct from the microarchitecture, which generally represents the specific design techniques chosen to implement the ISA. The logic processor can have any of a variety of complex instruction set computing (CISC) architectures, reduced instruction set computing (RISC) architectures, very long instruction word (VLIW) architectures, hybrid architectures, other types of architectures. In some cases, the processor 100 can optionally have multiple logic processors that can all have the same ISA, or can have two or more logic processors with different ISAs (e.g., different cores can have different ISAs).

[0025] The logic processor 101 and / or its ISA includes architectural registers 110 (e.g., one or more architectural register files). Architectural registers can represent architectural visible registers that are visible to software and / or programmers and / or registers that are specified by instructions of the instruction set to identify operands. These registers are in contrast to other non-architectural or non-architecturally visible registers in a given microarchitecture (e.g., temporary registers, microarchitectural buffers, reorder buffers, etc.). For simplicity, architectural registers can also be referred to herein simply as registers. Each of the registers can represent a die or processor on-chip storage location that stores data.

[0026] The architectural registers 110 can include various different types of registers. Examples of such registers include, but are not limited to, general-purpose registers, packed data registers, program status registers, control registers, memory addressing registers, and so on. Packed data registers are also sometimes referred to in the art as vector registers or single instruction multiple data (SIMD) registers. Packed data registers can operate to store packed data, vector data, or SIMD data. As shown, in some embodiments, the logical processor and / or the architectural registers can include a widest set of packed data registers 114. The widest set of packed data registers 114 represents the widest or largest size set of packed data registers of the logical processor in terms of their width in bits and / or the widest or largest size set of packed data registers supported by the logical processor. In some embodiments, the logical processor and / or the architectural registers can also optionally include a relatively narrower set of packed data registers 112, or potentially multiple sets of packed data registers of varying widths (each smaller than the width of each of the widest set of packed data registers 114), although this is not a requirement. As one particular, non-limiting example, each of the registers of the widest set of packed data registers 114 can have a width of 128 bits, while each of the registers of the narrower set of packed data registers 112 can only have a width of 64 bits.

[0027] The logical processor 101 and / or its ISA also includes an instruction set 102. The instructions of the instruction set represent macroinstructions, machine-level instructions, instructions provided to the logical processor for execution, or instructions that the logical processor is natively capable of decoding and executing, as opposed to microinstructions or micro-operations (e.g., those resulting from decoding instructions of the instruction set). The instruction set can include various different types of instructions. Several representative examples of these different types of instructions are shown and described below to illustrate certain concepts.

[0028] As shown, the instruction set can include a set of arithmetic and / or logical packed data instructions 104 that each operate on the widest set of packed data registers 114. As an example, the arithmetic and / or logical packed data instructions can include a packed multiply instruction to multiply corresponding data elements in the same relative data element position in two source registers of the widest set of packed data registers and store the resulting product in one of the two source registers or a third register. As another example, the arithmetic and / or logical packed data instructions can include a packed add instruction to add corresponding data elements in the same relative data element position in two source registers of the widest set of packed data registers and store the resulting sum in one of the two source registers or a third register. Similarly, there can optionally be packed logical instructions (e.g., a packed logical AND instruction, a packed logical OR instruction, a packed logical AND NOT instruction, a packed logical exclusive OR (XOR) instruction, etc.). In general, there can be anywhere from a few to tens (if not more) of such different types of packed data instructions each designed to operate on the widest set of packed data registers, although the scope of the present invention is not limited to any such number of these indications. The width of the widest set of packed data registers can represent the largest size of packed data operand that the arithmetic and / or logical packed data instructions are capable of specifying and / or operating on.

[0029] As shown, the processor 100 and / or the logical processor 101 can include at least one arithmetic and / or logical packed data execution unit (ALU) 118 that operates to execute arithmetic and / or logical packed data instructions 104 to operate on packed data operands stored in the widest set of packed data registers 114. Dotted lines are used to represent that the execution and certain other resources can be dedicated to a logical processor or shared by multiple logical processors, as discussed above. In some cases, the width in bits of the arithmetic and / or logical packed data execution unit can be the same as the width in bits of each register of the widest set of packed data registers. The width in bits of the arithmetic and / or logical packed data execution unit can represent the maximum width in bits of a packed data operation that it is capable of performing on one or more packed data operands (e.g., the maximum supported ALU operation). In other cases, the width in bits of the arithmetic and / or logical packed data execution unit can optionally be narrower than the width in bits of each register of the widest set of packed data registers, and different portions of an operand from the widest set of packed data registers can be sent through the narrower execution unit sequentially in an interleaved or sequential manner. As one example, a first half of a 128-bit packed data operand can be sent through a 64-bit wide execution unit, and then a second half of the 128-bit packed data operand can be sent through the 64-bit wide execution unit.

[0030] In some cases, the width in bits of a bus or other interconnect used to deliver data directly to and / or from the widest set of packed data registers can be narrower than the width in bits of each of the widest set of packed data registers. For example, the width of the bus or other interconnect used to deliver data directly to and from the widest set of packed data registers can be only half the width of each of the widest set of packed data registers. In such cases, different portions (e.g., different halves) of the data of a single packed data register of the widest set can be transferred through the bus or other interconnect sequentially or at different times. As one particular example, two 64-bit halves of data from a single 128-bit packed data register of the widest set can be transferred through a 64-bit interconnect sequentially one after the other.

[0031] As shown, the instruction set can also include at least one store-to-memory instruction 106 to store data from a single register of the widest set of packed data registers 114 to memory 125. The processor and / or logical processor can include a store execution unit 120 that operates to execute the store-to-memory instruction 106 to store data from a single register of the widest set of packed data registers to memory. As shown, the store-to-memory operation 122 can be communicated to the memory over a bus or other interconnect 123 or otherwise provided to the memory to provide data from a single register of the widest set of packed data registers. In some cases, the width of the data in bits communicated or otherwise provided by the operation 122 over the bus can be the same as the width of each register of the widest set of packed data registers in bits. In other cases, the width of the data provided over the bus can be less than the width of the widest data register. In the latter case, the contents of the widest set of packed data registers can be communicated in two or more sequential transmissions over the interconnect and can optionally be grouped by start and stop indications so that they can form a single atomic store.

[0032] Referring again to Figure 1 In some embodiments, the instruction set also includes at least one atomic store-to-memory instruction 108. The atomic store-to-memory instruction, when executed, can operate to cause the processor and / or logical processor to store data having a width in bits that is wider than a natively supported data width to memory 125. As shown, the atomic store-to-memory operation 124 can be performed over a bus or other interconnect. The atomic store can be such that all of the data is stored in its entirety, or no data is stored, but only a portion or subset of the data is guaranteed or ensured not to be stored. That is, there can be a store completion atomicity guarantee. The atomicity can also guarantee that the data stored by the atomic store will not be interleaved with data stored by other stores. The atomicity can be with respect to other accesses to the data such that any such accesses will observe all of the data stored in its entirety, or no data stored, but will not observe only a portion or subset of the data stored. The atomicity can also be with respect to power failures, system crashes, reboots, or other such events such that even in the face of such events, all of the data is stored in its entirety, or no data is stored, but only a portion or subset of the data is guaranteed or ensured not to be stored.

[0033] In some embodiments, atomic stores can be used for data that is wider than a natively supported data width of the logical processor 101 and / or the processor 100. The natively supported data width can manifest itself in different ways in different embodiments. In some embodiments, the natively supported data width can represent a width in bits of the widest set of packed data registers 114, and / or a width of one or more packed data operands to be operated on or by an arithmetic and / or logical packed data instruction 104. In some embodiments, the natively supported data width can represent a width of an arithmetic and / or logical packed data execution unit 118 (e.g., when it has the same width as a packed data operand indicated by an instruction such that multiple portions of the packed data operand are not sequentially pumped through it). In some embodiments, the natively supported data width can represent a width of a bus (e.g., of a load pipe) that is narrower than the widest set of packed data registers for which data is directly transferred to and from. For example, a processor can potentially have wide packed data registers, but the amount of data that can be atomically stored (i.e., without the methods disclosed herein) can be limited by the width of a bus leading from these wide packed data registers. In some embodiments, the natively supported data width can represent a width of a packed data operand to be stored to memory by a store to memory instruction 106. In some embodiments, the natively supported data width can represent a width of data to be stored to memory by a store to memory operation 122. The natively supported data width is at least related to the logical processor 101 that executes the atomic store to memory instruction 108 and / or has an instruction set 102 that includes the atomic store to memory instruction 108. In some embodiments, the processor 100 can optionally have additional cores, hardware threads, or other logical processors (not shown) that can have different natively supported data widths, but this additional logical processor can not be the logical processor that executes the atomic store to memory instruction 108 and / or can not have an instruction set that includes the atomic store to memory instruction 108.

[0034] There are various possible uses of such atomic store operations. One example of such a use is to atomically update a piece of data in a database. Another example of such a use is to atomically update a piece of shared data in a multi-processing environment. Yet another example of such a use is to atomically pass data to a shared device (e.g., through a memory-mapped input-output (MMIO) register). For example, as will be further explained below, this can be used to assign or provide work to an accelerator device or other type of device shared by multiple logical processors. Yet another possible example of such a use is to atomically store data to a 3D XPoint™ non-volatile memory. Yet another example of such a use is to atomically store data to some location to replace a lock, semaphore, update a shared variable, synchronize, coordinate, etc. Other uses of such atomic store operations are still contemplated and will be apparent to those of skill in the art and having the benefit of this disclosure.

[0035] The store completion atomicity guarantee for the wider data can be a store completion atomicity guarantee that generally cannot be achieved by executing multiple different instances of a store-to-memory instruction 106 that each store a different corresponding narrower portion of data from a different corresponding register of the widest set 114 of packed data registers. For example, the different instances of the store-to-memory instruction will generally be executed at different times. The cumulative amount of data from such different timing store instructions will not all be present in the memory at the same time. Rather, different narrower portions of the data will generally be stored in the memory at different times. Similarly, different narrower portions of the data will be transferred or provided in different timing transactions or signals on a bus or other interconnect. Due to the different times involved, it is possible for another logical processor to perform an intervening read and / or store operation to the location in the memory where the data is to be stored after only some of the different store operations have been performed. It is possible that an intervening power failure, system crash, reboot, or other such event can occur after only some of the different store operations have been performed. Due to such possibilities, such use of multiple different sequential store-to-memory instructions and / or different timing store operations transferred over a bus or other interconnect generally cannot be used to provide a store completion atomicity guarantee on wider data.

[0036] In Figure 1In particular example embodiments, the widest set of packed data registers 114 represents the widest data registers of the processor 100. However, in other embodiments, other data registers can represent the widest data registers of the processor. Likewise, the arithmetic and / or logical packed data instruction 104 indicates a widest packed data operand. However, in other embodiments, other instructions of the instruction set can specify a widest operand, which can not necessarily be a packed data operand. Similarly, in other embodiments, the instruction set can include a store to memory instruction to indicate an operand in another type of widest data register (i.e., not necessarily a packed data register) to store to memory. Likewise, the execution unit 116 can include an execution unit to operate on other widest data registers (i.e., not necessarily packed data registers) and operands (i.e., not necessarily packed data operands).

[0037] Figure 2 is a block flow diagram of an embodiment of a method 226 of an embodiment of executing an atomic store to memory instruction. In various embodiments, the method can be performed by a processor, an instruction processing apparatus, digital logic, or an integrated circuit.

[0038] The method includes receiving an atomic store to memory instruction at a given logical processor at block 228. In various aspects, the instruction can be received at an instruction fetch unit of the given logical processor, an instruction cache of the given logical processor, a prefetch unit of the given logical processor, or at a decode unit of the given logical processor. The atomic store to memory instruction can specify (e.g., explicitly specify by one or more fields or sets of bits) or otherwise indicate (e.g., implicitly indicate) data to atomically store. In some embodiments, the indicated data can be wider in bits than a widest data register (e.g., a widest packed data register) corresponding to the given logical processor, other instructions of the instruction set of the given logical processor (e.g., any packed multiply instruction, any packed add instruction, any packed arithmetic and / or logical instruction, etc.) are capable of specifying or otherwise indicating.

[0039] A few illustrative examples of widths that can be mentioned. For example, in some embodiments, the width of the indicated data can be 128 bits, and the width of the widest data register (e.g., packed data register) can be 256 bits. In other embodiments, the width of the indicated data can be 128 bits, and the width of the widest data register (e.g., packed data register) can be 512 bits. In yet other embodiments, the width of the indicated data can be 128 bits, and the width of the widest data register (e.g., packed data register) can be 1024 bits. In further embodiments, the width of the indicated data can be 256 bits, and the width of the widest data register (e.g., packed data register) can be 512 bits. In still further embodiments, the width of the indicated data can be 256 bits, and the width of the widest data register (e.g., packed data register) can be 1024 bits. In yet other embodiments, the width of the indicated data can be 512 bits, and the width of the widest data register (e.g., packed data register) can be 1024 bits.

[0040] The atomic store-to-memory instruction can also specify (e.g., explicitly specify through one or more fields or sets of bits), or otherwise indicate (e.g., implicitly indicate), memory address information. The memory address information can be associated with a memory location (e.g., a destination memory location to which the indicated data is to be atomically stored). For example, the memory address information can be usable (potentially in combination with other information (e.g., information from a segment register, etc.)) to generate a memory address of the memory location. In some embodiments, the memory location can correspond to an MMIO range (e.g., an MMIO control register of a device), although the scope of the application is not so limited.

[0041] In different embodiments, the indicated data (e.g., data to be atomically stored in response to the instruction) can be initially stored in and / or accessed from different initial storage locations. In some embodiments, such data can be initially stored in multiple data registers (e.g., multiple of the widest packed data or other widest registers corresponding to a given logical processor). In such embodiments, the atomic store to memory instruction can specify or otherwise indicate at least one of these data registers (e.g., specify one of a sequence of contiguous widest data registers, with an implicit understanding that other sequential registers are also to be used). Alternatively, in other embodiments, such data to be atomically stored can be initially stored in a source memory location. In such embodiments, the atomic store to memory instruction can specify or otherwise indicate additional memory address information associated with the source memory location (e.g., potentially used in conjunction with other information to generate a memory address for the source memory location). Again, in such embodiments, the atomic store to memory instruction can cause the data to be atomically stored to be initially loaded from such source memory location (e.g., into multiple of the architectural widest packed data or other widest data registers corresponding to a given logical processor or into one or more non-architectural temporary registers or storage locations of the processor).

[0042] The method also includes atomically storing the indicated data to the memory location in response to and / or as a result of the atomic store to memory instruction, at block 229. In some embodiments, this can include transferring the indicated data (which is wider than the widest packed data or other widest registers on a bus or other interconnect toward the memory location). In some embodiments, as will be further explained below, atomically storing the indicated data to the memory location can optionally be used to assign work to another device (e.g., an accelerator device), although the scope of the application is not so limited.

[0043] The illustrated method involves architectural operations (e.g., those visible from a software perspective). In other embodiments, the method can optionally include one or more microarchitectural operations. As an example, an instruction can be fetched by and / or corresponding to a fetch unit of a given logical processor, decoded by and / or corresponding to a decode unit of the given logical processor, data can be accessed, a microarchitectural operation can be performed by an execution unit corresponding to the given logical processor to implement the instruction, etc. In some embodiments, the microarchitectural operations to implement the instruction can optionally include sequentially storing a plurality of portions of the indicated data (which collectively represent the total amount of the indicated data) to a staging buffer, and then simultaneously storing the total amount of the indicated data from the staging buffer and / or the plurality of portions of the indicated data (e.g., to a write-combining buffer), as will be explained in further detail below.

[0044] Figure 3 is a block diagram of an embodiment of a processor 300 that operates to execute an embodiment of an atomic store to memory instruction 308. In various embodiments, a processor can represent at least a portion of an integrated circuit, can be included on a die or semiconductor substrate, can include semiconductor material, can include transistors, etc. In some embodiments, the processor 300 can optionally be and / or include a processor 100 of Figure 1 , although this is not required. The optional features and details of the previously described processor 100 can also optionally apply to the processor 300. In some embodiments, the processor 300 can optionally be used to execute the method 226 of Figure 2 . The components, features, and particular optional details described herein with respect to the processor 300 can also optionally apply to the method 226, which can optionally be executed by the processor 300. Alternatively, the method 226 can optionally be executed by a similar or different processor or device. Moreover, the processor 300 can optionally execute a similar or different method than the method 226.

[0045] The processor includes at least a logic processor 301. The logic processor includes and / or supports a set of architected packed data registers 310. Each of the packed data registers can represent a storage location on a die (or on an integrated circuit) that operates to store packed data, vector data, or SIMD data. The packed data registers can be implemented in different ways in different microarchitectures and are not limited to any particular type of design. Examples of suitable types of registers include, but are not limited to, dedicated physical registers, dynamically allocated physical registers using register renaming, and combinations thereof. As shown, in some embodiments, the packed data registers 310 corresponding to and / or supported by the logic processor 301 can include a widest set 314 of packed data registers. Each of the widest set of packed data registers can have a first width in bits. In some embodiments, the packed data registers can optionally include a narrower set 312 of packed data registers, although this is not required. Each of the narrower set of packed data registers can have a width that is narrower than each of the widest set of packed data registers. The widest set 314 of packed data registers represents the widest data registers of the processor in this particular example embodiment, although in other embodiments other widest data registers of the processor can optionally be non-packed data registers.

[0046] During operation, the processor 300 and / or the logic processor 301 can receive an atomic store to memory instruction 308. The instruction can be received from a memory on a bus or other interconnect, for example. In various embodiments, the instruction can be stored in and / or fetched by and / or corresponding to an instruction cache of the logic processor, fetched by and / or corresponding to a fetch unit of the logic processor, and so on. The instruction can represent a macro instruction, a machine code instruction, or other instruction or control signal of the instruction set of the logic processor 301 and / or the processor 300. In some embodiments, the atomic store to memory instruction can explicitly specify (e.g., by one or more fields or sets of bits) or otherwise indicate (e.g., implicitly indicate) data 334 that is to have a second width in bits that is wider than a first width in bits of each of the widest set of packed data registers (or other widest data registers of the processor).

[0047] To further illustrate, it can be helpful to specifically mention some illustrative examples of suitable widths. As an example, in some embodiments, the second width of the indicated data 334 can be 128 bits, and the first width of each of the widest packed data registers 314 (or other widest architected register) can be 256 bits. In other embodiments, the second width can be 128 bits and the first width can be 512 bits. Yet in other embodiments, the second width can be 128 bits and the first width can be 1024 bits. In still further embodiments, the second width can be 256 bits and the first width can be 512 bits. In still further embodiments, the second width can be 256 bits and the first width can be 1024 bits. Yet in other embodiments, the second width can be 512 bits and the first width can be 1024 bits. These are just a few illustrative examples of suitable widths.

[0048] The atomic store-to-memory instruction can also specify (e.g., explicitly specify through one or more fields or sets of bits), or otherwise indicate (e.g., implicitly indicate), memory address information. The memory address information can be associated with a memory location 338 (e.g., a destination memory location) in the memory 325 where the indicated data 334 is to be atomically stored as data 339 having a second width that is wider than the first width. For example, the indicated memory address information can be usable (potentially in combination with other information (e.g., information from a segment register, etc.)) to generate a memory address for the memory location. Various different types of memory address information are possible. The indicated address information can represent absolute memory address information or relative memory address information, which can indicate a memory location relative to a base memory address or other memory location. In addition, various different modes of indirect memory addressing can optionally be used. As one particular example, the instruction can implicitly indicate a register (e.g., a general-purpose register) to use for storing relative memory address information, which can be combined with additional memory address information stored in another implicit register (e.g., a code, data, or extension segment register) to generate a memory address for identifying the memory location 338 having the first byte or other addressable storage element (in which the data 339 is to be atomically stored). This is just one example. Other forms of address information are also possible. Again, some or all of the address information can potentially be provided by bits of the instruction (e.g., an immediate) rather than providing the address information in one or more registers.

[0049] In different embodiments, the indicated data 334 can initially be stored in and / or accessed from different initial storage locations. As shown, in some embodiments, the data 334 can be initially stored in the widest packed data register 314 (or in other widest data registers). Since the data 334 has a second width that is wider than a first width of each of the widest set of packed data registers, the data can be stored in at least two of the widest set of packed data registers. In such embodiments, the atomic store-to-memory instruction can specify or otherwise indicate at least one of the multiple packed data registers of the widest set. For example, the instruction can have a field or set of bits to specify one of the packed data registers of the widest set, and can implicitly indicate one or more other packed data registers of the widest set (e.g., one or more sequential registers) (e.g., the processor can understand from the opcode of the instruction that the instruction uses these registers without the instruction needing to have additional bits to explicitly specify it). Alternatively, in other embodiments, the data 334 can instead be initially stored in a source memory location (not shown) in memory 325. In such embodiments, the atomic store-to-memory instruction can specify or otherwise indicate additional memory address information associated with the source memory location (e.g., potentially used in combination with other information to generate a memory address for the source memory location). Again, in such embodiments, the atomic store-to-memory instruction can cause the data to be initially loaded atomically from this source memory location (e.g., into the multiple architectural widest packed data registers 314 or into one or more non-architectural temporary registers or storage locations (not shown) of the processor).

[0050] Referring again to Figure 3The logic processor 301 includes a decoding unit or decoder 330. The decoding unit is operable to receive and decode instructions of the instruction set of the logic processor 301, including instructions (e.g., arithmetic and / or logic packing data instructions 104) specifying registers (or other widest data registers) in the widest set 314 of packing data registers. The decoding unit is also operable to receive and decode atomic store-to-memory instructions 308. The decoding unit may output one or more relatively low-level instructions or control signals (e.g., one or more microinstructions, microoperations, microcode entry points, decoding instructions, or control signals, etc.) that reflect, represent, and / or are derived from relatively high-level atomic store-to-memory instructions. In some embodiments, the decoding unit may include one or more input structures (e.g., one or more ports, one or more interconnects, interfaces) to receive atomic store-to-memory instructions, instruction identification and decoding logic coupled thereto to identify and decode atomic store-to-memory instructions, and one or more output structures (e.g., one or more ports, one or more interconnects, interfaces) coupled thereto to output one or more lower-level instructions or one or more control signals. The decoding unit can be implemented using a variety of different mechanisms, including but not limited to microcode read-only memory (ROM), lookup tables, hardware implementation, programmable logic arrays (PLA), and other mechanisms suitable for implementing the decoding unit.

[0051] In some embodiments, instead of directly providing atomic store-to-memory instructions to the decoding unit 330, an instruction emulator, converter, transformer, interpreter, or other instruction conversion module may be optionally used. Various types of instruction conversion modules can be implemented using software, hardware, firmware, or a combination thereof. In some embodiments, the instruction conversion module may be located external to the processor, such as, for example, on a separate die and / or in memory (e.g., as a static, dynamic, or runtime emulation module). As an example, the instruction conversion module may receive atomic store-to-memory instructions, which may have a first instruction set, and may emulate, translate, transform, interpret, or otherwise convert the atomic store-to-memory instructions into one or more corresponding intermediate instructions or control signals, which may have a second, different instruction set. One or more intermediate instructions or control signals of the second instruction set may be provided to the decoding unit (e.g., decoding unit 330), which may decode them into one or more lower-level instructions or control signals executable by the processor's native hardware (e.g., one or more execution units).

[0052] Refer again Figure 3The logic processor 301 also includes an execution unit 332. The execution unit 332 is coupled with the decode unit 330 and with the packed data registers 310. The execution unit can receive one or more decoded or otherwise translated instructions or control signals that are representative of the atomic store-to-memory instruction and / or derived from the atomic store-to-memory instruction. The execution unit can also receive the indicated data 334. The execution unit can operate (e.g., in response to one or more instructions or control signals decoded from the instruction, and / or in response to the decoded instruction, and / or in response to the instruction provided to the decode unit) to atomically store the indicated data 334 to a memory location 338 in memory as data 339 in response to and / or as a result of the atomic store-to-memory instruction. As shown, in some embodiments, the data 339 can have a second width in bits that is wider than a first width in bits of each of the registers of the widest set 314 of packed data registers (or other widest architected data registers) of the logic processor 301. This is one way in which the data 334 and / or the data 339 can be wider than a natively supported data width of the logic processor 301. In other embodiments, the data 334 and / or the data 339 can be wider than a natively supported data width of the logic processor 301 (in various other ways), as described elsewhere herein.

[0053] The execution unit 332 and / or the logic processor 301 and / or the processor 300 can include specific or particular logic (e.g., transistors, integrated circuits, or other hardware potentially combined with firmware (e.g., instructions stored in non-volatile memory) and / or software) that operates in response to and / or as a result of the atomic store-to-memory instruction (e.g., in response to one or more instructions or control signals decoded from the atomic store-to-memory instruction) to execute the atomic store-to-memory instruction 308 and / or to atomically store the data 334 to the memory 325. In some embodiments, the execution unit can include one or more input structures (e.g., one or more ports, one or more interconnects, interfaces) to receive the data 334, circuitry or logic coupled therewith to receive and process the data 334, and one or more output structures (e.g., one or more ports, one or more interconnects, interfaces) coupled therewith to output the data 339 toward the memory 325.

[0054] In some embodiments, the execution unit can include one or more of Figure 5-6Any one or more of the circuits or logic shown and described in FIGS. 1-3 are illustrative examples of suitable microarchitectural arrangements, although the scope of the application is not so limited. As will be explained further below, in some embodiments, the execution unit can include a staging buffer (not shown). In some embodiments, the execution unit, in response to an atomic store-to-memory instruction, can be operable to sequentially store the multiple different portions of the indicated data 334 that collectively represent the indication of the total amount to the staging buffer, and then can be operable to simultaneously store the indication of the total amount of data and / or the multiple different portions of the indicated data from the staging buffer. In some embodiments, the execution unit can also have a write-combination buffer (not shown), and can optionally store the total amount of the indicated data to the write-combination buffer simultaneously. Alternatively, the total amount of the indicated data can be optionally stored to another storage location (e.g., a bus queue, another queue, etc.), written out directly to a bus, etc. In some embodiments, the execution unit, in response to an atomic store-to-memory instruction, can also be optionally operable to configure the write-combination buffer (if used) to disallow younger store operations to be merged with the write-combination buffer after the multiple different portions of the indicated data have been stored to the write-combination buffer. In some embodiments, the execution unit, in response to an atomic store-to-memory instruction, can also be optionally operable to configure the write-combination buffer (if used) for eviction after the multiple different portions of the indicated data have been stored to the write-combination buffer (e.g., typically within one or about ten clock cycles of that).

[0055] To avoid obscuring the description, relatively simple processors and logic processors have been shown and described. However, the processors can optionally include other processor components. For example, various different embodiments can include a memory management unit (MMU) (not shown) that is coupled between the execution unit and the memory (not shown) to translate virtual addresses in instructions into real addresses in memory. The MMU can also manage memory protection, paging, etc. Figure 7B and 8A Various different combinations and configurations of the components shown and described in any one of FIGS. 1-3. All of the components of the processor can be coupled together to allow them to operate according to intended design.

[0056] Figure 4 is a block flow diagram of a more detailed example embodiment of a method 440 of executing an atomic store-to-memory instruction. In various embodiments, the method can be performed by a processor, an instruction processing device, digital logic, or an integrated circuit. In some embodiments, the method 440 can be performed by a processor 300 and / or using an execution unit 302 of the processor 300. Figure 3 is a block flow diagram of a more detailed example embodiment of a method 440 of executing an atomic store-to-memory instruction. In various embodiments, the method can be performed by a processor, an instruction processing device, digital logic, or an integrated circuit. In some embodiments, the method 440 can be performed by a processor 300 and / or using an execution unit 302 of the processor 300. Figure 3 is a block flow diagram of a more detailed example embodiment of a method 440 of executing an atomic store-to-memory instruction. In various embodiments, the method can be performed by a processor, an instruction processing device, digital logic, or an integrated circuit. In some embodiments, the method 440 can be performed by a processor 300 and / or using an execution unit 302 of the processor 300. Figure 3instructions 308 are executed. The components, features, and particular optional details described herein in connection with processor 300 and / or instructions 308 are also optionally applied to method 440. Alternatively, method 440 can be performed by a similar or different processor or device and / or within a similar or different processor or device and / or using similar or different instructions. Moreover, processor 300 can perform a similar, identical, or different method than method 440.

[0057] The method includes receiving an atomic store to memory instruction at a given logical processor at block 441. In some embodiments, the instruction can indicate a source operand having data. In some embodiments, the data can be wider than a native supported data width of the given logical processor. For example, in some embodiments, the data can be wider than a widest packed data or other widest data register of and / or corresponding to and / or supported by the given logical processor. In response to the instruction, a plurality of different portions of data from the source operand collectively representing the total amount of data can be sequentially stored to a plurality of different corresponding portions of a staging buffer at block 442. In response to the instruction, the total amount of data and / or the plurality of different portions of data stored in the staging buffer can be simultaneously stored to a write-combined buffer at block 443. The write-combined buffer can be optionally configured to not allow merging in response to the instruction after the plurality of different portions of data have been stored to the write-combined buffer at block 444. This can help prevent younger store operations (e.g., younger and / or subsequent to the atomic store to memory instruction in program order) from merging with the write-combined buffer. The write-combined buffer can be optionally configured to be used for eviction in response to the instruction after the plurality of different portions of data have been stored to the write-combined buffer at block 445. The write-combined buffer can be evicted to a destination memory operand (e.g., memory location) of the atomic store to memory instruction at block 446. In some embodiments, the actual eviction can be performed in response to the atomic store to memory instruction. In other embodiments, the actual eviction can be performed outside of execution of the atomic store to memory instruction.

[0058] It is to be appreciated that this is merely one illustrative example method. In other embodiments, instead of writing the combination buffer, the total amount of data can instead be stored from the staging buffer to another storage location (e.g., a bus queue or other queue or buffer), or provided directly to the bus. For example, other embodiments can optionally omit block 445. Representatively, the processor can instead be allowed to evict the write combination buffer gradually or when it is ready. As another example, other embodiments can optionally omit block 444. Representatively, eviction of the write combination buffer can be optionally caused immediately after block 443, such that there can be no need to configure the write combination buffer to disallow merging. As yet another example, blocks 444 and 445 can optionally be performed in the reverse order of that shown. Other embodiments can add additional operations, replace one of the shown operations with a different operation, etc.

[0059] Figure 5 is a block diagram of an embodiment of a logic processor 501 having a first detailed example embodiment of an execution unit 532 including a staging buffer and a write combination buffer 556 to perform an embodiment of an atomic store to memory instruction 508. In some embodiments, the logic processor 501 can optionally be used to perform the method 226 and / or the method 440 of Figure 2 . The components, features, and specific optional details described herein for the logic processor 501 can also optionally be applied to the method 226 and / or the method 440. Alternatively, the method 226 and / or the method 440 can optionally be performed by a similar or different processor or device. Moreover, the logic processor 501 can optionally perform a similar or different method than the method 226 and / or the method 440. Figure 4

[0060] The logic processor 501 includes a widest set of packed data registers 514 each having a first width, a decode unit 530 to receive and decode an atomic store to memory instruction 508, and an execution unit 532. In the example embodiment shown, the widest set of packed data registers represents the widest architected data registers of the processor, although in other embodiments other non-packed data registers can represent the widest data registers. Unless otherwise specified, these components can optionally have some or all of the properties of the corresponding named components of Figure 3 . To avoid obscuring the description, the different and / or additional properties will be primarily described without repeating all properties that can optionally be the same or similar.

[0061] ​During operation, the decode unit can operate to receive and decode instructions of an instruction set of the logic processor 501, including instructions that specify a widest data register (e.g., a register in the widest set of packed data registers 514) (e.g., arithmetic and / or logical packed data instructions 104). The decode unit can also operate to receive and decode an atomic store to memory instruction 508. In some embodiments, the atomic store to memory instruction can indicate to have a second width in bits that is wider than a first width in bits of each of the processor's widest data registers (e.g., a register of the widest set of packed data registers 514). As shown, in some embodiments, the data can optionally be initially stored as a first data portion 550-1 of the first width in a first packed data register of the widest set 514-1, and a second data portion 550-2 of the first width in a second packed data register of the widest set 514-2. Alternatively, in other embodiments, the data can instead be optionally initially stored in a source memory location, as previously described.

[0062] The execution unit 532 is coupled with the decode unit 530 and with the packed data registers 510. The execution unit can operate to atomically store the indicated data 550-1, 550-2 to a destination memory operand and / or memory location indicated by the atomic store to memory instruction 508, in response to and / or as a result of the atomic store to memory instruction 508. As shown, in some embodiments, the execution unit can include a staging buffer 552 and a write-combining buffer 556. The staging buffer and write-combining buffer can be coupled together (e.g., the write-combining buffer can be coupled with an output of the staging buffer). In some embodiments, the staging buffer can represent a new non-architectural or microarchitectural structure or storage. In some embodiments, the staging buffer can be implemented by storage and / or logic that can optionally be similar to that used for the write-combining buffer but typically simpler in implementation due to looser architectural guarantees and requirements than those of the write-combining buffer. In some embodiments, the staging buffer can optionally be implemented in a memory execution unit, memory execution cluster, although the precise location in which the staging buffer is implemented is not required.

[0063] In some embodiments, responsive to instruction 508, the execution unit can be operative to sequentially store a plurality of different portions of data (e.g., first data portion 550-1 and second data portion 550-2) that collectively represent the total amount of data to different corresponding portions of the hierarchical buffer. In some embodiments, these different portions of data can be provided by different store operations, and can come from the store buffers of the load store queue, although the scope of the application is not so limited. As shown, the hierarchical buffer can have a first hierarchical buffer segment 554-1 of the first width for receiving and storing the first data portion 550-1, and a second hierarchical buffer segment 554-2 of the first width for receiving and storing the second data portion 550-2. Each of the first and second data portions can be stored at different times by different corresponding store operations, such as storing data from different corresponding ones of the widest packed data registers (or other widest data registers) to different corresponding segments or portions of the hierarchical buffer. In the example shown, only the first and second data portions are shown, although in other embodiments there can be more than two portions (e.g., four, eight, etc.). In some embodiments, each segment can optionally be the same width as the widest packed data or other widest registers of the logical processor, although this is not a requirement. In other embodiments, each segment can optionally be one quarter or one half of the width of the widest packed data or other widest registers of the logical processor.

[0064] In some embodiments, after all of the different portions of data that collectively represent the total amount of data to be atomically stored to memory have been stored to different corresponding portions of the hierarchical buffer, responsive to instruction 508, the execution unit can be operative to simultaneously store all of the different portions of data that collectively represent the total amount of data to be atomically stored from the hierarchical buffer 552 to memory (e.g., to another storage location, to a bus, etc.). In the particular example shown, the other storage location to which this data is to be stored is shown as a write-combining buffer 556, although the scope of the application is not so limited. As shown, the write-combining buffer can have a first write-combining buffer segment or portion 558-1 of the first width for storing data from the first hierarchical buffer segment or portion 554-1 of the first width, and a second write-combining buffer segment or portion 558-2 of the first width for storing data from the second hierarchical buffer segment or portion 554-2 of the first width. In some embodiments, the write-combining buffer can be allocated first, and then filled with data from the hierarchical buffer in a single store operation. In some embodiments, the write-combining buffer can be implemented in a data cache unit (e.g., in a level one (LI) data cache controller), although the scope of the application is not so limited.

[0065] As shown, in some embodiments, the write-combining buffer 556 can have one or more bits representing a non-merge field 560. In some embodiments, after multiple different portions of the indicated data have been stored to the write-combining buffer, the execution unit, in response to the instruction 508, can optionally operate to configure the non-merge field of the write-combining buffer to disallow merging (e.g., no allowed merging). As an example, this can help prevent younger store operations (e.g., younger and / or subsequent to the instruction 508 in the original program order) from merging with the write-combining buffer. This can help prevent other data that is not intended to be part of an atomic store to memory from inadvertently overwriting some of the data that has been in the write-combining buffer to be atomically stored to memory.

[0066] As shown, in some embodiments, the write-combining buffer 556 can have one or more bits representing an eviction field 562. In some embodiments, after multiple different portions of the indicated data have been stored to the write-combining buffer, the execution unit, in response to the instruction 508, can optionally operate to configure the eviction field of the write-combining buffer so that the write-combining buffer is marked and / or ready for eviction. In some embodiments, it can be desirable to do this immediately or at least soon after the data has been stored to the write-combining buffer from the staging buffer. Generally, no additional data should be merged or stored to the write-combining buffer at this time, so it is best to evict the write-combining buffer as soon as possible so that it can then be recycled and used for other store operations. Also, in cases where the data is used to assign work to an accelerator device or other device, as will be discussed further below, it can generally be best to send this data early rather than later so that the other device can begin acting on it. As an example, such configuration can generally be performed within about one to about ten clock cycles of the logical processor, or within about one to about five clock cycles, although this is not required. The eviction of the write-combining buffer can continue through the memory subsystem to memory. In some embodiments, the atomic store operations can bypass and / or not be stored to one or more cache memories of the processor. For example, they can be write-combining non-cacheable stores.

[0067] Advantageously, including a staging buffer 552 as a separate structure from the write-combining buffer 556 can tend to help simplify implementation. In some embodiments, the write-combining buffer can be designed to support the architectural capability to be flushed or evicted to memory at any given point in time. Without having a separate staging buffer, if the write-combining buffer is used instead to accumulate the different data portions of an atomic store operation, a flush or eviction to memory can occur at an intermediate point in time when some but not all of the different data portions of the atomic store operation are stored in the write-combining buffer. However, guaranteeing the atomicity of the entire store operation generally implies that either the entire store should be performed or no store should be performed of such an incomplete portion of the total store. However, the staging buffer is not required to support the capability to be flushed or evicted to memory at any given point in time. Accordingly, the staging buffer can accumulate or collect all of the different data portions of an atomic store operation and then write all of these different data portions to the write-combining buffer in one operation. This can help ensure the atomicity of the store of all of the data. Alternatively, if desired, the staging buffer can optionally be omitted and the write-combining buffer can instead be used with modifications to prevent a flush or eviction to memory at least at intermediate points in time when some but not all of the different data portions of the atomic store operation are stored in the write-combining buffer if the write-combining buffer is used to implement the atomic store to memory instruction 508. For example, a given write-combining buffer can be dedicated, reserved, or locked for use exclusively for implementation of the atomic store to memory instruction such that it is treated differently (e.g., does not require the capability to be flushed or evicted to memory at any given point in time when implementing the atomic store to memory instruction).

[0068] Figure 6 is a block diagram of an embodiment of a logic processor 601 having a more particular second detailed example embodiment of an execution unit 632 including a staging buffer and a write-combining buffer 656 to perform an embodiment of an atomic store to memory instruction 608. In some embodiments, the logic processor 601 can optionally be used to perform the method 226 of Figure 2 and / or the method 440 of Figure 4 Alternatively, the method 226 and / or the method 440 can optionally be performed by a similar or different processor or device. Moreover, the logic processor 601 can optionally perform a similar or different method than the method 226 and / or the method 440.

[0069] The logic processor 601 in this particular example includes a 128-bit packed data register set 614 (which represents the widest set of data registers of the logic processor and / or the widest set of data registers supported by the logic processor), a decoding unit 630 for receiving and decoding atomically stored-to-memory instructions 608, and an execution unit 632. Unless otherwise stated or otherwise clearly apparent, these components may optionally have Figure 3 The corresponding named components possess some or all of their characteristics. The execution unit in this particular example includes a 512-bit hierarchical buffer 652 and a 512-bit write combination buffer 656. Unless otherwise stated or clearly apparent, the hierarchical buffer and write combination buffer may optionally have... Figure 5 This describes some or all of the characteristics of those hierarchical buffers and write combination buffers. To avoid ambiguity, the different and / or additional characteristics will be described primarily, without repeating all characteristics that may optionally be the same or similar.

[0070] exist Figure 6 In this embodiment, the 128-bit packed data register 614 is the widest data register of the logic processor 601 and / or the widest data register supported by the logic processor 601. The atomic store-to-memory instruction 608 indicates data to be atomically stored to memory, which includes a first 128-bit data portion 650-1, a second 128-bit data portion 650-2, a third 128-bit data portion 650-3, and a fourth 128-bit data portion 650-4. The first 128-bit data portion 650-1 is stored in the first 128-bit packed data register 614-1, the second 128-bit data portion 650-2 is stored in the second 128-bit packed data register 614-2, the third 128-bit data portion 650-3 is stored in the third 128-bit packed data register 614-3, and the fourth 128-bit data portion 650-4 is stored in the fourth 128-bit packed data register 614-4. In other embodiments, temporary registers may alternatively be used to hold data loaded from source memory operands, as described elsewhere herein. Furthermore, 128 bits is merely an illustrative example of a suitable size for these data portions and the widest data register. In other embodiments, they may, for example, be 64 bits, 256 bits, or 512 bits, respectively.

[0071] The decode unit 630 is coupled with a microcode read-only memory (ROM) 668. The microcode ROM can be used to store microcode, microinstructions, or other lower level instructions, control signals, or operations of the instruction set for the logic processor, including the atomic store-to-memory instruction 608. As an example, the decode unit can decode the atomic store-to-memory instruction into a microcode entry point into the microcode in the microcode ROM to retrieve microcode, microinstructions, or other lower level instructions, control signals, or operations (e.g., a microcode sequence) to implement the atomic store-to-memory instruction. The identified lower level instructions or control signals (e.g., microcode sequence) can be output from the microcode ROM to the execution unit to implement the atomic store-to-memory instruction.

[0072] As shown in the example embodiment shown, the microcode ROM can include store-to-prefetch buffer instructions, control signals, or operations 670, and store-from-prefetch buffer to write-combining buffer instructions, control signals, or operations 671. In some embodiments, the store-to-prefetch buffer operations 670 can be executed to store a specified or indicated one of the 128-bit data portions 650 from its initial storage location (e.g., one of the 128-bit packed data registers 614 in this example) to a specified or indicated one of a plurality of different prefetch buffer segments or portions (e.g., four different 128-bit prefetch buffer segments or portions 654 in this example). For example, a first instance of the store-to-prefetch buffer operation can be executed to perform a first store operation 672-1 to store the first 128-bit data portion 650-1 to the first 128-bit prefetch buffer portion or segment 654-1, and a second instance of the store-to-prefetch buffer operation can be executed to perform a second store operation 672-2 to store the second 128-bit data portion 650-2 to the second 128-bit prefetch buffer portion or segment 654-2. Continuing, a third instance of the store-to-prefetch buffer operation can be executed to perform a third store operation 672-3 to store the third 128-bit data portion 650-3 to the third 128-bit prefetch buffer portion or segment 654-3 and a fourth instance of the store-to-prefetch buffer operation can be executed to perform a fourth store operation 672-4 to store the fourth 128-bit data portion 650-4 to the fourth 128-bit prefetch buffer portion or segment 654-4. In this particular example, the prefetch buffer is a 512-bit prefetch buffer, although the scope of the present application is not so limited.

[0073] In some embodiments, the store to hierarchical buffer operation 670 can indicate data to be copied. In this example, a 128-bit portion of the data is used, although in other examples, a wider or narrower portion of the data can be used instead. For example, the operation can have one or more bits or fields to specify one of: a 128-bit packed data register 614 with the data 650, or a temporary register with the data, etc. The operation can also have one or more bits or fields to specify or otherwise indicate one of a plurality of different segments or portions 654 of the hierarchical buffer. Typically, the hierarchical buffer need not be addressed by a full memory address. Rather, a simple index or selector value can be used to index, address or select one of the plurality of different segments or portions of the hierarchical buffer. For example, a 1-bit index can be used to index or select between two segments or portions of the hierarchical buffer, or a 2-bit index can be used to index or select between four segments or portions of the hierarchical buffer, or a 3-bit index can be used to index or select between eight segments or portions of the hierarchical buffer. Accordingly, for this store operation, the base and index (e.g., as used to address memory for other operations) can be set to zero, and the scale can be set to 1, and a 1-bit, 2-bit or 3-bit index can be configured to have an appropriate value to index or select one of the different segments or portions of the hierarchical buffer on which to store the data. Moreover, since the hierarchical buffer need not be addressed by a full memory address, there is no need for this store operation to search a translation lookaside buffer (TLB). There is also no need to support data forwarding to younger loads. This store operation can be non-blocking, since there is no need to apply address conflicts, etc. There can also be no need to perform breakpoint detection or any "nuke." This store operation also need not suffer from ordering restrictions.

[0074] In some embodiments, after the four different 128-bit data portions 650 have been stored to the staging buffer 652, the execution unit 632, responsive to the instruction 608, can be operable to perform a store from the staging buffer to the write-combining buffer operation 671 to store the entire contents of the staging buffer 652 (in this specific example, a 512-bit staging buffer) to the write-combining buffer 656 (in this specific example, a 512-bit write-combining buffer) simultaneously in a single store operation. Alternatively, instead of a write-combining buffer, another storage location can optionally be used, or the data can optionally be provided directly to a bus or other interconnect. In some embodiments, this store operation can be allowed to coalesce with older write-combining buffers. Or, if this store operation does not coalesce with older write-combining buffers, this store operation can be remiss and allocate a write-combining fill buffer. In being remiss, this store operation can block anything (e.g., younger store operations) in the pipeline after it, as well as possibly using a senior store pipe of the data cache fill port, e.g., resource conflict conditions, and fill the allocated write-combining buffer with the contents of the staging buffer.

[0075] In some embodiments, the operation 671 can use memory addresses according to memory address information indicated by the atomic store to memory instruction 608. As one specific example, an effective address can be computed to obtain a linear address using a displacement added to a base address from a segment register indicated by the atomic store to memory instruction, as well as a base, scale, index, although the scope of the application is not so limited. In some embodiments, the store, all address computation and right and limit checking can be associated with an address size and operand size of 512 bits for the operation, although the scope of the application is not so limited. In some embodiments, in 64-bit mode, a canonical address form violation can be checked instead of segment limit checking, although the scope of the application is not so limited. In some embodiments, when generating a linear address for the store, if the linear address is not 64-byte aligned, it can cause a general protection fault, although the scope of the application is not so limited. In some embodiments, the operation 671 can force the memory type to be uncacheable random-combined write (USWC) regardless of the underlying memory type. This store operation is a weakly-ordered store operation.

[0076] In some embodiments, depending on the particular implementation, the store corresponding to operation 671 can optionally be marked as non-forwardable. Typically, a processor can have the ability to satisfy a younger load with results of an older store that bypassed through an internal bypass, where the older store data is routed to the younger load. However, in some implementations, preventing such forwarding can be desirable. For example, this can be the case when an atomic store to memory instruction is used to submit work to an accelerator device, where in the case that the accelerator device modifies the data after it has been stored to the destination memory location, it can be appropriate for the younger read to obtain the data from the actual destination memory location. In other embodiments, for example for other uses of the atomic store to memory instruction, there can be no need to mark the store as non-forwardable.

[0077] As shown, in some embodiments, the write-combination buffer 656 can have one or more bits representing a non-merge field 660, and one or more bits representing an eviction field 662. In some embodiments, operation 671 can optionally operate to configure the non-merge field of the write-combination buffer to not allow merging (e.g., no merging allowed), and can optionally operate to configure the eviction field of the write-combination buffer so that the write-combination buffer is marked and / or ready for eviction.

[0078] The atomic store to memory instructions disclosed herein can provide architectural support for atomic stores for a total width of data to be stored. Further, in some embodiments, the data to be atomically stored can initially be loaded from a source memory operand. In some embodiments, due to the atomicity of the store to memory operation, if any part of the implementation of the atomic store to memory instruction fails, experiences a violation or exception condition, or otherwise malfunctions, no part of the data should be transmitted on the bus to memory, and no part of the data should be stored in memory. In some embodiments, a breakpoint, range-based check, failure check, etc. can be performed for the entire width of a destination operand on which data is to be atomically stored. As an example, in response to an atomic store to memory instruction, an execution unit can generate the memory addresses of the first byte and last byte of a memory location at which data is to be atomically stored (e.g., using any of a variety of possible addressing modes), and when the atomic store to memory instruction retires or commits, the processor can perform checks and signaling for a segment limit violation, range-based violation, failure, breakpoint, etc. on any byte from the first byte to the last byte. As an example with respect to a breakpoint, a breakpoint can potentially have been configured on any byte of a destination memory location for the total width of data to be stored atomically. In some embodiments, if there is a breakpoint on any of these bytes, the breakpoint can be signaled when the instruction completes (e.g., retires or commits).

[0079] In some embodiments, the atomic store-to-memory instructions disclosed herein can be employed as part of an algorithm to pass data to another device (e.g., an accelerator device, an input and / or output (I / O) device (e.g., a high performance memory controller), etc.) through a mutually accessible storage location in memory. As an example, the atomic store-to-memory instruction can represent a work submission instruction that is employed as part of an algorithm or instruction set that a logical processor can execute to store data associated with a work or task that an accelerator device is to perform to a memory location, and the accelerator device can retrieve the data from the memory location. In some cases, the memory location can correspond to an MMIO range (e.g., a MMIO control register of a device in the MMIP space of the device). A wide variety of different types of accelerators are suitable, such as, for example, a graphics accelerator, a networking accelerator, a machine learning accelerator, a computer vision accelerator, a cryptography accelerator, a fixed function accelerator, a general purpose graphics processing unit (GPGPU), a field programmable gate array (FPGA), etc., just to name a few examples. The memory location can represent a logical register (e.g., a work submission register) or other interface through which the processor and accelerator device communicate. In some embodiments, the memory location can also be accessible from one or more other logical processors that can also use the memory location to pass data to the device (e.g., to assign work to the accelerator device). In such embodiments, the ability to atomically store an entire quantity of data to the memory location can be beneficial such that the one or more other logical processors can not be able to perform interfering stores (e.g., simultaneous or interleaved stores to the same memory location and thereby corrupt the data), which can corrupt the entire quantity of data, incorrectly assign work, etc. The atomic store-to-memory instruction can help ensure that the entire quantity of data (e.g., an entire logical register in memory) is stored all at once and only by a single logical processor. Moreover, the atomic store-to-memory instruction can provide an efficient way in which two or more logical processors can be able to assign work to the same accelerator device without needing to mutually synchronize or coordinate with each other, acquire locks, etc.

[0080] In some embodiments, there can be different types of atomic store-to-memory instructions for implementing a work submission instruction or other instruction for passing data to another device. One such type can not expect a response from the other device related to the atomic store of data to memory. For this type, the retirement or commit unit of the processor can retire or commit the atomic store-to-memory instruction after the data has been atomically stored to memory without waiting and / or without needing to receive a response from the other device.

[0081] Another type of atomic store-to-memory instruction can anticipate a response from the other device related to the atomic store of data to memory. For example, the response from the other device can indicate that the atomic store of data to memory has been observed, confirmed, received, accepted, and so on (e.g., the work submission has been accepted). Representatively, such a response can indicate to the logical processor performing the atomic store operation that the atomic store operation is fully observed in the system and is now fully consistent. This response can be provided in different ways, such as, for example, by the other device configuring one or more bits in an architecturally visible register or storage location of the processor (e.g., setting one or more status bits in a status register), the other device providing a dedicated signal, the other device configuring one or more bits in the destination memory location, or in other ways. For this type of atomic store-to-memory instruction, after the data has been atomically stored to memory, the retirement unit of the processor can wait to retire the atomic store-to-memory instruction until after such a response from the other device is received. Until retirement, the instruction can command younger strongly-ordered instructions, such as, for example, fence instructions, strongly-ordered store instructions, lock instructions, and so on, until the instruction is retired (e.g., when the atomically stored data is globally observed in the system and is fully consistent).

[0082] As one particular example, such a response can indicate to the logical processor that the atomic store operation caused an accepted work submission to the accelerator device. As an example, the accelerator device can have an internal work queue or buffer (e.g., a shared work queue) that is fed by the data stored to the destination memory location of the atomic store-to-memory instruction (e.g., an MMIO mapped shared work queue portal register). In some cases, the internal work queue or buffer can have sufficient storage space or capacity to accept the data of the atomic store operation, the data can be moved from the destination memory location into the internal work queue or buffer, and the accelerator device can provide a response indicating that the work submission was accepted by the accelerator device. In other cases, the internal work queue or buffer can not have sufficient storage space or capacity to accept the data of the atomic store operation, and the accelerator device can provide a response indicating that the work submission was not accepted by the accelerator device.

[0083] Exemplary core, processor, and computer architectures

[0084] Processor cores can be implemented in different ways, for different purposes, and in different processors. For example, implementations of such cores can include: 1) general-purpose in-order cores intended for general purpose computing; 2) high- performance general-purpose out-of-order cores intended for general purpose computing; 3) special-purpose cores intended primarily for graphics and / or scientific (throughput) computing. Implementations of different processors can include: 1) CPUs with one or more general-purpose in-order cores and / or one or more general-purpose out-of-order cores; and 2) coprocessors with one or more special-purpose cores, e.g., graphics and / or scientific (throughput) computing cores. Such different processors lead to different computer system architectures, which can include: 1) computers with one or more processors as described above; and 2) computers with one or more coprocessors as described above. Exemplary core architectures are described next, followed by descriptions of exemplary processor and computer architectures.

[0085] Exemplary Core Architectures

[0086] In-Order and Out-of-Order Core Block Diagrams

[0087] Figure 7A is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue / execution pipeline according to embodiments of the application. Figure 7B is a block diagram illustrating both an exemplary in-order architecture core and an exemplary register renaming, out-of-order execution architecture core to be included in a processor according to embodiments of the application. Figure 7A The solid lined boxes in the Figure 9A represent a known in-order pipeline of a core according to embodiments of the application, while the dashed lined boxes represent a known out-of-order pipeline of a core. Thus, Figure 9A illustrates a core 900 having an in-order front end followed by an out-of-order back end, while Figure 9B illustrates a core having an out-of-order front end followed by an in-order back end.

[0088] In Figure 7A In the Figure 7A, the processor pipeline 700 includes a fetch stage 702, a length decode stage 704, a decode stage 706, an allocation stage 708, a renaming stage 710, a scheduling (also known as dispatch or issue) stage 712, a register read / memory read stage 714, an execution stage 716, a write back / memory write stage 718, an exception handling stage 722, and a commit stage 724.

[0089] Figure 7BA processor core 790 is shown including a front end unit 730 coupled to an execution engine unit 750, and both are coupled to a memory unit 770. The core 790 can be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As a yet further option, the core 790 can be a specialized core, such as, for example, a network or communication core, a compression engine, a coprocessor core, a general purpose computing graphics processing unit (GPGPU) core, a graphics core, and the like.

[0090] The front end unit 730 includes a branch prediction unit 732 coupled to an instruction cache unit 734, which is coupled to an instruction translation lookaside buffer (TLB) 736, which is coupled to an instruction fetch unit 738, which is coupled to a decode unit 740. The decode unit 740 (or decoder) can decode instructions, and generate one or more micro-operations, microcode entries, microinstructions, other instructions, or other control signals, which are used to control the functioning of the processor core 790. The decode unit 740 can be implemented using various different mechanisms, such as, for example, lookup tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), and the like. In one embodiment, the core 790 includes a microcode ROM or other medium, which stores microcode for certain macroinstructions (e.g., in the decode unit 740 or otherwise within the front end unit 730). The decode unit 740 is coupled to a rename / allocator unit 752 in the execution engine unit 750.

[0091] The execution engine unit 750 includes a rename / allocator unit 752 coupled to a retirement unit 754 and a set of one or more scheduler units 756. The scheduler units 756 represent any number of different schedulers, including a reservation station, a central instruction window, etc. The set of one or more scheduler units 756 are coupled to one or more physical register file units 758. Each of the physical register file units 758 represents a plurality of physical registers, and the different physical register file units 758 store different types of data (e.g., single and double precision floating point data, integer data, vector data, etc.). In one embodiment, the physical register file units 758 include a vector register unit, a write mask register unit, and a scalar register unit. These register units can provide architectural vector, vector mask, and scalar registers, respectively. One or more physical register file units 758 overlap with a retirement unit 754 to illustrate various ways in which register renaming and out-of-order execution can be implemented (e.g., using one or more re-order buffers and one or more physical register files to store values for the reordered instructions); using one or more reorder buffers, one or more history buffers, and one or more physical register files to store values for the reordered instructions; using register mapping and pools that are shared with other register sets; etc.). The retirement unit 754 and one or more physical register file units 758 are coupled to a set of one or more execution clusters 760. Each of the execution clusters 760 includes a set of one or more

[0092] A set of memory access units 764 are coupled to the memory unit 770, which includes a data TLB unit 772 coupled to a data cache unit 774, which is coupled to a level 2 (L2) cache unit 776. In one exemplary embodiment, the memory access units 764 can include load units, store address units, and store data units, each of which are coupled to the data TLB unit 772 in the memory unit 770. The instruction cache unit 734 is further coupled to the level 2 (L2) cache unit 776 in the memory unit 770. The L2 cache unit 776 is coupled to one or more other levels of cache, and ultimately to main memory.

[0093] By way of example, an exemplary register renaming, out-of-order issue / execution core architecture can implement the following pipeline 700: 1) instruction fetch 738 performs fetch and length decode; 2) a decode unit 740 decodes the fetched instructions; 3) a rename / allocator unit 752 allocates and names registers and queues micro-operations; 4) a scheduler unit 756 allocates the operation to the various execution units; 5) one or more

[0094] The core 790 can support one or more instruction sets (e.g., the x86 instruction set (with some extensions that have been added with newer versions); the MIPS instruction set; and / or the ARM instruction set (with optional additional extensions such as NEON)). The core 790 can also include logic to handle a

[0095] It should be appreciated that a core can support multithreading (two or more parallel sets of execution operations or threads), and can do so in a number of ways including those involving the time-sliced multithreading, simultaneous multithreading (where a physical core provides logical cores for each thread that the physical core is performing simultaneous multithreading), or a combination thereof (e.g., time-sliced fetch and decode with subsequent simultaneous multithreading, such as in Intel® Hyper-Threading Technology).

[0096] While register renaming is described in the context of out-of-order execution, it should be appreciated that register renaming can be used in in-order architectures. While the illustrated embodiment of the processor also includes separate instruction and data cache units 734 / 774, as well as a shared L2 cache unit 776, alternative embodiments can have a single internal cache for both instructions and data, such as for example, a unified cache, or multiple levels of internal caches. In some embodiments, a system can include a combination of internal caches and external caches that are external to, but accessed by, the cores and / or the processor. Alternatively, all caches can be external to the cores and / or processor.

[0097] A particular exemplary in-order core architecture

[0098] Figure 8A -B shows a block diagram of a more particular exemplary in-order core architecture that can be used within the cores 104, 104' of the processor 100 described herein. The core 100 includes integer and floating point logical units 1002A-M and 1002N-P coupled to a cache unit 1004 that is in turn coupled to a set of one or more bus controller units 1006 that enable the core 100 to communicate with the system bus 102. The core 100 also includes an integrated memory controller unit) 1008 that can include a cache unit and that can be used to communicate with the system memory 106. The core 100 also includes a set of execution units (including, for example, integer and floating point logical units) 1010A-D that can implement a variety of operations, as well as one or more microcode control units 1012A-B. One or more integer register files 1014A-B and one or more floating point register files 1016A-B can also be included.

[0099] Figure 8A is a block diagram of a single processor core in accordance with an embodiment of the present application, along with its connection to an on-die interconnect network 802 and its local set of level two (L2) cache 804. In one embodiment, the instruction decoder 800 supports the x86 instruction set with the AVX2 instruction set extension. The L1 cache 806 allows for low latency access to cache memory into the scalar and vector units. While in one embodiment (for simplicity of design) the scalar unit 808 and vector unit 810 use separate register sets (scalar and vector registers 812 and 814, respectively), and data transferred between them is written to memory and then read back from the level one (L1) cache 806, alternative embodiments of the present application can use different means (e.g., using a single register set or including a communication path that allows data to be transferred between the two register files without being written and read back).

[0100] The local subset of the L2 cache 804 is a portion of the global L2 cache that is partitioned into separate local subsets, one per processor core. Each processor core has a direct access path to its own local subset of the L2 cache 804. Data read by a processor core is stored in its L2 cache subset 804 and can be accessed quickly, in parallel with other processor cores accessing their own local L2 cache subsets. Data written by a processor core is stored in its own L2 cache subset 804 and, if necessary, evicted from other subsets. A ring network ensures coherence of shared data. The ring network is bidirectional to allow agents such as processor cores, the L2 cache, and other logical blocks to communicate with each other within the chip. Each ring data-path is 1012 bits wide in each direction.

[0101] Figure 8B is an expanded view of a portion of the processor core in Figure 8A according to embodiments of the application. Figure 8B includes the LI data cache 806A portion of the LI cache 804, and more details regarding the vector unit 810 and vector registers 814. Specifically, the vector unit 810 is a 16-wide vector processing unit (VPU) (see 16-wide ALU 828) that is configured to execute one or more integer, single precision floating point, and double precision floating point instructions. The VPU supports a move- packed operation that moves unaligned memory data into registers by shuffling the data in packs through a shuffle unit 820, a data conversion through a data conversion unit 822A-B, and a copy through a copy unit 824. A write mask register 826 allows prediction of results that can be written into a vector register file.

[0102] Processor with integrated memory controller and graphics

[0103] Figure 9 is a block diagram of a processor 900 that can have more than one core, that can have an integrated memory controller, and that can have integrated graphics, according to embodiments of the application. Figure 9 The solid line boxes in show the processor 900 with a single core 902A, system agent 910, set of one or more bus controller units 916, while the optional additional of the dashed line boxes show the alternative processor 900 with multiple cores 902A-N, set of one or more integrated memory controller units 914 in the system agent unit 910, and a special purpose logic 908.

[0104] Thus, different implementations of the processor 900 can include: 1) a CPU with the core(s) 902A-N being general -purpose cores (e.g., cores designed to execute a wide variety of instructions and / or sequences of instructions), the dedicated logic 908 being integrated graphics and / or scientific (throughput) logic (which can include one or more cores), and the core(s) 902A-N being one or more general -purpose cores (e.g., general -purpose in-order cores, general -purpose out-of-order cores, a combination of the two); 2) a coprocessor with the core(s) 902A-N being a large number of special -purpose cores intended primarily for graphics and / or scientific (throughput); and 3) a coprocessor with the core(s) 902A-N being a large number of general -purpose in-order cores. Thus, the processor 900 can be a general -purpose processor, a coprocessor or a special -purpose processor, such as for example, a network or communication processor (NCP), compression engine, graphics processor, GPGPU (General Purpose Graphics Processing Unit), a High-Throughput many integrated core (MIC) coprocessor (including 30 or more cores), embedded processor, and / or the like. The processor can be implemented on one or more chips. The processor 900 can be implemented using any of a wide variety of technologies, such as for example, BiCMOS, CMOS, or NMOS, on one or more substrates and / or be part of one or more substrates.

[0105] The memory hierarchy includes one or more levels of cache within a core, a set or one or more shared cache units 906, and external memories (not shown) coupled to the set of integrated memory controller units 914. The set of shared cache units 906 can include one or more levels of cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, last level cache (LLC), and / or combinations thereof. Although an on-chip, ring-based interconnect unit 912 interconnects the integrated graphics logic 908, the set of shared cache units 906, and the system agent units 910 / integrated memory controller units 914 in one embodiment, alternative embodiments can use any of a wide variety of known technologies for interconnecting such units. In one embodiment, the coherency between the one or more cache units 906 and the cores 902-A-N is maintained.

[0106] In some embodiments, one or more of the cores 902A-N have a multithreaded capability. The system agent 910 includes those components coordinating and operating cores 902A-N. The system agent unit 910 can include for example a power control unit (PCU) and a display unit. The PCU can be or include logic and components needed for regulating the power state of the integrated graphics logic 908 and the cores 902A-N. The display unit is an interface to one or more externally connected displays.

[0107] The cores 902A-N can be homogeneous or heterogeneous with respect to the architectural instruction sets; that is, two or more of the cores 902A-N can have the ability to execute the same instruction set while others can have the ability to execute a different instruction set or a subset of that instruction set.

[0108] Exemplary Computer Architecture

[0109] Figure 10-13 is a block diagram of an exemplary computer architecture. Other system designs and configurations known in the arts for laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network appliances, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, micro controllers, cell phones, portable media players, hand held devices, and various other electronic devices, are also suitable. In general, a huge variety of systems or electronic devices capable of incorporating a processor and / or other execution logic as disclosed herein are generally suitable.

[0110] Referring now to Figure 10 , a block diagram of a system 1000 is shown in accordance with one embodiment of the present application. The system 1000 can include one or more processors 1010, 1015 coupled to a controller hub 1020. In one embodiment the controller hub 1020 includes a graphics memory controller hub (GMCH) 1090 and an input / output controller hub (IOH) 1050, which can be separate chips. The GMCH 1090 includes memory and I / O controllers to the memory 1040 and to the graphics processor 1045, which can be integrated or discrete. The IOH 1050 is to couple the input / output (I / O) devices 1060 to the GMCH 1090. Alternatively, one or both of the memory and graphics controllers are integrated within the processor and the memory 1040 and graphics processor 1045 are coupled to the controller hub 1020 within the single package or chip.

[0111] The optional nature of additional processors 1015 is denoted in Figure 10 . Each processor 1010, 1015 can include one or more of the processing cores described herein and can be some version of the processor 900.

[0112] The memory 1040 can be, for example, dynamic random access memory (DRAM), phase change memory (PCM), or a combination of the two. For at least one embodiment, the controller hub 1020 communicates with the one or more processors 1010, 1015 via a multi-point bus, such as a frontside bus (FSB), a point-to-point interface such as a QuickPath Interconnect (QPI), or a similar connection 1095.

[0113] In one embodiment, the coprocessor 1045 is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, a GPGPU, embedded processor, or the like. In one embodiment, controller hub 1020 can include an integrated graphics processor.

[0114] There can be a variety of differences between the physical resources 1010, 1015 in terms of a spectrum of metrics of merit, such as architectural, microarchitectural, thermal, power consumption characteristics, and the like.

[0115] In one embodiment, the processor 1010 executes instructions to perform a data processing operation. Embedded within the instructions can be coprocessor instructions. The processor 1010 recognizes these coprocessor instructions as being of a type that should be executed by the attached coprocessors 1045. Accordingly, the processor 1010 issues these coprocessor instructions (or control signals representing the coprocessor instructions) on a coprocessor bus or other interconnect to the coprocessors 1045. One or more of the coprocessors 1045 accept and execute the received coprocessor instructions.

[0116] Referring now to the Figure 11 , a block diagram of a first more specific exemplary system 1100 according to an embodiment of the present application is shown. As shown in Figure 11 , a multiprocessor system 1100 is a point-to-point interconnect system, and includes a first processor 1170 and a second processor 1180 coupled via a point-to-point interconnect 1150. Each of the processors 1170 and 1180 can be some version of the processor 900. In one embodiment of the application, processors 1170 and 1180 are processors 1010 and 1015, respectively, while coprocessor 1138 is coprocessor 1045. In another embodiment, processors 1170 and 1180 are processors 1010, coprocessor 1045, respectively.

[0117] Processors 1170 and 1180 are shown including integrated memory controller (IMC) units 1172 and 1182, respectively. Processor 1170 also includes point-to-point (P-P) interfaces 1176 and 1178 as part of its bus controller units; similarly, second processor 1180 includes P-P interfaces 1186 and 1188. Processors 1170, 1180 can exchange information via a point-to-point (P-P) interface 1150 using P-P interface circuits 1178, 1188. Figure 11 As shown in , IMCs 1172 and 1182 couple the processors to respective memories, namely memory 1132 and memory 1134, which can be portions of main memory locally attached to the respective processors.

[0118] Using point-to-point interface circuits 1176, 1194, 1186, 1198, processors 1170, 1180 can inter- communicate via individual P-P interfaces 1152, 1154, respectively, with a chipset 1190. Chipset 1190 can optionally be coupled to a first bus 1131 representing a high speed (e.g., 6400 GB / s or higher) bus, representing, for example, a high speed memory bus, using bus interface 1198. Chipset 1190 can be coupled to a second bus 1130 representing a lower speed bus (e.g., 1.6 GB / s or lower) than first bus 1131 using bus interface 1196. Although first bus 1131 and second bus 1130 are shown as separate buses, two single buses can be implemented as a single double wide bus.

[0119] A shared cache (not shown) can be included in either processor or outside of both processors, connected via P-P interconnects, such that the local cache information for either or both processors can be stored in the shared cache if the processors are placed in a low power mode.

[0120] Chipset 1190 can be coupled to a first bus 1116 via an interface 1196. In one embodiment, first bus 1116 can be a Peripheral Component Interconnect (PCI) bus, or buses, such as a PCI Express bus or another third generation I / O interconnect bus, although the scope of the application is not so limited.

[0121] As shown in Figure 11 Various I / O devices 1114 can be coupled to first bus 1116, along with a bus bridge 1118, which couples first bus 1116 to a second bus 1120. In one embodiment, one or more additional processors 1115, such as coprocessors, high-speed MICs, GPGPU, accelerators, such as, for example, graphics accelerators or digital signal processing (DSP) units, field programmable gate arrays, or any other processor, can be coupled to first bus 1116. In one embodiment, second bus 1120 can be a low pin count (LPC) bus. Various devices can be coupled to second bus 1120 including, for example, a keyboard and / or mouse 1122, communication device 1127 and a storage unit 1128, such as a disk drive or other mass storage device, which can include instructions / codes and data 1130 (in one embodiment). Further, an audio I / O 1124 can be coupled to second bus 1120. Note that other architectures are possible. For example, a point-to-point architecture can be used instead of a bus architecture. Figure 11

[0122] Referring now to Figure 12 , shown is a block diagram of a second more particular exemplary system 1200, in accordance with an embodiment of the present application. Figure 11 and 12 ​Similar elements in the figures have similar reference numerals, and Figure 11 Some aspects have been from Figure 12 The middle part is omitted to avoid ambiguity. Figure 12 Other aspects.

[0123] Figure 12 Processors 1170 and 1180 are shown to include integrated memory and I / O control logic (“CL”) 1172 and 1182, respectively. Therefore, CL 1172 and 1182 include an integrated memory controller unit and I / O control logic. Figure 12 It is shown that not only are memories 1132 and 1134 coupled to CLs 1172 and 1182, but I / O device 1214 is also coupled to control logic 1172 and 1182. Legacy I / O device 1215 is coupled to chipset 1190.

[0124] Now for reference Figure 13 The diagram shown is a block diagram of a SoC 1300 according to an embodiment of the present invention. Figure 9 Similar components in the diagram have similar reference numerals. Similarly, the dashed box is an optional feature on more advanced SoCs. Figure 13 In this embodiment, one or more interconnect units 1302 are coupled to: an application processor 1310, which includes a collection of one or more cores 202A-N and one or more shared cache memory units 906; a system agent unit 910; one or more bus controller units 916; one or more integrated memory controller units 914; a set or one or more coprocessors 1320, which may include integrated graphics logic, an image processor, an audio processor, and a video processor; a static random access memory (SRAM) unit 1330; a direct memory access (DMA) unit 1332; and a display unit 1340 for coupling to one or more external displays. In one embodiment, one or more coprocessors 1320 include dedicated processors, such as, for example, network or communication processors, compression engines, GPGPUs, high-throughput MIC processors, embedded processors, and the like.

[0125] Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementations. Embodiments of the invention may be implemented as program code or a computer program executable on a programmable system, said programmable system including at least one processor, a storage system (including volatile and non-volatile memories and / or storage elements), at least one input device, and at least one output device.

[0126] Such as Figure 11The program code of the instructions 1130 illustrated in FIG. 11 can be applied to input instructions to perform the functions described herein and generate output information. The output information can be applied along with known methodologies for one or more output devices. For purposes of this application, a processing system includes any system that has a processor, such as, for example: a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

[0127] The program code can be implemented in a high level procedural or object oriented programming language to communicate with a processing system. If desired, the program code can also be implemented in an assembly or machine language. In fact, the mechanisms described herein are not limited in scope to any particular programming language. In any case, the language can be a compiled or interpreted language.

[0128] One or more aspects of at least one embodiment can be implemented by representative instructions stored on a machine-readable medium which represents various logic within the processor, which when read by a machine causes the machine to fabricate logic to perform the techniques described herein. Such representations, known as "IP cores" can be stored on a tangible, machine readable medium and supplied to various customers or manufacturing facilities to load into the fabrication machines that make the logic or processor.

[0129] Machine-readable storage media can include a non-transitory, tangible arrangement of items made by or comprising a machine or device, without limitation including storage media such as hard disks, floppy disks, optical disks, compact disc read-only memory (CD-ROM), compact disk recordable (CD-R), and magneto-optical disks, semiconductor memory devices such as read-only memory (ROM), random access memory (RAM), such as dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), phase change memory (PCM), magnetic or optical cards, or any other type of media suitable for storing electronic instructions.

[0130] Accordingly, embodiments of the application also include non-transitory, tangible machine-readable media containing instructions or containing design data, such as Hardware Description Language (HDL), which defines structures, circuits, apparatuses, processors and / or system features described herein. Such embodiments can also be referred to as program products.

[0131] Emulation (including binary translation, code morphing, etc.)

[0132] In some cases, an instruction translator can be used to translate instructions from a source instruction set to a target instruction set. For example, an instruction translator can translate (e.g., using static binary translation, dynamic binary translation including dynamic compilation), morph, emulate, or otherwise convert instructions to one or more other instructions to be processed by a core. An instruction translator is implemented in software, hardware, firmware, or a combination thereof. An instruction translator can be on a processor, off a processor, or partially on and partially off a processor.

[0133] Figure 14 is a block diagram that illustrates the use of a software instruction translator to translate binary instructions in a source instruction set to binary instructions in a target instruction set in accordance with an embodiment of the present application. In the illustrated embodiment, the instruction translator is a software instruction translator, although alternatively the instruction translator can be implemented in software, firmware, hardware, or various combinations thereof. Figure 14 x86 binary code 1406 that can be natively executed by a processor 1416 having at least one x86 instruction set core. The processor 1416 having at least one x86 instruction set core represents any processor that can generally execute the same software applications as an Intel processor with at least one x86 instruction set core, by virtue of compatibly implementing or otherwise supporting the instruction set for an Intel x86 instruction set core. More particularly, the processor 1416 having at least one x86 instruction set core represents any processor that can execute software applications that were compiled or otherwise written for an Intel processor with at least one x86 instruction set core, by virtue of compatibly implementing the instruction set for an Intel x86 instruction set core. As examples, the processor 1416 can include Intel processors with at least one x86 instruction set core, such as an Intel Core® processor, an Intel Core 2® processor, an Intel Core 2 Duo® processor, an Intel Core 2 Quad® processor, an Intel Xeon® processor, or an Intel Atom® processor; Intel Itanium® and Intel Itanium 2® processors; derived processors of any of the above, including Intel Cedar Mill® and Intel Orenna® processors; and / or any other processor that retains at least some compatibility with an Intel processor with at least one x86 instruction set core. Similarly, Figure 14It is shown that a program in a high level language 1402 can be compiled using alternative instruction set compiler 1408 to generate alternative instruction set binary code 1410, which can be natively executed by a processor 1414 that does not have at least one x86 instruction set core (e.g., a processor with cores executing the MIPS instruction set of MIPS Technologies of Sunnyvale, CA and / or executing the ARM instruction set of ARM Holdings of Sunnyvale, CA). An instruction translator 1412 is used to translate x86 binary code 1406 into code that can be natively executed by the processor 1414 that does not have x86 instruction set cores. The translated code would not likely be identical to the alternative instruction set binary code 1410 as it is difficult to do so; however, the translated code will perform the same functionality and be comprised of instructions from the alternative instruction set. Thus, the instruction translator 1412 represents software, firmware, hardware, or combinations thereof, which allows a processor or another electronic device without x86 instruction set processors or cores to execute x86 binary code 1406 by emulation, simulation, or any other process.

[0134] Any of the components, features, and details described for Figure 1 , 4 , 5, 6 can also optionally be applied to any of Figure 2-3 . Any of the components, features, and details described herein for a processor can optionally be applied to any of the methods described herein, which in embodiments can optionally be performed by and / or through such a processor. Any of the processors described herein can optionally be included in any of the systems disclosed herein, such as any of Figure 10-13 . Any of the instructions disclosed herein can optionally be performed by and / or through any of the processors disclosed herein, optionally in embodiments having any of the microarchitectures shown herein, and optionally in embodiments included in any of the systems shown herein.

[0135] In this description and in the claims, the terms "coupled" and / or "connected," along with their derivatives, can have been used. Such terms are not intended as synonyms for each other. Rather in embodiments, "connected" can be used to indicate that two or more elements are in direct physical and / or electrical contact with each other. "Coupled" can mean that two or more elements are in direct physical and / or electrical contact with each other. However, "coupled" can also mean that two or more elements are not in direct

[0136] The term "and / or" can have been used. As used herein, the term "and / or" means one or the other or both (e.g., A and / or B means A or B or both A and B).

[0137] In the foregoing description, specific details have been set forth in order to provide a thorough understanding of embodiments. However, embodiments can be practiced without some or all of these specific details. The scope of the disclosure is not to be determined with reference to specific examples provided above but only by the claims below. In other instances, well-known circuits, structures, devices, and operations have been shown in block diagram form and / or have been omitted, well-known circuits, structures, devices, and operations have been shown in block diagram form and / or have been omitted, to avoid obscuring the understanding of the description of the embodiments. Reference numerals or portions of reference numerals that have only one associated description can be repeated in alternate drawings to illustrate corresponding or analogous elements.

[0138] Certain operations can be performed by hardware components, or in machine- or circuit-executable instructions that can be used to cause and / or induce a machine, circuit, or hardware component (e.g., a processor, a portion of a processor, a circuit, etc.) programmed with the instructions to perform the operations. The operations can also optionally be performed by a combination of hardware and software. Processors, machines, circuits, or hardware can include specific or particular circuits or other logic (e.g., hardware potentially in combination with firmware and / or software) that are operable to execute and / or process instructions and store results in response to the instructions.

[0139] Some embodiments include an article such as a computer program product. An article of manufacture for use with a machine can include a machine-readable medium. The medium can include a mechanism that provides (e.g., stores) information in a form accessible by a machine (e.g., a computer, a processor, a processor of a computer, a circuit, etc.). The machine-readable medium can provide (or have stored thereon) instructions or a sequence of instructions that, if executed by the machine, cause the machine to perform a process of the present disclosure. The machine-readable medium can be a machine-readable storage medium or a machine-readable transmission medium.

[0140] In some embodiments, a machine readable medium can include a tangible and / or non-transitory machine readable storage medium. For example, a non-transitory machine readable storage medium can include a floppy diskette, optical storage medium such as a compact disc or DVD (Compact Disc-Read Only Memory), optical data storage device, a CD-ROM, a Blu-ray disc, a Blu- ray Disc™, a magnetic storage device, a magnetic data storage device, a magnetic disk, a magnetic tape, a magnetic strip, a RAM (Random Access Memory), a ROM (Read Only Memory), a PROM (Programmable Read Only Memory), an EPROM (Erasable Programmable Read Only Memory), an EEPROM (Electrically Erasable Programmable Read Only Memory), a flash memory, a phase change memory, a phase change data storage material, a nonvolatile memory, a nonvolatile data storage device, a non-transitory memory, a non-transitory data storage device, and / or the like. A non-transitory machine readable storage medium does not comprise a transitory propagating signal. In some embodiments, a storage medium can include a tangible medium that comprises a solid, semi-solid, or other physical form that includes a solid material, such as, for example, a semiconductor material, a phase change material, a magnetic solid material, a solid data storage material, and / or the like. Alternatively, a non-tangible transitory computer readable transmission medium such as, for example, a propagating signal (e.g., a carrier wave, an infrared signal, and a digital signal) can optionally be used.

[0141] Examples of suitable machines include, but are not limited to, general purpose processors, special purpose processors, digital logic circuits, integrated circuits, and / or the like. Further examples of suitable machines include computer systems or other electronic devices that include a processor, digital logic circuit, or integrated circuit. Examples of such computer systems or electronic devices include, but are not limited to, desktop computers, laptop computers, notebook computers, tablet computers, netbooks, smart phones, cellular telephones, servers, network devices (e.g., routers and switches), mobile Internet devices (MIDs), media players, smart televisions, nettops, set-top boxes, and video game consoles.

[0142] Reference throughout this specification to, for example, "one embodiment", "an embodiment", "one or more embodiments", "some embodiments", and / or the like means that a particular feature can be included in the practice of the present application. Similarly, the descriptions in this specification use terms like "one embodiment", "an embodiment", or the like, in describing certain features. However, these terms do not necessarily identify a commitment to specifically disclose all such features an embodiment can depend on. Rather, the disclosure of this approach is not interpreted to reflect an intent that the application require more features than are expressly recited in each claim. Rather, aspects of the application are based on less than all features of a single disclosed embodiment, as reflected in the claims that follow below. Thus, the claims that follow this detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this application.

[0143] Example Embodiments

[0144] The following examples pertain to further embodiments. Certain features in the examples can be used in any one or more of the embodiments.

[0145] Example 1 is a processor including a widest set of data registers corresponding to a given logical processor. Each of the widest set of the data registers has a first width in bits. The processor further includes a decode unit corresponding to the given logical processor to decode an instruction specifying the widest set of the data registers, and an atomic store-to-memory instruction. The atomic store-to-memory instruction is to indicate data to have a second width in bits that is wider than the first width in bits of each of the widest set of the data registers. The atomic store-to-memory instruction indicates memory address information associated with a memory location. The processor further has an execution unit coupled with the decode unit. The execution unit is to atomically store the indicated data to the memory location in response to the atomic store-to-memory instruction.

[0146] Example 2 includes the processor of Example 1, wherein the execution unit includes a staging buffer, and wherein the execution unit is to sequentially store a plurality of portions of the indicated data that collectively represent a total amount to the staging buffer in response to the instruction, and to concurrently store the total amount of the indicated data from the staging buffer after the total amount of the indicated data has been stored in the staging buffer.

[0147] Example 3 includes the processor of Example 2, further comprising a write-combining buffer, and wherein the execution unit is to concurrently store the total amount of the indicated data from the staging buffer to the write-combining buffer in response to the atomic store-to-memory instruction.

[0148] Example 4 includes the processor of Example 3, wherein the execution unit is to configure the write-combining buffer for eviction after the plurality of portions of the indicated data have been stored to the write-combining buffer in response to the atomic store-to-memory instruction.

[0149] Example 5 includes the processor of any one of Examples 3-4, wherein the execution unit is to configure the write-combining buffer to disallow younger store operations to coalesce with the write-combining buffer after the plurality of portions of the indicated data have been stored to the write-combining buffer in response to the atomic store-to-memory instruction.

[0150] Example 6 includes the processor of any of Examples 1 to 5, wherein the execution unit, in response to the atomic store to memory instruction, is to signal one of a breakpoint configured on any byte of the memory location from a first byte to a last byte of the data to be atomically stored, a segment limit violation on the any byte, a canonical address form violation on the any byte, and a range-based violation on the any byte when the atomic store to memory instruction retires.

[0151] Example 7 includes the processor of any of Examples 1 to 6, wherein the execution unit, in response to the atomic store to memory instruction, is to make the atomic store of the data non-postable and to force a memory type associated with the atomically stored data to be an Uncacheable Random Compose Write (USWC) regardless of an underlying memory type.

[0152] Example 8 includes the processor of any of Examples 1 to 7, wherein the first and second widths are one of: (1) the first width is 128 bits and the second width is 256 bits; (2) the first width is 128 bits and the second width is 512 bits; (3) the first width is 128 bits and the second width is 1024 bits; (4) the first width is 256 bits and the second width is 512 bits; and (5) the first width is 256 bits and the second width is 1024 bits.

[0153] Example 9 includes the processor of any of Examples 1 to 8, wherein the decode unit is to decode the atomic store to memory instruction, the instruction is to indicate second memory address information associated with a second different memory location, the indicated data is to be loaded from the second different memory location in response to the atomic store to memory instruction.

[0154] Example 10 includes the processor of any of Examples 1 to 8, wherein the decode unit is to decode the atomic store to memory instruction, the instruction is to indicate a plurality of the data registers of the widest set initially used to store the indicated data.

[0155] Example 11 includes the processor of any of Examples 1 to 10, further comprising a retirement unit. And optionally wherein the retirement unit is to wait to retire the atomic store to memory instruction until a response is received. And optionally wherein the response is to indicate whether the data to be atomically stored to the memory location has been completely observed and is now consistent.

[0156] Example 12 includes the processor of any of examples 1 to 11, wherein the second width is wider than a width in bits of a widest operation, the widest operation being one of: an arithmetic operation, a logical operation, and an arithmetic and logical operation that the given logical processor is capable of performing on one or more packed data operands.

[0157] Example 13 includes the processor of any of examples 1 to 12, wherein the second width is wider than a width in bits of a widest packed data operand, the widest packed data operand to be indicated by any of: any packed data add instruction to be decoded by the decode unit and any packed data multiply instruction to be decoded by the decode unit.

[0158] Example 14 is a method performed by a processor, comprising receiving an atomic store-to-memory instruction at a given logical processor of the processor. The atomic store-to-memory instruction indicates data that is wider in bits than a widest data register that instructions of an instruction set of the given logical processor are capable of specifying, and the atomic store-to-memory instruction indicates memory address information associated with a memory location. The method further comprises atomically storing the indicated data to the memory location in response to the atomic store-to-memory instruction.

[0159] Example 15 includes the method of example 14, wherein the atomic store comprises atomically storing the indicated data having a width of at least 512 bits to the memory location, and wherein a width of the widest data register is no more than 256 bits.

[0160] Example 16 includes the method of any of examples 14 to 15, wherein the atomically storing further comprises, in response to the atomic store-to-memory instruction, sequentially storing a plurality of portions of the indicated data collectively representing a total amount to a staging buffer. And optionally simultaneously storing the plurality of portions of the indicated data and / or the indicated data of the total amount from the staging buffer to another memory location.

[0161] Example 17 includes the method of example 16, wherein the simultaneously storing comprises simultaneously storing the total amount of the indicated data from the staging buffer to a write-combining buffer, and wherein the atomically storing further comprises, in response to the atomic store-to-memory instruction: after the plurality of portions of the indicated data have been stored to the write-combining buffer, configuring the write-combining buffer to disallow younger store operations to coalesce with the write-combining buffer. And optionally, after the plurality of portions of the indicated data have been stored to the write-combining buffer, configuring the write-combining buffer for eviction.

[0162] Example 18 includes the method of any of examples 14-17, wherein the atomically storing the indicated data to the memory location is for assigning work to an accelerator device.

[0163] Example 19 includes the method of any of examples 14-18, further comprising detecting and signaling one of a breakpoint on any byte of the memory location when the data is atomically stored, a segment limit violation, and a range-based violation when the atomically storing to memory instruction is committed.

[0164] Example 20 includes the method of any of examples 14-19, wherein the receiving comprises receiving the atomically storing to memory instruction indicating memory address information associated with a second memory location, and in response to the atomically storing to memory instruction, loading the indicated data from the second memory location.

[0165] Example 21 is a computer system comprising an interconnect, and a processor coupled with the interconnect. The processor has a given core with a widest set of data registers. Each of the data registers of the widest set has a first width in bits. The given core receives an atomically storing to memory instruction to indicate data to have a second width in bits, the second width being wider than the first width of each of the data registers of the widest set. The atomically storing to memory instruction indicates memory address information associated with a memory location, and in response to the atomically storing to memory instruction, the processor atomically stores the indicated data to the memory location. The computer system further comprises a dynamic random access memory (DRAM) coupled with the interconnect. The DRAM stores a set of instructions to commit work to another device using different instances of the atomically storing to memory instruction.

[0166] Example 22 includes the computer system of example 21, wherein the processor comprises a staging buffer and a write-combining buffer, and wherein the processor is to sequentially store a plurality of portions of the indicated data to the staging buffer in response to the atomically storing to memory instruction. And optionally store the plurality of portions of the indicated data from the staging buffer to the write-combining buffer.

[0167] Example 23 includes the computer system of any of examples 21-22, wherein the first width is no greater than 256 bits, and the second width is at least 512 bits.

[0168] Example 24 is an article of manufacture including a non-transitory machine- readable storage medium. The non-transitory machine-readable storage medium stores an atomic store-to-memory instruction. The atomic store-to-memory instruction, if executed by a processor, causes the processor to perform operations including receiving the atomic store-to-memory instruction at a given logical processor of the processor. The atomic store-to-memory instruction indicates data to have a width in bits that is wider than a widest arithmetic operation that the given logical processor is capable of performing, and the atomic store-to-memory instruction indicates memory address information associated with a memory address. The operations further include atomically storing the data to the memory location.

[0169] Example 25 includes the article of manufacture of Example 24, wherein the width of the data is to be at least 512 bits, and wherein the width of the widest arithmetic operation is to be no more than 256 bits.

[0170] Example 26 includes the processor of any one of Examples 1 to 13, further including an optional branch prediction unit to predict branches, and an optional instruction prefetch unit coupled with the branch prediction unit to prefetch instructions, including atomic store-to-memory instructions. The processor can also optionally include an optional level 1 (LI) instruction cache coupled with the instruction prefetch unit to store instructions, an optional LI data cache to store data, and an optional level 2 (L2) cache to store data and instructions. The processor can also optionally include an instruction fetch unit coupled with the decode unit, the LI instruction cache, and the L2 cache to fetch the atomic store-to-memory instruction from one of the LI instruction cache and the L2 cache in some cases, and to provide the atomic store-to-memory instruction to the decode unit. The processor can also optionally include a register rename unit to rename registers, an optional scheduler to schedule one or more operations decoded from the atomic store-to-memory instruction for execution, and an optional commit unit to commit results of execution of the atomic store-to-memory instruction.

[0171] Example 27 includes a system on a chip comprising at least one interconnect, a processor of any one of examples 1 to 13 coupled with the at least one interconnect, an optional graphics processing unit (GPU) coupled with the at least one interconnect, an optional digital signal processor (DSP) coupled with the at least one interconnect, an optional display controller coupled with the at least one interconnect, an optional memory controller coupled with the at least one interconnect, an optional wireless modem coupled with the at least one interconnect, an optional image signal processor coupled with the at least one interconnect, an optional universal serial bus (USB) 3.0 compatible controller coupled with the at least one interconnect, an optional Bluetooth 4.1 compatible controller coupled with the at least one interconnect, and an optional wireless transceiver controller coupled with the at least one interconnect.

[0172] Example 28 is a processor or other device operative to perform the method of any one of examples 14 to 20.

[0173] Example 29 is a processor or other device comprising means for performing the method of any one of examples 14 to 20.

[0174] Example 30 is a processor or other device comprising any combination of means and / or units and / or logic and / or circuitry and / or components operative to perform the method of any one of examples 14 to 20.

[0175] Example 31 is an optional non-transitory and / or tangible machine-readable medium that optionally stores or otherwise provides instructions comprising first instructions operative, if and / or when executed by a processor, computer system, electronic device, or other machine, to cause the machine to perform the method of any one of examples 14 to 20.

[0176] Example 32 is a processor or other device substantially as described herein.

[0177] Example 33 is a processor or other device operative to perform any method substantially as described herein.

[0178] Example 34 is a processor or other device operative to perform any atomic store to memory instruction to atomically store wider data than natively supported by the processor substantially as described herein.

[0179] Example 35 is a computer system or other electronic device that includes a processor having a decode unit operative to decode instructions of a first instruction set. The processor also has one or more execution units. The electronic device also includes a storage device coupled with the processor. The storage device is operative to store first instructions, which can be substantially any instructions as disclosed herein, and which are to have a second, different instruction set. The storage device is also operative to store instructions for converting the first instructions into one or more instructions of the first instruction set. The one or more instructions of the first instruction set, when executed by the processor, are operative to cause the processor to store wider data atomically to memory than natively supported by the processor.

[0180] Example 36 is a processor that includes a decode unit corresponding to a given logical processor. The decode unit is to decode an atomic store to memory instruction. The atomic store to memory instruction is to indicate data, and the atomic store to memory instruction is to indicate memory address information associated with a memory location. The processor also includes an execution unit coupled with the decode unit. The execution unit is to store the indicated data atomically to the memory location in response to the atomic store to memory instruction. A width in bits of the data to be stored atomically in response to the atomic store to memory instruction is to be wider than a width in bits of data that can be atomically loaded by any instruction that can be decoded by the decoder.

Claims

1. A processor comprising: a plurality of cache memories; decode circuitry to decode an atomic store-to-memory instruction, the atomic store-to-memory instruction having a field to specify a 64-bit register, wherein the 64-bit register is a first of eight sequential 64-bit registers to collectively store 512 bits of data; and execution circuitry, coupled with the decode circuitry, to execute the decoded atomic store-to-memory instruction to: atomically store the 512 bits of data to a memory location, bypassing the plurality of cache memories; and store state information in a storage location of the processor, the state information associated with the atomic store of the 512 bits of data to the memory location. the storage location is a first storage location, and wherein to execute the decoded atomic store-to-memory instruction, the execution circuitry is to:

2. The processor of claim 1, wherein, sequentially store different 64-bit portions of the 512 bits of data from the eight sequential 64-bit registers to a second storage location; and simultaneously store the 512 bits of data from the second storage location to the memory location. To sequentially store the different 64-bit portions of the 512 bits of data from the eight sequential 64-bit registers to the second storage location, the execution circuitry is to sequentially store the different 64-bit portions of the 512 bits of data to different 64-bit portions of the second storage location, the different 64-bit portions of the second storage location indicated by respective indices.

3. The processor of claim 2, wherein, Successful completion of the atomic store requires the memory location to be 64-byte aligned.

4. The processor of any one of claims 1 to 3, wherein, The state information is based on a received response regarding the atomic store of the 512 bits of data to the memory location.

5. The processor of any one of claims 1 to 3, wherein, The atomic store-to-memory instruction is an accelerator work submission instruction.

6. The processor of any one of claims 1 to 3, wherein, The processor is a reduced instruction set computing (RISC) processor.

7. The processor of any one of claims 1 to 3, wherein, Memory address information of the memory location is to be provided via a register of the processor.

8. The processor of any one of claims 1 to 3, wherein, A memory type of the memory location is a cacheless memory type.

9. The processor of any one of claims 1 to 3, wherein, The execution circuitry is to atomically store the 512 bits of data to the memory location via a cacheless store operation.

10. The processor of any one of claims 1 to 3, wherein, The state information indicates that the store of the 512 bits of data to the memory location has been acknowledged by another device when stored in a work queue of the other device.

11. The processor of any one of claims 1 to 3, wherein, The storage location is a register of the processor in which the state information is to be stored.

12. The processor of any one of claims 1 to 3, wherein, 13. A method performed by a processor comprising: decoding, in the processor, an atomic store-to-memory instruction, the atomic store-to-memory instruction having a field to specify a 64-bit register, wherein the 64-bit register is a first of eight sequential 64-bit registers to collectively store 512 bits of data; and executing, in the processor, the decoded atomic store-to-memory instruction, including: atomically storing the 512 bits of data to a memory location, bypassing a plurality of cache memories; and storing state information in a storage location of the processor, the state information associated with the atomic store of the 512 bits of data to the memory location. ​ storing state information in a storage location of the processor, the state information associated with the atomic store of the 512-bit data to the memory location.

14. The method of claim 13, wherein, the storage location is a first storage location, and wherein the decoded atomic store to memory instruction comprises: storing different 64-bit portions of the 512-bit data from the eight sequential 64-bit registers sequentially to a second storage location; and storing the 512-bit data from the second storage location to the memory location simultaneously.

15. The method of claim 14, wherein, storing the different 64-bit portions of the 512-bit data from the eight sequential 64-bit registers sequentially to the second storage location comprises storing the different 64-bit portions of the 512-bit data sequentially to different 64-bit portions of the second storage location, the different 64-bit portions of the second storage location indicated by respective indices.

16. The method of any one of claims 13 to 15, wherein, successful completion of the atomic store requires the memory location to be 64-byte aligned.

17. The method of any one of claims 13 to 15, wherein, the state information is based on a received response regarding the atomic store of the 512-bit data to the memory location.

18. The method of any one of claims 13 to 15, wherein, the atomic store to memory instruction is an accelerator work submission instruction.

19. The method of any one of claims 13 to 15, wherein, memory address information of the memory location is to be provided via a register of the processor.

20. The method of any one of claims 13 to 15, wherein, atomically storing the 512-bit data to the memory location comprises atomically storing the 512-bit data to the memory location via a cacheless store operation.

21. The method of any one of claims 13 to 15, wherein, the state information indicates that the store of the 512-bit data to the memory location has been acknowledged by another device when stored in a work queue of the other device.

22. A computer program product comprising at least one computer readable storage medium having program code instructions stored therein, the program code instructions, when executed by a computer, causing the computer to carry out the method of any one of claims 13 to 21.

23. A processor comprising: a plurality of cache memories; decode circuitry to decode an atomic store to memory instruction, the atomic store to memory instruction indicating first memory address information of a source memory location and second memory address information of a destination memory location; and execution circuitry coupled with the decode circuitry to execute the decoded atomic store to memory instruction to: bypass the plurality of cache memories to atomically store 512-bit data to the destination memory location irrespective of a memory type of the destination memory location, the 512-bit data comprising data loaded from the source memory location; and store state information in a status register of the processor, the state information associated with the atomic store of the 512-bit data to the destination memory location.

24. The processor of claim 23, wherein, successful completion of the atomic store requires the destination memory location to be 64-byte aligned.

25. The processor of any one of claims 23-24, wherein, To execute the decoded atomic store-to-memory instruction, the execution circuitry is to prevent merged data of a store younger than the atomic store-to-memory instruction from merging with the 512-bit data.

26. The processor of any one of claims 23-24, wherein, The atomic store-to-memory instruction is an accelerator work submission instruction.

27. The processor of any one of claims 23-24, wherein, The destination memory location corresponds to a work submission queue of an accelerator device.

28. The processor of any one of claims 23-24, wherein, The destination memory location is in a memory-mapped input-output range.

29. The processor of any one of claims 23-24, wherein, The execution circuitry is to store the status information based on receipt of a response regarding the atomic store of the 512-bit data to the destination memory location.

30. The processor of any one of claims 23-24, wherein, The status information indicates whether the 512-bit data has been stored in a work queue of a device and has been accepted by the device.

31. The processor of any one of claims 23-24, wherein, The successful completion of the atomic store requires that the destination memory location is 64-byte aligned, wherein the atomic store-to-memory instruction is an accelerator work submission instruction, wherein the status information indicates whether the 512-bit data has been stored in a work queue of a device and has been accepted by the device, and wherein the destination memory location is in a memory-mapped input-output range.

32. A processor, comprising: a widest set of data registers corresponding to a given logical processor, each of the data registers of the widest set having a first width in bits; a decode unit corresponding to the given logical processor, the decode unit to decode an instruction specifying the data registers of the widest set, and to decode an atomic store-to-memory instruction, the atomic store-to-memory instruction to indicate data to have a second width in bits wider than the first width in bits of each of the data registers of the widest set, and the atomic store-to-memory instruction to indicate memory address information associated with a memory location; and an execution unit coupled with the decode unit, the execution unit to atomically store the indicated data to the memory location in response to the atomic store-to-memory instruction.

33. A processor, comprising: a decode unit corresponding to a given logical processor, the decode unit to decode an atomic store-to-memory instruction, the atomic store-to-memory instruction to indicate data, and the atomic store-to-memory instruction to indicate memory address information associated with a memory location; and an execution unit coupled with the decode unit, the execution unit to atomically store the indicated data to the memory location in response to the atomic store-to-memory instruction, wherein a width in bits of the data to be atomically stored in response to the atomic store-to-memory instruction is to be wider than a width in bits of data to be atomically loaded by any instruction decodable by the decoder.

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