A row activation method, a DDR controller, and a system on chip

Abstract

This application relates to the field of memory management, and discloses a row activation method, a DDR controller, and a system on chip. Among them, the method includes: sending a data read / write instruction processed by a port processing unit to a first address mapping unit through a first data path, and when it is determined that a preset condition is satisfied, sending the first address information of the data read / write instruction to a bank management module through a second data path; the first address mapping unit performs address mapping on the data read / write instruction, sends the mapped second address information to the bank management module, writes the data read / write instruction after address mapping into a command queue, the first address information arrives at the bank management module earlier than the second address information, and the bank management module activates the row pointed to by the first address information in response to the first address information. The technical solution provided by one or more embodiments of this application can improve the memory access efficiency.

Description

Technical Field

[0001] This application relates to the technical field of memory management, and particularly to a row activation method, a DDR controller, and a system on chip. Background Art

[0002] Currently, when accessing DDR memory, the access instruction reaches the bank management module in the DDR controller through a series of operations such as parsing, judging, caching, and address mapping. The bank management module performs a row activation operation according to the address information of the access instruction. At this time, it is necessary to wait until the tRCD (RAS to CAS Delay, the delay time from row address strobe to column address strobe) timing is satisfied before performing the corresponding data read / write.

[0003] In practical applications, in low-bandwidth application scenarios, the processor accesses the memory at a relatively low frequency, and the time interval between adjacent access instructions is relatively long. However, the access instruction still needs to wait for the row activation time and the delay time of the tRCD timing in the bank management module, resulting in a large memory access delay and low memory access efficiency.

[0004] In view of this, how to improve the memory access efficiency has become the focus of current research in the field of memory management. Summary of the Invention

[0005] This application provides a row activation method, a DDR controller, and a system on chip, which can improve the efficiency of memory access.

[0006] A first aspect of the present application provides a row activation method, which is applied to a DDR controller. The DDR controller includes a port processing unit and a control core. The control core at least includes a first address mapping unit, a bank management module, and a command queue. The port processing unit includes a parallel first data path and a second data path. The first data path is connected to the bank management module through the first address mapping unit, and the second data path is directly connected to the bank management module. The method includes: receiving a data read / write instruction through the port processing unit, and processing the data read / write instruction in parallel through the first data path and the second data path. Among them, the first data path sends the processed data read / write instruction to the first address mapping unit, and the second data path sends the first address information of the data read / write instruction to the bank management module when it determines that the data read / write instruction meets a preset condition; performing address mapping on the received data read / write instruction through the first address mapping unit, sending the second address information obtained by the address mapping to the bank management module, and writing the data read / write instruction after the address mapping into the command queue; among them, the first address information arrives at the bank management module earlier than the second address information; activating, by the bank management module, in response to the first address information, the row pointed to by the first address information, and the activated row is used to process the data read / write instruction after the address mapping in the command queue after a preset delay.

[0007] The technical solution provided by this embodiment of the present application uses two parallel data paths to process read / write instructions, thereby improving the memory access efficiency. Specifically, two parallel data paths are used to process read / write instructions so that the instructions can be transmitted through two paths at the same time. Among them, when the preset condition is met, the second data path can parse the address information of the instruction in advance and transmit it to the bank management module to perform the row activation operation in advance. Therefore, when the command arrives at the bank management module through the first data path, it does not need to wait for the delay time of the row activation, but directly transmits the data read / write instruction to the downstream memory module faster. It can be seen that through the technical solution provided by this embodiment of the present application, the overall time required to process read / write instructions is shortened, and the memory access efficiency is improved.

[0008] In a possible implementation manner, after receiving the second address information, the bank management module discards the second address information when it determines that the row pointed to by the second address information has been activated.

[0009] The technical solution provided by this embodiment of the present application describes the processing situation where the row pointed to by the second address information has been activated. When the Bank management module determines that the row pointed to by the second address information has been pre-activated through the second data path, it directly discards the current second address information. At this time, there is no need to perform the activation operation, which simplifies the instruction processing flow of the bank management module.

[0010] In a possible implementation manner, the second data path includes a second address mapping unit and a logical judgment unit. The second data path processes the data read / write instruction in the following manner: the second address mapping unit maps the logical address of the data read / write instruction to a physical address and transfers the obtained physical address to the logical judgment unit; the logical judgment unit, when determining that the data read / write instruction meets a preset condition, sends the obtained physical address as the first address information of the data read / write instruction to the bank management module.

[0011] The technical solution provided by this embodiment of the present application describes the specific structure of the second data path and the instruction pre-processing flow. When the preset condition is met, the physical address information obtained by mapping the data read / write instruction is sent to the bank management module, so as to advance the row activation and the waiting process of the preset delay.

[0012] In a possible implementation manner, the data read / write instruction meeting the preset condition includes: the logical judgment unit obtains the current queue state of the command queue and determines whether the data read / write instruction is the first instruction to be processed in the command queue according to the queue state. If so, it is determined that the data read / write instruction meets the preset condition.

[0013] The technical solution provided by this embodiment of the present application details the preset conditions that the data read / write instruction needs to meet for pre-processing through the second data path. Only when it is the first instruction to be processed in the command queue will the instruction pre-processing flow of the second data path be performed, so as to ensure the normal data transmission of the two parallel data paths.

[0014] In a possible implementation manner, when the second data path determines that the data read / write instruction does not meet the preset condition, it discards the data read / write instruction, so that the bank management module activates the row pointed to by the second address information in response to the second address information.

[0015] The technical solution provided by this embodiment of the present application adds the situation where the second data path determines that the data read / write instruction does not meet the preset condition, so as to ensure that the two parallel data paths synchronously process the same instruction, and avoid bank resource conflicts caused by the adjustment of the instructions in the command queue.

[0016] In a possible implementation manner, the first data path at least includes a queue judgment unit and a first-in first-out (FIFO) queue; the first data path processes the data read / write instruction in the following manner: the data read / write instruction is written into the FIFO queue; the queue judgment unit obtains the current queue state of the command queue, and determines whether the instruction in the FIFO queue can be received by the command queue according to the queue state; if so, the instruction stored in the FIFO queue is popped to the first address mapping unit.

[0017] In a possible implementation manner, if the queue judgment unit determines that the instruction in the FIFO queue cannot be received by the command queue, it re-obtains the current queue state of the command queue, and determines whether the instruction in the FIFO queue can be received by the command queue based on the re-obtained queue state.

[0018] The technical solution provided by this embodiment of the present application describes the structural composition and instruction processing flow of the first data path, writes the data read / write instruction into the FIFO queue, and pops the instruction stored in the FIFO queue according to the queue state of the command queue, so as to ensure the orderly processing of instruction data and the stable operation of the system.

[0019] In a possible implementation manner, the control core further includes a scheduling module, and the first address mapping unit transfers the data read / write instruction after address mapping to the scheduling module, so as to write the data read / write instruction after address mapping into the command queue through the scheduling module.

[0020] In a possible implementation manner, the scheduling module obtains the address information of each instruction stored in the command queue, and determines the row conflict information in the command queue based on the obtained address information; the scheduling module reorders each instruction stored in the command queue according to the row conflict information; wherein, after the row pointed to by the first address information is activated, other instructions carrying the first address information in the command queue are preferentially processed after reordering.

[0021] The technical solution provided by this embodiment of the present application introduces the scheduling module and its specific functions, preferentially processes other instructions in the same row as the first instruction, ensures that other instructions of the same target row will be executed earlier, thereby reducing the number of row conflicts and shortening the processing time of commands.

[0022] The second aspect of the present application provides a DDR controller. The DDR controller includes a port processing unit and a control core. The control core at least includes a first address mapping unit, a bank management module, and a command queue. The port processing unit includes a parallel first data path and a second data path. The first data path is connected to the bank management module through the first address mapping unit, and the second data path is directly connected to the bank management module. Wherein: The port processing unit is configured to receive data read / write instructions, and process the data read / write instructions in parallel through the first data path and the second data path. Wherein, the first data path sends the processed data read / write instructions to the first address mapping unit, and the second data path sends the first address information of the data read / write instructions to the bank management module when it is determined that the data read / write instructions meet a preset condition; The first address mapping unit is configured to perform address mapping on the received data read / write instructions, send the second address information obtained by the address mapping to the bank management module, and write the data read / write instructions after the address mapping into the command queue; Wherein, the first address information arrives at the bank management module earlier than the second address information; The bank management module is configured to activate the row pointed to by the first address information in response to the first address information. After a preset delay, the activated row is used to process the data read / write instructions after the address mapping in the command queue.

[0023] The third aspect of the present application provides a system-on-chip. The system-on-chip includes a processor core, a network-on-chip, a DDR controller, and a physical layer. Wherein: The processor core is configured to send data read / write instructions to the DDR controller through the network-on-chip; The DDR controller is configured to execute the row activation method as described in the first aspect for the received data read / write instructions; The physical layer is configured to perform protocol conversion on the instructions output by the DDR controller and transmit the instructions after the protocol conversion to an external memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0025] Figure 1 It is a schematic diagram of the steps of a row activation method provided for an embodiment of the present application;

[0026] Figure 2 Schematic diagram of steps for processing instructions in the second data path provided by an embodiment of the present application;

[0027] Figure 3 Schematic diagram of the data processing flow using a single path provided by an embodiment of the present application;

[0028] Figure 4 Schematic diagram of the data processing flow using a parallel data path provided by an embodiment of the present application;

[0029] Figure 5 Schematic diagram of the transmission process of data read / write instructions provided by an embodiment of the present application;

[0030] Figure 6 Schematic diagram of the composition of a DDR controller provided by an embodiment of the present application;

[0031] Figure 7 Schematic diagram of the structure of a DDR controller provided by an embodiment of the present application;

[0032] Figure 8 Schematic diagram of the structure of a DDR controller provided by an embodiment of the present application;

[0033] Figure 9 Schematic diagram of the structure of a DDR controller provided by another embodiment of the present application;

[0034] Figure 10 Schematic diagram of the composition of a system-on-chip provided by an embodiment of the present application;

[0035] Figure 11 Schematic diagram of the structure of a system-on-chip provided by an embodiment of the present application. Detailed implementation manners

[0036] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0037] In addition, the descriptions involving "first", "second", etc. in this application are for descriptive purposes only, and should not be construed as indicating or implying their relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In the description of the embodiments of this application, unless otherwise specified, the meaning of "a plurality of" is two or more. In addition, the use of "based on" or "according to" means open and inclusive, because a process, step, calculation, or other action "based on" or "according to" one or more of the stated conditions or values may, in practice, be based on additional conditions or values beyond those stated.

[0038] With the continuous development of the computer industry, the requirements for memory access performance are increasing day by day. In a modern computer system, the memory access speed is a key factor affecting the overall system performance. Among them, the tRCD timing, as a key memory access timing parameter, represents the time to wait between row activation and the effectiveness of a read or write command. The above row activation operation is used to load the specified memory row data into the row buffer. It can be understood that in order to ensure that the data in the row buffer is stable and the command can be correctly read or written, it is necessary to wait for the tRCD timing to be satisfied after the row activation operation.

[0039] In the related art, usually, the traditional memory access process is adopted to process data read / write instructions. The processor issues data read / write instructions to the DDR controller and accesses the memory through the DDR controller. In the DDR controller, the data read / write instructions need to go through a series of operations such as parsing, judgment, caching, address mapping, etc. before reaching the bank management module, and then the row activation operation starts, and the data read / write instructions can be sent to the downstream memory after waiting for the tRCD timing to be satisfied.

[0040] In the above command processing process, the bank management module is in an idle state before the command arrives. When the command arrives at the bank management module, it also needs to wait an additional time to satisfy the tRCD timing, increasing the command latency. In low-bandwidth application scenarios, the processor accesses the memory less frequently, the bank management module is in an idle state for a longer time, the memory access latency is particularly obvious, and the memory access efficiency is low.

[0041] In view of this, one or more embodiments of this application provide a row activation method, a DDR controller, and a system-on-chip. By introducing an additional data path to parse the address information of the instruction and transmitting the address information to the bank management module to perform the row activation operation in advance, since the command interval is long, the operation of activating the row in advance will not cause conflicts or interference to other commands, thereby improving the memory access efficiency.

[0042] Please refer to Figure 1, an embodiment of the present application provides a row activation method, which is applied to a DDR controller. The DDR controller includes a port processing unit and a control core. The control core at least includes a first address mapping unit, a bank management module, and a command queue. The port processing unit includes a parallel first data path and a second data path. The first data path is connected to the bank management module through the first address mapping unit, and the second data path is directly connected to the bank management module. The method may include the following steps:

[0043] S1: Receive a data read / write instruction through the port processing unit, and process the data read / write instruction in parallel through the first data path and the second data path. Among them, the first data path sends the processed data read / write instruction to the first address mapping unit, and the second data path sends the first address information of the data read / write instruction to the bank management module when it determines that the data read / write instruction meets a preset condition.

[0044] On the basis of meeting the preset condition, the second data path is used to send the first address information of the data read / write instruction to the bank management module in advance. The preset condition may be that the current data read / write instruction needs to perform a row activation operation in advance. The first address information is preferably the physical address information obtained by address mapping of the data read / write instruction, which points to the target row of the current data read / write instruction. The target row is a certain row to be accessed by the current data read / write instruction. Since the bank management module is idle at this time, the bank management module can pre-activate the target row according to the first address information in advance.

[0045] Among them, the bank management module is used to manage the row activation operation of the memory bank and control the timing of row activation. Specifically, after receiving the first address information, the bank management module can preform a row activation operation in advance and wait for the tRCD timing to complete. When the data read / write instruction enters the bank management module, the bank management module can directly process the data read / write instruction.

[0046] In this embodiment, the first data path is used to synchronize data read / write instructions and send the processed data read / write instructions to the first address mapping unit. Specifically, the processing of data read / write instructions may include processing operations such as parsing, judging, and caching. The above parsing operation may be a preliminary parsing of data read / write instructions, such as identifying information such as command type and target address. The above judging operation may be to judge whether the command meets the sending conditions, such as checking the legality of the command. The above caching operation may be to put the commands that meet the conditions into the cache module. Preferably, the commands that meet the conditions can be put into a first-in-first-out queue for subsequent processing. Further, the first data path sends the processed data read / write instructions to the first address mapping unit for address parsing.

[0047] In this embodiment, two data paths are used to process the received data read / write instructions in parallel, and the address information of the data read / write instructions can be transmitted to the bank management module in advance for pre-activation operations, reducing the latency of the instructions.

[0048] S3: The first address mapping unit performs address mapping on the received data read / write instructions, sends the second address information obtained by the address mapping to the bank management module, and writes the data read / write instructions after the address mapping into the command queue; wherein, the first address information arrives at the bank management module earlier than the second address information.

[0049] The above first address mapping unit is used to perform address mapping on data read / write instructions after receiving the processed data read / write operations. Specifically, the logical address in the data read / write instructions is mapped to a physical address so that the control core can correctly access the memory. The above second address information can be understood as the physical address obtained by the data read / write instructions after address mapping. Further, the first address mapping unit sends the above second address information to the bank management module. Different from the first address information used for pre-row activation operations, the second address information is used to ensure the integrity and accuracy of the data read / write instructions, so as to optimize the efficiency of memory access while ensuring correct memory access.

[0050] It should be noted that, due to the different entities generating the address information of the data read / write instruction, the present application uses descriptions such as "first" and "second" to distinguish the address information obtained by different generating entities. In fact, the content carried by the first address information and the second address information of the current data read / write instruction is the same. Moreover, since a series of processing operations are performed on the data read / write instruction in the first data path, the time for the processed data read / write instruction to obtain the second address information through address mapping is relatively long, resulting in the first address information arriving at the bank management module earlier than the second address information. Therefore, when the data read / write instruction meets the preset conditions, the bank management unit can perform the row activation operation in advance according to the first address information.

[0051] Furthermore, the data read / write instruction after address mapping is written into the command queue by the first address mapping unit. The above command queue is used to store the data read / write instructions to be executed and send the data read / write instructions to the memory bank in a timely manner, so as to ensure that all the data read / write instructions to be executed can be executed in a certain order.

[0052] S5: In response to the first address information, the bank management module activates the row pointed to by the first address information. After a preset delay, the activated row is used to process the data read / write instruction after address mapping in the command queue.

[0053] Specifically, after receiving the first address information sent by the second data path, the bank management module activates the target row of the bank corresponding to the first address information and meets the tRCD timing after a preset delay to ensure that the data is stable in the row buffer. At this time, the command queue pops the corresponding data read / write instruction to read or write data to the row buffer. The above preset delay is determined according to the medium of the DRAM.

[0054] In view of this, by synchronously processing the data read / write instruction through two parallel data paths, when the preset conditions are met, the second data path can transfer the address information to the bank management module earlier to activate the target row and enter the waiting delay process in advance. Subsequently, after the data read / write instruction of the first data path reaches the command queue through the normal processing flow, it can directly perform the data read / write operation, reducing the command delay, thereby shortening the overall time required to process the data read / write instruction and improving the memory access efficiency.

[0055] In a possible implementation, since the first address information arrives at the bank management module earlier than the second address information, if the bank management module determines that the row pointed to by the second address information has already been activated and there is no need to perform the activation operation at this time, the bank management module directly discards the currently received second address information, and the command queue pops the corresponding data read / write instruction, thereby simplifying the instruction processing flow of the bank management module and improving the efficiency of memory access.

[0056] In a possible implementation, please refer to Figure 2 , based on the above step S1, the second data path includes a second address mapping unit and a logical judgment unit, and the second data path processes the data read / write instruction in the following manner:

[0057] S101: The second address mapping unit maps the logical address of the data read / write instruction to a physical address and transfers the mapped physical address to the logical judgment unit;

[0058] S103: When the logical judgment unit determines that the data read / write instruction meets the preset conditions, it sends the mapped physical address as the first address information of the data read / write instruction to the bank management module.

[0059] The address information carried by the above data read / write instruction is a logical address. Since the address in the memory unit is a physical address, the second address mapping unit is required to map the above logical address to a physical address to ensure that the address of the target row can be accurately located.

[0060] In this implementation, the second data path includes a second address mapping unit and a logical judgment unit. The above second address mapping unit is used to map the logical address of the data read / write instruction to a physical address and transfer the physical address to the logical unit. The above logical judgment unit is used to determine whether the data read / write instruction meets the preset conditions.

[0061] In this implementation, it can be set that the current data read / write command being the first instruction to be processed in the command queue is the preset condition. In the DDR controller, the first instruction in the command queue is usually the next instruction to be executed. When the bank management module performs row activation, it usually needs to make a comprehensive decision based on the information of other instructions in the command queue. Only when processing the first data read / write instruction to be executed in the command queue does it not need to consider the information of other instructions. Therefore, when the second data path determines that the current data read / write instruction is the first instruction to be processed in the command queue, the bank management module can perform row activation in advance.

[0062] Specifically, the logical judgment unit obtains the current queue state of the command queue, and determines whether the data read / write instruction in the current second data path is the first instruction to be processed in the command queue according to the above queue state. If so, it is determined that the data read / write instruction meets the preset conditions.

[0063] Exemplarily, when the second data path determines that the data read / write instruction meets the preset conditions, the logical judgment unit transfers the above physical address to the bank management module as the first address information to pre-activate the row and wait for a preset delay. When the data read / write instruction of the first data path reaches the command queue after the normal processing flow, the data read / write operation can be directly executed, thereby improving the efficiency of memory access.

[0064] Exemplarily, when the second data path determines that the data read / write instruction does not meet the preset conditions, the data read / write instruction is discarded, and the row is not pre-activated through the second data path. The normal instruction transmission is performed according to the first data path, so that the bank management module activates the row pointed to by the second address information in response to the second address information obtained by the first address mapping unit, thereby ensuring the correctness of memory access.

[0065] The technical solution provided by this embodiment of the present application elaborates on the specific structure of the second data path and the instruction pre-processing process, and refines the preset conditions that the data read / write instruction needs to meet for pre-processing through the second data path. Only when it is the first instruction to be processed in the command queue, will the pre-row activation be performed, thereby ensuring the normal data transmission of the two parallel data paths and avoiding bank resource conflicts caused by the instruction adjustment of the command queue.

[0066] In a possible implementation manner, the first data path at least includes a queue judgment unit and a first-in first-out queue. The data read / write instruction is written into the first-in first-out queue, and the instruction stored in the first-in first-out queue is popped according to the queue state of the command queue, thereby ensuring the orderly processing of instruction data and the stable operation of the system.

[0067] Specifically, the data read / write instruction is written into the first-in first-out queue. The queue judgment unit obtains the current queue state of the command queue, and determines whether the instruction in the first-in first-out queue can be received by the command queue according to the queue state. Further, if the queue judgment unit determines that the instruction in the first-in first-out queue can be received by the command queue, the instruction stored in the first-in first-out queue is popped to the first address mapping unit. If the queue judgment unit determines that the instruction in the first-in first-out queue cannot be received by the command queue, the current queue state of the command queue is re-obtained, and it is determined whether the instruction in the first-in first-out queue can be received by the command queue based on the re-obtained queue state.

[0068] The above FIFO queue manages data read / write instructions according to the FIFO principle to ensure that the data read / write instructions are processed in the order of arrival, ensuring data consistency. The above command queue has a certain capacity limit. By obtaining the current queue status of the command queue, such as the length of the command queue, and determining whether to pop the data read / write instructions according to the queue status, the memory access requests can be better scheduled, avoiding resource conflicts and processing delays, and improving the efficiency of memory access.

[0069] In a possible implementation, the control core further includes a scheduling module, which is used to sort and schedule the data read / write instructions in the command queue. The data read / write instructions after address mapping are passed to the scheduling module by the first address mapping unit, so that the data read / write instructions after address mapping can be written into the command queue through the scheduling module.

[0070] In this implementation, the above scheduling module transfers, sorts, and schedules the data read / write instructions in the command queue according to the status of the command queue. Among them, when the scheduling module receives the data read / write instructions passed by the first address mapping unit, it writes the data read / write instructions into the command queue and sorts and schedules the data read / write instructions in the command queue according to the status of the command queue.

[0071] Specifically, the row conflict information in the command queue is used as the scheduling basis. The scheduling module obtains the address information of each instruction stored in the command queue and determines the row conflict information in the command queue based on the obtained address information. The above row conflict information includes the instructions that have row conflicts in the command queue. The instructions with row conflicts can be understood as the data read / write instructions in the command queue whose row address information is different from that of the adjacent data read / write instructions. The scheduling module reorders the various instructions stored in the command queue according to the row conflict information. Among them, after the row pointed to by the first address information is activated, other instructions in the command queue carrying the first address information are preferentially processed after reordering.

[0072] In this implementation, by adding a scheduling module to adjust the arrangement order of the data read / write instructions in the command queue, the processing time of the command is shortened. Other instructions in the same row as the first instruction are preferentially processed to ensure that other instructions on the same target row will be executed earlier. At the same time, the scheduling module adjusts the order of other instructions with row conflicts according to the address information in the command queue. Since the command queue pops the data read / write instructions according to the principle of optimal timing, it can ensure that the data read / write instructions with the same address information can be preferentially processed, thereby reducing the number of row conflicts and further improving the efficiency of memory access.

[0073] This application provides one or more embodiments that can be used to transmit data read / write instructions in a DDR controller. The DDR controller includes a port processing unit and a control core. The embodiment proceeds according to the following steps:

[0074] In one embodiment, refer to Figure 3 , and process the data read / write instructions using a traditional single-path data processing flow. Specifically, after the port control unit receives the data read / write instructions, it parses the data read / write instructions and stores them in a first-in, first-out queue. It determines whether the command queue can receive the instructions in the first-in, first-out queue. If it can receive them, it pops the instructions stored in the first-in, first-out queue to the first address mapping unit. The first address mapping unit performs address mapping on the data read / write instructions, transfers the address information obtained based on the address mapping to the bank management module for row activation, and stores the data read / write instructions after address mapping in the command queue. Further, after the target row has been activated and waits for the tRCD timing, the data read / write instructions corresponding to the target row are taken out from the command queue and sent to the DFI interface to access the row buffer of the memory.

[0075] In another embodiment, refer to Figure 4 , and process the data read / write instructions using two parallel data paths. Based on the single-path data processing flow of the first data path in the above embodiment, a second data path is introduced. When the data read / write instruction is the first instruction to be processed in the command queue, address mapping and preset condition judgment are performed on the data read / write instructions, and the second address information obtained through address mapping is sent to the bank management module in advance for row activation operation. When the first address information of the data read / write instruction reaches the bank management module and the timing and data meet the requirements, the current data read / write instruction can be directly taken out from the command queue to access the row buffer.

[0076] Exemplarily, refer to Figure 5 , this application also provides an embodiment that uses the above row activation method, Figure 5 indicating the transmission process of data read / write instructions in the DDR controller. Specifically, when the DDR controller receives the data read / write instructions, it synchronously processes the data read / write instructions through two data paths. The second data path performs address mapping in advance to obtain the first address information, and determines whether the current data read / write instruction meets the preset conditions, that is, determines whether the data read / write instruction is the first command in the command queue. If so, the above first address information is sent to the bank management module. If not, the current data read / write instruction is discarded and no longer processed through the second data path.

[0077] Meanwhile, data read / write instructions are transmitted through the first data path according to the traditional data processing flow, parsed and cached in the first-in first-out queue, and then it is determined whether they can be received by the command queue. If they can be received, the data read / write instructions are address-mapped, and the second address information of the data read / write instructions obtained based on the address mapping is sent to the bank management module. Then, the data read / write instructions after address mapping are sent to the command queue through the scheduling module. The scheduling module adjusts the arrangement order of each instruction in the command queue according to the second address information of each data read / write instruction to ensure that the data read / write instructions with the same second address information can be preferentially executed. Further, after the bank management module receives the second address information sent through the first data path, it determines whether the row pointed to by the second address information has been pre-activated. If the row pointed to by the second address information has not been activated, an activation instruction is issued to perform an activation operation on the row pointed to by the second address information. If the row pointed to by the second address information has been pre-activated, the current second address information is discarded and the activation operation is no longer performed. Exemplarily, when the first data read / write instruction reaches the command queue, its corresponding target row has been pre-activated by the bank management module according to the first address information and meets the tRCD timing. At this time, the current data read / write instruction can be directly taken out from the command queue.

[0078] In view of this, the technical solutions provided by multiple embodiments of the present application use two parallel data paths to synchronously process read / write instructions to optimize the command processing flow, thereby improving the memory access efficiency. Specifically, a second data path is introduced on the basis of the original first data path so that instructions can be transmitted through two paths simultaneously. Among them, the second data path can parse the address information of the instructions in advance and transmit it to the bank management module for pre-row activation operation. Therefore, after the command reaches the bank management module through the first data path, there is no need to wait for the delay time of row activation, but the data read / write instructions are directly transmitted to the downstream memory module faster. It can be seen that through the technical solutions provided by multiple embodiments of the present application, the overall time required to process read / write instructions is shortened, and the memory access efficiency is improved.

[0079] Please refer to Figure 6 and Figure 7, this application also provides a DDR controller, which includes a port processing unit 10 and a control core 20. The control core at least includes a first address mapping unit 201, a bank management module 202, and a command queue 203. The port processing unit 10 includes a parallel first data path and a second data path. The first data path is connected to the bank management module 202 through the first address mapping unit 201, and the second data path is directly connected to the bank management module 202, where:

[0080] The port processing unit 10 is configured to receive data read / write instructions, and process the data read / write instructions through the first data path and the second data path respectively. Among them, the first data path sends the processed data read / write instructions to the first address mapping unit, and the second data path sends the first address information of the data read / write instructions to the bank management module when it determines that the data read / write instructions meet the preset conditions;

[0081] The first address mapping unit 201 is configured to receive data read / write instructions, and process the data read / write instructions in parallel through the first data path and the second data path respectively. Among them, the first data path sends the processed data read / write instructions to the first address mapping unit, and the second data path sends the first address information of the data read / write instructions to the bank management module when it determines that the data read / write instructions meet the preset conditions;

[0082] The bank management module 202 is configured to activate the row pointed to by the first address information in response to the first address information. After a preset delay, the activated row is used to process the data read / write instructions after address mapping in the command queue.

[0083] In one embodiment, the port processing unit is specifically configured to process data read / write instructions through the parallel first data path and second data path. Specifically, in the first data path, the data read / write instructions are sent to the first address mapping unit after basic processing. The first address mapping unit performs address mapping on the received data read / write instructions, sends the second address information obtained by the address mapping to the bank management module, and sends the data read / write instructions after address mapping to the command queue. At the same time, in the second data path, when the data read / write instructions meet the preset conditions, address mapping is performed on the data read / write instructions, and the address information obtained by the address mapping is sent to the bank management unit in advance as the first address information.

[0084] Please refer to Figure 8, in one embodiment, the port processing unit 10 further includes a parsing unit 101, a judging unit 102, and a first-in first-out queue 103. Specifically, after receiving a data read / write instruction, the data processing instruction sends the address information to the bank management unit in advance through the second data path. At the same time, the data read / write instruction in the first data path needs to be parsed and judged by the parsing unit and the judging unit of the port processing unit. The data read / write instruction that meets the requirements is sent to the first-in first-out queue for temporary storage, and the first-in first-out queue sends the data read / write instruction to the command queue through the first address mapping unit.

[0085] In one embodiment, the first address mapping unit is specifically configured to perform address mapping on the processed data read / write instruction received in the first data path, map the logical address of the data read / write instruction to a physical address, and send the mapped physical address to the bank management module as the second address information of the data read / write instruction.

[0086] Please refer to Figure 9 , in one embodiment, the control core further includes a scheduling module 204, which is configured to receive the data read / write instruction after address mapping in the first data path, write the data read / write instruction into the command queue, obtain the address information of each instruction in the command queue, judge the row conflict information in the command queue according to the above address information, and reorder the data read / write instructions in the command queue based on the row conflict information.

[0087] The further function descriptions of the above-mentioned various modules and units are the same as those in the corresponding embodiments above, and will not be repeated here.

[0088] A DDR controller in an embodiment of the present application is presented in the form of a functional unit. Here, the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and a memory that execute one or more software or fixed programs, or other devices that can provide the above functions.

[0089] Please refer to Figure 10 , the present application further provides a system-on-chip. When a component of the system-on-chip issues a command, under the condition that the processor core has not cached the data of the command, a data read / retrieve instruction is issued to access the memory. The system-on-chip includes a processor core 100, a network-on-chip 200, a DDR controller 300, and a physical layer 400, wherein:

[0090] The processor core 100 is configured to send the data read / write instruction to the DDR controller through the network-on-chip;

[0091] The DDR controller 200 is configured to execute the above-described row activation method for the received data read / write instruction;

[0092] The physical layer 400 is configured to perform protocol conversion on the instruction output by the DDR controller and transmit the instruction after protocol conversion to an external memory.

[0093] In one embodiment, the above physical layer may be a PHY (Physical, port physical layer), which is used to convert commands of the DFI (DDR PHY Interface, an interface protocol between a memory controller and a physical layer) protocol into an actual DDR protocol interface. The above physical layer can directly communicate with a memory device, and the commands and data after being processed by the physical layer access the external memory through the DDR protocol interface, thereby reading or writing data.

[0094] In one embodiment, the above DDR controller is specifically configured to perform operations such as address conversion and timing control on the data read / write instruction to ensure that the instruction meets the requirements of memory access, convert the data read / write instruction into a command format of the DFI protocol and output it to the physical layer, and the physical layer converts it into a command format applicable to the DDR protocol interface and transmits it to the external memory.

[0095] Please refer to Figure 11 , in one embodiment, the above system-on-chip may include one or more DDR controllers working in parallel, accessing different external memories through their respective physical layers, thereby improving the bandwidth and efficiency of memory access.

[0096] The above-mentioned processor cores can be selected from: CPU (Central Processing Unit), GPU (Graphics Processing Unit), NPU (Neural Network Processing Unit), TPU (Tensor Processing Unit), DPU (Deep learning Processing Unit), microprocessor, DSP (Digital Signal Processor), ASIC (Application Specific Integrated Circuit), FPGA (Field Programmable Gate Array), or a combination of at least two of these processor forms. The memory stores instructions executable by at least one processor, and the types of the at least one processor can be different. For example, it includes CPU and FPGA, CPU and artificial intelligence processor, CPU and GPU, etc.

[0097] The above-mentioned external memory can be implemented by DDR memory chips, and the DDR memory chips are DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory). The storage unit storage order is organized into a multi-level structure, which is channel, DIMM, rank, chip, Bank, row, and column in sequence. One channel corresponds to one DDR controller. Among them, each group of Rank can be regarded as an independent external memory, with an independent address space and control logic, and can perform read and write operations independently. In the external memory, different external memory modules can be accessed by selecting different Ranks.

[0098] The system-on-chip illustrated in the above embodiments can be specifically implemented by a computer chip or an entity, or by a product with certain functions. A typical implementation device is a computer. Specifically, the computer can be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0099] Those skilled in the art should understand that the embodiments of the present application can be provided as methods and systems. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memory, CD-ROM, optical memory, etc.) containing computer-usable program code.

[0100] The present application is described with reference to the flowcharts and / or block diagrams of methods and systems according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate means for implementing the functions specified in one Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0101] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory generate a manufactured article including instruction means, and the instruction means implements the functions specified in one Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0102] These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process. Thus, the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0103] It should also be noted that the term "including", "comprising", or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, commodity, or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or elements inherent to such process, method, commodity, or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of another identical element in the process, method, commodity, or device including the said element.

[0104] Each embodiment in this specification is described in a progressive manner. For the same or similar parts among the embodiments, reference can be made to each other, and the differences between each embodiment and other embodiments are emphasized. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and reference can be made to the relevant part of the method embodiment for the relevant content.

[0105] The above description is only for the embodiments of the present application and is not intended to limit the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the scope of the claims of the present application.

[0106] Although the embodiments of the present application are described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations fall within the scope defined by the appended claims.

Claims

1. A row activation method, characterized in that: The method is applied to a DDR controller, the DDR controller includes a port processing unit and a control core, the control core includes at least a first address mapping unit, a bank management module and a command queue, the port processing unit includes a first data path and a second data path in parallel, the first data path is connected to the bank management module through the first address mapping unit, and the second data path is directly connected to the bank management module, the method includes: receiving a data read / write instruction through the port processing unit, and processing the data read / write instruction in parallel through the first data path and the second data path, respectively, wherein the first data path sends the processed data read / write instruction to the first address mapping unit, and the second data path sends the first address information of the data read / write instruction to the bank management module when determining that the data read / write instruction meets a preset condition, wherein the preset condition is that the data read / write instruction is the first instruction to be processed in the command queue; Performing address mapping on the received data read / write instruction through the first address mapping unit, sending second address information obtained by address mapping to the bank management module, and writing the data read / write instruction after address mapping into the command queue; wherein the first address information arrives at the bank management module earlier than the second address information; The bank management module responds to the first address information and activates the row pointed to by the first address information, wherein the activated row is used to process the address-mapped data read / write instruction in the command queue after a preset delay.

2. The method according to claim 1, characterized in that The method further comprises: After receiving the second address information, the bank management module discards the second address information if it is determined that the row pointed to by the second address information has been activated.

3. The method according to claim 1, characterized in that The second data path includes a second address mapping unit and a logic judgment unit, and the second data path processes the data read / write instruction in the following manner: The second address mapping unit maps the logical address of the data read / write instruction into a physical address, and transmits the mapped physical address to the logic judgment unit; When the logic judgment unit determines that the data read / write instruction satisfies a preset condition, the mapped physical address is sent to the bank management module as first address information of the data read / write instruction.

4. The method according to any one of claims 1 to 3, characterized in that: The method further comprises: When determining that the data read / write instruction does not meet a preset condition, the second data path discards the data read / write instruction, so that the bank management module activates the row pointed to by the second address information in response to the second address information.

5. The method according to claim 1 or 2, characterized in that: The first data path at least includes a queue determination unit and a first-in-first-out queue; The first data path processes the data read / write instruction in the following manner: The data read / write instruction is written into the first-in-first-out queue; The queue determination unit obtains the current queue status of the command queue, and determines whether the instructions in the first-in-first-out queue can be received by the command queue according to the queue status; if so, the instructions stored in the first-in-first-out queue are popped out to the first address mapping unit.

6. The method according to claim 5, characterized in that The method further comprises: If the queue determination unit determines that the instructions in the FIFO queue cannot be received by the command queue, the current queue state of the command queue is re-acquired, and based on the re-acquired queue state, it is determined whether the instructions in the FIFO queue can be received by the command queue.

7. The method according to claim 1 or 2, characterized in that: The control core also includes a scheduling module, and the first address mapping unit transmits the address-mapped data read / write instruction to the scheduling module, so that the address-mapped data read / write instruction is written into the command queue through the scheduling module.

8. The method according to claim 7, characterized in that The method further comprises: The scheduling module obtains address information of each instruction stored in the command queue, and determines row conflict information in the command queue based on the obtained address information; The scheduling module reorders the instructions stored in the command queue according to the row conflict information; wherein, after the row pointed to by the first address information is activated, other instructions in the command queue carrying the first address information are processed preferentially after reordering.

9. A DDR controller, characterized in that: The DDR controller includes a port processing unit and a control core, wherein the control core includes at least a first address mapping unit, a bank management module and a command queue, and the port processing unit includes a first data path and a second data path in parallel, wherein the first data path is connected to the bank management module through the first address mapping unit, and the second data path is directly connected to the bank management module, wherein: The port processing unit is used to receive a data read / write instruction, and process the data read / write instruction in parallel through the first data path and the second data path, wherein the first data path sends the processed data read / write instruction to the first address mapping unit, and the second data path sends the first address information of the data read / write instruction to the bank management module when determining that the data read / write instruction meets a preset condition, wherein the preset condition is that the data read / write instruction is the first instruction to be processed in the command queue; The first address mapping unit is used to perform address mapping on the received data read / write instruction, send the second address information obtained by address mapping to the bank management module, and write the data read / write instruction after address mapping into the command queue; wherein the first address information arrives at the bank management module earlier than the second address information; The bank management module is used to activate the row pointed to by the first address information in response to the first address information, wherein the activated row is used to process the address-mapped data read / write instruction in the command queue after a preset delay.

10. A system on chip, characterized in that: The system on chip includes a processor core, an on-chip network, a DDR controller and a physical layer, wherein: The processor core is used to send data read / write instructions to the DDR controller through the on-chip network; The DDR controller is used to execute the row activation method according to any one of claims 1 to 8 for the received data read / write instruction; The physical layer is used to perform protocol conversion on the instructions output by the DDR controller, and transmit the instructions after protocol conversion to the external memory.

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