Logic processing method and device, equipment, medium and product

Abstract

The invention discloses a logic processing method and device, equipment, a medium and a product. The method comprises the following steps: acquiring a circuit design model of a target device and at least one to-be-used netlist associated with the circuit design model; updating at least one second module in the circuit design model based on the at least one netlist to be used; when the third module to which the tri-state logic belongs is a non-top-layer module in the circuit design model, moving the tri-state logic to a top-layer module in the circuit design model to obtain a processed circuit design model; and sending the processed circuit design model to a chip verification system, so that the chip verification system performs partition verification on the circuit design model. All three-state logics in the circuit design model can be moved to the model top layer, and the processed circuit design model is sent to the chip verification system for verification, so that the logic verification processing efficiency is improved, and the problem of design rule check errors is prevented.

Description

Technical Field

[0001] The present invention relates to the field of computer processing technology, and in particular to a logic processing method, device, equipment, medium and product. Background Art

[0002] In order to ensure the performance of the chip, a chip verification system is usually used to perform logic verification on the chip design model. As the integration and complexity of chips continue to increase, the capacity of a single verification system can no longer meet design requirements. To solve this problem, the chip verification system usually divides the chip design model into multiple parts and assigns them to different verification systems for verification.

[0003] When partitioning and synthesizing the chip design model, it is necessary to search out all interconnected three-state logics in the design model, process them accordingly, and convert them into non-interconnected three-state logics. However, since there are some black box modules in the chip design model whose internal structures cannot be seen by the chip verification system, these black box modules may contain three-state logics. Therefore, after the chip design model is partitioned and synthesized, there may still be interconnected three-state logics. This will cause the verification results to be reported incorrectly, affecting the verification efficiency. Summary of the invention

[0004] The present invention provides a logic processing method, device, equipment, medium and product, so as to realize moving all three-state logic in a circuit design model to the top level of the model, and sending the processed circuit design model to a chip verification system for verification, thereby improving the efficiency of logic verification processing and preventing design rule checking errors.

[0005] According to one aspect of the present invention, there is provided a logic processing method, the method comprising:

[0006] Acquire a circuit design model of a target device and at least one netlist to be used associated with the circuit design model; wherein the circuit design model includes at least two functional modules, the functional modules include a first module and a second module; the first module is a module visible to circuit logic; the second module is a module invisible to circuit logic; at least one of the first modules includes tri-state logic; the netlist to be used includes tri-state logic;

[0007] Based on the at least one to-be-used netlist, updating at least one of the second modules in the circuit design model;

[0008] For each tri-state logic in the updated circuit design model, when the third module to which the tri-state logic belongs is a non-top-level module in the circuit design model, the tri-state logic is moved to the top-level module in the circuit design model to obtain the processed circuit design model; wherein the third module includes the first module and the netlist to be used;

[0009] The processed circuit design model is sent to a chip verification system, so that the chip verification system performs partition verification on the circuit design model.

[0010] According to another aspect of the present invention, there is provided a logic processing device, the device comprising:

[0011] A module for determining a netlist to be used, used for acquiring a circuit design model of a target device and at least one netlist to be used associated with the circuit design model; wherein the circuit design model includes at least two functional modules, the functional modules include a first module and a second module; the first module is a module visible to circuit logic; the second module is a module invisible to circuit logic; at least one of the first modules includes tri-state logic; the netlist to be used includes tri-state logic;

[0012] A model updating module, configured to update at least one of the second modules in the circuit design model based on the at least one netlist to be used;

[0013] A tri-state logic moving module, for each tri-state logic in the updated circuit design model, when the third module to which the tri-state logic belongs is a non-top-level module in the circuit design model, moves the tri-state logic to the top-level module in the circuit design model to obtain the processed circuit design model; wherein the third module includes the first module and the netlist to be used;

[0014] The model sending module is used to send the processed circuit design model to a chip verification system so that the chip verification system performs partition verification on the circuit design model.

[0015] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0016] at least one processor; and a memory in communication with the at least one processor; wherein,

[0017] The memory stores a computer program that can be executed by the at least one processor. The computer program is executed by the at least one processor so that the at least one processor can execute the logic processing method described in any embodiment of the present invention.

[0018] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the logic processing method described in any embodiment of the present invention when executed.

[0019] According to another aspect of the present invention, a computer program product is provided, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements the logic processing method as described in any embodiment of the present invention.

[0020] The technical solution of the embodiment of the present invention is to obtain a circuit design model of a target device and at least one to-be-used netlist associated with the circuit design model; wherein the circuit design model includes at least two functional modules, the functional modules including a first module and a second module; the first module is a module visible to the circuit logic; the second module is a module invisible to the circuit logic; at least one first module includes a tri-state logic; the to-be-used netlist includes a tri-state logic; based on at least one to-be-used netlist, at least one second module in the circuit design model is updated; for each tri-state logic in the updated circuit design model, when the third module to which the tri-state logic belongs is a non-top-level module in the circuit design model, the tri-state logic is moved to the circuit design model The top-level module of the circuit design model is used to obtain a processed circuit design model; wherein the third module includes the first module and the netlist to be used; the processed circuit design model is sent to the chip verification system so that the chip verification system performs partition verification on the circuit design model, which solves the problem that the prior art cannot process the three-state logic in the second module, resulting in easy verification errors and low verification efficiency, and realizes that the second module with three-state logic in the circuit design model can be replaced by the netlist to be used, thereby moving the three-state logic in all functional modules in the circuit design model to the top level of the model, and sending the processed circuit design model to the chip verification system for verification, thereby improving the efficiency of logic verification processing and preventing errors in design rule checking.

[0021] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1is a flowchart of a logic processing method provided according to Embodiment 1 of the present invention;

[0024] Figure 2 is a schematic diagram of a logic processing method provided according to Embodiment 1 of the present invention;

[0025] Figure 3 is a schematic diagram of the structure of a circuit design model before characterization processing provided according to Embodiment 1 of the present invention;

[0026] Figure 4 is a schematic diagram of a structure of a circuit design model for characterizing a circuit design model after replacement processing provided according to the first embodiment of the present invention;

[0027] Figure 5 is a structural diagram for characterizing that the tri-state logic is not moved to the top-level module according to the first embodiment of the present invention;

[0028] Figure 6 is a structural diagram for characterizing moving a tri-state logic to a top-level module provided according to Embodiment 1 of the present invention;

[0029] Figure 7 is a structural diagram for characterizing moving a tri-state logic to a top-level module provided according to the first embodiment of the present invention;

[0030] Figure 8 is a structural diagram of a logic processing device provided according to Embodiment 2 of the present invention;

[0031] Fig. 9 It is a structural schematic diagram of an electronic device for implementing the logic processing method of an embodiment of the present invention. DETAILED DESCRIPTION

[0032] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0033] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0034] Embodiment 1

[0035] Figure 1 This is a flow chart of a logic processing method provided according to the first embodiment of the present invention. This embodiment is applicable to the case where all three-state logic in the circuit design model is processed and the processed circuit design model is sent to the chip verification system for verification. The method can be executed by a logic processing device, which can be implemented in the form of hardware and / or software, and the logic processing device can be configured in a computing device. Figure 1 As shown, the method includes:

[0036] S110. Obtain a circuit design model of a target device and at least one netlist to be used associated with the circuit design model; the circuit design model includes at least two functional modules, and the functional modules include a first module and a second module; the first module is a module visible to the circuit logic; the second module is a module invisible to the circuit logic; at least one first module includes tri-state logic; the netlist to be used includes tri-state logic.

[0037] Among them, the target device can be a chip. The circuit design model can be a mathematical description model of the behavior and function of the circuit system of the target device. For example, the circuit design model can be an RTL (Register-Transfer Level) design of the target device. In RTL design, a hardware description language (HDL) is used to describe the behavior and structure of digital circuits, and to decompose complex circuits into multiple modules, each of which performs a specific function, and the module is a functional module. In other words, a functional module is an independent unit in circuit design and implements a specific function. These functional modules can be first modules or second modules. The first module refers to a module where the circuit logic is visible, that is, the user can view and modify the circuit logic and structure inside the module. The second module refers to a module where the circuit logic is invisible, that is, the user can only see the input and output interfaces of the second module, but cannot view or modify the circuit logic inside the module. In other words, the second module is similar to a "black box", which can only know what data is input and what output results are obtained, but does not know the complex logic inside the box. The second module can be a module of a fixed circuit part that has been designed and packaged. In the design process, other users or systems can call this module without understanding its internal structure. The netlist to be used refers to a file used to describe the connection relationship between various components in the circuit in the device design. For example, the netlist to be used may contain information such as the hierarchy, components, connections, and properties of the circuit design. The netlist to be used may be in EDIF (Electronic Design Interchange Format) or HDL (Hardware Description Language) format. The netlist to be used includes the specific circuit design in the second module. Tri-state logic is a type of logic circuit that allows a signal line to switch between three states (high level, low level, or high impedance state).

[0038] In this embodiment, before logic verification is performed on the circuit design model, the circuit design model of the target device and the netlist to be used including the tri-state logic used when constructing the circuit design model can be obtained. After the circuit design model is processed based on the netlist to be used, logic verification is performed on the processed circuit design model to ensure that the design of the circuit design model meets the expected requirements.

[0039] In this embodiment, before obtaining the circuit design model of the target device, at least one netlist to be used that contains tri-state logic and is used in the process of building the circuit design model of the target device can be recorded, and the netlist to be used can be used as a netlist associated with the circuit design model of the target device. In this way, when the circuit design model of the target device is subsequently read, at least one netlist to be used associated with the circuit design model can be obtained together.

[0040] For example, see Figure 2 , read all netlists to be used imported by the user, and determine whether there is tri-state logic in the netlist to be used. If so, record the netlist to be used with tri-state logic. When the circuit design model of the target device is subsequently read in, the recorded netlist to be used containing tri-state logic is also read in.

[0041] S120: Update at least one second module in the circuit design model based on at least one netlist to be used.

[0042] In this embodiment, the corresponding second module in the circuit design model can be updated through each netlist to be used, and the second module is replaced with the netlist to be used which is visible to the circuit logic, so as to find all the tri-state logics in the circuit design model.

[0043] In this embodiment, at least one second module in the circuit design model is updated based on at least one netlist to be used, including: for each netlist to be used, searching the circuit design model for a second module to be replaced that matches the netlist to be used; and replacing the second module to be replaced based on the netlist to be used to obtain an updated circuit design model.

[0044] Specifically, the interface definition in the netlist to be used and the module interface in the circuit design model can be compared; or, the netlist identifier of the netlist to be used and the module identifier of the functional module in the circuit design model can be compared, and the second module that matches the netlist to be used can be found in the circuit design model, and the found second module can be used as the second module to be replaced. Further, the second module to be replaced can be replaced with the netlist to be used. Accordingly, each second module in the circuit design model that contains tri-state logic and is logically invisible can be replaced with the corresponding netlist to be used. After the replacement is completed, the updated circuit design model is obtained.

[0045] For example, see Figure 3 , i0 represents the first module in the circuit design model, i1 represents the second module in the circuit design model, and the second module is replaced with the corresponding netlist to be used. The structural diagram after replacement can be seen in Figure 4 .

[0046] S130. For each tri-state logic in the updated circuit design model, when the third module to which the tri-state logic belongs is a non-top-level module in the circuit design model, the tri-state logic is moved to the top-level module in the circuit design model to obtain a processed circuit design model; the third module includes the first module and the netlist to be used.

[0047] Among them, the tri-state logic in all modules in the updated circuit design model is visible. The third module can be understood as the module where the tri-state logic is located, which may be the first module or the netlist to be used. The top-level module in the circuit design model is designed based on RTL.

[0048] In this embodiment, the three-state logic in the updated circuit design model can be traversed. When it is detected that the third module to which the three-state logic belongs is not at the top level of the circuit design model, the three-state logic can be moved to the top level of the design in the circuit design model. Accordingly, all three-state logics can be moved to the top level of the design in the circuit design model, that is, to the top level module, to obtain a processed circuit design model. At this time, all three-state logics in the processed circuit design model are in the top level module.

[0049] For example, see Figure 2 , search whether there is tri-state logic in the circuit design model, find all tri-state logic, determine whether the tri-state logic exists in the top-level module, and if not, move it to the top-level module. Move the tri-state logic in non-top-level modules to the top level of the design, so that all tri-state logic is also located at the top level of the design in the synthesized netlist, which can effectively prevent the tri-state logic and its ports from being assigned to different verification systems (such as FPGA (Field-Programmable Gate Array, programmable logic device) in the subsequent verification split process.

[0050] In this embodiment, the three-state logic is moved to the top-level module in the circuit design model, including: deleting the three-state logic and the first bidirectional data transmission terminal corresponding to the three-state logic from the third module, and adding a first enable terminal and a three-state signal input terminal in the third module; moving the three-state logic to the top-level module in the circuit design model, connecting the second enable terminal of the moved three-state logic to the first enable terminal, connecting the data output terminal of the three-state logic to the three-state signal input terminal, and connecting the second bidirectional data transmission terminal of the top-level module to the data input terminal of the three-state logic.

[0051] Among them, the first bidirectional data transmission terminal and the second bidirectional data transmission terminal refer to interfaces that can be used as input ports to receive data and as output ports to send data. The tri-state logic includes a second enable terminal, a data output terminal and a data input terminal. The data input terminal is used to receive a logic signal. The data output terminal is used to output a logic signal. The tri-state signal input terminal is used to receive a logic signal output by the data output terminal. The second enable terminal is used to control the working state of the tri-state logic circuit. When the signal of the second enable terminal is high level (EN=1), the data output terminal will output the same logic signal as the data input terminal; when the signal of the second enable terminal is low level (EN=0), the data output terminal will output the opposite logic signal to the data input terminal; when the signal of the second enable terminal is in a high impedance state, the data output terminal will be in a high impedance state, neither outputting a high level nor a low level. The first enable terminal is used to receive the signal of the second enable terminal.

[0052] Specifically, the tri-state logic in the third module and the first bidirectional data transmission terminal corresponding to the tri-state logic can be deleted. And the first enable terminal and the tri-state signal input terminal are added in the third module. At the same time, the deleted tri-state logic is moved to the top-level module in the circuit design model, and a line connection is established between the second enable terminal of the tri-state logic after the move and the first enable terminal in the third module. A line connection is established between the data output terminal of the tri-state logic and the tri-state signal input terminal. A line connection is established between the second bidirectional data transmission terminal of the top-level module and the data input terminal of the tri-state logic. After the second bidirectional data transmission terminal of the top-level module transmits a signal to the data input terminal of the tri-state logic, the data input terminal transmits the signal to the third module. The advantage of this setting is that while all tri-state logics can be moved to the top-level module, the function of the third module can be ensured to be normal, in line with the original model design, and the correct implementation of the tri-state logic can be ensured. At the same time, it is convenient for subsequent partition verification of the circuit design module, and verification errors are effectively avoided.

[0053] For example, see Figure 5 , Figure 5 This is a schematic diagram showing the structure without moving the tri-state logic to the top module. At this time, the tri-state logic exists in the i0 module (i.e., the third module) and is not in the top module (i.e., the top module). The internal tri-state logic needs to be moved to the top module. Figure 6This is a schematic diagram of the structure after the three-state logic is moved to the top module. The specific method can be: delete the three-state logic in the i0 module, move the three-state logic to the top module, and delete the inout port (i.e., the first bidirectional data transmission terminal) in the i0 module. Add the e0 port (i.e., the first enable terminal) and the d0 port (i.e., the three-state signal input terminal) in the i0 module. Connect the inout port (i.e., the second bidirectional data transmission terminal) of the top module to the data input terminal of the three-state logic. Connect the e0 port (the second enable terminal) of the three-state logic to the e0 port in the i0 module. Connect the d0 port (i.e., the data output terminal) of the three-state logic to the d0 port in the i0 module, so that the signal originally input to the three-state logic is directly connected to the e0 port and the d0 port. It should be noted that if the third module still has a parent module, the ports are created in sequence according to the above scheme until the internal signal is transmitted to the second bidirectional data transmission terminal corresponding to the top module.

[0054] In this embodiment, connecting the second bidirectional data transmission terminal of the top-level module with the data input terminal of the tri-state logic includes: connecting the second bidirectional data transmission terminal of the top-level module with the data input terminal of the tri-state logic based on the first line. The first line includes a transfer port; accordingly, a top-level signal input terminal can be added in the third module; and the top-level signal input terminal is connected to the transfer port on the first line.

[0055] The top-level signal input terminal is used to receive the output signal of the top-level module. The first line refers to the signal path of the top-level module connecting the third module and the tri-state logic.

[0056] Specifically, the second bidirectional data transmission terminal of the top-level module can be connected to the data input terminal of the tri-state logic through the first line. A top-level signal input terminal is added to the third module, and a line connection is established between the top-level signal input terminal and the transfer port on the first line to ensure that the third module can correctly receive the output signal of the top-level module, so that the third module can work normally as expected.

[0057] For example, see Figure 6 , you can add the in0 port (i.e. the top-level signal input port) in the i0 module (i.e. the third module) and connect the tristate port (i.e. the transfer port) and the in0 port. This allows the inout port of the top module (i.e. the top-level module) to be connected to the in0 port. In other words, the input signal of the top-level inout port can be transmitted downward along the tri-state logic, and the corresponding port is also created until it is connected to the i0 module, creating port in0, and transmitting the top-level input signal to the in0 port.

[0058] In order to further clearly introduce the technical solution provided by the embodiment of the present invention, continue to refer to Figure 4 , module i0 represents the first module, module i1 represents the netlist to be used, and at this time, module i0 and module i1 are interconnected by tri-state logic. The structural diagram after moving the tri-state logic in modules i0 and i1 to the top module can be seen in Figure 7 Understandably, Figure 7 The i0 module shown in is represented as the third module of the first module, and the i1 module is represented as the third module of the netlist to be used. The i0 module and the i1 module are moved to the top-level module, and the two interconnected three-state logics are in the top-level module, so that the two interconnected three-state logics can be processed into one three-state logic during the subsequent partition verification to avoid verification errors.

[0059] The technical solution provided in this embodiment, by taking into account the three-state logic imported by the user in the netlist to be used, moves all the three-state logic to the top-level module, so that in the subsequent segmentation process, except for the top-level port, there is no two-port port declaration for the internal port, reducing the complexity of the signal direction judgment of the segmentation process. At the same time, the three-state logic is no longer used as the segmentation boundary, avoiding the occupation of the peripheral interface of the verification system in this case, and avoiding the problem of PR (Place & Route, layout and routing) failure caused by the three-state logic and its ports being segmented into different verification systems. PR failure in the verification system refers to the situation in which, during a partial reconfiguration operation, a clock failure occurs in the clock MUX shared by the static design area and the PR design area, resulting in a reconfiguration failure. Specifically, the PR failure is due to the existence of two three-state logic interconnections, and the interconnection ports of the modules to which the two three-state logics belong are both inout ports (i.e., the first bidirectional data transmission end), and are simultaneously connected to the inout port of the top-level module (i.e., the second bidirectional data transmission end). It can be seen from Figure 4 As you can see, this inout port may be driven by two tri-state logics, but this does not comply with the DRC (Design Rule Check) restriction that each signal has only one driving source, which will cause P&R failure.

[0060] S140: Send the processed circuit design model to a chip verification system, so that the chip verification system performs partition verification on the circuit design model.

[0061] In this embodiment, after moving the tri-state logic of the corresponding module in the circuit design model, the processed circuit design model can be sent to the chip verification system, and the chip verification system can divide the circuit design model, and each part is mapped to one or more verification systems to adapt to the resource constraints of the verification system. The verification system simulates the function and application environment of the chip to verify the correctness and performance of the circuit design.

[0062] In this embodiment, the processed circuit design model is sent to the chip verification system so that the chip verification system performs partition verification on the circuit design model, including: setting the third module of the processed circuit design model which is the netlist to be used as the second module; sending the set circuit design model to the chip verification system so that the chip verification system processes all the three-state logics with interconnected relationships in the circuit design model and then performs partition verification on the circuit design model.

[0063] Specifically, the third module in the circuit design model that has moved the tri-state logic and is the netlist to be used can be set as the second module, and at this time, there is no tri-state logic interconnection between the second module and other modules. The set circuit design model is sent to the chip verification system so that the chip verification system can correctly process all the tri-state logics with interconnection relationships in the circuit design model, and partition and verify the processed circuit design model.

[0064] The advantage of this setting is that, by considering that the third module of the netlist to be used is a module that does not need to be synthesized, repeating the synthesis through the synthesis tool will increase the process time. Therefore, the module imported by the netlist to be used will be removed, a new netlist will be output, and the third module will be reset to the second module, so that the third module does not participate in the synthesis process. At the same time, the three-state interconnection only needs to be automatically processed in the circuit design model, and there is no need to repeatedly develop the corresponding interconnection logic processing in the netlist process, which improves development efficiency.

[0065] Based on the above technical solution, it is possible to move the three-state logic inside the circuit design model to the logic of the top-level module. At the same time, the circuit design model before and after modification can be verified by an equivalence verification tool to make the two logically equivalent.

[0066] It should be noted that since the chip verification system cannot optimize the mapped tri-state device logic, the tri-state device corresponding to the third module of the netlist to be used can be converted to RTL-level tri-state logic to move the converted tri-state logic to the top-level module. Currently, there are generally two modes of tri-state logic, one is connected to the inout port, and the other is connected to the output port.

[0067] The first three-state RTL description is as follows:

[0068] assign io=e?i:1'bz;

[0069] assign out=io;

[0070] From the RTL description, we can see that io is used as an output terminal in the first line to receive signals, and as an input terminal in the second line to transmit signals. After synthesis, the three-state logic is mapped to the IOBUF device, so that the converted RTL logic can be equivalent to the IOBUF device logic based on the three-state logic corresponding to the first line and the assignment logic corresponding to the second line. For the equivalent replacement of the second three-state RTL logic, since there is no logic for transmitting signals at the input end, it can be implemented based on the content described in the first line of RTL code without adding additional modules.

[0071] The technical solution provided in this embodiment is to obtain a circuit design model of a target device and at least one to-be-used netlist associated with the circuit design model; wherein the circuit design model includes at least two functional modules, the functional modules including a first module and a second module; the first module is a module visible to the circuit logic; the second module is a module invisible to the circuit logic; at least one first module includes a tri-state logic; the to-be-used netlist includes a tri-state logic; based on at least one to-be-used netlist, at least one second module in the circuit design model is updated; for each tri-state logic in the updated circuit design model, when the third module to which the tri-state logic belongs is a non-top-level module in the circuit design model, the tri-state logic is moved to the top of the circuit design model The top-level module in the circuit design model is used to obtain a processed circuit design model; wherein the third module includes the first module and the netlist to be used; the processed circuit design model is sent to the chip verification system so that the chip verification system performs partition verification on the circuit design model, which solves the problem that the prior art cannot process the three-state logic in the second module, resulting in easy verification errors and low verification efficiency, and realizes that the second module with three-state logic in the circuit design model can be replaced by the netlist to be used, thereby moving the three-state logic in all functional modules in the circuit design model to the top level of the model, and sending the processed circuit design model to the chip verification system for verification, thereby improving the efficiency of logic verification processing and preventing errors in design rule checking.

[0072] Embodiment 2

[0073] Figure 8 is a schematic diagram of the structure of a logic processing device provided according to Embodiment 2 of the present invention. Figure 8 As shown, the apparatus includes: a to-be-used netlist determination module 210 , a model update module 220 , a tri-state logic movement module 230 and a model sending module 240 .

[0074] Among them, the to-be-used netlist determination module 210 is used to obtain the circuit design model of the target device and at least one to-be-used netlist associated with the circuit design model; wherein the circuit design model includes at least two functional modules, and the functional modules include a first module and a second module; the first module is a module visible to the circuit logic; the second module is a module invisible to the circuit logic; at least one of the first modules includes tri-state logic; the to-be-used netlist includes tri-state logic; the model update module 220 is used to update at least one of the second modules in the circuit design model based on the at least one to-be-used netlist; the tri-state logic moving module 230 is used to move each tri-state logic in the updated circuit design model to the top-level module in the circuit design model when the third module to which the tri-state logic belongs is a non-top-level module in the circuit design model to obtain the processed circuit design model; wherein the third module includes the first module and the to-be-used netlist; the model sending module 240 is used to send the processed circuit design model to the chip verification system so that the chip verification system performs partition verification on the circuit design model.

[0075] The technical solution of this embodiment is to obtain a circuit design model of a target device and at least one to-be-used netlist associated with the circuit design model; wherein the circuit design model includes at least two functional modules, the functional modules including a first module and a second module; the first module is a module visible to the circuit logic; the second module is a module invisible to the circuit logic; at least one first module includes a tri-state logic; the to-be-used netlist includes a tri-state logic; based on at least one to-be-used netlist, at least one second module in the circuit design model is updated; for each tri-state logic in the updated circuit design model, when the third module to which the tri-state logic belongs is a non-top-level module in the circuit design model, the tri-state logic is moved to the top-level module in the circuit design model. A top-level module is used to obtain a processed circuit design model; wherein the third module includes the first module and the netlist to be used; the processed circuit design model is sent to the chip verification system so that the chip verification system performs partition verification on the circuit design model, which solves the problem that the prior art cannot process the three-state logic in the second module, resulting in easy verification errors and low verification efficiency, and realizes that the second module with three-state logic in the circuit design model can be replaced by the netlist to be used, thereby moving the three-state logic in all functional modules in the circuit design model to the top level of the model, and sending the processed circuit design model to the chip verification system for verification, thereby improving the efficiency of logic verification processing and preventing errors in design rule checking.

[0076] Based on the above device, optionally, the model updating module 220 includes:

[0077] a second module to be replaced determining unit, configured to search, for each of the netlists to be used, from the circuit design model for a second module to be replaced that matches the netlist to be used;

[0078] The model update determination unit is used to replace the second module to be replaced based on the netlist to be used to obtain an updated circuit design model.

[0079] Based on the above device, optionally, the tri-state logic shift module 230 includes:

[0080] a first processing unit, configured to delete the tri-state logic and a first bidirectional data transmission terminal corresponding to the tri-state logic from the third module, and to add a first enable terminal and a tri-state signal input terminal to the third module;

[0081] A second processing unit is used to move the tri-state logic to the top-level module in the circuit design model, and connect the second enable terminal of the moved tri-state logic with the first enable terminal, connect the data output terminal of the tri-state logic with the tri-state signal input terminal, and connect the second bidirectional data transmission terminal of the top-level module with the data input terminal of the tri-state logic.

[0082] On the basis of the above device, optionally, a second processing unit is used to connect the second bidirectional data transmission terminal of the top-level module with the data input terminal of the three-state logic based on the first line.

[0083] Based on the above device, optionally, the first line includes a transfer port; and the device further includes:

[0084] A third processing unit, configured to add a top-level signal input terminal to the third module;

[0085] The fourth processing unit is used to connect the top-level signal input terminal to the transfer port on the first line.

[0086] Based on the above device, optionally, the model sending module 240 includes:

[0087] A fifth processing unit, configured to set the third module of the processed circuit design model, which is a netlist to be used, as the second module;

[0088] The sixth processing unit is used to send the set circuit design model to the chip verification system, so that the chip verification system processes all interconnected three-state logics in the circuit design model and then performs partition verification on the circuit design model.

[0089] The logic processing device provided in the embodiment of the present invention can execute the logic processing method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0090] Embodiment 3

[0091] Fig. 9 It is a structural diagram of an electronic device that implements the logical processing method of an embodiment of the present invention. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workbenches, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0092] like Fig. 9 As shown, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0093] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0094] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as a logic processing method.

[0095] In some embodiments, the logic processing method may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the logic processing method described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to execute the logic processing method in any other appropriate manner (e.g., by means of firmware).

[0096] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0097] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0098] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0099] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0100] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0101] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0102] An embodiment of the present invention further provides a computer program product, including a computer program, which implements the logic processing method provided by any embodiment of the present invention when executed by a processor.

[0103] In the process of implementation, the computer program product can be written in one or more programming languages ​​or a combination thereof to perform the computer program code of the present invention, including object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (for example, using an Internet service provider to connect through the Internet).

[0104] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0105] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A logic processing method, characterized in that: include: Acquire a circuit design model of a target device and at least one netlist to be used associated with the circuit design model; wherein the circuit design model includes at least two functional modules, the functional modules include a first module and a second module; the first module is a module visible to circuit logic; the second module is a module invisible to circuit logic; at least one of the first modules includes tri-state logic; the netlist to be used includes tri-state logic; Based on the at least one to-be-used netlist, updating at least one of the second modules in the circuit design model; For each tri-state logic in the updated circuit design model, when the third module to which the tri-state logic belongs is a non-top-level module in the circuit design model, the tri-state logic is moved to the top-level module in the circuit design model to obtain the processed circuit design model; wherein the third module includes the first module and the netlist to be used; The processed circuit design model is sent to a chip verification system, so that the chip verification system performs partition verification on the circuit design model.

2. The method according to claim 1, characterized in that The updating of at least one of the second modules in the circuit design model based on the at least one netlist to be used comprises: For each of the netlists to be used, searching the circuit design model for a second module to be replaced that matches the netlist to be used; The second module to be replaced is replaced based on the netlist to be used to obtain an updated circuit design model.

3. The method according to claim 1, characterized in that The step of moving the tri-state logic to a top-level module in the circuit design model comprises: Delete the tri-state logic and the first bidirectional data transmission terminal corresponding to the tri-state logic from the third module, and add a first enable terminal and a tri-state signal input terminal to the third module; Move the tri-state logic to the top-level module in the circuit design model, connect the second enable terminal of the moved tri-state logic with the first enable terminal, connect the data output terminal of the tri-state logic with the tri-state signal input terminal, and connect the second bidirectional data transmission terminal of the top-level module with the data input terminal of the tri-state logic.

4. The method according to claim 3, characterized in that The step of connecting the second bidirectional data transmission terminal of the top-level module to the data input terminal of the tri-state logic comprises: The second bidirectional data transmission terminal of the top-level module is connected to the data input terminal of the tri-state logic based on the first line.

5. The method according to claim 4, characterized in that The first line includes a transfer port; The method further comprises: Adding a top-level signal input terminal in the third module; The top-level signal input terminal is connected to the transfer port on the first line.

6. The method according to claim 1, characterized in that The step of sending the processed circuit design model to a chip verification system so that the chip verification system performs partition verification on the circuit design model includes: Setting the third module of the processed circuit design model, which is the netlist to be used, as the second module; The set circuit design model is sent to a chip verification system, so that the chip verification system processes all interconnected tri-state logics in the circuit design model and then performs partition verification on the circuit design model.

7. A logic processing device, characterized in that: include: A module for determining a netlist to be used, used for acquiring a circuit design model of a target device and at least one netlist to be used associated with the circuit design model; wherein the circuit design model includes at least two functional modules, the functional modules include a first module and a second module; the first module is a module visible to circuit logic; the second module is a module invisible to circuit logic; at least one of the first modules includes tri-state logic; the netlist to be used includes tri-state logic; A model updating module, configured to update at least one of the second modules in the circuit design model based on the at least one netlist to be used; A tri-state logic moving module, for each tri-state logic in the updated circuit design model, when the third module to which the tri-state logic belongs is a non-top-level module in the circuit design model, moves the tri-state logic to the top-level module in the circuit design model to obtain the processed circuit design model; wherein the third module includes the first module and the netlist to be used; The model sending module is used to send the processed circuit design model to a chip verification system so that the chip verification system performs partition verification on the circuit design model.

8. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory in communication with the at least one processor; wherein, The memory stores a computer program executable by the at least one processor. The computer program is executed by the at least one processor so that the at least one processor can perform the logic processing method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the logic processing method according to any one of claims 1 to 6 when executed.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the computer program implements the logic processing method according to any one of claims 1 to 6.

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