Method and device for chip performance simulation and chip performance simulation platform

Abstract

The invention relates to the technical field of chip performance simulation, and discloses a method and device for chip performance simulation and a chip performance simulation platform, and the method comprises the steps: configuring and starting a tested design and a performance reference program of a chip; loading and executing the performance reference program to perform performance simulation on the tested design to obtain a simulation result; and analyzing the collected simulation result to obtain a performance result so as to analyze the performance bottleneck of the tested design. According to the method, a layered system-level simulation architecture is arranged, so that each level can complete specific functions of the level, independent development and optimization can be realized, and the modularization degree of a simulation process is improved. When performance simulation of different performance reference programs is carried out, only the content of the loading execution stage of the performance reference programs needs to be replaced or modified, and the chip configuration and the simulation result collection and analysis stage can be kept unchanged, so that rapid switching is realized, and the performance simulation efficiency is improved.

Description

Technical Field

[0001] The present application relates to the technical field of chip performance simulation, for example, to a method and device for chip performance simulation, and a chip performance simulation platform. Background Art

[0002] SoC (System on Chip) chip is a highly integrated system, usually composed of a microprocessor, a bus system, and memory (various volatile and non-volatile storage devices).

[0003] As the scale of chips becomes larger and larger, in order to ensure that SoC chips have high performance, a reasonable chip architecture is one of the keys to performance. Quantitatively evaluating the performance of chips under the current architecture based on various performance benchmark programs has become an effective means to judge the rationality of the architecture. How to efficiently simulate and evaluate chip performance has become a top priority.

[0004] In order to realize chip performance simulation, the related technology discloses a performance simulation method, including: compiling and simulating a performance benchmark program together with a simulation platform, or configuring the performance benchmark program during the simulation process and then calling it for execution.

[0005] In the process of implementing the embodiments of the present disclosure, it is found that there are at least the following problems in the related art:

[0006] When switching between performance benchmark programs, the code needs to be modified and recompiled and executed, which is not conducive to adapting to different performance benchmark programs, has low cross-platform portability, and has low efficiency.

[0007] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0008] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0009] The embodiments of the present disclosure provide a method and device for chip performance simulation, and a chip performance simulation platform, which can adapt to performance simulation evaluation of a variety of different performance benchmark programs and improve the efficiency of performance simulation.

[0010] In some embodiments, the method for chip performance simulation includes: configuring and starting the chip's design under test and a performance benchmark program; loading and executing the performance benchmark program to perform performance simulation on the design under test and obtain simulation results; parsing the collected simulation results to obtain performance results to analyze the performance bottleneck of the design under test.

[0011] Optionally, the chip's design under test and performance benchmark program are configured and started, including: configuring the clock signal and reset signal of the design under test, generating the startup code of the design under test, configuring the CPU (Central Processing Unit) of the design under test, and adjusting the main function of the CPU of the design under test; configuring the configuration adaptation layer of the performance benchmark program; generating a binary file based on the startup code of the design under test and the main function of the CPU, as well as the configuration adaptation layer of the performance benchmark program, so that the verification platform can obtain the configuration information of the design under test and the performance benchmark program through the binary file.

[0012] Optionally, the clock signal and reset signal of the design under test are configured to generate the startup code of the design under test, including: connecting the clock signal and reset signal of the design under test with the verification platform, so as to respectively update the clock signal and reset signal by using the clock stimulus and reset stimulus generated by the verification platform, and generate the startup code of the design under test; and / or, configuring the central processing unit (CPU) of the design under test, and adjusting the main function of the CPU of the design under test, including: performing startup configuration and initialization operations on the CPU, and synchronizing the main function of the CPU between cores, so as to adjust the main function of the CPU of the design under test.

[0013] Optionally, configuring the configuration adaptation layer of the performance benchmark program includes: after setting the subroutine entry point and result location of the performance benchmark program, initializing the storage area of ​​the performance benchmark program to store a hex file corresponding to the performance benchmark program.

[0014] Optionally, loading and executing a performance benchmark program to perform performance simulation on the design under test to obtain simulation results, including: compiling and linking the performance benchmark program into a hex file; loading the hex file into a storage area of ​​the performance benchmark program through a subroutine entry point of the performance benchmark program; and performing performance simulation on the design under test according to the hex file in the storage area.

[0015] Optionally, the method for chip performance simulation further comprises: when it is necessary to perform performance simulation on the design under test through a different performance benchmark program, replacing the hex file and subroutine entry point in the performance benchmark program.

[0016] Optionally, the method for chip performance simulation further includes: when it is necessary to perform performance simulation on the design under test through different verification platforms, modifying the clock stimulus and reset stimulus generated by the verification platform.

[0017] In some embodiments, the device for chip performance simulation includes: a simulation configuration module, configured to configure and start the chip's design under test and a performance benchmark program; a simulation execution module, configured to load and execute the performance benchmark program to perform performance simulation on the design under test and obtain simulation results; and a result analysis module, configured to analyze the collected simulation results and obtain performance results to analyze the performance bottleneck of the design under test.

[0018] In some embodiments, the device for chip performance simulation includes a processor and a memory storing program instructions, and the processor is configured to execute the method for chip performance simulation as described above when running the program instructions.

[0019] In some embodiments, the chip performance simulation platform is characterized in that it includes: a chip performance simulation platform body; and a device for chip performance simulation as described above, installed on the chip performance simulation platform body.

[0020] The method and device for chip performance simulation and the chip performance simulation platform provided by the embodiments of the present disclosure can achieve the following technical effects:

[0021] First, configure the chip's design under test and the performance benchmark program at the same time. Then, perform performance simulation and collect the results after the simulation. Finally, parse the simulation log file, evaluate the performance of the design under test under a specific performance benchmark program, and analyze the performance bottleneck to make architectural modifications. By separating the three stages of chip configuration, performance benchmark program loading and execution, and simulation result collection and analysis, each stage can be independently developed and optimized, which improves the modularity of the simulation process. When performing performance simulation of different performance benchmark programs, only the content of the performance benchmark program loading and execution stage needs to be replaced or modified, while the chip configuration and simulation result collection and analysis stages can remain unchanged, thereby achieving fast switching and improving the efficiency of performance simulation. In addition, due to the independence of each stage, when the simulation method needs to be ported to other simulation platforms, only the platform-specific parts in the chip configuration stage, such as the configuration of the clock and reset signals, need to be adapted, while the other stages can remain unchanged, which greatly simplifies the porting work and speeds up the progress of the simulation work.

[0022] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0024] Figure 1 is a schematic diagram of a simulation system for a method for chip performance simulation provided by an embodiment of the present disclosure;

[0025] Figure 2 is a schematic diagram of a method for chip performance simulation provided by an embodiment of the present disclosure;

[0026] Figure 3 is a schematic diagram of another method for chip performance simulation provided by an embodiment of the present disclosure;

[0027] Figure 4 is a schematic diagram of another method for chip performance simulation provided by an embodiment of the present disclosure;

[0028] Figure 5 is a schematic diagram of a device for chip performance simulation provided by an embodiment of the present disclosure;

[0029] Figure 6 It is a schematic diagram of another device for chip performance simulation provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0031] The terms "first", "second", etc. in the technical solutions described in the embodiments of the present disclosure are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so as to describe the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0032] Unless otherwise stated, the term "plurality" means two or more.

[0033] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0034] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0035] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0036] The field of chip performance simulation is a key link in semiconductor design verification. With the surge in demand for high-performance computing and the increasing complexity of chip design, this field is experiencing unprecedented development. Currently, simulation technology involves the construction of high-performance simulation platforms, the application of virtual prototyping technology, the practice of parallel computing and distributed simulation, and the application of machine learning and artificial intelligence in simulation prediction and optimization. However, although technological advances have brought new possibilities to chip performance simulation, they are also accompanied by a series of challenges.

[0037] As the scale of design increases, the time and computing resources required for simulation increase significantly, which places higher demands on simulation efficiency. Tool integration and compatibility issues also complicate the design process, requiring better solutions to achieve seamless integration between different simulation tools.

[0038] Figure 1 FIG. 1 is a schematic diagram of a simulation system for a method for chip performance simulation according to an embodiment of the present disclosure. Figure 1 As shown, the implementation environment may include a verification platform 100 , a design under test 200 , a performance benchmark program 300 , and a result parser 400 .

[0039] The clock stimulus and reset stimulus are generated in the verification platform 100, and the clock signal and reset signal of the design under test 200 are connected to the verification platform 100. The simulation system generates a binary file together with the startup code of the design under test 200, the main function of the design under test 200 and the configuration adaptation layer of the performance benchmark program 300. The binary file is a binary executable program file.

[0040] In the performance simulation stage, the simulation system compiles and links the performance benchmark program 300 developed by itself or provided by the partner to generate a corresponding hex file, which is a hexadecimal executable program file. Then, according to the set subroutine entry point, the hex file is loaded into the corresponding storage area and the performance benchmark program simulation is started. After the simulation is completed, the result will be stored in the result location.

[0041] The result parser 400 will parse and obtain the corresponding performance results, thereby obtaining the performance value of interest, so as to further analyze the performance bottleneck point.

[0042] Combination Figure 2As shown, the embodiment of the present disclosure provides a method for chip performance simulation, including:

[0043] S201, the simulation system configures and starts the chip's design under test and performance benchmark program.

[0044] S202, the simulation system loads and executes the performance benchmark program to perform performance simulation on the design under test to obtain simulation results.

[0045] S203, the simulation system analyzes the collected simulation results to obtain performance results to analyze the performance bottleneck of the design under test.

[0046] According to the method for chip performance simulation provided by the embodiment of the present disclosure, first, the chip's design under test is configured, and the performance benchmark program is configured at the same time. Then, the performance simulation is performed and the results are collected after the simulation is completed. Finally, the simulation log file is parsed to evaluate the performance of the design under test under a specific performance benchmark program, and the performance bottleneck is analyzed to make architectural modifications. By separating the three stages of chip configuration, performance benchmark program loading and execution, and simulation result collection and analysis, each stage can be independently developed and optimized, thereby improving the modularity of the simulation process. When performing performance simulation of different performance benchmark programs, only the content of the performance benchmark program loading and execution stage needs to be replaced or modified, while the chip configuration and simulation result collection and analysis stages can remain unchanged, thereby achieving fast switching and improving the efficiency of performance simulation. In addition, due to the independence of each stage, when the simulation method needs to be transplanted to other simulation platforms, only the platform-specific parts in the chip configuration stage, such as the configuration of the clock and reset signals, need to be adapted, while the other stages can remain unchanged, which greatly simplifies the transplantation work and speeds up the progress of the simulation work.

[0047] Optionally, the chip's design under test and performance benchmark program are configured and started, including: configuring the clock signal and reset signal of the design under test, generating the startup code of the design under test, configuring the CPU of the design under test, and adjusting the main function of the CPU of the design under test; configuring the configuration adaptation layer of the performance benchmark program; generating a binary file based on the startup code of the design under test and the main function of the CPU, as well as the configuration adaptation layer of the performance benchmark program, so that the verification platform can obtain the configuration information of the design under test and the performance benchmark program through the binary file.

[0048] In the disclosed embodiment, the design under test is configured in detail, including connecting and setting the clock signal, reset signal and related configuration of the central processing unit CPU, to ensure that the design under test can correctly respond to basic control signals in the simulation environment. The configuration adaptation layer of the performance benchmark program is configured, which involves setting specific parameters of the performance benchmark program, such as cache allocation, storage area initialization and configuration of result collection conditions, to ensure that the performance benchmark program can run correctly and collect performance data. Subsequently, the startup code of the design under test, the main function of the CPU and the configuration adaptation layer of the performance benchmark program are integrated to generate a binary file. This binary file contains all the configuration information of the design under test and the performance benchmark program. The verification platform can use this file to load and execute the design under test and the performance benchmark program to perform performance simulation verification.

[0049] By accurately configuring the design under test and the performance benchmark program, we can ensure a high degree of consistency between the simulation environment and the actual operating environment, and improve the accuracy of the simulation results. Secondly, the binary file contains all the necessary configuration information and can be reused in different simulation platforms and environments, improving the repeatability and portability of the simulation.

[0050] Optionally, the clock signal and reset signal of the design under test are configured to generate the startup code of the design under test, including: connecting the clock signal and reset signal of the design under test with the verification platform, so as to respectively update the clock signal and reset signal by using the clock stimulus and reset stimulus generated by the verification platform, and generate the startup code of the design under test; and / or, configuring the central processing unit (CPU) of the design under test, and adjusting the main function of the CPU of the design under test, including: performing startup configuration and initialization operations on the CPU, and synchronizing the main function of the CPU between cores, so as to adjust the main function of the CPU of the design under test.

[0051] In the disclosed embodiment, the clock signal and reset signal of the design under test are connected to the verification platform to ensure that the verification platform can control and simulate these signals to generate clock stimulus and reset stimulus, thereby driving the timing behavior of the design under test. Next, the CPU is started and configured to ensure that the CPU is in the correct initial state at the beginning of the simulation. Then, the initialization operation of the CPU is performed, including configuring the interrupt system, setting the stack pointer, and initializing the memory, etc., to prepare the CPU to execute subsequent program code. Finally, the main function of the CPU is synchronized between cores to ensure that in a multi-core system, each core can work in coordination to avoid data competition and inconsistency problems.

[0052] In this way, by precisely controlling the clock and reset signals, various timing scenarios can be simulated, including normal operation and abnormal recovery, which enhances the robustness of the design. The startup configuration and initialization operations of the CPU ensure the correct state of the CPU at the beginning of the simulation. Inter-core synchronization ensures the consistency of data and the coordination of operations in a multi-core system. The disclosed embodiment ensures that the design under test can accurately simulate the actual working state in a controlled simulation environment, improving the accuracy and reliability of the simulation.

[0053] Optionally, configuring the configuration adaptation layer of the performance benchmark program includes: after setting the subroutine entry point and result location of the performance benchmark program, initializing the storage area of ​​the performance benchmark program to store a hex file corresponding to the performance benchmark program.

[0054] In the disclosed embodiment, the configuration adaptation layer of the performance benchmark program is configured in detail, including determining the subroutine entry point, which is the location where a specific function or test in the performance benchmark program begins to execute. And setting the result location, which is the address where the performance benchmark program running results are stored. It is ensured that the performance benchmark program can be accurately called and performance data can be collected during the simulation process. Next, the storage area of ​​the performance benchmark program is initialized to receive the hex file corresponding to the performance benchmark program. The initialization operation includes allocating the necessary memory space and setting the correct access rights and mappings to ensure that the CPU can correctly load and execute the hex file.

[0055] By accurately setting the subroutine entry point and result location, the correct execution of the performance benchmark program in the simulation environment and the accurate collection of performance data can be ensured. Initializing the storage area and loading the hex file provide the necessary environment for the execution of the performance benchmark program, so that the performance benchmark program can run efficiently on the simulation platform.

[0056] Optionally, loading and executing a performance benchmark program to perform performance simulation on the design under test to obtain simulation results, including: compiling and linking the performance benchmark program into a hex file; loading the hex file into a storage area of ​​the performance benchmark program through a subroutine entry point of the performance benchmark program; and performing performance simulation on the design under test according to the hex file in the storage area.

[0057] In the disclosed embodiment, first, the source code of the performance benchmark program is converted into a hex file that can be executed in a simulation environment, that is, a binary executable file. This ensures that the performance benchmark program can be understood and executed by the simulation platform. Next, through a pre-set subroutine entry point, the hex file is loaded into the storage area of ​​the performance benchmark program, which can be achieved by mapping the compiled hex file to a specific address space in the simulation environment, ensuring that the CPU can correctly access and execute the performance benchmark program. Finally, the simulation platform performs performance simulation on the design under test based on the hex file in the storage area, executes the instructions in the hex file, and simulates the operation of the performance benchmark program on the design under test, thereby evaluating the performance of the design under test.

[0058] This way of loading and executing hex files allows fast switching between different performance benchmark programs by simply replacing the corresponding hex files without reconfiguring the entire simulation environment, which improves the efficiency and flexibility of simulation.

[0059] Optionally, the method for chip performance simulation further comprises: when it is necessary to perform performance simulation on the design under test through a different performance benchmark program, replacing the hex file and subroutine entry point in the performance benchmark program.

[0060] Combination Figure 3 As shown, the embodiment of the present disclosure provides another method for chip performance simulation, including:

[0061] S301, the simulation system configures and starts the chip's design under test and performance benchmark program.

[0062] S302, the simulation system loads and executes the performance benchmark program to perform performance simulation on the design under test to obtain simulation results.

[0063] S303, the simulation system analyzes the collected simulation results to obtain performance results to analyze the performance bottleneck of the design under test.

[0064] S304, when the simulation system needs to perform performance simulation on the design under test through a different performance benchmark program, the simulation system replaces the hex file and the subroutine entry point in the performance benchmark program.

[0065] In the disclosed embodiment, by replacing the hex file and updating the subroutine entry point, different performance benchmark programs can be quickly adapted, so that the same simulation environment can be used for a variety of different performance tests, improving the flexibility and adaptability of the simulation. Without changing other configurations of the simulation platform, the performance benchmark program can be quickly switched, thereby saving the time of reconfiguration and recompilation and improving the efficiency of the simulation. In addition, only the hex file needs to be replaced and a small amount of configuration needs to be updated, without large-scale modifications to the entire simulation environment, which also helps to maintain the consistency of the simulation environment.

[0066] Optionally, the method for chip performance simulation further includes: when it is necessary to perform performance simulation on the design under test through different verification platforms, modifying the clock stimulus and reset stimulus generated by the verification platform.

[0067] Combination Figure 4 As shown, the embodiment of the present disclosure provides a method for chip performance simulation, including:

[0068] S401, the simulation system configures and starts the chip's design under test and performance benchmark program.

[0069] S402, the simulation system loads and executes the performance benchmark program to perform performance simulation on the design under test to obtain simulation results.

[0070] S403, the simulation system analyzes the collected simulation results to obtain performance results to analyze the performance bottleneck of the design under test.

[0071] S404, when the simulation system needs to perform performance simulation on the design under test through different verification platforms, the simulation system modifies the clock stimulus and reset stimulus generated by the verification platform.

[0072] In the disclosed embodiment, the verification platform is configured according to the characteristics and requirements of the new verification platform to generate clock excitation and reset excitation adapted to the new platform. This includes adjusting the frequency, phase and duty cycle of the clock signal, as well as the duration and polarity of the reset signal to ensure that the timing requirements of the new platform are met. The clock signal and reset signal of the design under test are connected to the output of the new verification platform to ensure that the DUT can receive the correct clock and reset signals. Then, write or update the test script in the verification platform to control the generation of clock and reset signals, and simulate different working scenarios and abnormal recovery situations. Finally, run the updated verification platform, perform performance simulation on the design under test, collect performance data, and analyze the simulation results.

[0073] By modifying the clock stimulus and reset stimulus generated by the verification platform, it is possible to ensure that the design under test receives the correct clock and reset signals on different verification platforms, thereby obtaining accurate performance evaluation results in different simulation environments. Performance simulation can be quickly repeated on different verification platforms, saving time for manual configuration and debugging and improving the efficiency of performance simulation.

[0074] Combination Figure 5 As shown, the embodiment of the present disclosure provides a device 50 for chip performance simulation, including: a simulation configuration module 501, a simulation execution module 502 and a result analysis module 503.

[0075] The simulation configuration module 501 is configured to configure and start the chip's design under test and performance benchmark program; the simulation execution module 502 is configured to load and execute the performance benchmark program to perform performance simulation on the design under test and obtain simulation results; the result analysis module 503 is configured to analyze the collected simulation results and obtain performance results to analyze the performance bottleneck of the design under test.

[0076] Using the device 50 for chip performance simulation provided by the embodiment of the present disclosure, first, the chip's design under test is configured, and the performance benchmark program is configured at the same time. Next, the performance simulation is performed and the results are collected after the simulation is completed. Finally, the simulation log file is parsed to evaluate the performance of the design under test under a specific performance benchmark program, and the performance bottleneck is analyzed to make architectural modifications. By separating the three stages of chip configuration, performance benchmark program loading and execution, and simulation result collection and analysis, each stage can be independently developed and optimized, thereby improving the modularity of the simulation process. When performing performance simulation of different performance benchmark programs, only the content of the performance benchmark program loading and execution stage needs to be replaced or modified, while the chip configuration and simulation result collection and analysis stages can remain unchanged, thereby achieving fast switching and improving the efficiency of performance simulation. In addition, due to the independence of each stage, when the simulation method needs to be transplanted to other simulation platforms, only the platform-specific parts in the chip configuration stage, such as the configuration of the clock and reset signals, need to be adapted, while the other stages can remain unchanged, which greatly simplifies the transplantation work and speeds up the progress of the simulation work.

[0077] Combination Figure 6 As shown, the embodiment of the present disclosure provides a device 60 for chip performance simulation, including a processor 600 and a memory 601. Optionally, the device 60 may also include a communication interface 602 and a bus 603. The processor 600, the communication interface 602, and the memory 601 may communicate with each other through the bus 603. The communication interface 602 may be used for information transmission. The processor 600 may call the logic instructions in the memory 601 to execute the method for chip performance simulation of the above embodiment.

[0078] In addition, the logic instructions in the memory 601 described above can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.

[0079] The memory 601 is a computer-readable storage medium that can be used to store software programs and computer executable programs, such as program instructions / modules corresponding to the method in the embodiment of the present disclosure. The processor 600 executes the functional application and data processing by running the program instructions / modules stored in the memory 601, that is, the method for chip performance simulation in the above embodiment is implemented.

[0080] The memory 601 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function; the data storage area may store data created according to the use of the terminal device, etc. In addition, the memory 601 may include a high-speed random access memory and may also include a non-volatile memory.

[0081] The embodiments of the present disclosure provide a chip performance simulation platform, including: a chip performance simulation platform body, and the above-mentioned device for chip performance simulation. The device for chip performance simulation is installed in the chip performance simulation platform body. The installation relationship described here is not limited to placement inside the chip performance simulation platform body, but also includes installation connections with other components of the chip performance simulation platform, including but not limited to physical connections, electrical connections or signal transmission connections, etc. Those skilled in the art can understand that the device for chip performance simulation can be adapted to a feasible chip performance simulation platform body, thereby realizing other feasible embodiments.

[0082] The technical solution of the embodiment of the present disclosure can be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiment of the present disclosure. The aforementioned storage medium may be a non-transient storage medium, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, and other media that can store program codes.

[0083] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent only possible changes. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the claims. As used in the description of the embodiments and the claims, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of listings containing one or more associated ones. In addition, when used in the present application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the presence of other identical elements in the process, method or device comprising the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

[0084] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. The technicians may use different methods for each specific application to implement the described functions, but such implementations should not be considered to exceed the scope of the embodiments of the present disclosure. The technicians may clearly understand that, for the convenience and simplicity of description, the specific working processes of the systems, devices and units described above may refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.

[0085] In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units can be only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to implement this embodiment. In addition, each functional unit in the embodiment of the present disclosure may be integrated in a processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit.

[0086] The flowchart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to the embodiment of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. In the description corresponding to the flowchart and the block diagram in the accompanying drawings, the operations or steps corresponding to different boxes can also occur in a different order from the order disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified functions or actions, or may be implemented by a combination of dedicated hardware and computer instructions.

Claims

1. A method for chip performance simulation, characterized in that: include: Configure and start the chip's design under test and performance benchmark program; Load and execute the performance benchmark program to perform performance simulation on the design under test and obtain simulation results; Analyze the collected simulation results and obtain performance results to analyze the performance bottlenecks of the design under test.

2. The method according to claim 1, characterized in that Configure and launch the chip's design under test and performance benchmarks, including: Configure the clock signal and reset signal of the design under test, generate the startup code of the design under test, configure the central processing unit (CPU) of the design under test, and adjust the main function of the CPU of the design under test; Configuring the configuration adaptation layer of the performance benchmark program; A binary file is generated according to the startup code of the design under test, the main function of the CPU, and the configuration adaptation layer of the performance benchmark program, so that the verification platform can obtain the configuration information of the design under test and the performance benchmark program through the binary file.

3. The method according to claim 2, characterized in that Configure the clock signal and reset signal of the design under test and generate the startup code of the design under test, including: Connecting the clock signal and reset signal of the design under test to the verification platform, so as to update the clock signal and reset signal respectively by using the clock stimulus and reset stimulus generated by the verification platform, and generate the startup code of the design under test; and / or, Configure the central processing unit (CPU) of the design under test and adjust the main function of the CPU under test, including: Perform startup configuration and initialization operations on the CPU, and synchronize the main function of the CPU between cores to adjust the main function of the CPU under verification.

4. The method according to claim 2, characterized in that: Configure the configuration adaptation layer of the performance benchmark program, including: After setting the subroutine entry point and result location of the performance benchmark program, the storage area of ​​the performance benchmark program is initialized to store the hex file corresponding to the performance benchmark program.

5. The method according to claim 4, characterized in that Load and execute the performance benchmark program to simulate the performance of the design under test and obtain simulation results, including: Compile and link performance benchmark programs into hex files; Loading the hex file into the storage area of ​​the performance benchmark program through the subroutine entry point of the performance benchmark program; Perform performance simulation on the design under test based on the hex file in the storage area.

6. The method according to any one of claims 1 to 5, characterized in that: Also includes: When it is necessary to perform performance simulation on the design under test through different performance benchmark programs, replace the hex file and subroutine entry point in the performance benchmark program.

7. The method according to any one of claims 1 to 5, characterized in that: Also includes: When it is necessary to perform performance simulation on the design under test through different verification platforms, modify the clock stimulus and reset stimulus generated by the verification platform.

8. A device for chip performance simulation, characterized in that: include: A simulation configuration module, configured to configure and start a chip design under test and a performance benchmark program; A simulation execution module is configured to load and execute a performance benchmark program to perform performance simulation on the design under test and obtain simulation results; The result analysis module is configured to analyze the collected simulation results to obtain performance results in order to analyze the performance bottleneck of the design under test.

9. A device for chip performance simulation, comprising a processor and a memory storing program instructions, characterized in that: The processor is configured to execute the method for chip performance simulation according to any one of claims 1 to 7 when running the program instructions.

10. A chip performance simulation platform, characterized in that: include: Chip performance simulation platform itself; The device for chip performance simulation as described in claim 8 or 9 is installed on the chip performance simulation platform body.

Images