Oscillation Detection and Optimization Method and System for Strongly Connected Components of Combinational Logic Circuits

Abstract

The present invention discloses a method and system for detecting and optimizing the oscillation of strongly connected components in a combinational logic circuit. The method constructs an oscillation detection module based on the external input signals and their signal values in the strongly connected components, and then constructs an equivalent transformation module in combination with a multiplexer. The equivalent transformation module is inserted into the output end of the common logic gate of the nested logic loop containing a negative feedback loop and the modified netlist is output. The present invention can successfully detect and interrupt the oscillation when the circuit oscillates, and does not affect the original circuit logic function when the circuit does not oscillate, improving the simulation efficiency and stability of the combinational circuit.

Description

Technical Field

[0001] The present invention relates to the simulation optimization technology of digital combinational logic circuits, in particular to an oscillation detection and optimization method and system for strongly connected components of combinational logic circuits. Background Art

[0002] In modern digital logic circuit design, with the continuous expansion of the scale and the improvement of the integration degree of integrated circuits, the design complexity of digital circuits has increased significantly, and the problem of combinational logic loops in combinational logic circuits has become particularly important. A combinational logic loop refers to the output signal of a combinational logic circuit being fed back to its input through a certain path, thus forming a closed-loop structure. Such a structure is not desired in digital circuit design because the signals in the combinational logic loop will continuously cycle between the input and the output, which may cause the circuit to fail to reach a stable state, thereby triggering high-frequency oscillations. Such oscillations not only affect the normal operation of the circuit but may also cause the simulator to enter a deadlock state, that is, the simulator cannot continue the simulation, the signals cannot converge to a definite state, and the simulation of the entire circuit will be invalidated accordingly.

[0003] In actual integrated circuit design, combinational logic loops may be nested with each other to form strongly connected components (SCCs). Especially in modern large-scale circuit designs, IC designers may inadvertently introduce such strongly connected components, resulting in unexpected oscillation situations. Traditional oscillation detection methods check the change of signal states through a simulator in simple logic circuits to determine whether the circuit oscillates. However, in complex large-scale circuits, this method has extremely high time and computing resource overheads and is not practical. In addition, in actual digital logic circuit simulation, by simply inserting registers on the logic loops of SCCs to break the possible oscillation loops, although this method can successfully prevent the circuit from oscillating, it may also break combinational logic loops that would not oscillate originally, resulting in the transformed circuit not being equivalent to the original in terms of function. It cannot effectively help IC designers discover potential problems that may exist in the circuit in a timely manner. Summary of the Invention

[0004] Object of the Invention: The object of the present invention is to provide an oscillation detection and optimization method and system for strongly connected components of combinational logic circuits, so as to solve the problems in the prior art that it is difficult to accurately determine whether the circuit oscillates while reducing computing resources and time overheads, and to break oscillations without affecting the original function of the circuit.

[0005] Technical Solution: The oscillation detection and optimization method for strongly connected components of combinational logic circuits according to the present invention includes the following steps:

[0006] (1) Obtain the netlist information of the circuit to be optimized, and detect the circuit structure information of the strongly connected components in the circuit to be optimized;

[0007] (2) For each strongly connected component, determine the external input signals that cause the circuit to be optimized to oscillate and their signal values;

[0008] (3) Build an oscillation detection module according to the external input signals and their signal values determined in step (2), such that when the circuit to be optimized oscillates, the output value of the oscillation detection module is logic 1;

[0009] (4) Build an equivalent transformation module, where the equivalent transformation module includes a two-to-one multiplexer, and the control input terminal of the two-to-one multiplexer is used to connect to the output of the oscillation detection module;

[0010] (5) Insert the equivalent transformation module at the output node of the logic gate shared by two loops in the circuit to be optimized to obtain an equivalently transformed circuit. At least one negative feedback logic loop is included in the two loops; when the circuit operates normally, connect to the first input terminal of the two-to-one multiplexer, and select the second input terminal of the two-to-one multiplexer when the circuit to be optimized oscillates to interrupt the oscillation.

[0011] Further, step (2) specifically includes:

[0012] For each strongly connected component, determine the signal values of the external input signals that cause the circuit to be optimized to oscillate by searching for the partially assigned induced boundaries of the external input signals. The method for searching for the partially assigned induced boundaries of the external input signals includes:

[0013] Set the control values of each type of logic gate. The first external input signal is input from the first logic gate and transmitted backward. When the signal value reaches the second logic gate and is different from the control value of the second logic gate, and all the inputs of the second logic gate are internal circuit inputs, then the second logic gate is the partially assigned induced boundary of the first external input signal; where the signal value of the first external input signal is assigned as the control value of the first logic gate;

[0014] Combine the external input signals and their signal values that contain the same partially assigned induced boundary to form a non-empty boundary set;

[0015] Combine the external input signals and their signal values that do not have a partially assigned induced boundary to form a boundary-empty set.

[0016] Further, step (3) specifically includes:

[0017] Build a first oscillation detection branch according to the non-empty boundary set and the boundary-empty set, such that when the external input signals and their signal values in the non-empty boundary set and the boundary-empty set are satisfied, even if the circuit to be optimized reaches the first oscillation condition, the output of the first oscillation detection branch is logic 1;

[0018] Build a second oscillation detection branch according to the negative feedback logic loop in the circuit to be optimized, so that the input of the logic gate in the negative feedback logic loop meets the oscillation condition, that is, when the circuit to be optimized reaches the second oscillation condition, the output of the second oscillation detection branch is logic 1;

[0019] The negative feedback logic loop is a loop in the strongly connected component that contains an odd number of logic gates with inversion characteristics;

[0020] Connect the outputs of the first oscillation detection branch and the second oscillation detection branch with an AND gate to obtain an oscillation detection module, so that when both oscillation conditions are met, the circuit to be optimized oscillates, and the output value of the oscillation detection module is logic 1.

[0021] Further, setting the control values of each type of logic gate includes: setting the control values of AND gates and NAND gates to logic 0, and setting the control values of OR gates and NOR gates to logic 1.

[0022] Further, in step (4), a D flip-flop is inserted into the second input terminal of the multiplexer, and the clock input terminal of the D flip-flop is grounded and kept at a low level.

[0023] The oscillation detection and optimization system for the strongly connected components of the combinational logic circuit described in the present invention includes:

[0024] A strongly connected component detection unit for obtaining the netlist information of the circuit to be optimized and detecting the circuit structure information of the strongly connected components in the circuit to be optimized;

[0025] An external input signal determination unit for determining, for each strongly connected component, the external input signal that causes the circuit to be optimized to oscillate and its signal value;

[0026] An oscillation detection module building unit for building an oscillation detection module according to the external input signal and its signal value determined by the external input signal determination unit, so that when the circuit to be optimized oscillates, the output value of the oscillation detection module is logic 1;

[0027] An equivalent transformation module building unit for building an equivalent transformation module, which includes a multiplexer, and the control input terminal of the multiplexer is used to connect the output of the oscillation detection module;

[0028] A circuit oscillation optimization unit for inserting the equivalent transformation module at the output node of the logic gate shared by the two loops in the circuit to be optimized to obtain an equivalent transformed circuit, where at least one negative feedback logic loop is included in the two loops; when the circuit operates normally, the first input terminal of the multiplexer is connected, and when the circuit to be optimized oscillates, the second input terminal of the multiplexer is selected to interrupt the oscillation.

[0029] Further, the external input signal determination unit includes:

[0030] For each strongly connected component, by searching for the induced boundary of the partial assignment of the external input signal, the signal value of the external input signal that causes the circuit to be optimized to oscillate is determined; the method for searching for the induced boundary of the partial assignment of the external input signal includes:

[0031] Set the control values of each type of logic gate. The first external input signal is input from the first logic gate and transmitted backward. When the signal value reaches the second logic gate and is different from the control value of the second logic gate, and all the inputs of the second logic gate are internal circuit inputs, then the second logic gate is the induced boundary of the partial assignment of the first external input signal; wherein the signal value of the first external input signal is assigned the control value of the first logic gate.

[0032] Merge the external input signals and their signal values that contain the same induced boundary of the partial assignment to form a non-empty boundary set.

[0033] Form a boundary empty set with the external input signals and their signal values that do not have an induced boundary of the partial assignment.

[0034] Further, the oscillation detection module building unit includes:

[0035] Build a first oscillation detection branch according to the non-empty boundary set and the boundary empty set, so that when the external input signals and their signal values in the non-empty boundary set and the boundary empty set are satisfied, even if the circuit to be optimized reaches the first oscillation condition, the output of the first oscillation detection branch is logic 1.

[0036] Build a second oscillation detection branch according to the negative feedback logic loop in the circuit to be optimized, so that when the inputs of the logic gates in the negative feedback logic loop satisfy the oscillation condition, even if the circuit to be optimized reaches the second oscillation condition, the output of the second oscillation detection branch is logic 1.

[0037] The negative feedback logic loop is a loop in the strongly connected component that contains an odd number of logic gates with an inversion characteristic.

[0038] Connect the outputs of the first oscillation detection branch and the second oscillation detection branch with an AND gate to obtain an oscillation detection module, so that when both oscillation conditions are satisfied, the circuit to be optimized oscillates, and the output value of the oscillation detection module is logic 1.

[0039] The electronic device according to the present invention includes a memory, a processor, and a computer program stored on the memory and executable on the processor. When the computer program is loaded into the processor, it implements the oscillation detection and optimization method for the strongly connected components of the combinational logic circuit described above.

[0040] The computer-readable storage medium described in the present invention stores a computer program, and when the computer program is executed by a processor, it implements the method for detecting and optimizing the oscillation of the strongly connected components of the combinational logic circuit.

[0041] Advantages: Compared with the prior art, the advantages of the present invention are as follows: (1) After equivalent transformation of the combinational logic circuit, the present invention can not only effectively prevent oscillation from affecting circuit simulation, but also help IC designers discover design problems, find the positions of circuit structures that do not meet expectations, and improve the efficiency and reliability of circuit simulation; (2) The oscillation detection module proposed by the present invention can improve the oscillation recognition accuracy compared with the feedback loop analysis and isolation method based on graph theory, and can also provide a signal OscFlag for detecting oscillation, which is logic 1 when oscillation occurs and logic 0 when oscillation does not occur; (3) The equivalent transformation module proposed by the present invention can perform equivalent transformation on the circuit without introducing sequential logic and without changing the original function of the circuit, and the transformed circuit can successfully detect and interrupt oscillation. Brief Description of the Drawings

[0042] Figure 1 It is a flowchart of the oscillation detection and optimization method of the present invention.

[0043] Figure 2 It is a schematic diagram of the circuit structure to be optimized in the embodiment of the present invention.

[0044] Figure 3 It is a schematic diagram of the circuit structure of the oscillation detection module in the embodiment of the present invention.

[0045] Figure 4 It is a schematic diagram of the circuit structure of the equivalent transformation module in the embodiment of the present invention.

[0046] Figure 5 It is a schematic diagram of the circuit structure after equivalent transformation in the embodiment of the present invention. Detailed Embodiment

[0047] The technical solution of the present invention will be further described below with reference to the accompanying drawings.

[0048] As Figure 1 shown, the method for detecting and optimizing the oscillation of the strongly connected components of the combinational logic circuit includes the following steps.

[0049] Step 1, read the Verilog source code netlist information through the VPI interface.

[0050] Interact with the C language program through the VPI interface of the Verilog simulator, read the input Verilog source code file, and extract circuit information such as the topological structure of the combinational logic circuit and the circuit signal connections. The circuit information includes the types of logic gates (such as AND gates, OR gates, NOT gates, etc.), the names of input and output ports, and their signal connection relationships. In this embodiment, the schematic diagram of the circuit structure to be optimized generated according to the circuit information is as Figure 2 shown. In practice, combinational logic loops may be nested with each other to form strongly connected component circuits (in the mathematical theory of directed graphs, if every vertex of a graph can be reached from any other point in the graph, then the graph is said to be strongly connected. In any directed graph, the part that can achieve strong connectivity is called a strongly connected component). Simple combinational logic loops also conform to the definition of strongly connected component circuits. The circuit to be optimized in this embodiment is a strongly connected component (SCC). In fact, the circuit can be abstracted as a directed node graph and then the strongly connected components in the circuit can be identified using graph theory algorithms such as depth-first search (DFS). The strongly connected component includes AND gates: I1, I3, I4, I7, I8, I9, I10, I11, I12; NOT gates: I2, I5; NAND gates: I6, I13, I14. It includes external input signals: w1, w2, w3, w4, w5, w6, w7, w8. And some internal signals marked out: w5_6, w8_9, w9_12, w13_14.

[0051] Step 2, find the external input part assignment induced boundaries of the strongly connected component and classify and merge them.

[0052] The method for finding the partial assignment (PA) induced boundary, hereinafter referred to as the PA induced boundary, is as follows: First, assign values to the external input signals of the SCC. According to the control value of the first logic gate corresponding to the external input signal, assign a value to this input, so that the output of the first logic gate can be forced to a given value and continue to be transmitted backward until the signal reaches a logic gate that is not the control value of this logic gate, and all input signals of this logic gate are internal signals of the SCC. Then, it is said that the external input signal boundary is non-empty and this logic gate is the PA induced boundary of the input signal. By this method, the effect of partially cutting the SCC into an acyclic combinational circuit can be achieved.

[0053] If an external input signal of an SCC does not meet the condition that the boundary is non-empty, that is, after assigning a control value to the input of the first logic gate corresponding to the external input signal, when the signal is transmitted backward to a certain logic gate, there is an external input signal of the SCC among the remaining input signals of the logic gate, or after assigning a control value to the input signal, after the signal is transmitted within the SCC, it causes a control value to exist in the out-of-loop input signals of each negative feedback loop contained in the SCC without oscillation, and further makes it impossible for the entire SCC to oscillate, then the PA-induced boundary of the input signal is called an empty set.

[0054] The control value of the logic gate can be determined according to the actual situation. In this embodiment, the control values of the AND gate and NAND gate are logic 0. The NOT gate only realizes the function of single-input inversion. The control values of other common logic gates such as the OR gate and NOR gate are logic 1. According to Figure 2 the circuit structure shown, the results of finding the PA-induced boundaries of the external input signals w1 - w8 are as follows: Since the input w1 corresponds to an AND gate I1, partially assigning w1 the control value of I1, which is logic 0, the signal is logic 1 when it is transmitted to I3, which is not the control value of I3. Therefore, the PA-induced boundary corresponding to w1 is I3; similarly, the induced boundary of w2 assigned logic 0 is I6 and I14; the boundary of w3 assigned logic 0 is an empty set; the boundary of w4 assigned logic 0 is I6; the boundary corresponding to w5 assigned logic 0 is I14; the boundary corresponding to w6 assigned logic 0 is I3 and I9; the boundary corresponding to w7 assigned logic 0 is I3 and I9; the boundary corresponding to w8 assigned logic 0 is an empty set.

[0055] After observation, it can be seen that the signals with reachable logic boundaries being empty sets are w3 and w8; then try to merge the non-empty boundary cases with the same reachable logic boundaries. The boundaries corresponding to the signals w6 and w7 are the same, and they can be merged. Finally, the inputs with empty boundaries are R1 = {w3 = 0} and R2 = {w8 = 0}; the merged non-empty boundary inputs are R3 = {w6 = 0, w7 = 0}.

[0056] Step 3, build an oscillation monitoring module.

[0057] The oscillation detection module consists of two detection branches, namely the first oscillation detection branch and the second oscillation detection branch. In order to ensure that when both oscillation detection branches are logic 1 at the same time, the circuit to be optimized oscillates, that is, the value of OscFlag is logic 1. The two branches are merged through AND logic to obtain the oscillation detection module. As Figure 3 shown, when the output signal OscFlag of the oscillation detection module is logic 1, it represents that the strongly connected component oscillates, and when OscFlag is logic 0, it represents that the strongly connected component does not oscillate.

[0058] The structure of the first oscillation detection branch depends on the PA-induced boundary of the external input signal of the strongly connected component. For the inputs R1 = {w3 = 0} and R2 = {w8 = 0} with an empty boundary, they must both be non-control values to meet the oscillation condition. For the input {w6 = 0, w7 = 0} with a non-empty boundary after merging, it is sufficient if any one of them is a non-control value. To meet the condition that the circuit can oscillate only when the inputs w3 and w8 with an empty boundary are both logic 1, two serial OR gates U4 and U5 are set. Since the control value of the OR gate is logic 1, an inverter U6 and U7 are respectively set after the input signals w3 and w8, so that when w3 and w8 are logic 1, they cannot be used as the control values of the logic gates U4 and U5 to affect the output of the first oscillation detection branch. To meet the condition that the first oscillation detection branch outputs logic 1 only when the external inputs w6 and w7 with a non-empty boundary after merging are both logic 0, an AND gate U3 serial to the previous OR gates U4 and U5 is set, with the input signals w6 and w7 as the inputs of U3. Since the control value of the AND gate is 0, inverters U1 and U2 are respectively set after the signals w6 and w7. According to the above condition constraints, the first oscillation detection branch can be obtained.

[0059] There may be the following two types of combinational logic loops in the strongly connected component: positive feedback loops and negative feedback loops. A negative feedback loop refers to a combinational logic loop that contains an odd number of logic gates with an inversion characteristic, such as NOT gates and NAND gates. A positive feedback loop refers to a logic loop that contains an even number of or no logic gates with an inversion characteristic. If the negative feedback loops contained in the circuit are not processed during circuit simulation, it may cause oscillations, resulting in the entire simulator falling into a deadlock state, greatly increasing the simulation running time until it automatically interrupts.

[0060] The structure of the second oscillation detection branch depends on the external input signals of the negative feedback loops contained in the strongly connected component. If all the input signals outside the negative feedback loops are non-control values, it is determined that the logic loop meets the oscillation condition. Observe Figure 2It can be known later that as long as the out-of-loop signals w8, w5_6, w9_12, and w6 of the negative feedback loop: {I8 - I9 - I10 - I6 - I8} are all non-control values, or the out-of-loop signals w7, w13_14, w8_9, and w3 of another negative feedback loop: {I9 - I11 - I14 - I12 - I9} are all non-control values, the condition can be satisfied. To meet the above conditions, two branches are set to be in parallel and then connected to an OR gate U15. The first parallel branch is composed of three AND gates U9, U10, and U11 in series, with the signals w8, w5_6, w9_12, and w6 as the inputs of the AND gates. The second parallel branch is also composed of three AND gates U12, U13, and U14 in series, with the signals w7, w13_14, w8_9, and w3 as the inputs of the AND gates. According to the above conditions, the second oscillation detection branch is obtained.

[0061] Step 4, build an equivalent transformation module.

[0062] To ensure that when the combinational logic strongly connected component is equivalently transformed, the circuit can successfully detect oscillations in a timely manner when oscillations occur, and does not affect the normal operation of the original circuit's logic function when the circuit does not oscillate, it is necessary to design an equivalent transformation module.

[0063] The equivalent transformation module is as Figure 4 shown. Based on the oscillation detection module obtained in step S3, its output signal OscFlag is used as the input of the control terminal sel0 of the multiplexer. The first data input terminal a of the multiplexer is directly connected to the input terminal in without processing, and this path is selected when there is no oscillation or the circuit is in the initial state to ensure that the circuit operates with the original logic function. The second data input terminal b of the multiplexer will insert a D flip-flop that does not introduce timing logic. The clock input terminal of the flip-flop is grounded to GND and always remains low level. When oscillations occur in the circuit, this path will be selected to interrupt the oscillations through the flip-flop. Finally, the equivalent transformation module is obtained, with its input being the signal in and its output being the signal out.

[0064] Step 5, insert the equivalent transformation module into the circuit for equivalent transformation.

[0065] The strongly connected component is composed of several nested combinational logic loops. Among them, the negative feedback loop may cause oscillations because the positive feedback loop contains an even number of logic gates with an inversion characteristic and does not have the condition to cause the signal to flip infinitely and lead to oscillations. To minimize the number of inserted equivalent transformation modules, the equivalent transformation module is selected to be inserted at the output node of the logic gate shared by two logic loops, and at least one negative feedback loop must be included in the two combinational logic loops, so as to ensure that the oscillations are completely interrupted when oscillations occur. Based on this idea, in Figure 2Equivalent transformation modules are inserted at the output nodes of logic gates I9 and I6 in the shown circuit, and the circuit structure after the final equivalent transformation is as Figure 5 shown.

[0066] After the circuit after the equivalent transformation receives a new set of external excitation signals, the oscillation detection module will immediately react to determine whether the strongly connected component oscillates under the output excitation signal. If oscillation occurs, the OscFlag signal is logic 1, and the multiplexer selects a path with a D flip-flop inserted, immediately interrupting the combinational logic loop to prevent the occurrence of oscillation. The IC designer can discover the faults existing in the circuit according to the OscFlag signal. If no oscillation occurs, the OscFlag signal is logic 0, and the multiplexer selects another path without any processing, which will not affect the logic function of the original circuit.

[0067] To better verify and illustrate the technical effects achieved by the method of the present invention, in this embodiment, the method of the present invention is tested by comparing with the feedback loop analysis and isolation method based on graph theory, and the test results are compared by means of scientific demonstration to verify the real effects of the method of the present invention. Among them, the steps of the feedback loop analysis and isolation method based on graph theory are as follows:

[0068] First, the combinational logic circuit is abstracted into a directed node graph. In this process, each logic gate in the circuit is regarded as a node in the graph, and the connection relationship between logic gates is represented as a directed edge. Specifically, if the output of a logic gate is connected to the input of another logic gate, a directed edge is drawn between the corresponding nodes to represent the signal flow direction. In this way, the entire combinational logic circuit is transformed into a directed graph, providing a basis for subsequent loop detection.

[0069] Then, graph theory algorithms such as depth-first search (DFS) are used to traverse the directed graph to detect all loops existing therein. The DFS algorithm starts from a starting node, searches deeply along the path until it can no longer proceed and then backtracks. During the search process, if a node that has been visited is encountered and this node is not the starting node of the current path, it means that a loop has been found. In this way, the entire directed graph can be systematically traversed to find all possible existing loops. These loops are the feedback loops in the combinational logic circuit and are the potential causes of oscillation.

[0070] After all loops are detected, these loops need to be analyzed to determine which loops are the key factors causing oscillations. Generally, the length of the loop, the types of logic gates it contains, and the signal propagation characteristics, etc. will all affect its impact on circuit stability. By analyzing the structure and characteristics of the loops, those loops that are most likely to cause oscillations can be processed preferentially. For example, determine whether the loop is a positive feedback loop or a negative feedback loop, and insert a register or flip-flop on the negative feedback loop to break the loop, while the positive feedback loop is not processed.

[0071] Finally, the loop is broken by inserting a register on the combinational logic loop. The insertion position of the register needs to be carefully selected to ensure that the loop can be effectively broken while minimizing the impact on the circuit function. Generally speaking, the register should be inserted on the critical path of the loop, that is, the path where the signal circulates in the loop. In this way, the register can temporarily store the signal, break the continuous feedback of the signal, and thus prevent oscillations from occurring.

[0072] Based on the digital circuit simulation platform verisim, the circuits modified under the above two methods are run, and three combinational logic circuits with different scales and complexities are respectively adopted for testing: T_CCA_1, T_ACA_1, and T_ACA_2, which are strongly connected components containing multiple double-loop nestings, triple-loop nestings, and multiple triple-loop nestings respectively. In order to verify whether the logic function of the modified combinational circuit is equivalent to that of the original circuit without oscillations, all possible input vectors are applied to the input terminals of the modified circuit, the internal node signals under each input vector are monitored, and compared with the internal node signals of the original circuit under the same input vector, and the number of input vectors with exactly the same internal signals without oscillations is counted. In order to verify whether the modified circuit can successfully detect and break oscillations, the number of oscillations successfully detected and broken by the modified circuit is counted.

[0073] Table 1: Operation results of the method of the present invention

[0074]

[0075] Table 2: Operation results of the feedback loop analysis and isolation method based on graph theory

[0076]

[0077] Referring to Table 1 and Table 2, the number of input vectors with completely consistent internal signals in the circuit transformed by the method of the present invention is the same as the total number of non-oscillating input vectors when the circuit is non-oscillating, indicating that the logical values of the internal nodes are exactly the same as those of the original circuit under the condition of non-oscillating input vectors. It is proved that the circuit transformed by the method of the present invention can achieve complete matching with the internal node signals of the original circuit without oscillation, does not affect the function of the original circuit, and realizes the effect of equivalent transformation. While for the circuit transformed by the method based on graph theory, the matching degree of the internal node signals with the original circuit only reaches 83% on average. Compared with the method based on graph theory, the signal matching degree is increased by 16% on average, and the number of detected and interrupted oscillations is increased by 12% on average. In summary, the present invention effectively achieves equivalent transformation of the original circuit while detecting and interrupting circuit oscillations, improving the efficiency and stability of combinational circuit simulation.

[0078] The oscillation detection and optimization system for strongly connected components of the combinational logic circuit described in the present invention includes:

[0079] A strongly connected component detection unit for obtaining the netlist information of the circuit to be optimized and detecting the circuit structure information of the strongly connected components in the circuit to be optimized;

[0080] An external input signal determination unit for determining, for each strongly connected component, the external input signals that cause the circuit to be optimized to oscillate and their signal values;

[0081] An oscillation detection module building unit for building an oscillation detection module according to the external input signals and their signal values determined in the external input signal determination unit, such that when the circuit to be optimized oscillates, the output value of the oscillation detection module is logic 1;

[0082] An equivalent transformation module building unit for building an equivalent transformation module, the equivalent transformation module including a two-to-one multiplexer, and the control input terminal of the two-to-one multiplexer is used to connect the output of the oscillation detection module;

[0083] A circuit oscillation optimization unit for inserting the equivalent transformation module at the output node of the logic gate shared by two loops in the circuit to be optimized to obtain an equivalently transformed circuit, where at least one negative feedback logic loop is included in the two loops; when the circuit operates normally, the first input terminal of the two-to-one multiplexer is connected, and when the circuit to be optimized oscillates, the second input terminal of the two-to-one multiplexer is selected to interrupt the oscillation.

[0084] The electronic device described in the present invention includes a memory, a processor, and a computer program stored on the memory and executable on the processor. When the computer program is loaded into the processor, it implements the oscillation detection and optimization method for strongly connected components of the combinational logic circuit described above.

[0085] The computer-readable storage medium described in the present invention stores a computer program, and when the computer program is executed by a processor, it implements the oscillation detection and optimization method for strongly connected components of the combinational logic circuit.

[0086] The computer-readable storage medium may include RAM, ROM, EEPROM, CD-ROM, or other optical disc storage devices, magnetic disk storage devices, or other magnetic storage devices, flash memory, or any other medium that can store program code in the form of instructions or data structures and can be accessed by a computer.

[0087] The processor is configured to execute the computer program stored in the memory to implement each step in the method described in the above embodiments.

Claims

1. A method for detecting and optimizing the oscillation of strongly connected components in a combinational logic circuit, characterized in that It includes the following steps: (1) Obtain the netlist information of the circuit to be optimized, and detect the circuit structure information of the strongly connected components in the circuit to be optimized; (2) For each strongly connected component, determine the external input signal that causes the circuit to be optimized to oscillate and its signal value; (3) Build an oscillation detection module according to the external input signal and its signal value determined in step (2), so that when the circuit to be optimized oscillates, the output value of the oscillation detection module is logic 1; (4) Build an equivalent transformation module, and the equivalent transformation module includes a two-way multiplexer, and the control input terminal of the two-way multiplexer is used to connect the output of the oscillation detection module; (5) Insert the equivalent transformation module at the output node of the logic gate shared by the two loops in the circuit to be optimized to obtain an equivalent transformed circuit. At least one negative feedback logic loop is included in the two loops; when the circuit operates normally, connect to the first input terminal of the two-way multiplexer, and select the second input terminal of the two-way multiplexer to interrupt the oscillation when the circuit to be optimized oscillates; Step (2) specifically includes: For each strongly connected component, determine the signal value of the external input signal that causes the circuit to be optimized to oscillate by searching for the partial assignment induced boundary of the external input signal. The method for searching for the partial assignment induced boundary of the external input signal includes: Set the control value of each type of logic gate. The first external input signal is input from the first logic gate and transmitted backward. When the signal value reaches the second logic gate and is different from the control value of the second logic gate, and all the inputs of the second logic gate are internal circuit inputs, then the second logic gate is the partial assignment induced boundary of the first external input signal; wherein the signal value of the first external input signal is assigned the control value of the first logic gate; Combine the external input signals and their signal values that contain the same partial assignment induced boundary to form a non-empty boundary set; Combine the external input signals and their signal values that do not have a partial assignment induced boundary to form a boundary empty set; Step (3) specifically includes: Build a first oscillation detection branch according to the non-empty boundary set and the boundary empty set, so that when the external input signals and their signal values in the non-empty boundary set and the boundary empty set are satisfied, even if the circuit to be optimized reaches the first oscillation condition, the output of the first oscillation detection branch is logic 1; the first oscillation detection branch is composed of logic gates, and its inputs are the external input signals and their signal values in the non-empty boundary set and the boundary empty set; Build a second oscillation detection branch according to the negative feedback logic loop in the circuit to be optimized, so that when the inputs of the logic gates in the negative feedback logic loop satisfy the oscillation condition, even if the circuit to be optimized reaches the second oscillation condition, the output of the second oscillation detection branch is logic 1; the second oscillation detection branch is composed of logic gates, and its inputs are the input signals and their signal values of the logic gates in the negative feedback logic loop; The negative feedback logic loop is a loop that contains an odd number of logic gates with an inversion characteristic in a strongly connected component; Connect the outputs of the first oscillation detection branch and the second oscillation detection branch with an AND gate to obtain an oscillation detection module, so that when both oscillation conditions are satisfied, the circuit to be optimized oscillates, and the output value of the oscillation detection module is logic 1; In step (4), the second input terminal of the one - of - two multiplexer is inserted with a D - flip - flop, and the clock input terminal of the D - flip - flop is grounded and kept at a low level.

2. The method for detecting and optimizing the oscillation of strongly connected components of a combinational logic circuit according to claim 1, characterized in that The setting of the control value of each type of logic gate includes: the control values of AND gates and NAND gates are set to logic 0, and the control values of OR gates and NOR gates are set to logic 1.

3. An oscillation detection and optimization system for strongly connected components of a combinational logic circuit based on the method described in claim 1, characterized in that, It includes: A strongly - connected component detection unit, which is used to obtain the netlist information of the circuit to be optimized and detect the circuit structure information of the strongly - connected components in the circuit to be optimized; An external input signal determination unit, which is used to determine, for each strongly - connected component, the external input signal that causes the circuit to be optimized to oscillate and its signal value; An oscillation detection module construction unit, which is used to construct an oscillation detection module according to the external input signal and its signal value determined by the external input signal determination unit, so that when the circuit to be optimized oscillates, the output value of the oscillation detection module is logic 1; An equivalent transformation module construction unit, which is used to construct an equivalent transformation module. The equivalent transformation module includes a one - of - two multiplexer, and the control input terminal of the one - of - two multiplexer is used to connect to the output of the oscillation detection module; A circuit oscillation optimization unit, which is used to insert the equivalent transformation module at the output node of the logic gate shared by two loops in the circuit to be optimized to obtain an equivalent transformed circuit. At least one negative - feedback logic loop is included in the two loops. When the circuit operates normally, the first input terminal of the one - of - two multiplexer is accessed, and when the circuit to be optimized oscillates, the second input terminal of the one - of - two multiplexer is selected to interrupt the oscillation.

4. The oscillation detection and optimization system for strongly connected components of a combinational logic circuit according to claim 3, wherein The external input signal determination unit includes: For each strongly - connected component, by searching for the partial - assignment induced boundary of the external input signal, to determine the signal value of the external input signal that causes the circuit to be optimized to oscillate; the method of searching for the partial - assignment induced boundary of the external input signal includes: Set the control value of each type of logic gate. The first external input signal is input from the first logic gate and transmitted backward. When the signal value reaches the second logic gate and is different from the control value of the second logic gate, and all the inputs of the second logic gate are internal circuit inputs, then the second logic gate is the partial - assignment induced boundary of the first external input signal; where the signal value of the first external input signal is assigned the control value of the first logic gate; Merge the external input signals and their signal values that contain the same partial - assignment induced boundary to form a non - empty boundary set; Form a boundary - empty set with the external input signals and their signal values that have no partial - assignment induced boundary.

5. The oscillation detection and optimization system for strongly connected components of a combinational logic circuit according to claim 4, characterized in that, The oscillation detection module construction unit includes: Construct a first oscillation detection branch according to the non - empty boundary set and the boundary - empty set, so that when the external input signals and their signal values in the non - empty boundary set and the boundary - empty set are satisfied, even if the circuit to be optimized reaches the first oscillation condition, the output of the first oscillation detection branch is logic 1; Construct a second oscillation detection branch according to the negative - feedback logic loop in the circuit to be optimized, so that when the inputs of the logic gates in the negative - feedback logic loop satisfy the oscillation condition, even if the circuit to be optimized reaches the second oscillation condition, the output of the second oscillation detection branch is logic 1; The negative - feedback logic loop is a loop in the strongly - connected component that contains an odd number of logic gates with an inversion characteristic. The outputs of the first oscillation detection branch and the second oscillation detection branch are connected by an AND gate to obtain an oscillation detection module, such that when two oscillation conditions are simultaneously satisfied, the circuit to be optimized oscillates, and the output value of the oscillation detection module is logic 1.

6. An electronic device, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, When the computer program is loaded into the processor, it implements the oscillation detection and optimization method for the strongly connected component of the combinational logic circuit according to any one of claims 1-2.

7. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the oscillation detection and optimization method for the strongly connected component of the combinational logic circuit according to any one of claims 1-2.

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