Graphics pipeline sampling method, graphics processor and electronic equipment

Abstract

Embodiments of the present invention provide a graphics pipeline sampling method, a graphics processor, and an electronic device. The method is applied to a graphics processor comprising a graphics pipeline, an instruction processing front end, and several levels of functional modules sequentially connected to the instruction processing front end, with a sampling module pre-installed in each level of the functional module. The method includes: the instruction processing front end sequentially reads instructions to be executed from an instruction buffer. If a sampling instruction is identified, it is converted into a target instruction stream and input into each level of the graphics pipeline functional module for sequential processing; for a target sampling module that receives the target instruction stream, if it identifies that a target event hits an event corresponding to a functional module at this level, then, after determining that the functional module at this level is empty, it obtains a sample value of the target event and inserts it into the target instruction stream to obtain an updated target instruction stream, and then forwards the updated target instruction stream. The present invention can reduce unnecessary waiting and improve the performance of the graphics pipeline.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a graphics pipeline sampling method, a graphics processor, and an electronic device. Background Art

[0002] The graphics pipeline is a series of processing steps that transforms a 3D scene into a 2D image displayed on the screen. The graphics pipeline consists of multiple pipeline stages, such as the Input Assembler, Vertex Shader, Rasterizer, Pixel Shader, and Output Merger.

[0003] The input assembly stage is the first fixed-function stage in the graphics pipeline. It packages vertex information sent by the application into processing tasks required by subsequent pipelines. Its output serves as the input for the vertex shader. The vertex shader receives vertex data from the input assembly stage and processes each vertex, including transforming position coordinates and calculating attributes such as color. It calculates the final position, color, normal, and other attributes for each vertex and passes the vertex data to the rasterizer. The rasterizer takes the vertex data output by the vertex shader as input, converts it into pixels on the screen, and provides pixel information for the pixel shader to process. The pixel shader processes each pixel generated by the rasterizer, calculating the final display color for each pixel. The calculated pixel color and other information are passed to the output blending stage, whose output determines the final color displayed on the screen for each pixel. The output blending stage blends the pixel color with the value in the render target buffer to generate the final image.

[0004] The graphics pipeline is a general model of how a graphics processing unit (GPU) operates. It takes a three-dimensional scene represented in some form as input and outputs two-dimensional raster images to the display. During the graphics rendering process, it may be necessary to use sampling instructions to sample events in the graphics pipeline to check the execution status of the graphics pipeline in real time. Several events are defined in the graphics pipeline, such as the number of vertices, the number of primitives, and the number of clipped primitives. To ensure that the sampling values ​​of the events are correct, when a sampling instruction is parsed, it is necessary to wait until the entire graphics pipeline is drained before executing the sampling instruction. In other words, the sampling process requires pausing the entire graphics pipeline, which may introduce unnecessary waiting and reduce the performance of the graphics pipeline. Summary of the Invention

[0005] In view of the above problems, embodiments of the present invention are proposed to provide a graphics pipeline sampling method that overcomes the above problems or at least partially solves the above problems, which can achieve a more refined event sampling process, reduce unnecessary waiting, and improve the performance of the graphics pipeline.

[0006] Accordingly, embodiments of the present invention further provide a graphics processor, an electronic device, a readable storage medium, and a computer program product to ensure the implementation and application of the above method.

[0007] In a first aspect, an embodiment of the present invention discloses a graphics pipeline sampling method, which is applied to a graphics processor. The graphics processor includes a graphics pipeline, the graphics pipeline includes an instruction processing front end and several levels of functional modules sequentially connected to the instruction processing front end, and each level of the functional module is pre-installed with a sampling module. The method includes:

[0008] The instruction processing front end sequentially reads instructions to be executed from the instruction buffer. If the instructions to be executed are identified as sampling instructions, the sampling instructions are converted into a target instruction stream and input into the functional modules of each level of the graphics pipeline for sequential processing. The target instruction stream is used to obtain a sampling value of a target event indicated by the sampling instruction.

[0009] For the target sampling module that receives the target instruction stream, if it is recognized that the target event hits the event corresponding to the current-level functional module, after determining that the current-level functional module is empty, the sampling value of the target event is obtained and inserted into the target instruction stream to obtain an updated target instruction stream;

[0010] The target sampling module forwards the updated target instruction stream to the next module.

[0011] In a second aspect, an embodiment of the present invention discloses an instruction processing method applied to a graphics processor, wherein the graphics processor includes a graphics pipeline, and the graphics pipeline includes several levels of functional modules connected in sequence. The method includes:

[0012] Identifying whether the instruction to be executed is a sampling instruction; the sampling instruction includes a first operand for indicating a target event and a second operand for indicating a target address; the target address is the first memory address of the sampling value of the target event to be written;

[0013] If the instruction to be executed is identified as a sampling instruction, a first instruction is generated according to the first operand, and a second instruction is generated according to the second operand, to obtain a target instruction stream consisting of the first instruction and the second instruction; the target instruction stream is used to obtain a sample value of a target event indicated by the sampling instruction; the first instruction is used to transmit the target event, and the second instruction is used to transmit the target address;

[0014] The target instruction stream is processed in sequence by the functional modules of each level of the graphics pipeline, and is updated based on the sampled value of the target event after the corresponding functional module that hits the target event is drained.

[0015] In a third aspect, an embodiment of the present invention discloses a graphics processor, comprising a graphics pipeline, the graphics pipeline comprising an instruction processing front end and several levels of functional modules sequentially connected to the instruction processing front end, each level of the functional module being pre-installed with a sampling module, wherein:

[0016] The instruction processing front end is used to sequentially read the instructions to be executed from the instruction buffer. If the instructions to be executed are identified as sampling instructions, the sampling instructions are converted into a target instruction stream and input into the functional modules of each level of the graphics pipeline for sequential processing; the target instruction stream is used to obtain the sampling value of the target event indicated by the sampling instruction;

[0017] The sampling module is used to receive the target instruction stream. If it is identified that the target event hits the event corresponding to the functional module at this level, then after determining that the functional module at this level is empty, the sampling value of the target event is obtained and inserted into the target instruction stream to obtain an updated target instruction stream; and the updated target instruction stream is forwarded to the next module.

[0018] In a fourth aspect, an embodiment of the present invention discloses a graphics processor, the graphics processor comprising a graphics pipeline, the graphics pipeline comprising an instruction recognition module, an instruction conversion module, and several levels of functional modules sequentially connected to the instruction conversion module;

[0019] The instruction recognition module is used to identify whether the instruction to be executed is a sampling instruction; the sampling instruction includes a first operand for indicating a target event and a second operand for indicating a target address; the target address is the first memory address of the sampling value to be written into the target event;

[0020] The instruction conversion module is configured to, if the instruction to be executed is identified as a sampling instruction, generate a first instruction based on the first operand and generate a second instruction based on the second operand, thereby obtaining a target instruction stream consisting of the first instruction and the second instruction; the target instruction stream is configured to obtain a sampling value of a target event indicated by the sampling instruction; the first instruction is configured to transmit the target event, and the second instruction is configured to transmit the target address;

[0021] The functional module is used to process the target instruction stream passing through, and update the target instruction stream based on the sampling value of the target event after the corresponding functional module hitting the target event is drained.

[0022] In a fifth aspect, an embodiment of the present invention discloses an electronic device, comprising: a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the steps of any of the graphics pipeline sampling methods described above.

[0023] In a sixth aspect, an embodiment of the present invention discloses a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the graphics pipeline sampling method as described above can be implemented.

[0024] In a seventh aspect, an embodiment of the present invention discloses a computer program product, comprising a computer program, which, when executed by a processor, performs the steps of any of the aforementioned graphics pipeline sampling methods.

[0025] The embodiments of the present invention include the following advantages:

[0026] In this embodiment of the present invention, a sampling instruction specifies a target event to be sampled. The instruction processing front end then converts the sampling instruction into a target instruction stream recognizable by a sampling module. This target instruction stream is used to obtain sampled values ​​for the target event indicated by the sampling instruction. The target instruction stream is sequentially processed by each level of the graphics pipeline's functional modules (built-in sampling modules). When a sampling module built into a functional module at a certain level receives the target instruction stream and identifies that the target event to be sampled matches the event corresponding to that level's functional module, it obtains the sampled value of the hit target event and inserts it into the target instruction stream. After the target instruction stream has been processed by each level of the graphics pipeline's functional modules (built-in sampling modules), statistical analysis can be performed to obtain the sampled values ​​for all target events indicated by the sampling instruction. This process eliminates the need to wait for the entire graphics pipeline to drain. When the target instruction stream reaches a sampling module, it only waits for the functional module at that level to drain, pausing execution of that functional module without affecting the execution of other functional modules. The embodiment of the present invention distributes sampling points across functional modules at all levels in the graphics pipeline, which can reduce the granularity of sampling and enable sampling instructions to be executed in designated functional modules without blocking other functional modules in the graphics pipeline. This enables a more refined event sampling process, reduces unnecessary waiting, improves the performance of the graphics pipeline, and thus improves the efficiency of GPU graphics drawing. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a flowchart of the steps of an embodiment of a graphics pipeline sampling method of the present invention;

[0028] Figure 2It is a schematic diagram of the structure of a functional module at a certain level in the graphics pipeline of the present invention;

[0029] Figure 3 This is a schematic flow chart of the steps of a sampling module in the present invention;

[0030] Figure 4 This is an example schematic diagram of obtaining a current-stage water emptying signal according to the present invention;

[0031] Figure 5 It is a structural diagram of setting an event counter in a certain functional module of the present invention;

[0032] Figure 6 It is a structural diagram of a graphics pipeline in the present invention;

[0033] Figure 7 is a flowchart of steps of an embodiment of an instruction processing method of the present invention;

[0034] Figure 8 is a structural block diagram of an embodiment of a graphics processor 300 of the present invention;

[0035] Figure 9 is a structural block diagram of an embodiment of a graphics processor 400 of the present invention;

[0036] Figure 10 It is a structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0037] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0038] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects before and after the association are in an "or" relationship. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0039] Reference Figure 1, shows a flowchart of an embodiment of a graphics pipeline sampling method of the present invention. The method is applied to a graphics processing unit (GPU). The GPU includes a graphics pipeline. The graphics pipeline includes an instruction processing front end and several levels of functional modules sequentially connected to the instruction processing front end. A sampling module is pre-installed in each level of the functional module. The method may include the following steps:

[0040] Step 101: The instruction processing front end sequentially reads instructions to be executed from the instruction buffer. If the instructions to be executed are identified as sampling instructions, the sampling instructions are converted into a target instruction stream and input into the functional modules of each level of the graphics pipeline for processing in sequence. The target instruction stream is used to obtain a sample value of a target event indicated by the sampling instruction.

[0041] Step 102: For the target sampling module that receives the target instruction stream, if it is recognized that the target event hits the event corresponding to the current-level functional module, after determining that the current-level functional module is empty, the target sampling module obtains the sample value of the target event and inserts it into the target instruction stream to obtain an updated target instruction stream.

[0042] Step 103: The target sampling module forwards the updated target instruction stream to the next module.

[0043] The graphics pipeline sampling method of the present invention can be applied to a graphics processing unit (GPU) to sample specified events of specified functional modules in a graphics pipeline comprising an instruction processing front end and several levels of functional modules sequentially connected to the instruction processing front end.

[0044] For example, the graphics pipeline may include the following modules from front to back: a command processing front end (CF), a geometry engine (GE), a primitive engine (PE), and a rendering output unit (OM).

[0045] In a specific implementation, the graphics drawing tasks generated by the application are stored in the instruction buffer in the form of an instruction stream. The instruction processing front end CF can be used to sequentially retrieve instructions from the instruction stream from the instruction buffer to prepare for subsequent processing and ensure the orderly supply of instructions. The instruction processing front end CF sequentially retrieves instructions from the instruction stream from the instruction buffer and sends them to the first-level functional module of the graphics pipeline (such as the geometry engine GE) for processing, and then passes through the various functional modules of the primitive engine PE and the rendering output unit OM for processing. Among them, the geometry engine GE, the primitive engine PE, and the rendering output unit OM are the three main functional modules of the graphics pipeline, which are used for vertex task assembly and shading, rasterization and pixel shading, and output post-processing, respectively.

[0046] Each functional module in the graphics pipeline refers to the relatively independent yet interrelated processing units or subsystems that divide the entire graphics processing process according to a specific processing order and logic to achieve specific graphics processing tasks. The functional modules at each level in the graphics pipeline may vary depending on the processor architecture and application scenario.

[0047] It should be noted that the functional modules at each level described above are merely examples of applications of the present invention. The present invention does not limit the number or types of functional modules included in the graphics pipeline. For example, the graphics pipeline may be a graphics pipeline defined by a graphics programming interface such as OpenGL or Direct3D, and the functional modules included therein may be functional modules included in a graphics pipeline defined by a graphics programming interface such as OpenGL or Direct3D.

[0048] Furthermore, each level of the functional module in the graphics pipeline may include one or more sub-modules, and each level of the functional module implements the function of the functional module at that level through one or more sub-modules within it. In the embodiment of the present invention, a sampling module (or sampling point) is pre-installed in each level of the functional module. For example, a sampling module is pre-installed before the first sub-module in each level of the functional module. Figure 2 , shows a schematic diagram of the structure of a certain level of functional modules in the graphics pipeline of the present invention. Figure 2 A sampling module is pre-installed before the first submodule in the functional module shown. The present invention adds a sampling module to each level of the functional module in the graphics pipeline. It is understandable that Figure 2 The functional modules shown may be any functional modules such as a geometry engine GE, a primitive engine PE, or a rendering output unit OM.

[0049] The instruction processing front end (CF) sequentially reads pending instructions from the instruction buffer and inputs them into the first-level functional module of the graphics pipeline (e.g., the geometry engine GE). These pending instructions are then executed sequentially by each level of the functional module in the graphics pipeline. These pending instructions are instructions in the instruction stream corresponding to the graphics drawing task generated by the application. In this embodiment of the present invention, sampling modules are pre-installed within each level of the functional module. When a pending instruction flows through each level of the graphics pipeline for processing, upon entering a particular level of the functional module, it first enters the sampling module within that level for identification and processing.

[0050] In an embodiment of the present invention, the instructions to be executed may be instructions defined at the graphics hardware and related graphics programming interface levels. For example, the instructions to be executed may include any of the following: a sample (Opcode 1) instruction, a DRAW instruction, a SYNC instruction, a CFGW (register write) instruction, etc.

[0051] Among them, the sampling (Opcode1) instruction is used to sample the specified event (that is, the target event), that is, to obtain the sampling value of the target event. In the process of executing the drawing instruction in the graphics pipeline, the functional modules at each level are used to perform different operations, that is, corresponding to different events. For example, the geometry engine GE is used to assemble and shade vertex tasks, so the events corresponding to the geometry engine GE can be defined as: the number of vertices, the number of primitives, and the number of vertex shader calls, etc. The primitive engine PE is used to perform rasterization and pixel shading, so the events corresponding to the primitive engine PE can be defined as: the number of clipping calls, the number of clipping-generated primitives, and the number of fragment shader calls, etc. Among them, Opcode1 in the sampling (Opcode1) instruction represents the opcode of the sampling instruction; all the opcode encoding forms described in the embodiment of the present invention can be set according to the characteristics of the instruction system.

[0052] Furthermore, the sampling instruction may include a first operand and a second operand, wherein the first operand is used to indicate a target event, and the second operand is used to indicate a target address, wherein the target address is a first memory address of a sampling value to be written into the target event.

[0053] Exemplarily, the sampling instruction may be as follows:

[0054] Opcode first operand, second operand

[0055] The opcode is used to indicate that the instruction type is a sampling instruction. The opcode can be represented by a preset keyword. For example, the opcode Opcode1 is used to indicate that the instruction type is a sampling instruction. The first operand is used to indicate the target event. For example, Operand1 is used to represent the first operand. The second operand is used to indicate the target address. For example, Operand2 is used to represent the second operand.

[0056] Exemplarily, the sampling instruction may be expressed as follows:

[0057] Opcode1 Operand1, Operand2

[0058] The instruction processing front end CF reads the to-be-executed instructions from the instruction buffer in sequence. If it is recognized that the currently read to-be-executed instruction contains the preset operation code "Opcode1", it is determined that the to-be-executed instruction is a sampling instruction.

[0059] Furthermore, the first operand Operand1 can be a vector (called an event vector), in which each bit of the event vector has a mapping relationship with the event corresponding to each level of functional module. The event vector can be in the form of binary code or hexadecimal code. The embodiment of the present invention does not limit the specific form of the event vector. It only needs to represent multiple bits. Different bits can be used to represent different events, thereby using a single vector to simultaneously represent multiple events. For example, bits 0, 1, and 2 of Operand1 correspond to three events in the geometry engine GE, respectively; bits 3, 4, and 5 correspond to three events in the primitive engine PE, respectively; and so on.

[0060] If a bit in the event vector is a preset value, it indicates that the event corresponding to that bit is the target event. For example, assuming the preset value is 1, if the value of a bit is 1, it indicates that the event corresponding to that bit needs to be sampled, that is, the event corresponding to that bit is the target event. If the value of a bit is 0, it indicates that the event corresponding to that bit does not need to be sampled, that is, the event corresponding to that bit is not the target event.

[0061] For example, the mapping relationship between each bit of the event vector Operand1 and the corresponding events of each level of functional modules is shown in Table 1.

[0062] Table 1

[0063]

[0064] As shown in Table 1, the bits of the event vector Operand1 are counted from low to high, starting from 0. The event corresponding to bit 0 is the "number of vertices", which is an event in the functional module GE. The event corresponding to bit 1 is the "number of primitives", which is an event in the functional module GE. The event corresponding to bit 2 is the "number of vertex shader calls", which is an event in the functional module GE. The event corresponding to bit 3 is the "number of clipping calls", which is an event in the functional module PE. The event corresponding to bit 4 is the "number of clipping-generated primitives", which is an event in the functional module PE. The event corresponding to bit 5 is the "number of fragment shader calls", which is an event in the functional module PE.

[0065] It should be understood that the embodiments of the present invention do not restrict the length of the event vector Operand1, nor do they restrict the events corresponding to each bit of Operand1. In the example shown in Table 1, six consecutive bits of the event vector Operand1, starting with the least significant bit, represent events corresponding to different functional modules. Each bit represents an event. Events responsible for a sampling module are placed consecutively in the event vector, and events responsible for different sampling modules are placed from lowest to highest bits in the order of the graphics pipeline. For example, in a graphics pipeline, if the first-level functional module is the geometry engine GE, then the least significant bit of Operand1 represents events corresponding to the geometry engine GE, such as bits 0, 1, and 2. If the next-level functional module is the primitive engine PE, then bits 3 and above in Operand1 represent events corresponding to the primitive engine PE, such as bits 3, 4, and 5. If the next-level functional module is the rendering output unit OM, then bits 6 and above in Operand1 represent events corresponding to the rendering output unit OM, such as bits 6, 7, and so on (not shown in Table 1), and so on.

[0066] In an example, assume a sampling instruction is as follows:

[0067] Opcode1 0x1a, 0x10012345600

[0068] Among them, 0x1a is the first operand and 0x10012345600 is the second operand. This sampling instruction is used to obtain the sampled value of the target event indicated by 0x1a and write it into the memory space with the target address 0x10012345600. The number of target events can be greater than or equal to 1. The binary representation of 0x1a is 011010, and each bit in 011010 corresponds to an event. As shown in Table 1, the event corresponding to the 0th bit is "number of vertices", which is an event in the functional module GE. Since the value of the 0th bit is 0, "number of vertices" is not a target event. The event corresponding to the 1st bit is "number of primitives", which is an event in the functional module GE. Since the value of the 1st bit is 1, "number of primitives" is a target event. Similarly, the values ​​of the 3rd and 4th bits in 011010 are 1, so "number of clipping calls" and "number of clipping generated primitives" are also target events. That is, the target events to be sampled by this sampling instruction include the following three events: primitive count, number of clipping calls, and number of clipping-generated primitives. "Primitive count" is an event in the geometry engine (GE), while "number of clipping calls" and "number of clipping-generated primitives" are events in the primitive engine (PE).

[0069] It should be noted that the embodiments of the present invention do not restrict the number or type of events in a sampling instruction. The event type can be defined in accordance with an API specification (e.g., OpenGL / Direct3D) or customized as needed. When generating a sampling instruction, the first operand in the sampling instruction, such as 0x1a, is generated based on the event to be sampled and the correspondence between the event to be sampled and the predefined event type.

[0070] Furthermore, in the embodiment of the present invention, the first operand can be in vector form, and each bit in a vector can correspond to an event, thereby, multiple events can be specified through a vector. The event types corresponding to bits at different positions can be predefined, as shown in Table 1. When generating a sampling instruction, the bit position of the event to be sampled can be determined according to Table 1, and then the corresponding first operand can be generated. The first operand uses a vector form, and multiple different types of events can be sampled using one sampling instruction. Taking Table 1 as an example, one sampling instruction can sample 6 different types of events.

[0071] Furthermore, when there are many types of events to be sampled, for example, a vector is insufficient to represent the events to be sampled, in which case the first operand can be in the form of a number. Specifically, a number corresponding to each event type can be predefined. When generating a sampling instruction, the corresponding first operand is generated based on the predefined correspondence between the event type and the number. One first operand uses one number, and one number corresponds to one type of event. If the first operand uses a number, one sampling instruction can be used to sample one type of event. Ten different types of events require 10 sampling instructions.

[0072] In a specific implementation, when the number of event types to be sampled is small and a vector is sufficient to represent them, a first operand in vector form can be used. When the number of event types to be sampled is large and a vector is insufficient to represent them, a first operand in numbered form can be used. Of course, the specific form of the first operand can also be other forms, and the present invention does not limit this.

[0073] In related technologies, the instruction processing front-end CF reads the instructions to be executed from the instruction buffer in sequence. If the currently read instruction to be executed is identified as a sampling (Opcode1) instruction, in order to avoid the situation where the previous drawing operation has not been processed and the sampling result is inaccurate, it is necessary to wait until the entire graphics pipeline is emptied. At this time, it can be ensured that the previous drawing operation has been processed and completed before executing the sampling instruction and obtaining the sampling value of the target event, which can ensure that the obtained sampling value of the target event is correct.

[0074] In an embodiment of the present invention, if the instruction processing front end CF identifies that the currently read instruction to be executed is a sampling instruction, the sampling instruction is converted into a target instruction stream and input into the functional modules of each level of the graphics pipeline for processing in sequence. The target instruction stream is used to obtain the sampling value of the target event indicated by the sampling instruction. The target instruction stream can be an instruction that can be recognized by each module in the graphics pipeline. For the target sampling module that receives the target instruction stream, if it is identified that the target event to be sampled by the target instruction stream hits the event corresponding to the functional module of this level, then after determining that the functional module of this level is empty, the sampling value of the target event is obtained and inserted into the target instruction stream to obtain an updated target instruction stream.

[0075] For example, assuming that the target event is the number of vertices drawn by the geometry engine GE, the instruction processing front end CF extracts the instruction to be executed as a sampling (Opcode1) instruction, which is then converted into a target instruction stream recognizable by the sampling module and input into the geometry engine GE. After receiving the target instruction stream, the sampling module built into the geometry engine GE recognizes that the target event to be sampled by the target instruction stream hits the event corresponding to the functional module at this level. After determining that the functional module at this level (geometry engine GE) is empty, the sampling value of the target event is obtained, that is, the sampling value of the event "number of vertices" is obtained, and inserted into the target instruction stream to obtain an updated target instruction stream. The updated target instruction stream is forwarded to the next module to pass the inserted sampling value of the target event "number of vertices" downward in the graphics pipeline, so that the sampling value can be used in subsequent steps.

[0076] The next module may be the first submodule of the functional module at this level, or the next module may be a sampling module built into the functional module at the next level, or the next module may be an instruction processing backend. For example, when the target sampling module is a sampling module in the functional module at this level, the next module refers to the first submodule of the functional module at this level. When the target sampling module is the last submodule of the functional module at this level, the next module refers to the sampling module built into the functional module at the next level. When the target sampling module is the last submodule in the functional module at the last level in the graphics pipeline, the next module refers to the instruction processing backend.

[0077] Among them, the emptying of the functional module at this level means that the functional module where the target sampling module is located has completed the operations it needs to process, so that it can be guaranteed that the sampling value of the target event obtained is obtained after the operations of the functional module at this level have been completed, so as to ensure that the correct sampling value is obtained. For example, in this example, it is necessary to obtain the number of vertices drawn by the geometry engine GE. If the sampling instruction is executed upon receiving the sampling instruction, the operation of drawing the vertices by the geometry engine GE may not have been completed at this time, and the number of vertices drawn by the geometry engine GE obtained may be inaccurate. In addition, since it is only necessary to obtain the sampling value of the target event (number of vertices) of the functional module at this level (geometry engine GE) at this time, it is only necessary to wait for the functional module at this level (geometry engine GE) to be empty, without waiting for the entire graphics pipeline to be empty. This will not affect the normal execution of other functional modules outside the geometry engine GE, can reduce unnecessary waiting, and improve the performance of the graphics pipeline.

[0078] The target sampling module obtains the sampled value of the target event and inserts it into the target instruction stream, resulting in an updated target instruction stream. The updated target instruction stream carries the sampled value of the target event in the functional module at the current level into which the target sampling module inserted it. The target sampling module forwards the updated target instruction stream to the next module, which can then continue to identify whether it needs to process the updated target instruction stream. Thus, after being converted into a target instruction stream by the instruction processing front end (CF), the sampled instruction flows through each level of the graphics pipeline and is sequentially identified and processed by the sampling modules pre-installed in each level of the functional module. If an event corresponding to the functional module at the current level is hit, the sampling module inserts the sampled value of the hit target event. After processing by the functional modules at each level of the graphics pipeline, the sampled value of the specified event for the specified module at the specified level can be obtained. Furthermore, when sampling an event corresponding to a functional module at a certain level, execution of the functional module at that level only needs to be paused to wait for the functional module at that level to be depleted, without affecting the execution of other functional modules.

[0079] Furthermore, the instruction processing front end sequentially reads instructions to be executed from the instruction buffer, and if it is identified that the instructions to be executed are not sampling instructions, the instructions to be executed are input into the functional modules of each level of the graphics pipeline for sequential processing.

[0080] In an optional embodiment of the present invention, converting the sample instruction into a target instruction stream may include:

[0081] A first instruction is generated based on the first operand, and a second instruction is generated based on the second operand, to obtain a target instruction stream consisting of the first instruction and the second instruction; the first instruction is used to transmit the target event, and the second instruction is used to transmit the target address. In this embodiment of the present invention, the graphics pipeline can be used to process the sampling instruction.

[0082] In this embodiment of the present invention, assume that the instruction processing front-end (CF) reads the instruction to be executed as "Opcode1 0x1a, 0x10012345600." The CF recognizes this as a sampling instruction and generates a first instruction based on the first operand (0x1a), and a second instruction based on the second operand (0x10012345600), resulting in a target instruction stream consisting of the first and second instructions. The first instruction is used to transmit the target event, and the second instruction is used to transmit the target address.

[0083] In this embodiment of the present invention, internal and external instructions of the graphics pipeline are distinguished. Sampled instructions are external instructions received by the graphics pipeline (e.g., from an application program). The instruction processing front end (CF) processes these external instructions and converts them into instructions to be executed by the graphics pipeline (internal instructions of the graphics pipeline), such as the first instruction and the second instruction, which are then input into the graphics pipeline for processing.

[0084] Exemplarily, the first instruction is expressed as follows:

[0085] Opcode2 first operand (such as Operand1)

[0086] The operation code Opcode2 indicates that the instruction type is a first instruction, which is used to transmit the target event indicated by the first operand. The first operand is the same as the first operand in the sampling instruction.

[0087] Exemplarily, the second instruction is expressed as follows:

[0088] Opcode3 second operand (such as Operand2)

[0089] The operation code Opcode 3 indicates that the instruction type is a second instruction, which is used to transfer the target address indicated by the second operand. The second operand is the same as the second operand in the sampling instruction.

[0090] For example, the instruction processing front end CF converts the above sample instructions into the following target instruction stream:

[0091] Opcode3 0x10012345600

[0092] Opcode2 0x1a

[0093] "Opcode2 0x1a" is the first instruction, "0x1a" is the first operand, and "Opcode2" is the opcode of the first instruction. "Opcode3 0x10012345600" is the second instruction, "0x10012345600" is the second operand, and "Opcode3" is the opcode of the second instruction. The first and second instructions can be custom instructions that can be recognized and processed by modules in the graphics pipeline. The first instruction is used to pass the target event, such as the event vector. The second instruction is used to pass the target address, that is, the starting address to be written by the sampling instruction.

[0094] Reference Figure 3 , shows a schematic flow chart of the steps of a sampling module in the present invention. Figure 3As shown, a sampling module receives the current instruction. If the current instruction is identified as the first instruction, the first instruction can carry an event vector to indicate the target event to be sampled. Therefore, after the sampling module recognizes that the first instruction has been received, it further determines whether the target event indicated by the first instruction hits the event corresponding to the functional module at this level; if it hits, it waits until the functional module at this level is emptied, obtains the sampling value of the hit target event and inserts it into the target instruction stream to obtain an updated target instruction stream, and forwards the updated target instruction stream to the next module. If the sampling module recognizes that the target event indicated by the first instruction does not hit the event corresponding to the functional module at this level after receiving the first instruction, it forwards the instruction to the next module. Figure 3 The sampling module shown can be a sampling module built into any functional module.

[0095] In a specific implementation, the sampling module built into each level of functional modules can record the mapping relationship between the event corresponding to the functional module at this level and the bit position of the event vector. The identification of the event corresponding to the target event hitting the functional module at this level may include:

[0096] The target sampling module determines whether the bit with the preset value belongs to the functional module of this level. If so, it determines that the target event hits the event corresponding to the functional module of this level.

[0097] For example, as shown in Table 1, the events corresponding to the geometry engine GE include: the number of vertices, the number of primitives, and the number of vertex shader calls, which correspond to bits 0, 1, and 2 of the event vector, respectively. The sampling module built into the geometry engine GE records this mapping relationship. The events corresponding to the primitive engine PE include: the number of clipping calls, the number of clipping-generated primitives, and the number of fragment shader calls, which correspond to bits 3, 4, and 5 of the event vector, respectively. The sampling module built into the primitive engine PE records this mapping relationship.

[0098] When the instruction processing front end CF reads the sample instruction "Opcode1 0x1a, 0x10012345600", it converts the sample instruction into the following target instruction stream:

[0099] Opcode3 0x10012345600

[0100] Opcode2 0x1a

[0101] The instruction processing front-end (CF) sends the target instruction stream to the geometry engine (GE). The sampling module (herein referred to as the target sampling module) within the geometry engine (GE) receives the target instruction stream, recognizes the first instruction, and then further determines whether the target event indicated by the first instruction matches the event corresponding to the current functional module. The target events indicated by the operand "0x1a" (i.e., the event vector "011010") of the first instruction include the number of primitives, the number of clipping calls, and the number of primitives generated by clipping. Bits 0, 1, and 2 of operand 0x1a correspond to the events of the current functional module (GE). Since the value of bit 1 of the event vector "011010" is 1, the event "number of primitives" is the target event. Since the event corresponding to bit 1 of the event vector belongs to the current functional module (GE), the target event "number of primitives" is determined to match the event corresponding to the current functional module (GE). After determining that the functional module at this level (geometry engine GE) is drained, the sampling module built into the geometry engine GE obtains the sampling value of the target event (number of primitives) and inserts it into the target instruction stream to obtain an updated target instruction stream.

[0102] For example, you can use the following custom instructions to obtain the sample value of the target event:

[0103] Opcode4 Operand3

[0104] The operation code Opcode4 indicates that the instruction type is a custom instruction for obtaining the sampled value of the target event. Operand3 is the operand of the custom instruction, which indicates the sampled value of the target event.

[0105] In an example, after inserting the sample value of the target event (number of primitives), the updated target instruction stream is obtained as follows:

[0106] Opcode3 0x10012345600

[0107] Opcode4 Number of graphics elements

[0108] Opcode2 0x1a

[0109] The Opcode4 instruction is a custom instruction that can be recognized and processed by modules in the graphics pipeline. The inserted Opcode4 instruction is used to pass the sampled value of the target event. For example, by inserting the "Opcode4 Primitive Count" instruction into the target instruction stream, the sampled value of the target event "Primitive Count" is inserted into the target instruction stream.

[0110] In an optional embodiment of the present invention, each level of the functional module of the graphics pipeline may include an event counter, and the event counter is used to record the sampling value of the event corresponding to the functional module;

[0111] The acquiring the sample value of the target event may include:

[0112] The value of the event counter corresponding to the target event in the current-level functional module is read to obtain a sampling value of the target event.

[0113] In practice, each functional module in the graphics pipeline may include several event counters. These counters correspond one-to-one with events and are used to count corresponding events. For example, the geometry engine (GE) may include a counter for maintaining the "number of primitives" event. This counter increments by 1 each time a primitive is processed. Acquiring a sampled value for an event is the process of reading the value of the corresponding event counter.

[0114] For example, the geometry engine GE includes an event counter corresponding to the "number of vertices" (e.g., counter 0), an event counter corresponding to the "number of primitives" (e.g., counter 1), and an event counter corresponding to the "number of vertex shader calls" (e.g., counter 2). The sampling module built into the geometry engine GE obtains the sampled value of the hit target event "number of primitives" by reading the value of counter 1.

[0115] In an optional embodiment of the present invention, determining that the functional modules at this level are empty may include:

[0116] Step S11, obtaining a pipeline emptying signal of the current stage; the pipeline emptying signal of the current stage is determined according to the pipeline busy signals of each submodule within the functional module of the current stage, and the value of the pipeline busy signal indicates the execution state of the corresponding module;

[0117] Step S12: If the value of the water drain signal at this stage is a preset value, it is determined that the functional module at this stage is drained.

[0118] In an embodiment of the present invention, each functional module at each level in the graphics pipeline (including its submodules) can output its own pipeline busy signal. The value of the pipeline busy signal can indicate the execution status of the corresponding module. For example, a pipeline busy signal value of 1 indicates that the corresponding module is busy (i.e., executing), indicating that the module has not yet completed the required processing operation; a pipeline busy signal value of 0 indicates that the corresponding module is not busy (i.e., execution completed), indicating that the module has completed the required processing operation, i.e., the module has been drained.

[0119] The pipeline drain signal for a functional module is determined based on the pipeline busy signals of each submodule within the functional module. In one example, the pipeline drain signal for the functional module can be the inverted version of the pipeline busy signals of all submodules within the functional module. If the value of the pipeline drain signal is a preset value (assuming the preset value is 1), the pipeline busy signals of all submodules within the functional module are all 0, indicating that all submodules within the functional module have been drained, and therefore the functional module is drained.

[0120] Reference Figure 4 , shows an example schematic diagram of obtaining the current stage water emptying signal of the present invention. Figure 4 As shown, a functional module at a certain level of the graphics pipeline (e.g., functional module GE) includes, from front to back, a sampling module and its submodules. In this embodiment of the present invention, the functional module at this level executes or operates on the pipeline busy signals of its internal submodules and then inverts them to generate a pipeline drain signal for this level. The functional module at this level sends the pipeline drain signal to the internal sampling module. If the sampling module recognizes that the value of the pipeline drain signal for this level is a preset value, it determines that the functional module at this level has been drained.

[0121] It should be noted that Figure 4 Each level of functional module may also include several event counters (not shown in the figure). The embodiment of the present invention does not limit the number and position of event counters. For example, several event counters may be set outside the sampling module, and the event counters have a one-to-one correspondence with the events. The event counters may be set inside each submodule, or outside the submodule, or at the top level of the pipeline level. Figure 5 , shows a schematic diagram of the structure of setting an event counter in a certain functional module of the present invention, and the functional module can be any functional module in the graphics pipeline. Figure 5 As shown, multiple event counters are set outside the sampling module and submodule, and the values ​​of the multiple event counters are sent to the sampling module, which can then statistically obtain the sampling values ​​of the target events in the functional modules at this level.

[0122] In an embodiment of the present invention, instructions for sampling target events, such as sampling instructions, or a target instruction stream obtained after conversion of the sampling instructions, or an updated target instruction stream obtained after processing by a sampling module, may be forwarded sequentially to each module (including the sampling modules built into each level of functional modules and each submodule of each level of functional modules) when forwarded in the graphics processor, or may be forwarded sequentially only to the sampling modules built into each level of functional modules.

[0123] For example, the sampling module built into the geometry engine (GE) inserts a sampled value of the target event "number of primitives" into the target instruction stream. After obtaining the updated target instruction stream, it forwards the updated target instruction stream to the next module. This next module can be the first submodule of the current functional module (e.g., the geometry engine (GE)), or it can be a sampling module built into the next functional module (e.g., the primitive engine (PE)).

[0124] After the sampling module within the geometry engine GE sends the updated target instruction stream to the first submodule of the current-level functional module (geometry engine GE), the first submodule recognizes that the received instruction is not the instruction it is intended to process and continues forwarding the instruction until the sampling module within the next-level functional module (graphics engine PE) receives the updated target instruction stream. Alternatively, the sampling module within the geometry engine GE directly sends the updated target instruction stream to the sampling module within the next-level functional module (graphics engine PE).

[0125] After receiving the updated target instruction stream, the sampling module built into the primitive engine (PE) recognizes the first instruction "Opcode2 0x1a" contained in the updated target instruction stream and further determines whether the target event indicated by operand "0x1a" matches the event corresponding to the current functional module (the primitive engine PE). Since the third, fourth, and fifth bits of operand "0x1a" (i.e., event vector "011010") correspond to the event of the current functional module (the primitive engine PE), and the values ​​of the third and fourth bits of "011010" are 1, the target events corresponding to the third and fourth bits match the event corresponding to the current functional module (the primitive engine PE). The hit target events include the "number of cropping calls" and the "number of primitives generated by cropping." After determining that the functional module at this level (the primitive engine PE) is drained, the sampling module built into the primitive engine PE obtains the sampling values ​​of the target events ("number of clipping calls" and "number of clipping generated primitives") and inserts them into the updated target instruction stream in sequence. The updated target instruction stream is as follows:

[0126] Opcode3 0x10012345600

[0127] Opcode4 Number of graphics elements

[0128] Opcode4 pruning call count

[0129] Opcode4 cropping generates the number of primitives

[0130] Opcode2 0x1a

[0131] In the above updated target instruction stream, after the inserted "Opcode4 Number of primitives" instruction, the "Opcode4 Number of cropping calls" instruction and the "Opcode4 Number of cropping generated primitives" instruction are inserted in sequence, which are used to pass the sampling value of the target event "Number of cropping calls" and the sampling value of the target event "Number of cropping generated primitives", respectively.

[0132] Therefore, after the target instruction stream is processed in sequence by the functional modules (built-in sampling modules) of each level of the graphics pipeline, the sampling values ​​of all target events indicated by the sampling instruction can be statistically obtained based on the target instruction stream updated by the last sampling module.

[0133] In an optional embodiment of the present invention, the graphics pipeline may further include an instruction processing backend after the last-stage functional module, and the method may further include:

[0134] After receiving the updated target instruction stream and identifying the second instruction, the instruction processing backend sequentially writes the sampled values ​​of each target event inserted into the updated target instruction stream, starting with the target address indicated by the second instruction.

[0135] In an embodiment of the present invention, the graphics pipeline may further include an instruction processing backend CB located at the tail. Figure 6 , shows a schematic diagram of the structure of a graphics pipeline of the present invention. Figure 6 As shown, the graphics pipeline includes, from front to back, a command processing front end CF, a geometry engine GE, a primitive engine PE, a rendering output unit OM, and a command processing back end CB.

[0136] In an embodiment of the present invention, the target instruction stream includes a first instruction and a second instruction. When the target instruction stream flows through the graphics pipeline, the sampling module built into the functional modules at each level identifies the first instruction therein, and when the target event indicated by the first instruction hits the event corresponding to the functional module at this level, the first instruction is processed, the sampling value of the hit target event is obtained and inserted into the target instruction stream. When the second instruction in the target instruction stream reaches the instruction processing backend CB, the instruction processing backend CB processes the second instruction when it recognizes that the second instruction has been received, and writes the sampling values ​​of each target event inserted in the updated target instruction stream in sequence with the target address indicated by the second instruction as the first address. Other modules do not process the second instruction when they receive it.

[0137] Taking the above example as an example, the updated target instruction stream received by the instruction processing backend CB is as follows:

[0138] Opcode3 0x10012345600

[0139] Opcode4 Number of graphics elements

[0140] Opcode4 pruning call count

[0141] Opcode4 cropping generates the number of primitives

[0142] Opcode2 0x1a

[0143] After the instruction processing backend CB recognizes the second instruction "Opcode3 0x10012345600", it uses the target address "0x10012345600" as the first address and writes the sampling values ​​of each target event inserted in the updated target instruction stream in sequence, that is, the sampling value of the event "number of primitives", the sampling value of the event "number of cropping calls" and the sampling value of the event "number of cropping generated primitives" are written into the memory space with the first address "0x10012345600" in sequence.

[0144] Specifically, in an embodiment of the present invention, after the instruction processing backend CB recognizes that it has received the second instruction, it can perform the following operations: update the write target address register according to the target address indicated by the second instruction; write the sampling value of the first target event inserted in the target instruction stream to the first address pointed to by the value in the target address register, and update the target address register, so that the value in the updated target address register points to the first address to be written to the next sampling value; and so on, until the sampling values ​​of all target events inserted in the target instruction stream are written. Among them, updating the target address register refers to increasing the value in the target address register by the length of the event sampling value, and the length is set according to actual needs. For example, if the sampling value of an event is stored using 64 bits, then updating the target address register means increasing the value in the target address register by 8 (bytes).

[0145] Specifically, in this example, after the instruction processing backend CB recognizes that it has received the second instruction, it updates the write target address register according to the target address "0x10012345600" indicated by the second instruction, that is, writes the target address "0x10012345600" into the target address register. First, the first target event is processed, and the sampled value of the target event "number of primitives" is written into the memory space with the first address "0x10012345600" pointed to by the value in the target address register, and the target address register is updated, and the value in the target address register is added by 8 and updated to "0x10012345608". Then the second target event is processed, and the sampled value of the target event "number of cropping calls" is written into the memory space with the first address "0x10012345608" pointed to by the value in the target address register, and the value of the target address register is updated to "0x10012345610". Next, the third target event is processed. The sampled value of the target event "Number of clipping primitives" is written to the memory space with the first address "0x10012345610" pointed to by the value in the target address register, and the target address register is updated. As a result, the memory space with the target address "0x10012345600" as the first address stores the sampled value of the target event "Number of primitives", the sampled value of the target event "Number of clipping calls", and the sampled value of the target event "Number of clipping primitives".

[0146] In an optional embodiment of the present invention, the instructions to be executed may include, in sequence: a first sampling instruction, a drawing instruction, and a second sampling instruction.

[0147] Example 1: Assume that the number of primitives processed by a drawing instruction, the number of clipping calls, and the number of clipping generated primitives need to be sampled, and the sampled values ​​are written to the memory at the target address 0x10012345670. The following instruction stream can be generated to be executed:

[0148] …

[0149] Opcode1 0x1a, 0x10012345600

[0150] DRAW

[0151] Opcode1 0x1a, 0x10012345620

[0152] …

[0153] Here, ... indicates omitted instructions.

[0154] The instruction stream shown in Example 1 includes, in sequence: a sample (Opcode1) instruction, a draw (DRAW) instruction, and a sample (Opcode1) instruction. The first Opcode1 instruction, called the first sample instruction, samples the event before the DRAW instruction (called the old event) and writes the sampled value to the memory address "0x10012345600." In the first Opcode1 instruction, 0x1a is the first operand, indicating the target event to be sampled.

[0155] The second Opcode1 instruction is used to sample the event after the DRAW instruction (called the new event) and write the sampled value to the memory space with the target address "0x10012345620".

[0156] After the execution of the above two Opcode1 instructions is completed, the sampling value of the new event can be read from the memory space with the target address 0x10012345600, and the sampling value of the old event can be read from the memory space with the target address 0x10012345600. The sampling value of the old event is subtracted from the sampling value of the new event to obtain the number of primitives processed, the number of cropping calls and the number of cropping-generated primitives in the process of the graphics pipeline executing the DRAW instructions between the two Opcode1 instructions.

[0157] In an optional embodiment of the present invention, the method may further include:

[0158] Step S21: obtaining a first sampling value obtained by the graphics pipeline executing the first sampling instruction, and obtaining a second sampling value obtained by the graphics pipeline executing the second sampling instruction;

[0159] Step S22: Subtract the first sampling value from the second sampling value to obtain a sampling value of a target event generated by the graphics pipeline executing the drawing instruction.

[0160] In Example 1, the instruction processing front-end (CF) first reads the instruction to be executed from the instruction buffer, which is the first sample instruction "Opcode1 0x1a, 0x10012345600." The aforementioned embodiment describes the specific process of the graphics pipeline of the present invention processing the first sample instruction "Opcode1 0x1a, 0x10012345600." After processing is completed, the memory space starting with the target address "0x10012345600" stores the sample values ​​of the target event "Number of primitives," the target event "Number of clipping calls," and the target event "Number of clipping generated primitives," in sequence. The sample value stored at the target address "0x10012345600" is referred to as the first sample value.

[0161] Then, the instruction processing front end CF reads the instruction to be executed from the instruction buffer as a DRAW instruction, and inputs it into the functional modules of each level of the graphics pipeline for processing in sequence.

[0162] Next, the instruction processing front-end CF reads the instruction to be executed from the instruction buffer as the second sampling instruction "Opcode1 0x1a, 0x10012345620." The processing process for the second sampling instruction is identical to that for the first sampling instruction and will not be repeated here. After the second sampling instruction flow graph pipeline is processed, the memory space starting with the target address "0x10012345620" stores the sampled values ​​of the target event "Number of primitives," the target event "Number of cropping calls," and the target event "Number of cropped generated primitives," in that order. The sampled value stored at the target address "0x10012345620" is referred to as the second sampling value.

[0163] Subtracting the first sampling value from the second sampling value can obtain the sampling value of the target event generated by the graphics pipeline executing the drawing instruction. For example, reading 8 bytes starting from the target address "0x10012345600" will obtain the first sampling value as the sampling value of the "number of primitives" before the DRAW instruction; reading 8 bytes starting from the target address "0x10012345620" will obtain the second sampling value as the sampling value of the "number of primitives" after the DRAW instruction; the subtraction of the second sampling value by the first sampling value is the number of primitives drawn by the DRAW instruction. For another example, adding 8 bytes to the target address "0x10012345600" and starting to read 8 bytes will obtain the first sampling value as the sampling value of the "number of crop calls" before the DRAW instruction; adding 8 bytes to the target address "0x10012345620" and starting to read 8 bytes will obtain the second sampling value as the sampling value of the "number of crop calls" after the DRAW instruction; the subtraction of the second sampling value by the first sampling value is the number of crop calls executed by the DRAW instruction.

[0164] The embodiment of the present invention also provides an instruction processing method, referring to Figure 7 , shows a flowchart of an embodiment of an instruction processing method of the present invention. The method is applied to a graphics processor, the graphics processor includes a graphics pipeline, and the graphics pipeline includes several levels of functional modules connected in sequence. The method may include the following steps:

[0165] Step 201: Identify whether the instruction to be executed is a sampling instruction; the sampling instruction includes a first operand for indicating a target event and a second operand for indicating a target address; the target address is the first address of a memory into which a sample value of the target event is to be written;

[0166] Step 202: If the instruction to be executed is identified as a sampling instruction, a first instruction is generated according to the first operand, and a second instruction is generated according to the second operand, to obtain a target instruction stream consisting of the first instruction and the second instruction; the target instruction stream is used to obtain a sample value of a target event indicated by the sampling instruction; the first instruction is used to transmit the target event, and the second instruction is used to transmit the target address;

[0167] Step 203: The target instruction stream is processed in sequence by the functional modules of each level of the graphics pipeline, and the sampling value based on the target event is updated after the corresponding functional module that hits the target event is drained.

[0168] This embodiment of the present invention uses a custom sampling instruction. When a to-be-executed instruction is identified as a custom sampling instruction, the sampling instruction is converted into a target instruction stream, which is then fed into the functional modules of each level of the graphics pipeline for sequential processing. The target instruction stream is used to obtain the sampled value of the target event indicated by the sampling instruction. The target instruction stream includes a first custom instruction and a second custom instruction. The first instruction is used to transmit the target event, and the second instruction is used to transmit the target address.

[0169] During the process of the target instruction stream being sequentially processed by the functional modules of each level of the graphics pipeline in the graphics processor, for the functional module currently entered by the target instruction stream, it is possible to identify whether the target event hits the event corresponding to the functional module of the current level. If it is identified that the target event hits the event corresponding to the functional module of the current level, after determining that the functional module of the current level is empty, a sample value of the target event can be obtained and inserted into the target instruction stream to obtain an updated target instruction stream; and the updated target instruction stream is forwarded backward.

[0170] As a result, as the target instruction stream passes through each level of the graphics pipeline in the graphics processor, the corresponding functional module that hits the target event will process the target instruction stream. After the functional modules at that level are exhausted, the target instruction stream is updated based on the sampled values ​​of the target event that hit it. The flow continues until the last functional module completes processing, at which point the sampled values ​​of each target event can be written to the memory space indicated by the target address. While the functional module that hits the target event is processing the target instruction stream, the execution of the functional module at that level only needs to be paused until the functional modules at that level are exhausted, without affecting the execution of other functional modules.

[0171] Among them, the emptying of the functional modules at this level means that the corresponding functional modules that hit the target event have completed the operations they need to process, thereby ensuring that the sampling value of the target event is obtained after the operations of the functional modules at this level have been executed, so as to ensure that the correct sampling value is obtained.

[0172] Furthermore, the graphics pipeline may further include an instruction processing front end before the first-level functional module, and a sampling module may be pre-installed in each functional module. Before identifying whether the instruction to be executed is a sampling instruction, the method may further include the following steps:

[0173] Step S31: the instruction processing front end sequentially reads instructions to be executed from the instruction buffer;

[0174] Step S32: After converting the sampled instruction into a target instruction stream, the sampled instruction is input into the functional modules of each level of the graphics pipeline for processing in sequence;

[0175] Step S33: For the target sampling module that receives the target instruction stream, if it is recognized that the target event hits the event corresponding to the current-level functional module, after determining that the current-level functional module is empty, the target sampling module obtains the sample value of the target event and inserts it into the target instruction stream to obtain an updated target instruction stream;

[0176] Step S34: The target sampling module forwards the updated target instruction stream to the next module.

[0177] Optionally, the first operand is an event vector, and each bit of the event vector has a mapping relationship with an event corresponding to each level of functional module, wherein the event corresponding to the bit with a preset value is the target event;

[0178] The identifying that the target event hits the event corresponding to the functional module at this level may include:

[0179] The target sampling module determines whether the bit with the preset value belongs to the functional module of this level. If so, it determines that the target event hits the event corresponding to the functional module of this level.

[0180] Optionally, the number of target events may be greater than 1, and the last-stage functional module of the graphics pipeline further includes an instruction processing backend. The method may further include:

[0181] After receiving the updated target instruction stream and identifying the second instruction, the instruction processing backend sequentially writes the sampled values ​​of each target event inserted into the updated target instruction stream, starting with the target address indicated by the second instruction.

[0182] Optionally, the instructions to be executed may include, in sequence: a first sampling instruction, a drawing instruction, and a second sampling instruction; the method may further include:

[0183] Step S41: obtaining a first sampling value obtained by the graphics pipeline executing the first sampling instruction, and obtaining a second sampling value obtained by the graphics pipeline executing the second sampling instruction;

[0184] Step S42: Subtract the first sampling value from the second sampling value to obtain a sampling value of a target event generated by the graphics pipeline executing the drawing instruction.

[0185] In summary, the present invention specifies a target event to be sampled in a sampling instruction. The instruction processing front-end (CF) then converts the sampling instruction into a target instruction stream recognizable by the sampling module. This target instruction stream is used to obtain sampled values ​​for the target event indicated by the sampling instruction. The target instruction stream is sequentially processed by each level of the graphics pipeline's functional modules (built-in sampling modules). When a sampling module built into a functional module at a certain level receives the target instruction stream and identifies that the target event to be sampled matches the event corresponding to that level's functional module, it obtains the sampled value of the hit target event and inserts it into the target instruction stream. After the target instruction stream has been processed by each level of the graphics pipeline's functional modules (built-in sampling modules), the sampled values ​​for all target events indicated by the sampling instruction are statistically obtained. This entire process eliminates the need to wait for the entire graphics pipeline to drain. When the target instruction stream reaches a sampling module, it only waits for the functional module at that level to drain, pausing execution of that functional module without affecting the execution of other functional modules. The embodiment of the present invention distributes sampling points across functional modules at all levels in the graphics pipeline, which can reduce the granularity of sampling and enable sampling instructions to be executed in designated functional modules without blocking other functional modules in the graphics pipeline. This enables a more refined event sampling process, reduces unnecessary waiting, improves the performance of the graphics pipeline, and thus improves the efficiency of GPU graphics drawing.

[0186] It should be noted that for the sake of simplicity, the method embodiments are described as a series of actions. However, those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0187] Reference Figure 8 , shows a structural block diagram of an embodiment of a graphics processor 300 of the present invention. The graphics processor 300 includes a graphics pipeline, which includes an instruction processing front end 301 and several levels of functional modules 302 sequentially connected to the instruction processing front end. A sampling module 303 is pre-installed in each level of the functional module, wherein:

[0188] The instruction processing front end 301 is used to sequentially read the instructions to be executed from the instruction buffer. If the instructions to be executed are identified as sampling instructions, the sampling instructions are converted into a target instruction stream and input into the functional modules 302 of each level of the graphics pipeline for processing in sequence. The target instruction stream is used to obtain the sampling value of the target event indicated by the sampling instruction.

[0189] The sampling module 303 is used to receive the target instruction stream. If it is identified that the target event hits the event corresponding to the functional module at this level, then after determining that the functional module at this level is empty, the sampling value of the target event is obtained and inserted into the target instruction stream to obtain an updated target instruction stream; and the updated target instruction stream is forwarded to the next module.

[0190] Optionally, the sampling instruction includes a first operand for indicating a target event and a second operand for indicating a target address; the target address is a first memory address of a sample value to be written into the target event;

[0191] The instruction processing front end is specifically used to:

[0192] A first instruction is generated according to the first operand, and a second instruction is generated according to the second operand, to obtain a target instruction stream consisting of the first instruction and the second instruction; the first instruction is used to transfer the target event, and the second instruction is used to transfer the target address.

[0193] Optionally, the first operand is an event vector, and each bit of the event vector has a mapping relationship with an event corresponding to each level of functional module, wherein the event corresponding to the bit with a preset value is the target event;

[0194] The sampling module is specifically used to:

[0195] It is determined whether the bit with the preset value belongs to the functional module of this level. If so, it is determined that the target event hits the event corresponding to the functional module of this level.

[0196] Optionally, the number of target events is greater than 1, and the last-level functional module of the graphics pipeline further includes an instruction processing backend;

[0197] The instruction processing backend is used to receive the updated target instruction stream and identify the second instruction, and then write the sampling values ​​of each target event inserted in the updated target instruction stream in sequence with the target address indicated by the second instruction as the first address.

[0198] Optionally, the instructions to be executed include, in sequence: a first sampling instruction, a drawing instruction, and a second sampling instruction; and the graphics processor further includes:

[0199] a value reading module, configured to obtain a first sampling value obtained by the graphics pipeline executing the first sampling instruction, and to obtain a second sampling value obtained by the graphics pipeline executing the second sampling instruction;

[0200] The numerical processing module is configured to subtract the first sampling value from the second sampling value to obtain a sampling value of a target event generated when the graphics pipeline executes the drawing instruction.

[0201] Optionally, each level of the functional module of the graphics pipeline includes an event counter, and the event counter is used to record the sampling value of the event corresponding to the functional module;

[0202] The sampling module is specifically used to:

[0203] The value of the event counter corresponding to the target event in the current-level functional module is read to obtain a sampling value of the target event.

[0204] Optionally, the sampling module is specifically configured to:

[0205] Obtain the pipeline emptying signal of this level; the pipeline emptying signal of this level is determined according to the pipeline busy signals of each sub-module inside the functional module of this level, and the value of the pipeline busy signal represents the execution status of the corresponding module; if the value of the pipeline emptying signal of this level is a preset value, it is determined that the functional module of this level is empty.

[0206] Reference Figure 9 , shows a structural block diagram of an embodiment of a graphics processor 400 of the present invention, wherein the graphics processor 400 includes a graphics pipeline, which includes an instruction recognition module 4011, an instruction conversion module 4012, and several levels of functional modules 402 sequentially connected to the instruction conversion module;

[0207] The instruction identification module 4011 is used to identify whether the instruction to be executed is a sampling instruction; the sampling instruction includes a first operand for indicating a target event and a second operand for indicating a target address; the target address is the first memory address of the sample value to be written into the target event;

[0208] an instruction conversion module 4012 configured to, if the instruction to be executed is identified as a sampling instruction, generate a first instruction based on the first operand and generate a second instruction based on the second operand, thereby obtaining a target instruction stream consisting of the first and second instructions; the target instruction stream is configured to obtain a sample value of a target event indicated by the sampling instruction; the first instruction is configured to transmit the target event, and the second instruction is configured to transmit the target address;

[0209] The functional module 402 is configured to process the target instruction stream passing through, and update the target instruction stream based on the sampled value of the target event after the corresponding functional module hitting the target event is drained.

[0210] Optionally, the graphics pipeline further includes an instruction processing front end before the first-level functional module, and the instruction processing front end includes: an instruction reading module, the instruction recognition module and the instruction conversion module in sequence; a sampling module is pre-installed in each level of the functional module;

[0211] The instruction reading module is used to read the instructions to be executed from the instruction buffer in sequence and input them into the instruction recognition module;

[0212] The instruction conversion module is further configured to, after converting the sampled instruction into a target instruction stream, input the target instruction stream into the first-stage functional module, so that the target instruction stream is processed sequentially by the functional modules of each stage of the graphics pipeline;

[0213] The sampling module is used to receive the target instruction stream. If it is identified that the target event hits the event corresponding to the functional module at this level, then after determining that the functional module at this level is empty, the sampling value of the target event is obtained and inserted into the target instruction stream to obtain an updated target instruction stream; and the updated target instruction stream is forwarded to the next module.

[0214] Optionally, the first operand is an event vector, and each bit of the event vector has a mapping relationship with an event corresponding to each level of functional module, wherein the event corresponding to the bit with a preset value is the target event;

[0215] The sampling module is specifically used to:

[0216] It is determined whether the bit with the preset value belongs to the functional module of this level. If so, it is determined that the target event hits the event corresponding to the functional module of this level.

[0217] Optionally, the number of target events is greater than 1, and the last-level functional module of the graphics pipeline further includes an instruction processing backend;

[0218] The instruction processing backend is used to receive the updated target instruction stream and identify the second instruction, and then write the sampling values ​​of each target event inserted in the updated target instruction stream in sequence with the target address indicated by the second instruction as the first address.

[0219] Optionally, the instructions to be executed include, in sequence: a first sampling instruction, a drawing instruction, and a second sampling instruction; and the graphics processor further includes:

[0220] a value reading module, configured to obtain a first sampling value obtained by the graphics pipeline executing the first sampling instruction, and to obtain a second sampling value obtained by the graphics pipeline executing the second sampling instruction;

[0221] The numerical processing module is configured to subtract the first sampling value from the second sampling value to obtain a sampling value of a target event generated when the graphics pipeline executes the drawing instruction.

[0222] In this embodiment of the present invention, a sampling module is pre-installed within each functional module level of the graphics pipeline. By specifying the target event to be sampled in a sampling instruction, the instruction processing front-end (CF) converts the sampling instruction into a target instruction stream recognizable by the sampling module. This target instruction stream is used to obtain the sampled value of the target event indicated by the sampling instruction. The target instruction stream is sequentially processed by each functional module (built-in sampling module) at each level of the graphics pipeline. When the built-in sampling module of a functional module at a certain level receives the target instruction stream and identifies that the target event to be sampled matches the event corresponding to the functional module at that level, it obtains the sampled value of the hit target event and inserts it into the target instruction stream. After the target instruction stream has been processed by each functional module (built-in sampling module) at each level of the graphics pipeline, the sampled values ​​of all target events indicated by the sampling instruction are statistically calculated. This entire process does not require waiting for the entire graphics pipeline to drain. When the target instruction stream reaches a sampling module, it only waits for the functional module at that level to drain, pausing the execution of that functional module without affecting the execution of other functional modules. The embodiment of the present invention distributes sampling points across functional modules at all levels in the graphics pipeline, which can reduce the granularity of sampling and enable sampling instructions to be executed in designated functional modules without blocking other functional modules in the graphics pipeline. This enables a more refined event sampling process, reduces unnecessary waiting, improves the performance of the graphics pipeline, and thus improves the efficiency of GPU graphics drawing.

[0223] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0224] Reference Figure 10 , is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Figure 10 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the steps of the graphics pipeline sampling method of the aforementioned embodiment.

[0225] An embodiment of the present invention provides a non-transitory computer-readable storage medium. When instructions in the storage medium are executed by a program or processor of a terminal, the terminal is enabled to perform the steps of the graphics pipeline sampling method of the aforementioned embodiment.

[0226] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0227] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, apparatus, or computer program products. Thus, embodiments of the present invention may take the form of a fully hardware embodiment, a fully software embodiment, or an embodiment combining software and hardware. Furthermore, embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0228] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0229] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0230] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 a process or multiple processes and / or boxes Figure 1The steps for the function specified in one or more boxes.

[0231] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0232] Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A graphics pipeline sampling method, characterized in that: The method is applied to a graphics processor, the graphics processor including a graphics pipeline, the graphics pipeline including an instruction processing front end and several levels of functional modules sequentially connected to the instruction processing front end, each level of the functional module being pre-installed with a sampling module, the sampling module being located before the first submodule in each level of the functional module, and comprising: The instruction processing front end sequentially reads instructions to be executed from the instruction buffer. If the instructions to be executed are identified as sampling instructions, the sampling instructions are converted into a target instruction stream and input into the functional modules of each level of the graphics pipeline for sequential processing. The target instruction stream is used to obtain a sampling value of a target event indicated by the sampling instruction. For the target sampling module that receives the target instruction stream, if it is recognized that the target event hits the event corresponding to the current-level functional module, after determining that the current-level functional module is empty, the sampling value of the target event is obtained and inserted into the target instruction stream to obtain an updated target instruction stream; The target sampling module forwards the updated target instruction stream to the next module.

2. The method according to claim 1, characterized in that The sampling instruction includes a first operand for indicating a target event and a second operand for indicating a target address; the target address is the first address of a memory into which the sample value of the target event is to be written; Converting the sampled instruction into a target instruction stream comprises: generating a first instruction according to the first operand and generating a second instruction according to the second operand, to obtain a target instruction stream consisting of the first instruction and the second instruction; The first instruction is used to transfer the target event, and the second instruction is used to transfer the target address.

3. The method according to claim 2, characterized in that The first operand is an event vector, and each bit of the event vector has a mapping relationship with the event corresponding to each level of functional module, wherein the event corresponding to the bit with the preset value is the target event; The identifying that the target event hits the event corresponding to the functional module at this level includes: The target sampling module determines whether the bit with the preset value belongs to the functional module of this level. If so, it determines that the target event hits the event corresponding to the functional module of this level.

4. The method according to claim 2, characterized in that The number of target events is greater than 1, the graphics pipeline further includes an instruction processing backend after the last level functional module, and the method further includes: After receiving the updated target instruction stream and identifying the second instruction, the instruction processing backend sequentially writes the sampled values ​​of each target event inserted into the updated target instruction stream, starting with the target address indicated by the second instruction.

5. The method according to any one of claims 1 to 4, characterized in that The instructions to be executed include, in sequence: a first sampling instruction, a drawing instruction, and a second sampling instruction; the method further includes: Obtaining a first sampling value obtained by the graphics pipeline executing the first sampling instruction, and obtaining a second sampling value obtained by the graphics pipeline executing the second sampling instruction; The first sampling value is subtracted from the second sampling value to obtain a sampling value of a target event generated by the graphics pipeline executing the drawing instruction.

6. The method according to any one of claims 1 to 4, characterized in that Each level of the functional module of the graphics pipeline includes an event counter, and the event counter is used to record the sampling value of the event corresponding to the functional module; The acquiring the sampling value of the target event includes: The value of the event counter corresponding to the target event in the current-level functional module is read to obtain a sampling value of the target event.

7. The method according to any one of claims 1 to 4, characterized in that Determining that the functional modules at this level are empty includes: Obtaining a pipeline emptying signal of this level; the pipeline emptying signal of this level is determined according to pipeline busy signals of each submodule within the functional module of this level, and the value of the pipeline busy signal indicates the execution state of the corresponding module; If the value of the water drain signal at this stage is a preset value, it is determined that the functional module at this stage is drained.

8. A method for processing an instruction, characterized in that: The method is applied to a graphics processor, the graphics processor including a graphics pipeline, the graphics pipeline including several levels of functional modules connected in sequence, each level of the functional module having a sampling module pre-installed therein, the sampling module being located before the first submodule in each level of the functional module, and comprising: Identifying whether the instruction to be executed is a sampling instruction; the sampling instruction includes a first operand for indicating a target event and a second operand for indicating a target address; the target address is the first memory address of the sampling value of the target event to be written; If the instruction to be executed is identified as a sampling instruction, a first instruction is generated according to the first operand, and a second instruction is generated according to the second operand, to obtain a target instruction stream consisting of the first instruction and the second instruction; the target instruction stream is used to obtain a sample value of a target event indicated by the sampling instruction; the first instruction is used to transmit the target event, and the second instruction is used to transmit the target address; The target instruction stream is processed in sequence by the functional modules of each level of the graphics pipeline. The sampling modules in the functional modules of each level identify whether the target event hits the event corresponding to the functional module of this level, and the sampling value based on the target event is updated after the corresponding functional module that hits the target event is emptied.

9. The method according to claim 8, characterized in that The graphics pipeline also includes an instruction processing front end before the first-level functional module, and a sampling module is pre-installed in each level of the functional module; Before identifying whether the instruction to be executed is a sampling instruction, the method further includes: The instruction processing front end sequentially reads instructions to be executed from the instruction buffer; After converting the sampled instructions into a target instruction stream, the sampled instructions are input into the functional modules of each level of the graphics pipeline for processing in sequence; For the target sampling module that receives the target instruction stream, if it is recognized that the target event hits the event corresponding to the current-level functional module, after determining that the current-level functional module is empty, the sampling value of the target event is obtained and inserted into the target instruction stream to obtain an updated target instruction stream; The target sampling module forwards the updated target instruction stream to the next module.

10. The method according to claim 9, characterized in that The first operand is an event vector, and each bit of the event vector has a mapping relationship with the event corresponding to each level of functional module, wherein the event corresponding to the bit with the preset value is the target event; The identifying that the target event hits the event corresponding to the functional module at this level includes: The target sampling module determines whether the bit with the preset value belongs to the functional module of this level. If so, it determines that the target event hits the event corresponding to the functional module of this level.

11. The method according to claim 9, characterized in that The number of target events is greater than 1, the graphics pipeline further includes an instruction processing backend after the last level functional module, and the method further includes: After receiving the updated target instruction stream and identifying the second instruction, the instruction processing backend sequentially writes the sampled values ​​of each target event inserted into the updated target instruction stream, starting with the target address indicated by the second instruction.

12. The method according to any one of claims 8 to 11, characterized in that The instructions to be executed include, in sequence: a first sampling instruction, a drawing instruction, and a second sampling instruction; the method further includes: Obtaining a first sampling value obtained by the graphics pipeline executing the first sampling instruction, and obtaining a second sampling value obtained by the graphics pipeline executing the second sampling instruction; The first sampling value is subtracted from the second sampling value to obtain a sampling value of a target event generated by the graphics pipeline executing the drawing instruction.

13. A graphics processor, characterized in that: The graphics processor includes a graphics pipeline, which includes an instruction processing front end and several levels of functional modules sequentially connected to the instruction processing front end. A sampling module is pre-installed in each level of the functional module. The sampling module is located before the first submodule in each level of the functional module, wherein: The instruction processing front end is used to sequentially read the instructions to be executed from the instruction buffer. If the instructions to be executed are identified as sampling instructions, the sampling instructions are converted into a target instruction stream and input into the functional modules of each level of the graphics pipeline for sequential processing; the target instruction stream is used to obtain the sampling value of the target event indicated by the sampling instruction; The sampling module is used to receive the target instruction stream. If it is identified that the target event hits the event corresponding to the functional module at this level, then after determining that the functional module at this level is empty, the sampling value of the target event is obtained and inserted into the target instruction stream to obtain an updated target instruction stream; and the updated target instruction stream is forwarded to the next module.

14. The graphics processor according to claim 13, wherein: The sampling instruction includes a first operand for indicating a target event and a second operand for indicating a target address; the target address is the first address of a memory into which the sample value of the target event is to be written; The instruction processing front end is specifically used to: A first instruction is generated according to the first operand, and a second instruction is generated according to the second operand, to obtain a target instruction stream consisting of the first instruction and the second instruction; the first instruction is used to transfer the target event, and the second instruction is used to transfer the target address.

15. The graphics processor according to claim 14, wherein: The first operand is an event vector, and each bit of the event vector has a mapping relationship with the event corresponding to each level of functional module, wherein the event corresponding to the bit with the preset value is the target event; The sampling module is specifically used to: It is determined whether the bit with the preset value belongs to the functional module of this level. If so, it is determined that the target event hits the event corresponding to the functional module of this level.

16. The graphics processor according to claim 14, wherein: The number of target events is greater than 1, and the last level functional module of the graphics pipeline further includes an instruction processing backend; The instruction processing backend is used to receive the updated target instruction stream and identify the second instruction, and then write the sampling values ​​of each target event inserted in the updated target instruction stream in sequence with the target address indicated by the second instruction as the first address.

17. The graphics processor according to any one of claims 13 to 16, characterized in that: The instructions to be executed include, in sequence: a first sampling instruction, a drawing instruction, and a second sampling instruction; the graphics processor also includes: a value reading module, configured to obtain a first sampling value obtained by the graphics pipeline executing the first sampling instruction, and to obtain a second sampling value obtained by the graphics pipeline executing the second sampling instruction; The numerical processing module is configured to subtract the first sampling value from the second sampling value to obtain a sampling value of a target event generated when the graphics pipeline executes the drawing instruction.

18. The graphics processor according to any one of claims 13 to 16, characterized in that: Each level of the functional module of the graphics pipeline includes an event counter, and the event counter is used to record the sampling value of the event corresponding to the functional module; The sampling module is specifically used to: The value of the event counter corresponding to the target event in the current-level functional module is read to obtain a sampling value of the target event.

19. The graphics processor according to any one of claims 13 to 16, characterized in that: The sampling module is specifically used to: Obtain the pipeline emptying signal of this level; the pipeline emptying signal of this level is determined according to the pipeline busy signals of each sub-module inside the functional module of this level, and the value of the pipeline busy signal represents the execution status of the corresponding module; if the value of the pipeline emptying signal of this level is a preset value, it is determined that the functional module of this level is empty.

20. A graphics processor, characterized in that: The graphics processor includes a graphics pipeline, which includes an instruction recognition module, an instruction conversion module, and several levels of functional modules sequentially connected to the instruction conversion module. A sampling module is pre-installed in each level of the functional module, and the sampling module is located before the first submodule in each level of the functional module. The instruction recognition module is used to identify whether the instruction to be executed is a sampling instruction; the sampling instruction includes a first operand for indicating a target event and a second operand for indicating a target address; the target address is the first memory address of the sampling value to be written into the target event; The instruction conversion module is configured to, if the instruction to be executed is identified as a sampling instruction, generate a first instruction according to the first operand and generate a second instruction according to the second operand, thereby obtaining a target instruction stream consisting of the first instruction and the second instruction; the target instruction stream is used to obtain a sampling value of a target event indicated by the sampling instruction; The first instruction is used to transmit the target event, and the second instruction is used to transmit the target address; The functional module is used to process the target instruction stream passing through, identify whether the target event hits the event corresponding to the functional module at this level through the sampling modules in the functional modules at each level, and update the target instruction stream based on the sampling value of the target event after the corresponding functional module that hits the target event is emptied.

21. The graphics processor according to claim 20, wherein: The graphics pipeline also includes an instruction processing front end before the first-level functional module, and the instruction processing front end includes the instruction recognition module, the instruction conversion module and the instruction reading module; a sampling module is pre-installed in each level of the functional module; The instruction reading module is used to read the instructions to be executed from the instruction buffer in sequence and input them into the instruction recognition module; The instruction conversion module is further configured to, after converting the sampled instruction into a target instruction stream, input the target instruction stream into the first-stage functional module, so that the target instruction stream is processed sequentially by the functional modules of each stage of the graphics pipeline; The sampling module is used to receive the target instruction stream. If it is identified that the target event hits the event corresponding to the functional module at this level, then after determining that the functional module at this level is empty, the sampling value of the target event is obtained and inserted into the target instruction stream to obtain an updated target instruction stream; and the updated target instruction stream is forwarded to the next module.

22. The graphics processor according to claim 21, wherein: The first operand is an event vector, and each bit of the event vector has a mapping relationship with the event corresponding to each level of functional module, wherein the event corresponding to the bit with the preset value is the target event; The sampling module is specifically used to: It is determined whether the bit with the preset value belongs to the functional module of this level. If so, it is determined that the target event hits the event corresponding to the functional module of this level.

23. The graphics processor according to claim 21, wherein: The number of target events is greater than 1, and the last level functional module of the graphics pipeline further includes an instruction processing backend; The instruction processing backend is used to receive the updated target instruction stream and identify the second instruction, and then write the sampling values ​​of each target event inserted in the updated target instruction stream in sequence with the target address indicated by the second instruction as the first address.

24. The graphics processor according to any one of claims 20 to 23, characterized in that: The instructions to be executed include, in sequence: a first sampling instruction, a drawing instruction, and a second sampling instruction; the graphics processor also includes: a value reading module, configured to obtain a first sampling value obtained by the graphics pipeline executing the first sampling instruction, and to obtain a second sampling value obtained by the graphics pipeline executing the second sampling instruction; The numerical processing module is configured to subtract the first sampling value from the second sampling value to obtain a sampling value of a target event generated when the graphics pipeline executes the drawing instruction.

25. An electronic device, characterized in that: include: A processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other via the communication bus; The memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the steps of the graphics pipeline sampling method according to any one of claims 1 to 7 or the steps of the instruction processing method according to any one of claims 8 to 12.

26. A readable storage medium, characterized in that The readable storage medium stores a program or instruction, and when the program or instruction is executed by the processor, the steps of the graphics pipeline sampling method according to any one of claims 1 to 7 or the steps of the instruction processing method according to any one of claims 8 to 12 are implemented.

27. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the graphics pipeline sampling method according to any one of claims 1 to 7 or the steps of the instruction processing method according to any one of claims 8 to 12 are implemented.

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