A method and device for identifying a wafer defect pattern

Abstract

An embodiment of the present invention provides a method and device for identifying a wafer defect pattern. The method includes performing point cloud conversion on a wafer map of a wafer to be identified to obtain an original point cloud set of the wafer to be identified; performing normalization processing on each point cloud in the original point cloud set to obtain a normalized target point cloud set; constructing a point cloud feature map of the wafer to be identified according to the target point cloud set; and determining an identification result of the defect pattern of the wafer to be identified according to the point cloud feature map and a pre-constructed classification network model. By using this method, the original information and geometric characteristics of the wafer map are fundamentally retained based on the point cloud normalization method, and at the same time, the problem of information loss or introduction of false information during the process of unifying the image size is solved, which is more suitable for the defect pattern identification task of multi-size wafer maps. Compared with the traditional image normalization method, it can provide a more stable and real feature representation, and improve the accuracy of wafer defect pattern identification.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and in particular, to a method and device for identifying wafer defect patterns. Background Art

[0002] With the continuous progress of semiconductor manufacturing technology, the integration and complexity of chips have increased year by year, which also puts higher requirements on chip manufacturing processes. This complexity and high integration are not only reflected in chip design but also pose more stringent technical requirements for wafer processing, which is the basis of chips. During wafer processing, various defects may occur, and these defects will affect the product yield and manufacturing cost. As a two-dimensional image representing the state of chips in a wafer, a wafer map can effectively help analyze whether there are defect patterns in the wafer. Each defect is usually related to specific process problems. Wafer defect patterns can not only track abnormalities in production but also provide an important basis for process optimization. Therefore, the identification of wafer map defect patterns has become a key task in semiconductor production.

[0003] Currently, for methods of identifying semiconductor wafer defect patterns, whether traditional machine learning algorithms or deep learning-based algorithms, essentially directly identify through this two-dimensional image of the wafer map. These image-based methods regard the wafer map and the chips therein as a two-dimensional single-channel image, and each pixel represents the state of a chip. However, in actual production, there may be significant differences in the resolution and shape of wafer maps of different chips. To facilitate the unified processing of a large amount of data, the resolution of the wafer map is usually normalized. This approach may lose some information or introduce inaccurate information. Due to the limitations of normalizing the resolution of the wafer map, when the resolution of the original wafer map differs significantly from the normalized resolution, it may lead to a significant decline in the recognition effect. Summary of the Invention

[0004] The present invention provides a method and device for identifying wafer defect patterns, which can provide a more stable and real feature representation compared with traditional image normalization methods, and improve the accuracy of wafer defect pattern recognition.

[0005] In a first aspect, an embodiment of the present invention provides a method for identifying wafer defect patterns, including:

[0006] Performing point cloud conversion on the wafer map of the wafer to be identified to obtain the original point cloud set of the wafer to be identified;

[0007] Performing normalization processing on each point cloud in the original point cloud set to obtain a normalized target point cloud set;

[0008] Constructing a point cloud feature map of the wafer to be identified according to the target point cloud set;

[0009] Determine the defect mode recognition result of the wafer to be recognized according to the point cloud feature map and the pre-constructed classification network model.

[0010] In a second aspect, an embodiment of the present invention provides a device for recognizing a wafer defect mode, including:

[0011] A point cloud conversion module, configured to perform point cloud conversion on the wafer map of the wafer to be recognized to obtain the original point cloud set of the wafer to be recognized;

[0012] A normalization module, configured to perform normalization processing on each point cloud in the original point cloud set to obtain a normalized target point cloud set;

[0013] A feature extraction module, configured to construct a point cloud feature map of the wafer to be recognized according to the target point cloud set;

[0014] A result determination module, configured to determine the defect mode recognition result of the wafer to be recognized according to the point cloud feature map and the pre-constructed classification network model.

[0015] An embodiment of the present invention provides a method and device for recognizing a wafer defect mode. The method includes: first, performing point cloud conversion on the wafer map of the wafer to be recognized to obtain the original point cloud set of the wafer to be recognized; second, performing normalization processing on each point cloud in the original point cloud set to obtain a normalized target point cloud set; then, constructing a point cloud feature map of the wafer to be recognized according to the target point cloud set; finally, determining the defect mode recognition result of the wafer to be recognized according to the point cloud feature map and the pre-constructed classification network model. In the above technical solution, the wafer map of the wafer to be recognized is first converted into a point cloud, and then normalized based on the point cloud. The normalization method based on the point cloud fundamentally retains the original information and geometric characteristics of the wafer map, and at the same time solves the problem of information loss or introduction of false information during the process of unifying the size of the image, and is more suitable for the defect mode recognition task of wafers of multiple sizes. Compared with the traditional image normalization method, it can provide a more stable and real feature representation, and improve the accuracy of wafer defect mode recognition.

[0016] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0018] Figure 1 It is a schematic flowchart of a method for identifying a wafer defect pattern provided in the first embodiment of the present invention;

[0019] Figure 2 It is a schematic flowchart of another method for identifying a wafer defect pattern provided in the second embodiment of the present invention;

[0020] Figure 3 It is a schematic structural diagram of a device for identifying a wafer defect pattern provided in the third embodiment of the present invention;

[0021] Figure 4 It is a schematic structural diagram of an electronic device provided in the fourth embodiment of the present invention. Detailed implementation manners

[0022] In order to enable those skilled in the art to better understand the solution of the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0023] It should be noted that the terms "original", "target", etc. in the specification and claims of the present invention and the above drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order different from those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those clearly listed steps or units, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0024] It should be clear that automated methods based on image processing and machine learning are gradually emerging, such as defect pattern recognition through texture analysis, morphological processing, and classification algorithms. However, these methods usually rely on manually designed features and are difficult to adapt to the diversity and complexity of the actual chip manufacturing scenario. Deep learning techniques, especially methods based on convolutional neural networks and attention mechanisms, bring new opportunities for wafer defect pattern recognition, capable of automatically extracting defect features and significantly improving the recognition accuracy. At the same time, methods based on generative adversarial networks and data augmentation are also applied to handle compound defects and class imbalance problems, and contrastive learning has also achieved good results in defect pattern recognition of small-sample wafer images.

[0025] Currently, methods for semiconductor wafer defect pattern recognition, whether traditional machine learning algorithms or deep learning-based algorithms, essentially directly recognize through the two-dimensional image of the wafer map. These image-based methods regard the wafer map and the chips in it as a two-dimensional single-channel image, and each pixel represents the state of a chip. However, in actual production, there may be significant differences in the resolution and shape of wafer maps for different chips. For example, if the chip size is large, the resolution of the wafer map is low; if the chip size is small, the resolution of the wafer map is high; if the aspect ratio of the chip is large, the aspect ratio of the wafer map will also be large. To facilitate unified processing of a large amount of data, the resolution of the wafer map is usually normalized. A common approach is to unify wafer maps with different resolutions to the same resolution (e.g., 224×224) through methods such as interpolation.

[0026] However, this approach may lose some information or introduce inaccurate information. When the resolution of the original wafer map needs to be reduced, some chip data will inevitably be lost; when the resolution of the original wafer map is small and needs to be enlarged, virtual pixels will be added, and these virtual pixels do not represent actual existing chips. Due to the limitations of normalizing the resolution of the wafer map, when the difference between the resolution of the original wafer map and the normalized resolution is large, it may lead to a significant decline in the recognition effect. More intuitively, in the case where the difference between the resolution of the original wafer map and the normalized resolution is large, the recognition effect is more likely to be worse. Therefore, there is an urgent need for a method to solve the problem of poor recognition effect caused by excessive differences in wafer map resolution.

[0027] Embodiment 1

[0028] Figure 1 It is a schematic flowchart of a method for recognizing wafer defect patterns provided in Embodiment 1 of the present invention. This method is applicable to the situation of recognizing wafer defect patterns. This method can be executed by a device for recognizing wafer defect patterns, and this device can be implemented in the form of hardware and / or software and can be configured in an electronic device. As Figure 1As shown in the figure, the method for identifying the wafer defect mode provided in the first embodiment may specifically include the following steps:

[0029] S101. Perform point cloud conversion on the wafer map of the wafer to be identified to obtain the original point cloud set of the wafer to be identified.

[0030] In this embodiment, the wafer map can be specifically understood as a two-dimensional image representing the chip state in the wafer. A two-dimensional wafer map I is expressed as: , where i and j represent the row and column indices of the pixel, represents the gray value of the pixel, and H and respectively represent the height and width of the wafer map. Each pixel in the wafer map represents a chip, and the pixel gray value represents the state of this chip. There are three states in total: 0 indicates that there is no chip at this position, 1 indicates that there is a chip at this position and it passes the test, and 2 indicates that there is a chip at this position but it fails the test. The area composed of pixels with values of 1 and 2 usually presents a circular or elliptical shape.

[0031] In the prior art, the defect mode is directly identified through this two-dimensional image of the wafer map. The large difference between the original resolution and the normalized resolution of the wafer map will lead to the problem of the decline in the defect mode recognition effect. Therefore, it is necessary to ensure how to solve the problem of the decline in the wafer defect mode recognition effect caused by the large difference in the wafer map resolution without losing the original wafer map information and without introducing additional false information, so as to improve the accuracy and robustness of the wafer defect mode recognition. Considering that the point cloud is discretely distributed in space, while the image is densely distributed in space. This discrete distribution characteristic makes it possible that when normalizing wafer maps of different sizes, the point cloud method will not introduce additional information or lose any existing information. Therefore, using the point cloud for normalization can retain the characteristics of the original data to the greatest extent.

[0032] Based on the above description, in this embodiment, perform point cloud conversion on the wafer map of the wafer to be identified, convert each pixel included in the wafer map into a point cloud respectively, and obtain the point cloud set of the wafer to be identified, denoted as the original point cloud set. Exemplarily, the coordinates of each pixel in the wafer map can be converted into point cloud coordinates in the Cartesian coordinate system, and the chip state of each chip can be used as the value of the point cloud, so as to obtain the point cloud in the Cartesian coordinate system. Or, each pixel in the wafer map can be converted into a point cloud in the polar coordinate system.

[0033] S102. Perform normalization processing on each point cloud in the original point cloud set to obtain the normalized target point cloud set.

[0034] In this embodiment, since the sizes of the point cloud contours converted from different wafer maps are different, it is necessary to normalize the point clouds in the original point cloud set. Normalizing the point clouds means changing the coordinates of all points in the original point cloud set proportionally. Specifically, each point cloud in the original point cloud set is normalized, and the normalized point cloud set is denoted as the target point cloud set.

[0035] S103. Construct a point cloud feature map of the wafer to be recognized according to the target point cloud set.

[0036] In this embodiment, feature extraction is performed on the point clouds in the target point cloud set to construct a point cloud feature map of the wafer to be recognized. In this embodiment, the point clouds in the target point cloud set are divided into regions, and the purpose is to more effectively extract local features. According to the manual experience of wafer defect pattern recognition, in many cases, the defect pattern of a wafer can be determined by judging a specific region without comprehensively analyzing the entire wafer. Dividing the point clouds in the target point cloud set into regions can be divided into multiple regions denoted as point cloud regions.

[0037] Continuing from the above description, after dividing the point clouds into each point cloud region, feature extraction can be performed based on the statistical situation of the tested chips and untested chips included in the point cloud region. It can also be to obtain a feature map by performing some other feature extraction operations on the points within the point cloud region. Since many defect patterns can be judged only according to the chips that have not passed the test, the data of the untested chips can be retained for feature extraction. It is equivalent to constructing a point cloud feature map of the wafer to be recognized according to the chip status of each chip included in each point cloud region.

[0038] S104. Determine the defect pattern recognition result of the wafer to be recognized according to the point cloud feature map and the pre-constructed classification network model.

[0039] Among them, the classification network model can be specifically understood as a model for recognizing the defect pattern of the wafer to be recognized. Its input is the point cloud feature map, and the output is the defect pattern recognition result. In this embodiment, the obtained point cloud feature map is input into the classification network model for classification and recognition of the wafer defect pattern. As a way of recognizing the defect pattern of a wafer, the point cloud feature map can be directly input into a classification network model, and then the classification result is directly output, denoted as the defect pattern recognition result of the wafer to be recognized. For example, the classification network model can adopt a deep residual network (ResNet50) or a convolutional neural network (DenseNet121), etc., which is not specifically limited here. Since there may be multiple different defect patterns in the same wafer, preferably a network for multi-label classification tasks is used. After experimental verification, the effect of this method is better than directly inputting the wafer map into the same network. It should be noted that there may be one or more defect patterns in the wafer to be recognized.

[0040] In the above technical solution, first, the wafer map of the wafer to be recognized is converted into a point cloud, and then normalization processing is performed based on the point cloud. The normalization method based on the point cloud fundamentally preserves the original information and geometric characteristics of the wafer map, and at the same time solves the problem of information loss or introduction of false information during the process of unifying the size of the image, and is more suitable for the defect pattern recognition task of wafers of multiple sizes. Compared with the traditional image normalization method, it can provide a more stable and real feature representation, and improve the accuracy of wafer defect pattern recognition.

[0041] As an alternative embodiment of the embodiment of the present invention, on the basis of the above embodiment, after determining the defect pattern recognition result of the wafer to be recognized, the method may further include: performing post-processing on the defect pattern recognition result to obtain a verified defect pattern recognition result.

[0042] In this embodiment, after performing pattern recognition on the point cloud feature map based on the classification network model to obtain the defect pattern recognition result, the defect pattern recognition result can be further verified based on the characteristics presented by different defect patterns on the wafer map to determine whether the recognition result is correct, and a verified defect pattern recognition result is obtained.

[0043] As a specific implementation manner, the step of performing post-processing on the defect pattern recognition result to obtain a verified defect pattern recognition result may be optimized to include:

[0044] 1) If the defect pattern recognition result includes at least one of edge location defect (Edge-Loc), edge ring defect (Edge-Ring), and local defect (Loc), for each defect, a first maximum connected domain is respectively determined according to the set first connection rule;

[0045] 2) For the local defect, if the number of consecutive pixels included in the first maximum connected domain is greater than the first quantity threshold, it is determined that the wafer to be recognized includes the local defect as the verified defect pattern recognition result;

[0046] 3) For the edge location defect, if the number of consecutive pixels included in the first maximum connected domain adjacent to the edge of the wafer to be recognized is greater than the first quantity threshold, it is determined that the wafer to be recognized includes the edge location defect as the verified defect pattern recognition result;

[0047] 4) For the edge ring defect, if the number of consecutive pixels included in the first maximum connected domain adjacent to the edge of the wafer to be recognized is greater than the second quantity threshold, it is determined that the wafer to be recognized includes the edge ring defect as the verified defect pattern recognition result;

[0048] Specifically, if the defect mode recognition result includes at least one of edge position defects, edge ring defects, and local defects, the largest connected region of the wafer map can be determined according to the set first connectivity rule. The first connectivity rule can be the eight-connectivity rule. An eight-connected region means that starting from each pixel in the region, through the combination of movements in eight directions, namely up, down, left, right, upper left, upper right, lower left, and lower right, any pixel in the region can be reached without going beyond the region.

[0049] In this embodiment, post-recognition can be performed simultaneously for each defect included in the defect mode recognition result. For local defects, if the number of consecutive pixels included in the first largest connected region of the wafer map is greater than the first quantity threshold, it is determined that the wafer to be recognized includes local defects as the verified defect mode recognition result.

[0050] For edge ring defects and edge position defects, if it is detected that there are not enough consecutive pixels representing failed chips at the boundary of the original wafer map, it is considered that there are actually no such two types of defects. For edge position defects, if the number of consecutive pixels included in the first largest connected region adjacent to the edge of the wafer to be recognized is greater than the first quantity threshold, it is determined that the wafer to be recognized includes edge position defects as the verified defect mode recognition result. For edge ring defects, if the number of consecutive pixels is greater than the second quantity threshold, it is determined that the wafer to be recognized includes edge ring defects as the verified defect mode recognition result. The first quantity threshold can be different from the second quantity threshold. For example, the second quantity threshold can be greater than the first quantity threshold.

[0051] It should be noted that the thresholds corresponding to these two types of defects are usually different. The number of pixels corresponding to the Edge-Ring defect is larger than that of the Edge-Loc defect. Therefore, the threshold corresponding to the Edge-Ring defect can be denoted as the second quantity threshold, and the threshold corresponding to the Edge-Loc defect can be denoted as the first quantity threshold. This threshold can be of a fixed size or can be dynamically adjusted according to the wafer map resolution.

[0052] As another specific implementation manner, the steps of post-processing the defect mode recognition result to obtain the verified defect mode recognition result can be optimized, including:

[0053] 1) If the defect mode recognition result includes scratch defects (Scratch), the second largest connected region in the wafer map is determined according to the set second connectivity rule;

[0054] 2) If the length of the farthest line segment corresponding to the two pixels with the farthest distance in the second largest connected region is greater than the set distance threshold, and the ratio of the length of the farthest line segment to the projection length is greater than the set ratio threshold, then the scratch defect mode included in the wafer to be recognized is used as the recognized result of the verified defect mode, where the projection length is the length of the projection of the target line segment in the direction perpendicular to the farthest line segment, and the two endpoints of the target line segment are the two pixels with the farthest distance in the direction perpendicular to the farthest line segment.

[0055] In this embodiment, if the recognized result of the defect mode includes a scratch defect, the second largest connected region in the wafer image can be determined according to the set second connectivity rule. For scratch defects, the connectivity rule can be a custom twelve-connectivity rule, which can better extract curves. Among them, the custom twelve-connectivity rule includes, in addition to the pixels in the eight directions of the eight-connectivity rule, the pixels in the four directions of up, down, left, and right outside the region determined by the eight-connectivity rule.

[0056] Exemplarily, if the two pixels with the farthest distance in the second largest connected region are found and the length of the farthest distance is calculated. Then, a line segment is formed by these two farthest pixels, and the two pixels with the farthest distance in the direction perpendicular to this line segment in the second largest connected region are found, and the length of the projection of the line segment formed by these two pixels in the direction perpendicular to the farthest line segment is determined. If the length of this farthest distance is large and the ratio of this length to this projection length is large enough, it is considered that the sample actually has a Scratch mode. Generally speaking, it is to judge whether the largest connected region is "slender" enough. If it is "slender" enough, it is considered that the wafer to be recognized has a Scratch defect. If the ratio is less than or equal to the set ratio threshold, the wafer to be recognized not including a scratch defect can be used as the recognized result of the verified defect mode.

[0057] The above technical solution specifies the steps for post-processing the model recognition result, and improves the accuracy of defect recognition through further verification of the recognized result of the defect mode.

[0058] Embodiment 2

[0059] Figure 2Schematic diagram of another method for identifying wafer defect patterns provided in the second embodiment of the present invention. This embodiment is a further optimization of the above embodiment. In this embodiment, the limitation and optimization of "converting the wafer map of the wafer to be identified into point cloud to obtain the original point cloud set of the wafer to be identified" are further carried out, and the limitation and optimization of "normalizing each point cloud in the original point cloud set to obtain the normalized target point cloud set" are further carried out, and the limitation and optimization of "constructing the point cloud feature map of the wafer to be identified according to the target point cloud set" are further carried out, and the limitation and optimization of "determining the defect pattern recognition result of the wafer to be identified according to the point cloud feature map and the pre-constructed classification network model" are further carried out.

[0060] As Figure 2 shown, the second embodiment provides a method for identifying wafer defect patterns, which specifically includes the following steps:

[0061] S201. According to the coordinates of each pixel in the wafer map and the center coordinates of the wafer to be identified in the wafer map, and combining the states of each chip in the wafer to be identified, convert each pixel into a point cloud in the Cartesian coordinate system.

[0062] In this embodiment, the two-dimensional wafer map is converted into a point cloud in the Cartesian coordinate system. The coordinates of the point cloud (x, y) correspond to the position of each pixel in the image, and the value v of the point cloud represents the state of the corresponding chip.

[0063] Convert the wafer map I into a point cloud in the Cartesian coordinate system. Define the point cloud as set P:

[0064] , where i and j are the horizontal and vertical coordinates of the current pixel in the map respectively, represents the coordinates of the point cloud, represents the state of the chip. Traverse all pixels. If the current pixel value is 0, skip it; if the current pixel value is 1 or 2, convert the pixel into a point p, and the calculation formula is:

[0065] ;

[0066] where, is the coordinate of the wafer center in the wafer map, is the grayscale value of this pixel, representing the chip state. Convert all pixels into points according to this formula, and the point cloud in the Cartesian coordinate system can be obtained, with the coordinate origin being the wafer center. Let , then the point cloud P can be expressed as:

[0067] ;

[0068] Based on the above formula, each pixel can be converted into a point cloud in the Cartesian coordinate system.

[0069] S202. Convert the point cloud in the Cartesian coordinate system into a point cloud in the polar coordinate system to form the original point cloud set of the wafer to be recognized.

[0070] Among them, the polar coordinate system takes the center of the wafer to be recognized in the wafer map as the pole and the positive direction of the horizontal axis of the Cartesian coordinate system as the polar axis.

[0071] In this embodiment, the point cloud in the Cartesian coordinate system is converted into a point cloud in the polar coordinate system. The pole of the polar coordinate system is the center of the wafer, and the positive direction of the x-axis of the Cartesian coordinate system is the polar axis. The point cloud in the Cartesian coordinate system is converted into a point cloud in the polar coordinate system to conform to the distribution characteristics of wafer defects. In the polar coordinate system, the center of the wafer is taken as the pole, and the positive direction of the axis of the wafer map is the polar axis. For each point in the point cloud , calculate its corresponding polar coordinates . The conversion formula is as follows:

[0072] ;

[0073] Among them, after all points are converted, a point cloud in the polar coordinate system is obtained :

[0074] ;

[0075] Based on the above formula, the point cloud in the Cartesian coordinate system is converted into a point cloud in the polar coordinate system to form the original point cloud set of the wafer to be recognized.

[0076] S203. Determine the scaling ratio according to the original point cloud radius of the original point cloud set and the set normalized radius.

[0077] Among them, the original point cloud radius is the distance between the farthest point from the center point of the original point cloud and the center point.

[0078] In this embodiment, since the point cloud contours converted from different wafer maps are of different sizes, it is necessary to normalize the point clouds in the original point cloud set. Exemplarily, let the radius of the wafer to be recognized (i.e., the original point cloud radius) be , and let this radius be normalized to R. Then the value obtained by dividing R by can be used as the scaling ratio.

[0079] It should be noted that wafer defects are usually caused by process problems. Some of these defects show a circular or annular distribution on the wafer. For example, defective die show an annular distribution at the wafer edge, most of the defective die are located near the center of the wafer, and the spatial distribution of the defective die is similar to a doughnut. A possible cause of Edge-Ring defects is the coating problem of photoresist during the lithography process. In the lithography process, the photoresist is first dropped at the center of the wafer and then uniformly coated on the wafer surface by high-speed rotation. However, due to problems such as inappropriate temperature, improper rotation parameter settings, or problems with the photoresist itself, the photoresist may be unevenly distributed at the wafer edge, thus forming Edge-Ring defects.

[0080] Through the analysis of Edge-Ring defects, it can be found that using a polar coordinate system with the center of the wafer as the pole to represent data can be more in line with the fundamental causes of various wafer defect patterns in principle. Therefore, adopting a polar coordinate system helps to improve the accuracy and performance of defect recognition algorithms.

[0081] S204. Scale the coordinates of each point cloud in the original point cloud set according to the scaling ratio to obtain a normalized target point cloud set.

[0082] In this embodiment, the coordinates of all point clouds in the original point cloud set are changed proportionally at the same time, so as to obtain a normalized point cloud set, denoted as the target point cloud set. This point cloud-based normalization method fundamentally retains the original information and geometric characteristics of the wafer map, and at the same time solves the problems of information loss or introduction of false information during the process of unifying the image size, and is more suitable for the defect pattern recognition task of multi-size wafer maps. Compared with the traditional image normalization method, it can provide a more stable and real feature representation.

[0083] S205. Divide the point clouds in the target point cloud set into regions to obtain multiple point cloud regions.

[0084] In this embodiment, the point clouds in polar coordinates are divided into regions, and the purpose is to extract local features more effectively. According to the manual experience of wafer defect pattern recognition, in many cases, the defect pattern of the wafer can be determined by judging specific regions without a comprehensive analysis of the entire wafer. For example, for Loc and Edge-Loc defect patterns, only the features of these specific regions need to be concerned to conclude that the entire wafer has this defect. Through this regional division, the regions with obvious defects can be concentrated for processing, improving the efficiency and accuracy of defect recognition.

[0085] Continuing with the above description, in this embodiment, the point clouds in the target point cloud set can be divided into multiple regions, denoted as point cloud regions. Exemplarily, the point clouds can be divided into several annular regions, or the point clouds can be divided into several fan-shaped regions.

[0086] As a specific implementation, the steps of optimizing the regional division of the point clouds in the target point cloud set to obtain multiple point cloud regions include:

[0087] 1) Divide the radii of the point clouds in the target point cloud set into equal parts according to a first quantity to obtain a first quantity of annular regions.

[0088] In this embodiment, the point clouds in the normalized target point cloud set are regionally divided. The first quantity can be set according to the actual situation, and the radii of the normalized point clouds are divided into equal parts according to the first quantity. Specifically, assume that the radius of the normalized wafer is R, and the circular region C with a radius less than R is divided. First, divide the radius R into p equal parts to obtain p concentric circles , where , and assume corresponding to the center point. Through these concentric circles, p annular regions are obtained, where i = 1, 2, …, p, and in this way, the circular region C is divided into p annular regions.

[0089] 2) Divide the angular range of each annular region into equal parts according to a second quantity to obtain a third quantity of point cloud regions.

[0090] Among them, the third quantity is equal to the product of the first quantity and the second quantity.

[0091] In this embodiment, after dividing the radii of the normalized point clouds into equal parts according to the first quantity to obtain a first quantity of annular regions, the angular range is simultaneously divided into equal parts according to the second data, so that the entire point cloud is divided into multiple annular regions according to the radius and multiple sector regions according to the angular range, thereby obtaining multiple point cloud regions. The second quantity is set according to the actual situation.

[0092] Specifically, divide the angular range [0, 2π] into k parts, and the angle of each part is 2π / k, so that each annular region is further divided into k equal-area sector regions. Through this division method, the point cloud is divided into regions. Each region belongs to both an annular region of a certain concentric circle and a sector region divided by a certain angular range, and is represented by to represent these regions, where i = 1, 2, …, p, j = 1, 2, …, k.

[0093] S206. Construct a point cloud feature map of the wafer to be recognized according to the chip states of each chip included in each point cloud region.

[0094] In this embodiment, after dividing the point cloud into each point cloud region, feature extraction can be performed based on the statistical situation of the tested chips and untested chips included in the point cloud region. It can also be to obtain a feature map by performing some other feature extraction operations on the points within the point cloud region. Since many defect patterns can be judged only according to the chips that have not passed the test, the data of the untested chips can be retained for feature extraction. In this embodiment, based on the chip status of each chip included in each point cloud region, feature extraction is performed to obtain the features of each point cloud region. The features of all point cloud regions are stitched together into a feature map, denoted as the point cloud feature map of the wafer to be recognized.

[0095] As an implementation manner, the step of constructing the point cloud feature map of the wafer to be recognized according to the chip status of the chips included in each point cloud region can be optimized, including:

[0096] 1) For each point cloud region, according to the tested chips and untested chips included in the point cloud region, feature extraction is performed according to the first feature extraction method to construct the first feature map of the wafer to be recognized.

[0097] In this embodiment, after dividing the point cloud into each point cloud region, feature extraction can be performed based on the statistical situation of the tested chips and untested chips included in the point cloud region. This method is denoted as the first feature extraction method, and the extracted feature result is denoted as the first feature map. Exemplarily, the first feature extraction method can be to statistically calculate the proportion of chips in different states in each point cloud region, or the respective centroids of the tested chips and untested chips, or the degree of dispersion of the point cloud, etc. The first feature extraction method is not specifically limited here, and a suitable extraction method can be selected according to the actual situation.

[0098] Exemplarily, the proportion of chips in different states in each point cloud region can be statistically calculated. Specifically, calculate the number of chips that have passed the test in the point cloud region and the number of chips that have not passed the test , and calculate the proportion of the chips that have passed the test in all chips in this region , and use to represent the proportion of the chips that have passed the test in region . After obtaining the proportions of point cloud regions, a feature map with a size of [p, k, 1] can be obtained, where p and k represent the size of the feature map, and 1 represents the number of feature channels, that is, extract the features of one channel. At the same time, some statistical quantities can also be calculated through other statistical methods to describe the features of this region. Here are several relatively common statistical quantities: the respective centroids of the points with value 1 and value 2, the degree of dispersion of the point cloud, and a first feature map with a size of can be obtained , where represents the number of feature channels, that is, extracting features of

[0099] It should be noted that the purpose of dividing the point cloud into regions and calculating the proportion of chips in different states in each region is to solve the problem of feature map differences caused by the difference in the number of chips in the region after converting wafers of different sizes into point clouds. Directly using the number of chips for analysis will result in too large a difference in the feature maps between wafers with more chips and wafers with fewer chips. Therefore, it is hoped to find a variable that is not affected by the number of chips to characterize the features of the region, and the proportion just meets this requirement. Regardless of the number of chips, if there is a certain defect in the wafer, in the region where the defect is located, the proportion of chips in different states will be highly similar. In this way, the defect characteristics of the wafer can be reflected more objectively and consistently.

[0100] 2) Alternatively, for each point cloud region, according to the untested chips included in the point cloud region, feature extraction is performed according to the second feature extraction method to construct a second feature map of the wafer to be recognized.

[0101] In addition, in this embodiment, the feature map can also be obtained by performing some other feature extraction operations on the points in the point cloud region. The feature map obtained in this step is denoted as the second feature map, expressed as , with a shape of . Since many defect patterns can be judged only based on the chips that have not passed the test, the data of the chips that have not passed the test can be retained only. The specific method is to remove the points with v = 1 and only retain the points with v = 2. The second feature extraction method can be a point-based network such as PointNet, max pooling, or average pooling.

[0102] Exemplarily, the points of the point cloud region that only retain the data of the untested chips are input into a point-based network PointNet, and a depth-adjustable feature vector can be obtained. After using this PointNet to extract features from all regions, a second feature map with a shape of can be obtained. If simplicity is pursued, the PointNet network can be replaced by some simple operations, such as max pooling and average pooling.

[0103] 3) Use the first feature map and / or the second feature map as the point cloud feature map.

[0104] In this embodiment, the first feature map or the second feature map can be used alone as the final point cloud feature map, or the first feature map and the second feature map can be concatenated as the point cloud feature map. Exemplarily, assume that the first feature map is , and the second feature map is , it can directly use as a point cloud feature map with dimensions [p, k, C] , or it can directly use as the point cloud feature map , or it can be to and stitch them together as the point cloud feature map .

[0105] S207. Input the point cloud feature map into the classification network model to obtain the defect mode recognition result of the wafer to be recognized. Alternatively, perform normalization processing and convolution processing on the wafer map to obtain the image feature map of the wafer map; splice the image feature map and the point cloud feature map to obtain the spliced fusion feature map; input the fusion feature map into the classification network model to obtain the defect mode recognition result of the wafer to be recognized.

[0106] As a method for recognizing the defect mode of a wafer, the point cloud feature map can be directly input into a classification network model, and then the classification result is directly output, denoted as the defect mode recognition result of the wafer to be recognized.

[0107] As another method for recognizing the defect mode of a wafer, the wafer map and the point cloud feature map can be used simultaneously. First, since the sizes of the wafer map and the point cloud feature map are inconsistent and cannot be directly stitched together and input into the network, a shape alignment operation needs to be performed first. The original wafer maps usually have different sizes and are normalized to the same shape through methods such as interpolation. Perform a convolution operation on the wafer map with the unified shape. Here, the size of the feature map of the wafer map after several convolution operations can be controlled by setting the shape after normalization and the parameters of the convolution operation to be consistent with the point cloud feature Figure 1 . Performing a convolution operation on the wafer map is equivalent to extracting features from the wafer map, and the obtained features are denoted as the image feature map.

[0108] Continuing from the above description, at this time, the images can be stitched together to form a feature map, denoted as the fusion feature map. The fusion feature map contains both the features of the image and the features of the point cloud.

[0109] In this embodiment, after obtaining the fusion feature map, it can be input into the classification network model, and finally the defect mode recognition result of the wafer to be recognized is obtained.

[0110] The above technical solution embodies the steps of performing point cloud conversion on a wafer map, normalizing the point cloud, extracting features from the normalized point cloud, and determining the defect pattern recognition result. By converting the wafer map into a point cloud and normalizing the point cloud, the point cloud method does not introduce additional information or lose any existing information. Using the point cloud for normalization can maximize the retention of the features of the original data, improving the accuracy and robustness of wafer defect pattern recognition. In addition, using a polar coordinate system with the wafer center as the pole to represent the data can better conform to the root causes of various wafer defect patterns in principle. Adopting the polar coordinate system helps improve the accuracy and performance of the defect recognition algorithm. Dividing the point cloud in the polar coordinates into regions aims to more effectively extract local features. Through this region division, areas with obvious defects can be concentrated for processing, improving the efficiency and accuracy of defect recognition. Additionally, pattern recognition is performed after fusing the features of the original wafer map and the point cloud, further improving the accuracy of the defect recognition result.

[0111] Embodiment III

[0112] Figure 3 FIG. is a schematic structural diagram of a device for recognizing wafer defect patterns provided in Embodiment III of the present invention. This device is applicable to the situation of recognizing wafer defect patterns. The device for recognizing wafer defect patterns can be configured in an electronic device, such as Figure 3 As shown, the device includes: a point cloud conversion module 31, a normalization module 32, a feature extraction module 33, and a result determination module 34; wherein,

[0113] The point cloud conversion module 31 is configured to perform point cloud conversion on the wafer map of the wafer to be recognized, and obtain the original point cloud set of the wafer to be recognized;

[0114] The normalization module 32 is configured to perform normalization processing on each point cloud in the original point cloud set, and obtain the normalized target point cloud set;

[0115] The feature extraction module 33 is configured to construct a point cloud feature map of the wafer to be recognized according to the target point cloud set;

[0116] The result determination module 34 is configured to determine the defect pattern recognition result of the wafer to be recognized according to the point cloud feature map and a pre-constructed classification network model.

[0117] In the above technical solution, first, the wafer map for identifying the wafer is converted into a point cloud, and then normalization processing is performed based on the point cloud. The normalization method based on the point cloud fundamentally preserves the original information and geometric characteristics of the wafer map, and at the same time solves the problem of information loss or introduction of false information during the process of unifying the image size, which is more suitable for the defect pattern recognition task of wafers of multiple sizes. Compared with the traditional image normalization method, it can provide a more stable and real feature representation, and improve the accuracy of wafer defect pattern recognition.

[0118] Optionally, the point cloud conversion module 31 is specifically used for:

[0119] According to the coordinates of each pixel in the wafer map and the center coordinates of the wafer to be recognized in the wafer map, combined with the chip status of each chip in the wafer to be recognized, convert each pixel into a point cloud in the Cartesian coordinate system;

[0120] Convert the point cloud in the Cartesian coordinate system into a point cloud in the polar coordinate system to form the original point cloud set of the wafer to be recognized. The polar coordinate system takes the center of the wafer to be recognized in the wafer map as the pole and the positive direction of the horizontal axis of the Cartesian coordinate system wafer as the polar axis.

[0121] Optionally, the normalization module 32 is specifically used for:

[0122] Determine the scaling ratio according to the original point cloud radius of the original point cloud set and the set normalization radius, where the original point cloud radius is the distance between the farthest point from the center point of the original point cloud and the center point;

[0123] Scale the coordinates of each point cloud in the original point cloud set according to the scaling ratio to obtain the normalized target point cloud set.

[0124] Optionally, the feature extraction module 33 includes:

[0125] The region division unit is used to divide the point clouds in the target point cloud set to obtain multiple point cloud regions;

[0126] The feature extraction unit is used to construct a point cloud feature map of the wafer to be recognized according to the chip status of each chip included in each point cloud region.

[0127] Optionally, the region division unit is specifically used for:

[0128] Divide the radius of the point cloud in the target point cloud set into equal parts according to the first quantity to obtain a first quantity of annular regions;

[0129] Divide the polar angle range of each annular region into equal parts according to the second quantity to obtain a third quantity of point cloud regions, and the third quantity is equal to the product of the first quantity and the second quantity.

[0130] Optionally, the feature extraction unit is specifically used for:

[0131] For each point cloud region, according to the tested chips and untested chips included in the point cloud region, feature extraction is performed according to the first feature extraction method to construct a first feature map of the wafer to be recognized; or,

[0132] For each point cloud region, according to the untested chips included in the point cloud region, feature extraction is performed according to the second feature extraction method to construct a second feature map of the wafer to be recognized;

[0133] The first feature map and / or the second feature map is used as the point cloud feature map.

[0134] Optionally, the result determination module 34 is specifically configured to:

[0135] Input the point cloud feature map into a classification network model to obtain a defect pattern recognition result of the wafer to be recognized; or,

[0136] Perform normalization processing and convolution processing on the wafer map to obtain an image feature map of the wafer map;

[0137] Stitch the image feature map and the point cloud feature map to obtain a stitched fusion feature map;

[0138] Input the fusion feature map into a classification network model to obtain a defect pattern recognition result of the wafer to be recognized.

[0139] Optionally, the device further includes a post-processing module, which is used for: after determining the defect pattern recognition result of the wafer to be recognized,

[0140] Perform post-processing on the defect pattern recognition result to obtain a verified defect pattern recognition result.

[0141] Optionally, the post-processing module is specifically configured to:

[0142] If the defect pattern recognition result includes at least one of edge position defects, edge ring defects, and local defects, then for each defect, according to the set first connectivity rule, the first largest connected domain is determined respectively;

[0143] For the local defect, if the number of consecutive pixels included in the first largest connected domain is greater than the first quantity threshold, then determine that the wafer to be recognized includes a local defect as the verified defect pattern recognition result;

[0144] For the edge position defect, if the number of consecutive pixels included in the first largest connected domain adjacent to the edge of the wafer to be recognized is greater than the first quantity threshold, then determine that the wafer to be recognized includes an edge position defect as the verified defect pattern recognition result;

[0145] For the edge ring defect, if the number of consecutive pixels included in the first largest connected component adjacent to the edge of the wafer to be recognized is greater than the second quantity threshold, then it is determined that the wafer to be recognized includes an edge ring defect as the verified defect mode recognition result.

[0146] Optionally, the post-processing module is specifically configured to:

[0147] If the defect mode recognition result includes a scratch defect, then according to the set second connectivity rule, determine the second largest connected component in the wafer map;

[0148] If the length of the farthest line segment corresponding to the two pixels with the farthest distance in the second largest connected component is greater than the set distance threshold, and the ratio of the length of the farthest line segment to the projection length is greater than the set ratio threshold, then it is determined that the wafer to be recognized includes a scratch defect mode as the verified defect mode recognition result, where the projection length is the length of the projection of the target line segment in the direction perpendicular to the farthest line segment, and the two endpoints of the target line segment are the two pixels with the farthest distance in the direction perpendicular to the farthest line segment.

[0149] The wafer defect mode recognition device provided by the embodiments of the present invention can execute the wafer defect mode recognition method provided by any embodiment of the present invention, and has the corresponding functional modules and beneficial effects for executing the method.

[0150] Embodiment 4

[0151] Figure 4 It is a schematic structural diagram of an electronic device provided by Embodiment 4 of the present invention. The electronic device is intended to represent various forms of digital computers, such as, a laptop computer, a desktop computer, a workbench, a personal digital assistant, a server, a blade server, a mainframe computer, and other suitable computers. The components shown herein, their connections and relationships, and their functions are only examples and are not intended to limit the implementation of the present invention described and / or claimed herein.

[0152] Such as Figure 4As shown, the electronic device 40 includes at least one processor 41 and a memory communicatively connected to the at least one processor 41, such as a read-only memory (ROM) 42, a random access memory (RAM) 43, etc. Among them, the memory stores a computer program executable by the at least one processor. The processor 41 can execute various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 42 or the computer program loaded from the storage unit 48 into the random access memory (RAM) 43. In the RAM 43, various programs and data required for the operation of the electronic device 40 can also be stored. The processor 41, the ROM 42, and the RAM 43 are connected to each other through a bus 44. An input / output (I / O) interface 45 is also connected to the bus 44.

[0153] Multiple components in the electronic device 40 are connected to the I / O interface 45, including: an input unit 46, such as a keyboard, a mouse, etc.; an output unit 47, such as various types of displays, speakers, etc.; a storage unit 48, such as a disk, an optical disc, etc.; and a communication unit 49, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 49 allows the electronic device 40 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0154] The processor 41 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the processor 41 include but are not limited to a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 41 executes the various methods and processes described above, such as the method for identifying wafer defect patterns.

[0155] In some embodiments, the method for identifying wafer defect patterns can be implemented as a computer program tangibly contained in a computer-readable storage medium, such as the storage unit 48. In some embodiments, part or all of the computer program can be loaded and / or installed onto the electronic device 40 via the ROM 42 and / or the communication unit 49. When the computer program is loaded into the RAM 43 and executed by the processor 41, one or more steps of the method for identifying wafer defect patterns described above can be executed. Alternatively, in other embodiments, the processor 41 can be configured to execute the method for identifying wafer defect patterns by any other appropriate means (e.g., by means of firmware).

[0156] The various embodiments of the systems and techniques described above in this specification can be implemented in digital electronic circuitry, integrated circuit systems, field programmable gate arrays (FPGA), application specific integrated circuits (ASIC), application specific standard products (ASSP), systems on chip (SOC), complex programmable logic devices (CPLD), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include: being implemented in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which may be a special-purpose or general-purpose programmable processor that receives data and instructions from, and transmits data and instructions to, a storage system, at least one input device, and at least one output device.

[0157] The computer program for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions / operations specified in the flowchart and / or block diagram to be implemented. The computer program may be executed entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.

[0158] In the context of the present invention, a computer-readable storage medium may be a tangible medium that can contain, or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. Alternatively, the computer-readable storage medium may be a machine-readable signal medium. More specific examples of the machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0159] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the electronic device. Other kinds of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0160] The systems and techniques described herein can be implemented in a computing system including backend components (e.g., as a data server), or a computing system including middleware components (e.g., an application server), or a computing system including frontend components (e.g., a user computer having a graphical user interface or a web browser through which the user can interact with an implementation of the systems and techniques described herein), or a computing system including any combination of such backend components, middleware components, or frontend components. The components of the system can be interconnected to each other by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local area network (LAN), wide area network (WAN), blockchain network, and the Internet.

[0161] The computing system can include a client and a server. The client and the server are generally remote from each other and typically interact through a communication network. The client-server relationship is created by computer programs running on respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or a cloud host, which is a host product in the cloud computing service system, and solves the defects of difficult management and weak business scalability existing in traditional physical hosts and VPS services.

[0162] An embodiment of the present invention also provides a computer program product, including a computer program which, when executed by a processor, implements the method for identifying a wafer defect pattern provided in any embodiment of the present invention.

[0163] In the process of implementing the computer program product, computer program code for performing the operations of the present disclosure can be written in one or more programming languages or combinations thereof. The above-mentioned programming languages include, but are not limited to, object-oriented programming languages - such as Java, Smalltalk, C++, and also include conventional procedural programming languages - such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, executed as an independent software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer through any type of network - including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (for example, by using an Internet service provider to connect through the Internet).

[0164] It should be understood that various forms of the processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in the present invention can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved, and no limitation is imposed herein.

[0165] The above specific embodiments do not constitute a limitation on the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for identifying a wafer defect pattern, characterized in that: include: Performing point cloud conversion on a wafer image of a wafer to be identified to obtain an original point cloud set of the wafer to be identified, wherein each pixel in the wafer image represents a chip; Normalizing each point cloud in the original point cloud set to obtain a normalized target point cloud set; Constructing a point cloud feature map of the wafer to be identified according to the target point cloud set; Determining a defect pattern recognition result of the wafer to be identified according to the point cloud feature map and the pre-built classification network model; The step of constructing a point cloud feature map of the wafer to be identified according to the target point cloud set includes: Dividing the point cloud in the target point cloud set into regions to obtain a plurality of point cloud regions; Constructing a point cloud feature map of the wafer to be identified according to the chip status of each chip contained in each point cloud area; The step of constructing a point cloud feature map of the wafer to be identified according to the chip status of the chip contained in each point cloud area includes: For each of the point cloud regions, according to the chips that have passed the test and the chips that have failed the test contained in the point cloud region, feature extraction is performed according to a first feature extraction method to construct a first feature map of the wafer to be identified, wherein the first feature extraction method includes counting the proportions of chips in different states in each point cloud region; The first feature map is used as the point cloud feature map.

2. The method according to claim 1, characterized in that: The step of performing point cloud conversion on the wafer image of the wafer to be identified to obtain an original point cloud set of the wafer to be identified includes: According to the coordinates of each pixel in the wafer image and the center coordinates of the wafer to be identified in the wafer image, combined with the state of each chip in the wafer to be identified, each pixel is converted into a point cloud in a Cartesian coordinate system; The point cloud in the Cartesian coordinate system is converted into a point cloud in the polar coordinate system to form an original point cloud set of the wafer to be identified, wherein the polar coordinate system takes the center of the wafer to be identified in the wafer image as the pole and takes the positive direction of the horizontal axis of the Cartesian coordinate system as the polar axis.

3. The method according to claim 1, characterized in that The step of normalizing the point cloud included in the original point cloud set to obtain a normalized target point cloud set includes: Determine a scaling ratio according to an original point cloud radius of the original point cloud set and a set normalized radius, wherein the original point cloud radius is a distance between the farthest point of the center point of the original point cloud and the center point; The coordinates of each point cloud in the original point cloud set are scaled according to the scaling ratio to obtain a normalized target point cloud set.

4. The method according to claim 1, characterized in that The step of dividing the point cloud in the target point cloud set into regions to obtain a plurality of point cloud regions includes: Divide the radius of the point cloud in the target point cloud set into equal parts according to a first number to obtain a first number of annular regions; The polar angle range of each of the annular areas is equally divided according to a second number to obtain a third number of point cloud areas, where the third number is equal to the first number multiplied by the second number.

5. The method according to claim 1, characterized in that The step of constructing a point cloud feature map of the wafer to be identified according to the chip status of the chip contained in each point cloud area includes: For each of the point cloud regions, according to the chips that failed the test and are contained in the point cloud region, feature extraction is performed according to a second feature extraction method to construct a second feature map of the wafer to be identified; The second feature map is used as the point cloud feature map.

6. The method according to claim 1, characterized in that Determining the defect pattern recognition result of the wafer to be identified according to the point cloud feature map and the pre-built classification network model includes: Inputting the point cloud feature map into the classification network model to obtain the defect pattern recognition result of the wafer to be identified; or, Performing normalization and convolution processing on the wafer image to obtain an image feature map of the wafer image; Splicing the image feature map and the point cloud feature map to obtain a spliced ​​fusion feature map; The fused feature map is input into the classification network model to obtain the defect pattern recognition result of the wafer to be identified.

7. The method according to claim 1, characterized in that After determining the defect pattern recognition result of the wafer to be recognized, the method further includes: The defect pattern recognition result is post-processed to obtain a verified defect pattern recognition result.

8. The method according to claim 7, characterized in that The post-processing of the defect pattern recognition result to obtain a verified defect pattern recognition result includes: if the defect pattern recognition result includes at least one of an edge position defect, an edge ring defect, and a local defect, determining a first maximum connected domain for each defect according to a set first connectivity rule; For the local defect, if the number of continuous pixels included in the first maximum connected domain is greater than a first number threshold, determining that the wafer to be identified includes the local defect is a verified defect pattern recognition result; For the edge position defect, if the number of continuous pixels contained in the first maximum connected domain adjacent to the edge of the wafer to be identified is greater than the first number threshold, then it is determined that the wafer to be identified contains the edge position defect as a verified defect pattern recognition result; For the edge ring defect, if the number of continuous pixels contained in the first maximum connected domain adjacent to the edge of the wafer to be identified is greater than a second number threshold, then it is determined as a verified defect pattern recognition result that the wafer to be identified contains an edge ring defect.

9. The method according to claim 7, characterized in that: The post-processing of the defect pattern recognition result to obtain a verified defect pattern recognition result includes: If the defect pattern recognition result includes a scratch defect, determining a second maximum connected domain in the wafer map according to a set second connectivity rule; If the length of the farthest line segment corresponding to the two pixels farthest from each other in the second maximum connected domain is greater than a set distance threshold, and the ratio of the length of the farthest line segment to the projection length is greater than a set ratio threshold, then the scratch defect pattern contained in the wafer to be identified is taken as a verified defect pattern recognition result, wherein the projection length is the length of the projection of the target line segment in the vertical direction of the farthest line segment, and the two endpoints of the target line segment are the two pixel points farthest apart in the vertical direction of the farthest line segment.

10. A wafer defect pattern recognition device, characterized in that: include: A point cloud conversion module is used to perform point cloud conversion on a wafer image of a wafer to be identified to obtain an original point cloud set of the wafer to be identified, wherein each pixel in the wafer image represents a chip; A normalization module, used for normalizing each point cloud in the original point cloud set to obtain a normalized target point cloud set; A feature extraction module, used to construct a point cloud feature map of the wafer to be identified according to the target point cloud set; A result determination module, used to determine the defect pattern recognition result of the wafer to be identified according to the point cloud feature map and the pre-built classification network model; Feature extraction module, including: A region division unit is used to divide the point cloud in the target point cloud set into regions to obtain multiple point cloud regions; A feature extraction unit, used to construct a point cloud feature map of the wafer to be identified according to the chip status of each chip contained in each point cloud area; The feature extraction unit is specifically used for: For each point cloud region, according to the chips that have passed the test and the chips that have failed the test contained in the point cloud region, feature extraction is performed according to a first feature extraction method to construct a first feature map of the wafer to be identified, wherein the first feature extraction method includes counting the proportion of chips in different states in each point cloud region; The first feature map is used as the point cloud feature map.

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