Processor and display device

Abstract

The invention relates to a processor and a display device. The processor includes an interface circuit that receives first image data and converts the first image data into second image data; a pattern detection circuit that detects a pattern in the first image data or the second image data; a luminance detection circuit that detects a panel luminance value and detects a ratio of pixels that emit light; and a real-time sensing circuit wherein, when the pattern is not detected, the real-time sensing circuit performs / stops real-time sensing of the pixel based on whether the panel luminance value is within a range and whether the ratio of the pixel emitting light is greater than or equal to a first threshold; and when the pattern is detected, the real-time sensing circuit performs / stops the real-time sensing of the pixel based on whether the panel luminance value is within the range and whether the ratio of the pixel emitting light is greater than or equal to a second threshold.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0144217 filed in the Korean Intellectual Property Office on October 25, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to a processor, a display device including the processor, and a method for driving the display device. Background Art

[0004] As information technology advances, the importance of display devices as a connection medium between users and information has become increasingly prominent. Therefore, the use of display devices such as liquid crystal display devices and organic light emitting display devices has increased significantly.

[0005] The display device may include a display panel in which a plurality of pixels are arranged. For example, each of the plurality of pixels may include a pixel circuit including one or more switching elements such as transistors.

[0006] When a display device is driven, a characteristic value of a transistor within a pixel circuit may be changed. Sensing the change in the characteristic value of the transistor and compensating for the change may improve display quality.

[0007] When a change in a characteristic value of a transistor is sensed while displaying a low grayscale image in a display device, a dark horizontal line may become visible. Therefore, a method of reducing the visibility of the horizontal line is needed. Summary of the invention

[0008] The present disclosure provides a processor that can prevent a horizontal line from becoming visible, a display device including the processor, and a method for driving the display device.

[0009] An embodiment of the present disclosure provides a processor, which includes: an interface circuit configured to receive first image data and convert the first image data into second image data; a pattern detection circuit configured to detect a pattern in the first image data or the second image data; a brightness detection circuit configured to detect a panel brightness value and detect a ratio of pixels among a plurality of pixels that emit light in response to the second image data, wherein the panel brightness value is a brightness value of the plurality of pixels that emit light in response to the second image data; and a real-time sensing circuit, wherein when the pattern is not detected, the real-time sensing circuit performs or stops real-time sensing of the plurality of pixels based on whether the panel brightness value is within a set range and whether the ratio of the pixels that emit light is greater than or equal to a first threshold value; and when the pattern is detected, the real-time sensing circuit performs or stops real-time sensing of the plurality of pixels based on whether the panel brightness value is within the set range and whether the ratio of the pixels that emit light is greater than or equal to a second threshold value.

[0010] When the pattern is not detected, the real-time sensing circuit stops the real-time sensing of the multiple pixels when the panel brightness value is within the set range and the ratio of the luminous pixels is greater than or equal to the first threshold, and the real-time sensing circuit performs the real-time sensing of the multiple pixels when the panel brightness value is outside the set range or the ratio of the luminous pixels is less than the first threshold.

[0011] When the pattern is detected, the real-time sensing circuit stops the real-time sensing of the multiple pixels when the panel brightness value is within the set range and the ratio of the luminous pixels is greater than or equal to the second threshold, and the real-time sensing circuit performs the real-time sensing of the multiple pixels when the panel brightness value is outside the set range or the ratio of the luminous pixels is less than the second threshold.

[0012] The first threshold is greater than the second threshold.

[0013] At least one pixel displaying the pattern among the plurality of pixels is controlled to alternate between emitting light and not emitting light as a frame progresses.

[0014] An embodiment of the present disclosure provides a processor, which includes: an interface circuit configured to receive first image data and convert the first image data into second image data; a pattern detection circuit configured to detect a pattern in the first image data or the second image data; a brightness detection circuit configured to detect a panel brightness value and detect a ratio of pixels among a plurality of pixels that emit light in response to the second image data, wherein the panel brightness value is a brightness value of the plurality of pixels that emit light in response to the second image data; and a real-time sensing circuit, wherein, when the pattern is not detected, the real-time sensing circuit performs or stops real-time sensing of the plurality of pixels based on whether the panel brightness value is within a set range and whether the ratio of the pixels that emit light is greater than or equal to a set threshold; and when the pattern is detected, the real-time sensing circuit stops the real-time sensing of the plurality of pixels.

[0015] The real-time sensing circuit stops the real-time sensing of the multiple pixels when the panel brightness value is within the set range and the ratio of the luminous pixels is greater than or equal to the set threshold, and performs the real-time sensing of the multiple pixels when the panel brightness value is outside the set range or the ratio of the luminous pixels is less than the set threshold.

[0016] An embodiment of the present disclosure provides a display device, the display device comprising: a display panel, comprising a plurality of pixels, a plurality of data lines electrically connected to the plurality of pixels, and a plurality of reference voltage lines electrically connected to the plurality of pixels; an output circuit configured to supply data voltages to the plurality of data lines; a sensing circuit configured to sense the plurality of pixels through the plurality of reference voltage lines; and a timing controller configured to control the driving timing of the output circuit and the sensing circuit, wherein the timing controller receives first image data and converts the first image data into second image data to be input to the output circuit; the timing controller detects a pattern in the first image data or the second image data; the timing controller detects a pattern in the first image data or the second image data; The timing controller measures a panel brightness value, and detects the ratio of pixels among the multiple pixels that emit light in response to the second image data, wherein the panel brightness value is a brightness value of the multiple pixels that emit light in response to the second image data; when the pattern is not detected, the timing controller performs or stops the real-time sensing of the multiple pixels based on whether the panel brightness value is within a set range and whether the ratio of the pixels that emit light is greater than or equal to a set first threshold; and when the pattern is detected, the timing controller performs or stops the real-time sensing of the multiple pixels based on whether the panel brightness value is within the set range and whether the ratio of the pixels that emit light is greater than or equal to a second threshold that is less than the first threshold.

[0017] When the pattern is not detected, the timing controller stops the real-time sensing of the multiple pixels when the panel brightness value is within the set range and the ratio of the luminous pixels is greater than or equal to the first threshold, and the timing controller performs the real-time sensing of the multiple pixels when the panel brightness value is outside the set range or the ratio of the luminous pixels is less than the first threshold.

[0018] When the pattern is detected, the timing controller stops the real-time sensing of the multiple pixels when the panel brightness value is within the set range and the ratio of the luminous pixels is greater than or equal to the second threshold, and performs the real-time sensing of the multiple pixels when the panel brightness value is outside the set range or the ratio of the luminous pixels is less than the second threshold.

[0019] The pattern is a pattern in which pixels that emit light and pixels that do not emit light among the plurality of pixels are repeated as a unit.

[0020] The pattern is a pattern in which pixels that emit light and pixels that do not emit light among the plurality of pixels are repeated in two or more units.

[0021] Each of the plurality of pixels includes a plurality of sub-pixels, and the pattern is a pattern in which sub-pixels that emit light and sub-pixels that do not emit light among the plurality of sub-pixels are repeated in one unit.

[0022] Each of the plurality of pixels includes a plurality of sub-pixels, and the pattern is a pattern in which sub-pixels that emit light and sub-pixels that do not emit light among the plurality of sub-pixels are repeated in two or more units.

[0023] The timing controller detects a pattern in pixels disposed in a predetermined area among the plurality of pixels.

[0024] A plurality of first scan lines and a plurality of second scan lines electrically connected to the plurality of pixels are also included in the display panel; the display device also includes a scan drive circuit configured to supply a first scan signal to the plurality of first scan lines and a second scan signal to the plurality of second scan lines; each of the plurality of pixels includes at least one pixel circuit; and the pixel circuit also includes: a first transistor including a gate electrode electrically connected to a first node, a first electrode electrically connected to a first power line, and a second electrode electrically connected to a second node; a second transistor configured to switch the electrical connection between the first node and a corresponding one of the plurality of data lines in response to the first scan signal; a third transistor configured to switch the electrical connection between the second node and a corresponding one of the plurality of reference voltage lines in response to the second scan signal; and a storage capacitor including a first electrode connected to the first node and a second electrode connected to the second node.

[0025] The timing controller calculates a voltage increase per unit time of the reference voltage line during a period in which the second scan signal at an on level is input to the second transistor while performing the real-time sensing on one of the plurality of pixels.

[0026] An embodiment of the present disclosure provides a driving method for a display device including a processor, the driving method including: receiving first image data and converting the first image data into second image data; detecting a pattern in the first image data or the second image data; and detecting a panel brightness value, the panel brightness value being a brightness value of a plurality of pixels emitting light in response to the second image data, and detecting a ratio of pixels among the plurality of pixels emitting light in response to the second image data, and determining whether the panel brightness value is within a set range and whether the ratio of the pixels emitting light is greater than or equal to a first threshold when the pattern is not detected, and determining whether the panel brightness value is within the set range and whether the ratio of the pixels emitting light is greater than or equal to a second threshold less than the first threshold when the pattern is detected.

[0027] The driving method also includes: when the panel brightness value is within the set range and the ratio of the pixels that emit light is greater than or equal to the first threshold, stopping the sensing of the multiple pixels, and when the panel brightness value is outside the set range or the ratio of the pixels that emit light is less than the first threshold, performing the sensing of the multiple pixels.

[0028] The driving method also includes: when the panel brightness value is within the set range and the ratio of the pixels that emit light is greater than or equal to the second threshold, stopping the sensing of the multiple pixels, and when the panel brightness value is outside the set range or the ratio of the pixels that emit light is less than the second threshold, performing the sensing of the multiple pixels. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A system block diagram of a display device according to an embodiment of the present disclosure is shown.

[0030] Figure 2 A schematic diagram showing a display area according to an embodiment of the present disclosure.

[0031] Figure 3 An example of a sub-pixel according to an embodiment of the present disclosure is shown.

[0032] Figure 4 A sensing circuit according to an embodiment of the present disclosure is shown.

[0033] Figure 5 An example of a timing chart for performing real-time sensing in a display device according to an embodiment of the present disclosure is shown.

[0034] Figure 6 A block diagram of a timing controller according to an embodiment of the present disclosure is shown.

[0035] Figure 7 An example of a detection area in a display device according to an embodiment of the present disclosure is shown.

[0036] Figure 8 An example of a first pattern in a display device according to an embodiment of the present disclosure is shown.

[0037] Fig. 9 An example of a second pattern in a display device according to an embodiment of the present disclosure is shown.

[0038] Fig.10 An example of a third pattern in the display device according to an embodiment of the present disclosure is shown.

[0039] Fig.11 An example of a fourth pattern in the display device according to an embodiment of the present disclosure is shown.

[0040] Fig.12 An example of a fifth pattern in the display device according to an embodiment of the present disclosure is shown.

[0041] Fig.13 is a diagram for explaining a panel brightness value in a display device according to an embodiment of the present disclosure.

[0042] Fig.14An example of a flowchart of a driving method of a display device according to an embodiment of the present disclosure is shown.

[0043] Fig.15 Another example of a flowchart of a method of driving a display device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0044] Hereinafter, embodiments of the present disclosure will be described more fully with reference to the accompanying drawings.As those skilled in the art will appreciate, the described embodiments may be modified in various different ways.

[0045] In order to clearly describe the present disclosure, parts or portions not related to the description may be omitted, and the same or similar components may be denoted by the same reference numerals throughout the specification. For example, a reference numeral used in one figure may be used in another figure.

[0046] In addition, in the drawings, for ease of description, the size and thickness of each element are shown, and therefore, the present disclosure is not necessarily limited to the size and thickness of the elements shown in the drawings. In the drawings, the thickness of layers, films, panels, regions, areas, etc. may be exaggerated for clarity.

[0047] In addition, the expression "equal to or the same as" in the specification may mean "substantially equal to or the same as".

[0048] Terms such as first and second will be used to describe various components and should not be interpreted as limiting these components. These terms are used to distinguish one component from other components. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. Unless the context clearly indicates otherwise, the singular form is intended to include the plural form.

[0049] Terms such as "below", "lower side", "upper side" and "upper side" are used to describe the relationship or configuration of elements shown in the figures. These terms should be understood to provide relative descriptions based on one or more directions shown in the figures.

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. In addition, unless expressly provided herein, terms should be interpreted as having a meaning consistent with their meanings defined in the context of the relevant art or in a general dictionary. In addition, these terms should not be limited to being interpreted in an ideal or overly formal sense.

[0051] It should be understood that the terms "comprises", "includes", "has" or "configuration" indicate the presence of the features, numbers, steps, operations, components, parts or combinations thereof described in the specification, but do not exclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts or combinations.

[0052] Figure 1 A system block diagram of a display device 100 according to an embodiment of the present disclosure is shown.

[0053] Reference Figure 1 The display device 100 according to an embodiment of the present disclosure may include a display panel 110 , a data driving circuit 120 , a scan driving circuit 130 , a timing controller 140 , a power supply circuit 150 , and the like.

[0054] A plurality of sub-pixels SP are provided in the display panel 110. A plurality of data lines DL1 to DLn (n is an integer greater than or equal to 2), a plurality of scan lines SL1 to SLm (m is an integer greater than or equal to 2), a plurality of reference voltage lines RVL1 to RVLh (h is an integer greater than or equal to 2), etc. electrically connected to the plurality of sub-pixels SP may be provided in the display panel 110. One or more power supply voltage lines configured to apply a power supply voltage (e.g., a first power supply voltage ELVDD and a second power supply voltage ELVSS, etc.) to the plurality of sub-pixels SP may be provided in the display panel 110.

[0055] The display panel 110 may include a display area AA where a plurality of sub-pixels SP are disposed, and a non-display area NA disposed around the display area AA (eg, at an edge of the display area AA).

[0056] The display panel 110 may be formed as a plane, but the embodiments of the present disclosure are not limited thereto. For example, the display panel 110 may include curved portions formed at its left and right ends. The curved portions may have a constant curvature or a varying curvature. In addition, the display panel 110 may be flexibly formed to be curved, bent, folded, or curled.

[0057] The plurality of sub-pixels SP may be arranged in a matrix type in the display area AA. In some embodiments, the plurality of sub-pixels SP may be arranged in a matrix type in the display area AA. Structural settings.

[0058] The plurality of data lines DL1 to DLn may be disposed to extend in a first direction DR1 in the display panel 110. The first direction DR1 may be, for example, a direction passing from an upper side to a lower side of the display panel 110, but embodiments of the present disclosure are not limited thereto.

[0059] The plurality of scan lines SL1 to SLm may be arranged to extend in the second direction DR2 in the display panel 110. The second direction DR2 may be a direction different from the first direction DR1, but the embodiments of the present disclosure are not limited thereto. For example, the second direction may be a direction passing from the left side to the right side of the display panel 110.

[0060] A plurality of reference voltage lines RVL1 to RVLh may be disposed to extend in the first direction DR1 in the display panel 110. However, embodiments of the present disclosure are not limited thereto.

[0061] The data driving circuit 120 may include an output circuit 122 and a sensing circuit 124. In some embodiments, the output circuit 122 and the sensing circuit 124 may be provided functionally separately in the same integrated circuit. In some embodiments, the output circuit 122 and the sensing circuit 124 may be provided in different integrated circuits, respectively.

[0062] The output circuit 122 may be configured to supply data voltages to the plurality of data lines DL1 to DLn. The output circuit 122 may generate data voltages based on the input second image data DATA2 and the data driving circuit control signal DCS, and output the generated data voltages to the plurality of data lines DL1 to DLn according to a specific timing. The data driving circuit control signal DCS may include, for example, a source start pulse (SSP), a source shift clock (SSC), and a source output enable (SOE), etc.

[0063] The sensing circuit 124 is configured to input a reference voltage to a plurality of reference voltage lines RVL1 to RVLk in response to a data driving circuit control signal DCS and sense the voltages of the plurality of reference voltage lines RVL1 to RVLk. The sensing circuit 124 may convert the sensed voltages of the plurality of reference voltage lines RVL1 to RVLk into corresponding digital values ​​Dsen and output the converted digital values ​​Dsen. The sensing circuit 124 may include one or more analog-to-digital converters (ADCs). The data driving circuit control signal DCS may include, for example, a reference voltage switch signal, a sampling control signal, and a holding control signal. This will be described later. Figure 4 A detailed description of the signal.

[0064] The data driving circuit 120 may be implemented as an integrated circuit (eg, a source driver integrated circuit (SDIC)) formed separately from the display panel 110 , or may be formed together with the display panel 110 in at least a portion of the non-display area NA of the display panel 110 .

[0065] The scan driving circuit 130 is configured to output scan signals to the plurality of scan lines SL1 to SLm in response to a scan driving circuit control signal SCS. The scan driving circuit control signal SCS may include a start signal indicating the start of a frame, and a horizontal synchronization signal for outputting a scan signal according to a timing of applying a data voltage.

[0066] The scan driving circuit 130 may be implemented as a gate driver integrated circuit (GDIC) formed separately from the display panel 110 , or may be formed together with the display panel 110 to be formed in at least a partial area of ​​the non-display area NA of the display panel 110 .

[0067] The timing controller 140 may be configured to control the data driving circuit 120 and the scan driving circuit 130. The timing controller 140 may generate and output control signals DCS and SCS for controlling the data driving circuit 120 and the scan driving circuit 130 based on a control signal CS (e.g., a vertical synchronization signal, a clock signal, a data enable signal, etc.) received through the host 160. In some embodiments, the timing controller 140 may generate a synchronization signal and a data enable signal, etc. based on a control signal CS (e.g., information about a driving frequency or a frame rate of an image displayed in the display panel 110) received through the host 160.

[0068] The timing controller 140 may receive the first image data DATA1 from the host 160, and arrange the input first image data DATA1 in units of pixel rows. The timing controller 140 may convert the input first image data DATA1 according to a preset interface (e.g., low voltage differential signaling (LVDS), display port (DP), embedded display port (eDP), etc.). The second image data DATA2 output by the timing controller 140 to the data driving circuit 120 may be converted inside the timing controller 140 according to the preset interface.

[0069] In some embodiments, the timing controller 140 may be a logic type and disposed in the display device 100. In some embodiments, the timing controller 140 may be a processor type and disposed in the display device 100. The timing controller 140 may include one or more memories (eg, registers, etc.).

[0070] The power supply circuit 150 may be configured to output a constant voltage at a constant voltage level. The power supply circuit 150 may output a power supply voltage (e.g., a first power supply voltage ELVDD and a second power supply voltage ELVSS, etc.) and supply it to the display panel 110. In some embodiments, the power supply circuit 150 may output a voltage (e.g., a gate high voltage and a gate low voltage, etc.) and supply it to the scan drive circuit 130. In some embodiments, the power supply circuit 150 may output a voltage (e.g., a gamma voltage and a reference voltage, etc.) and supply it to the data drive circuit 120. The power supply circuit 150 may include, for example, a regulator (e.g., a low dropout (LDO) regulator). The power supply circuit 150 may be implemented as, for example, a power management integrated circuit (PMIC).

[0071] The host 160 may include a set-top box and an application processor (AP), etc. In some embodiments, the host 160 may be a component outside the display device 100 that is not included in the display device 100, and in some embodiments, the host 160 may be installed in the display device 100. The first image data DATA1 and the control signal CS may be transmitted and received between the host 160 and the display device 100 through an interface (e.g., a serial programming interface (SPI), an inter-integrated circuit (I2C), a mobile industry processor interface (MIPI), etc.).

[0072] The display system DS according to an embodiment of the present disclosure may include a display device 100 and a host 160 .

[0073] exist Figure 1 , the data driving circuit 120, the scan driving circuit 130, the timing controller 140, and the power supply circuit 150 that supply signals and voltages, etc. to the display panel 110 are classified according to their functions. For example, the data driving circuit 120 and the timing controller 140 may be formed in one integrated circuit. The data driving circuit 120 and the timing controller 140 may be classified in one integrated circuit within the display device 100 according to their functions.

[0074] The display device 100 according to an embodiment of the present disclosure can be used as a display screen of portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notes, electronic books, portable multimedia players (PMPs), navigation devices, and ultra mobile personal computers (UMPCs), and can also be used as a display screen of various products such as televisions, notebook computers, monitors, billboards, and Internet of Things (IoT) devices.

[0075] Figure 2 A schematic diagram showing a display area AA according to an embodiment of the present disclosure.

[0076] Reference Figure 2 , schematically illustrating a plurality of pixels (eg, a first pixel PXL1, a second pixel PXL2, a third pixel PXL3, and a fourth pixel PXL4; hereinafter also referred to as PXL1 to PXL4) arranged in a matrix form. Figure 2 , the four pixels PXL1 to PXL4 may be disposed adjacent to each other in a row direction, or may be disposed adjacent to each other in a column direction.

[0077] One of the four pixels PXL1 to PXL4 (for example, the first pixel PXL1 disposed at the upper left end) may include a plurality of sub-pixels (for example, a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3). Hereinafter, for better understanding and ease of description, the display area AA will be described with focus on the four pixels PXL1 to PXL4 disposed in two rows and two columns. In addition, an embodiment in which each of the four pixels PXL1 to PXL4 includes three sub-pixels SP1 to SP3 will be described as an example. However, the embodiments of the present disclosure are not limited thereto.

[0078] The three sub-pixels SP1, SP2, and SP3 constituting one pixel (e.g., the first pixel PXL1) may each be configured to emit light of different wavelength bands. For example, the first sub-pixel SP1 may be configured to emit light of a red wavelength band. For example, the second sub-pixel SP2 may be configured to emit light of a green wavelength band. For example, the third sub-pixel SP3 may be configured to emit light of a blue wavelength band. In some embodiments, one pixel (e.g., the first pixel PXL1) may further include a white sub-pixel configured to emit white light. In some embodiments, one pixel (e.g., the first pixel PXL1) may include two or more sub-pixels (e.g., two or more second sub-pixels SP2) configured to emit green light.

[0079] The red wavelength band may be a wavelength band of about 600 nm (nanometers) to about 750 nm. The green wavelength band may be a wavelength band of about 480 nm to about 560 nm. The blue wavelength band may be a wavelength band of about 370 nm to about 460 nm.

[0080] In an embodiment of the present disclosure, the sub-pixels SP1, SP2, and SP3 constituting one pixel (e.g., the first pixel PXL1) may be electrically connected to corresponding data lines. For example, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 of the first pixel PXL1 (or the third pixel PXL3) may be electrically connected to three consecutive data lines DL(3k-2), DL(3k-1), and DL(3k) (k is an integer greater than or equal to 1 and less than h), respectively. For example, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 of the second pixel PXL2 (or the fourth pixel PXL4) may be electrically connected to three consecutive data lines DL(3k+1), DL(3k+2), and DL(3k+3), respectively.

[0081] In an embodiment of the present disclosure, the sub-pixels SP1, SP2, and SP3 constituting one pixel (e.g., the first pixel PXL1) may be electrically connected to one reference voltage line. For example, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 of the first pixel PXL1 (or the third pixel PXL3) may be electrically connected to the kth reference voltage line RVLk. For example, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 of the second pixel PXL2 (or the fourth pixel PXL4) may be electrically connected to the (k+1)th reference voltage line RVL(k+1). In some embodiments, the sub-pixels SP1, SP2, and SP3 constituting one pixel (e.g., the first pixel PXL1) may be electrically connected to different reference voltage lines, respectively. In some embodiments, the sub-pixels SP1 and SP2 of the first pixel PXL1 may be electrically connected to the first reference voltage line, and the sub-pixel SP3 of the first pixel PXL1 may be electrically connected to the second reference voltage line.

[0082] In an embodiment of the present disclosure, sub-pixels SP1, SP2, and SP3 constituting one pixel (e.g., the first pixel PXL1) may be electrically connected to one scan line. For example, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 of the first pixel PXL1 (or the second pixel PXL2) may be electrically connected to the i-th scan line SLi (i is an integer greater than or equal to 1 and less than or equal to m, hereinafter referred to as the scan line SLi). For example, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 of the third pixel PXL3 (or the fourth pixel PXL4) may be electrically connected to the (i+1)-th scan line SL(i+1) (hereinafter referred to as the scan line SL(i+1)).

[0083] Reference Figure 2, the first pixel PXL1 and the second pixel PXL2 electrically connected to the same scan line SLi can be understood as being arranged in the same row (or pixel row). For example, the first pixel PXL1 and the second pixel PXL2 can be arranged in the first row. The third pixel PXL3 and the fourth pixel PXL4 electrically connected to the same scan line SL(i+1) can be understood as being arranged in the same row (or pixel row). For example, the third pixel PXL3 and the fourth pixel PXL4 can be arranged in the second row.

[0084] Reference Figure 2 , the first pixel PXL1 and the third pixel PXL3 electrically connected to the same data line DL(3k-2), DL(3k-1) and DL(3k) can be understood as being arranged in the same column (or pixel column). For example, the first pixel PXL1 and the third pixel PXL3 can be arranged in the first column. The second pixel PXL2 and the fourth pixel PXL4 electrically connected to the same data line DL(3k+1), DL(3k+2) and DL(3k+3) can be understood as being arranged in the same column (or pixel column). For example, the second pixel PXL2 and the fourth pixel PXL4 can be arranged in the second column.

[0085] In an embodiment of the present disclosure, the plurality of pixels PXL may be disposed in two or more rows (or pixel rows) and two or more columns (or pixel columns) in the display area AA.

[0086] Figure 3 An example of a sub-pixel SP according to an embodiment of the present disclosure is shown.

[0087] The sub-pixel SP according to an embodiment of the present disclosure includes a light emitting element LE and a pixel circuit PXC, and the pixel circuit PXC is configured to supply current (e.g., drive current) to the light emitting element LE. The pixel circuit PXC may include two or more switching elements (e.g., transistors) and one or more storage elements (e.g., capacitors).

[0088] Figure 3 1 and 2 are schematic diagrams showing a pixel circuit PXC including a first transistor TR1, a second transistor TR2, a third transistor TR3 and a storage capacitor Cst. However, the embodiments of the present disclosure are not limited thereto. Hereinafter, an embodiment in which the pixel circuit PXC includes a first transistor TR1, a second transistor TR2, a third transistor TR3 and a storage capacitor Cst will be described as an example.

[0089] The light emitting element LE may include a first electrode (one of the anode electrode and the cathode electrode), a second electrode (the other of the anode electrode and the cathode electrode) and a light emitting layer. The light emitting layer may include, for example, an organic material and / or an inorganic material. For example, the light emitting element LE may be implemented as an organic light emitting diode having an organic light emitting layer. For example, the light emitting element LE may be implemented as an inorganic light emitting diode having an inorganic light emitting layer. For example, the light emitting layer of the light emitting element LE may include nanorods.

[0090] Reference Figure 3 A first electrode (eg, an anode electrode) of the light emitting element LE may be electrically connected to the second node N2. A second electrode (eg, a cathode electrode) of the light emitting element LE may be electrically connected to the second power line PL2.

[0091] The second power voltage ELVSS is applied to the second power line PL2. The second power voltage ELVSS may be, for example, a ground voltage GND, or a low potential voltage having a level lower than the ground voltage GND.

[0092] The first transistor TR1 may be configured to switch the electrical connection between the first power line PL1 and the second node N2. The first transistor TR1 may include a gate electrode, a first electrode (one of a source electrode and a drain electrode), and a second electrode (the other of a source electrode and a drain electrode). The gate electrode of the first transistor TR1 may be electrically connected to the first node N1. The first electrode (e.g., the drain electrode) of the first transistor TR1 may be electrically connected to the first power line PL1. A first power supply voltage ELVDD may be applied to the first power line PL1. The first power supply voltage ELVDD may be, for example, a high potential voltage. The second electrode (e.g., the source electrode) of the first transistor TR1 may be electrically connected to the second node N2. A data voltage Vdata or a voltage corresponding to the data voltage Vdata may be applied to the first node N1. A current corresponding to the voltage applied to the first node N1 may flow through the first transistor TR1.

[0093] The second transistor TR2 is configured to switch the electrical connection between the data line DLj and the first node N1 (j is an integer greater than or equal to 1 and less than or equal to n). The operation timing of the second transistor TR2 can be controlled by the first scan signal SCAN[i]. The first scan signal SCAN[i] can be applied to the i-th first scan line SCLi (hereinafter referred to as the first scan line SCLi). The second transistor TR2 can be turned on in response to the first scan signal SCAN[i] at the on level. When the second transistor TR2 is turned on, the data voltage Vdata can be applied to the first node N1, thereby being applied to the gate electrode of the first transistor TR1.

[0094] The third transistor TR3 is configured to switch the electrical connection between the second node N2 and the reference voltage line RVLk. The operation timing of the third transistor TR3 can be controlled by the second scan signal SENSE[i]. The second scan signal SENSE[i] can be applied to the i-th second scan line SNLi (hereinafter referred to as the second scan line SNLi). The third transistor TR3 can be turned on in response to the second scan signal SENSE[i] being at an on level. When the third transistor TR3 is turned on, the second node N2 and the reference voltage line RVLk can be electrically connected. The voltage applied to the reference voltage line RVLk can be stored in the line capacitor Cline. The line capacitor Cline can be a capacitor element formed intentionally and physically, rather than a parasitic capacitor. However, embodiments of the present disclosure are not limited thereto.

[0095] Reference Figure 3 , each of the first transistor TR1, the second transistor TR2, and the third transistor TR3 may be a transistor including an N-type semiconductor layer. In this case, the on-level voltage of the first transistor TR1, the second transistor TR2, and the third transistor TR3 may be a high-level voltage (e.g., a gate high voltage), and the off-level voltage of the first transistor TR1, the second transistor TR2, and the third transistor TR3 may be a low-level voltage (e.g., a gate low voltage). In some embodiments, at least one of the first transistor TR1, the second transistor TR2, and the third transistor TR3 may include a P-type semiconductor layer. In this case, the on-level voltage of the transistor including the P-type semiconductor layer may be a low-level voltage (e.g., a gate low voltage), and the off-level voltage of the transistor including the P-type semiconductor layer may be a high-level voltage (e.g., a gate high voltage).

[0096] At least one of the first transistor TR1, the second transistor TR2, and the third transistor TR3 may include a semiconductor layer of amorphous silicon (a-Si). At least one of the first transistor TR1, the second transistor TR2, and the third transistor TR3 may include a semiconductor layer of polycrystalline silicon (poly-Si). At least one of the first transistor TR1, the second transistor TR2, and the third transistor TR3 may include a semiconductor layer containing a metal oxide.

[0097] The storage capacitor Cst may be configured to maintain a voltage difference between the first node N1 and the second node N2. The storage capacitor Cst may include one electrode (e.g., a first electrode) electrically connected to the first node N1 and another electrode (e.g., a second electrode) electrically connected to the second node N2. The storage capacitor Cst may be an intentionally and physically formed capacitor element rather than a parasitic capacitor.

[0098] The output circuit 122 may output the data voltage Vdata to the data line DLj (the data voltage applied to the data line DLj is referred to as data voltage Vdata[i−1], Vdata[i], Vdata[i+1]). The analog sensing voltage Vsen applied to the reference voltage line RVLk may be input to the sensing circuit 124 .

[0099] Figure 4 A sensing circuit 124 is shown according to an embodiment of the present disclosure.

[0100] The sensing circuit 124 may be included in the data driving circuit 120. The sensing circuit 124 may receive an analog sensing voltage Vsen from the reference voltage line RVLk. The sensing circuit 124 may convert the received analog sensing voltage Vsen into a corresponding digital value Dsen. The sensing circuit 124 may output the converted digital value Dsen.

[0101] Reference Figure 4 , the sensing circuit 124 may include a first switching element SW1 , a second switching element SW2 , a multiplexer MUX, a sensing capacitor Csen, and an analog-to-digital converter 410 .

[0102] The first switch element SW1 may be configured to switch the electrical connection between the third node N3 and the reference voltage line RVLk. The operation timing of the first switch element SW1 may be controlled by the reference voltage switch signal SPRE. When the first switch element SW1 is turned on in response to the reference voltage switch signal SPRE (e.g., the reference voltage switch signal SPRE of the on level), the reference voltage VREF may be applied to the reference voltage line RVLk. The first switch element SW1 may be implemented as a transistor.

[0103] The second switch element SW2 can be configured to switch the electrical connection between the reference voltage line RVLk and the sensing capacitor Csen. The operation timing of the second switch element SW2 can be controlled by the sampling control signal SAMP. When the second switch element SW2 is turned on by the sampling control signal SAMP (e.g., the sampling control signal SAMP of the on level), the analog sensing voltage Vsen or a voltage corresponding thereto can be stored in the sensing capacitor Csen.

[0104] The sensing capacitor Csen may include one electrode (e.g., a first electrode) electrically connected to the second switching element SW2 and another electrode (e.g., a second electrode) to which a constant voltage is applied (or grounded). A voltage corresponding to the analog sensing voltage Vsen may be applied to one electrode of the sensing capacitor Csen. The analog sensing voltage Vsen or a corresponding voltage may be stored in the sensing capacitor Csen.

[0105] The multiplexer MUX can be configured to switch the electrical connection between the sensing capacitor Csen and the analog-to-digital converter 410. For example, the multiplexer MUX can be implemented as an N:1 multiplexer, which includes two or more input terminals (e.g., N (N is an integer of 2 or greater) input terminals) and an output terminal. The operation timing of the multiplexer MUX can be controlled by the hold control signal HOLD. When the multiplexer MUX is turned on by the hold control signal HOLD (e.g., the hold control signal HOLD of the on level), the voltage stored in the sensing capacitor Csen connected (e.g., electrically connected) to the corresponding input terminal of the multiplexer MUX can be output. The voltage output from the multiplexer MUX can be input to the analog-to-digital converter 410.

[0106] The analog-to-digital converter 410 can be configured to convert an analog voltage into a corresponding digital value. Figure 4 The analog-to-digital converter 410 may receive the analog voltage output from the multiplexer MUX and may convert the received analog voltage into a corresponding digital value Dsen. The analog-to-digital converter 410 may output the converted digital value Dsen. The output digital value Dsen may be input to the timing controller 140 (see Figure 1 ).

[0107] Figure 5 The display device 100 (see FIG. Figure 1 ) is an example of a timing diagram for performing real-time sensing.

[0108] In the following, reference will be made to Figures 1 to 5 A timing diagram describing real-time sensing performed in the display device 100 according to an embodiment of the present disclosure.

[0109] The real-time sensing involves sensing a characteristic value of the first transistor TR1 to compensate for a change in the characteristic value of the first transistor TR1. The characteristic value of the first transistor TR1 sensed by the real-time sensing may be, for example, mobility.

[0110] The period during which real-time sensing is performed may include a first period PR1, a second period PR2, and a third period PR3. The first period PR1 may correspond to a writing period of a data voltage. The second period PR2 may correspond to an initialization period. The third period PR3 may correspond to a sampling period.

[0111] In the first period PR1, the data voltage Vdata[i] may be written to the pixel PXL (or sub-pixel SP) as the sensing target among the plurality of pixels PXL. In the first period PR1, the first switching element SW1 may be turned on, and the second switching element SW2 may be turned off. The reference voltage VREF may be applied to the reference voltage line RVLk. Figure 5, the initial voltage V0 of the reference voltage line RVLk may correspond to the reference voltage VREF.

[0112] In the first period PR1, the first scan signal SCAN[i] may be converted from a cut-off level to an on-level. During a period in which the first scan signal SCAN[i] of the on-level is input to the first scan line SCLi, a data voltage Vdata[i] may be applied to the data line DLj. The data voltage Vdata[i] may be written to the pixel PXL (or sub-pixel SP) as a sensing target. The data voltage Vdata[i] may be, for example, a data voltage for sensing the first transistor TR1. However, embodiments of the present disclosure are not limited thereto. In the first period PR1, the data voltage Vdata[i] may be applied to the first node N1. The data voltage Vdata[i] may be an on-level voltage of the first transistor TR1.

[0113] In the first period PR1, the second scan signal SENSE[i] may be converted from an off level to an on level. During a period in which the on-level second scan signal SENSE[i] is input to the second scan line SNLi, the second node N2 may be electrically connected to the reference voltage line RVL. The reference voltage VREF may be applied to the second node N2. The voltage of the second node N2 may be initialized to the reference voltage VREF.

[0114] In the second period PR2, the first switching element SW1 may be turned on. The reference voltage VREF may be applied to the reference voltage line RVL.

[0115] In the second period PR2, the second scan signal SENSE[i] of the on level is applied to the pixel PXL (or sub-pixel SP) as the sensing target among the plurality of pixels PXL. Therefore, the second node N2 and the reference voltage line RVL can be electrically connected for a sufficient time (for example, the first period PR1 and the second period PR2). The voltage of the second node N2 can be initialized to the reference voltage VREF within a more accurate range.

[0116] In the second period PR2, the storage capacitor Cst may charge a voltage corresponding to a difference between the data voltage Vdata[i] and the reference voltage VREF.

[0117] In the second period PR2, the second switching element SW2 may be turned on. The sensing capacitor Csen may be charged with a voltage corresponding to the analog sensing voltage Vsen.

[0118] In the third period PR3, the first switching element SW1 may be turned off, and the electrical connection between the reference voltage line RVLk and the third node N3 may be disconnected.

[0119] In the third period PR3, the second node N2 may be in a state where a constant voltage is not applied (or in a floating state). The first transistor TR1 may be turned on by a voltage applied to the first node N1, and charges may be accumulated in the second node N2 by a current flowing through the first transistor TR1. The voltage of the second node N2 may increase. In the third period PR3, a voltage difference between the voltage of the second node N2 and the second power supply voltage ELVSS may be less than a threshold voltage of the light emitting element LE. In the third period PR3, the light emitting element LE may not emit light.

[0120] In the third period PR3 , the second scan signal SENSE[i] of the on level may be applied to the pixel PXL (or the sub-pixel SP) as a sensing target among the plurality of pixels PXL The reference voltage line RVLk and the second node N2 may be electrically connected.

[0121] In the third period PR3, the second switch element SW2 may be turned on. For example, the second switch element SW2 may remain turned on. At a first time point t1 during the third period PR3, the first voltage V1 may be stored in the sensing capacitor Csen. At a second time point t2 during the third period PR3, the second voltage V2 may be stored in the sensing capacitor Csen.

[0122] During the third period PR3, the voltage increase amount per unit time of the second node N2 (or the slope of the voltage increase) may correspond to the characteristic value (e.g., mobility) of the first transistor TR1. For example, when the sampling voltages of the reference voltage line RVLk at the first time point t1 and the second time point t2 during the third period PR3 are the first voltage V1 and the second voltage V2, respectively, the mobility of the first transistor TR1 has a relationship between the above values ​​as shown in the following formula 1.

[0123] (Formula 1)

[0124]

[0125] In Formula 1, μ represents the mobility of the first transistor TR1. t2-t1 represents the time difference between the second time point t2 and the first time point t1. V2-V1 represents the voltage difference between the second voltage V2 and the first voltage V1. As a result, a change in the characteristic value (eg, mobility) of the first transistor TR1 can be sensed.

[0126] Figure 6 A block diagram of the timing controller 140 according to an embodiment of the present disclosure is shown.

[0127] The timing controller 140 according to an embodiment of the present disclosure may be implemented as a processor, for example. The timing controller 140 according to an embodiment of the present disclosure may include an interface block 610, a pattern detection block 620, a brightness detection block 630, and a real-time sensing block 640. Each of the interface block 610, the pattern detection block 620, the brightness detection block 630, and the real-time sensing block 640 may be implemented as a circuit in hardware.

[0128] The interface block 610 may be configured to convert the first image data DATA1 into the second image data DATA2. For example, the interface block 610 may convert the first image data DATA1 into the second image data DATA2 according to a preset interface (or a predefined standard).

[0129] The pattern detection block 620 may be configured to detect a pattern in the image data. For example, the pattern detection block 620 may be configured to detect a pattern (eg, a preset pattern) in the first image data DATA1 and / or the second image data DATA2 of the detection area. Figure 7 Example description. Pattern reference Figures 8 to 12 Exemplary description.

[0130] The brightness detection block 630 can be configured to detect the panel brightness value and the ratio of the light-emitting pixels. Figure 2 ) when emitting light based on the second image data DATA2, the panel brightness value may correspond to the brightness value (e.g., the overall brightness value or the local brightness value) of the display panel 110. The ratio of the pixels emitting light may refer to the ratio of the pixels PXL emitting light based on the second image data DATA2 among the plurality of pixels PXL. In some embodiments, the ratio of the pixels emitting light may refer to the plurality of sub-pixels SP (see Figure 1 ) is a ratio of sub-pixels SP that emit light based on the second image data DATA2 among the plurality of pixels PXL. Hereinafter, for better understanding and ease of description, the panel brightness value will be described by taking the overall brightness value of the display panel 110 when the plurality of pixels PXL emit light based on the second image data as an example. In addition, for better understanding and ease of description, the ratio of pixels that emit light will be described by taking the ratio of the pixels PXL that emit light based on the second image data DATA2 among the plurality of pixels PXL as an example. However, the embodiments of the present disclosure are not limited thereto. Reference will be made to Fig.13 The panel brightness value and the ratio of the pixels that emit light are exemplarily described.

[0131] The real-time sensing block 640 is configured to perform or stop real-time sensing based on whether a pattern is detected in the pattern detection block 620, the panel brightness value detected in the brightness detection block 630, and the ratio of the pixels that emit light. Fig.14 and Fig.15 An embodiment in which the real-time sensing block 640 performs or stops the real-time sensing is exemplarily described.

[0132] Figure 7 A display device 100 (see FIG. Figure 1 ) in an example of a detection area DTA.

[0133] The detection area DTA may be set to at least a portion of the display panel 110. In some embodiments, the detection area DTA may be set to the entire display area AA. In some embodiments, the detection area DTA may be set to a portion of the display area AA. Hereinafter, an embodiment in which the detection area DTA is set to a portion of the display area AA will be described as an example, but the embodiments of the present disclosure are not limited thereto.

[0134] The detection area DTA may overlap with one or more pixels PXL. For example, the detection area DTA may overlap with a plurality of pixels PXL.

[0135] In some embodiments, only one detection area DTA may be provided in the display area AA. In some embodiments, two or more detection areas DTA may be provided in the display area AA. Hereinafter, for better understanding and convenience of description, an embodiment in which two or more detection areas DTA are provided in the display area AA will be described as an example, but the embodiments of the present disclosure are not limited thereto.

[0136] In some embodiments, at least some of the plurality of detection areas DTA may be disposed in edge (eg, vertex) regions of the display area AA. In some embodiments, the remaining plurality of detection areas DTA may be disposed in a central region of the display area AA.

[0137] Reference Figure 7 , the first detection area DTA1, the second detection area DTA2, the third detection area DTA3, the fourth detection area DTA4 and the fifth detection area DTA5 can be set in the display area AA. The first detection area DTA1 to the fourth detection area DTA4 can be respectively set to correspond to the four vertices of the display area AA. For example, the first detection area DTA1 to the fourth detection area DTA4 can correspond to the four corners of the display area AA. The fifth detection area DTA5 can be set to correspond to the center of the display area AA.

[0138] In some embodiments, the sizes of the plurality of detection areas may all be the same. In some embodiments, at least one of the plurality of detection areas DTA may have a size different from that of the other detection areas DTA. The sizes of the first detection area DTA1 to the fifth detection area DTA5 may all be the same.

[0139] The shape of the detection area DTA can be set in various ways. Figure 7, showing an embodiment in which the first to fifth detection areas DTA1 to DTA5 are all set to a square shape. However, the embodiments of the present disclosure are not limited thereto, and the first to fifth detection areas DTA1 to DTA5 may be set to have various shapes, such as a rectangular shape, a circular shape, and a polygonal shape other than a quadrilateral shape.

[0140] The pattern detection block 620 (see Figure 6 ) can detect a pattern PTRN of an image displayed by a plurality of pixels PXL arranged to overlap with the detection area DTA. The pattern detection block 620 can compare the detected pattern PTRN with a preset pattern.

[0141] In the display area AA, at least one pixel of the display pattern PTRN among the plurality of pixels PXL may or may not emit light alternately according to the progress of the frame. For example, the processor (e.g., the timing controller 140) may control at least one pixel of the display pattern PTRN among the plurality of pixels PXL to alternate between emitting light and not emitting light according to the progress of the frame. Therefore, a low grayscale image can be expressed within a more precise range.

[0142] Figure 8 An example of the first pattern PTRN1 in the display device according to an embodiment of the present disclosure is shown.

[0143] Pattern detection block 620 (see Figure 6 ) can determine the detected pattern PTRN (see Figure 7 ) is the same as the first pattern PTRN1.

[0144] The first pattern PTRN1 may be a pattern in which pixels that emit light and pixels that do not emit light among the plurality of pixels PXL provided in the detection area DTA are repeated in one unit.

[0145] Reference Figure 8 , showing 36 pixels PXL arranged to overlap with the detection area DTA. The 36 pixels PXL may be arranged in 6 rows and 6 columns. The row direction may be the second direction DR2. The column direction may be the first direction DR1.

[0146] The first pixel PXL1, the second pixel PXL2, the third pixel PXL3, the fourth pixel PXL4, the fifth pixel PXL5 and the sixth pixel PXL6 may be arranged in the first row. The seventh pixel PXL7, the eighth pixel PXL8, the ninth pixel PXL9, the tenth pixel PXL10, the eleventh pixel PXL11 and the twelfth pixel PXL12 may be arranged in the second row. The thirteenth pixel PXL13, the fourteenth pixel PXL14, the fifteenth pixel PXL15, the sixteenth pixel PXL16, the seventeenth pixel PXL17 and the eighteenth pixel PXL18 may be arranged in the third row. The nineteenth pixel PXL19, the twentieth pixel PXL20, the twenty-first pixel PXL21, the twenty-second pixel PXL22, the twenty-third pixel PXL23 and the twenty-fourth pixel PXL24 may be arranged in the fourth row. The twenty-fifth pixel PXL25, the twenty-sixth pixel PXL26, the twenty-seventh pixel PXL27, the twenty-eighth pixel PXL28, the twenty-ninth pixel PXL29 and the thirtieth pixel PXL30 may be arranged in the fifth row. A thirty-first pixel PXL31 , a thirty-second pixel PXL32 , a thirty-third pixel PXL33 , a thirty-fourth pixel PXL34 , a thirty-fifth pixel PXL35 , and a thirty-sixth pixel PXL36 may be disposed in a sixth row.

[0147] The first pattern PTRN1 is described below by taking the first row and the second row as examples.

[0148] The first pixel PXL1 may be a light-emitting pixel. The second pixel PXL2 disposed adjacent to the first pixel PXL1 in the second direction DR2 may be a non-light-emitting pixel. The third pixel PXL3 disposed adjacent to the second pixel PXL2 in the second direction DR2 may be a light-emitting pixel. The fourth pixel PXL4 disposed adjacent to the third pixel PXL3 in the second direction DR2 may be a non-light-emitting pixel. The fifth pixel PXL5 disposed adjacent to the fourth pixel PXL4 in the second direction DR2 may be a light-emitting pixel. The sixth pixel PXL6 disposed adjacent to the fifth pixel PXL5 in the second direction DR2 may be a non-light-emitting pixel.

[0149] The seventh pixel PXL7 disposed adjacent to the first pixel PXL1 in the first direction DR1 may be a non-luminous pixel. The eighth pixel PXL8 disposed adjacent to the second pixel PXL2 in the first direction DR1 may be a luminous pixel. The ninth pixel PXL9 disposed adjacent to the third pixel PXL3 in the first direction DR1 may be a non-luminous pixel. The tenth pixel PXL10 disposed adjacent to the fourth pixel PXL4 in the first direction DR1 may be a luminous pixel. The eleventh pixel PXL11 disposed adjacent to the fifth pixel PXL5 in the first direction DR1 may be a non-luminous pixel. The twelfth pixel PXL12 disposed adjacent to the sixth pixel PXL6 in the first direction DR1 may be a luminous pixel.

[0150] In addition, pixels PXL13, PXL15, PXL17, PXL20, PXL22, PXL24, PXL25, PXL27, PXL29, PXL32, PXL34, and PXL36 may be pixels that emit light, and pixels PXL14, PXL16, PXL18, PXL19, PXL21, PXL23, PXL26, PXL28, PXL30, PXL31, PXL33, and PXL35 may be pixels that do not emit light.

[0151] According to the first pattern PTRN1 as described above, among the plurality of pixels PXL set in the detection area DTA, the luminous pixels and the non-luminous pixels can be repeated as a unit. Therefore, the overall brightness of the detection area DTA can be half the brightness of the luminous pixels in the detection area DTA. Therefore, a low grayscale image can be easily displayed in the detection area DTA.

[0152] Pattern detection block 620 (see Figure 6 ) can determine the detected pattern PTRN (see Figure 7 ) is the same as the first pattern PTRN1. When the detected pattern PTRN is the same as the first pattern PTRN1, a low grayscale image may be displayed in the detection area DTA.

[0153] Fig. 9 An example of the second pattern PTRN2 in the display device according to an embodiment of the present disclosure is shown.

[0154] The second pattern PTRN2 may be a pattern in which pixels that emit light and pixels that do not emit light among the plurality of pixels PXL provided in the detection area DTA are repeated in a plurality of units. Fig. 9 The second pattern PTRN2 may be a pattern in which pixels that emit light and pixels that do not emit light among the plurality of pixels PXL provided in the detection area DTA are repeated in two units.

[0155] The layout of the first pixel PXL1 to the thirty-sixth pixel PXL36 is similar to Figure 8 The layout is the same as that of FIG. 1 , so its description is omitted.

[0156] The second pattern PTRN2 is described below by taking the first row and the second row as examples.

[0157] The first pixel PXL1 may be a light-emitting pixel. The second pixel PXL2 disposed adjacent to the first pixel PXL1 in the second direction DR2 may be a light-emitting pixel. The third pixel PXL3 disposed adjacent to the second pixel PXL2 in the second direction DR2 may be a non-light-emitting pixel. The fourth pixel PXL4 disposed adjacent to the third pixel PXL3 in the second direction DR2 may be a non-light-emitting pixel. The fifth pixel PXL5 disposed adjacent to the fourth pixel PXL4 in the second direction DR2 may be a light-emitting pixel. The sixth pixel PXL6 disposed adjacent to the fifth pixel PXL5 in the second direction DR2 may be a light-emitting pixel.

[0158] The seventh pixel PXL7 disposed adjacent to the first pixel PXL1 in the first direction DR1 may be a non-luminous pixel. The eighth pixel PXL8 disposed adjacent to the second pixel PXL2 in the first direction DR1 may be a non-luminous pixel. The ninth pixel PXL9 disposed adjacent to the third pixel PXL3 in the first direction DR1 may be a luminous pixel. The tenth pixel PXL10 disposed adjacent to the fourth pixel PXL4 in the first direction DR1 may be a luminous pixel. The eleventh pixel PXL11 disposed adjacent to the fifth pixel PXL5 in the first direction DR1 may be a non-luminous pixel. The twelfth pixel PXL12 disposed adjacent to the sixth pixel PXL6 in the first direction DR1 may be a non-luminous pixel.

[0159] In addition, pixels PXL13, PXL14, PXL17, PXL18, PXL21, PXL22, PXL25, PXL26, PXL29, PXL30, PXL33, and PXL34 may be pixels that emit light, and pixels PXL15, PXL16, PXL19, PXL20, PXL23, PXL24, PXL27, PXL28, PXL31, PXL32, PXL35, and PXL36 may be pixels that do not emit light.

[0160] According to the second pattern PTRN2 as described above, among the plurality of pixels PXL set in the detection area DTA, the luminous pixels and the non-luminous pixels can be repeated in a plurality of units (e.g., two units). Therefore, the overall brightness of the detection area DTA can be half the brightness of the luminous pixels in the detection area DTA. Therefore, a low grayscale image can be easily displayed in the detection area DTA.

[0161] Pattern detection block 620 (see Figure 6 ) can determine the detected pattern PTRN (see Figure 7 ) is the same as the second pattern PTRN2. When the detected pattern PTRN is the same as the second pattern PTRN2, a low grayscale image can be displayed in the detection area DTA.

[0162] Fig.10 An example of the third pattern PTRN3 in the display device according to an embodiment of the present disclosure is shown.

[0163] The third pattern PTRN3 may be a pattern in which pixels that emit light and pixels that do not emit light among the plurality of pixels PXL provided in the detection area DTA are repeated in a plurality of units. Fig.10 The third pattern PTRN3 may be a pattern in which pixels that emit light and pixels that do not emit light among the plurality of pixels PXL provided in the detection area DTA are repeated in three units.

[0164] The layout of the first pixel PXL1 to the thirty-sixth pixel PXL36 is similar to Figure 8 The layout is the same as that of FIG. 1 , so its description is omitted.

[0165] The third pattern PTRN3 is described below by taking the first and second rows as examples.

[0166] The first pixel PXL1 may be a light-emitting pixel. The second pixel PXL2 disposed adjacent to the first pixel PXL1 in the second direction DR2 may be a light-emitting pixel. The third pixel PXL3 disposed adjacent to the second pixel PXL2 in the second direction DR2 may be a light-emitting pixel. The fourth pixel PXL4 disposed adjacent to the third pixel PXL3 in the second direction DR2 may be a non-light-emitting pixel. The fifth pixel PXL5 disposed adjacent to the fourth pixel PXL4 in the second direction DR2 may be a non-light-emitting pixel. The sixth pixel PXL6 disposed adjacent to the fifth pixel PXL5 in the second direction DR2 may be a non-light-emitting pixel.

[0167] The seventh pixel PXL7 disposed adjacent to the first pixel PXL1 in the first direction DR1 may be a non-luminous pixel. The eighth pixel PXL8 disposed adjacent to the second pixel PXL2 in the first direction DR1 may be a non-luminous pixel. The ninth pixel PXL9 disposed adjacent to the third pixel PXL3 in the first direction DR1 may be a non-luminous pixel. The tenth pixel PXL10 disposed adjacent to the fourth pixel PXL4 in the first direction DR1 may be a luminous pixel. The eleventh pixel PXL11 disposed adjacent to the fifth pixel PXL5 in the first direction DR1 may be a luminous pixel. The twelfth pixel PXL12 disposed adjacent to the sixth pixel PXL6 in the first direction DR1 may be a luminous pixel.

[0168] In addition, pixels PXL13, PXL14, PXL15, PXL22, PXL23, PXL24, PXL25, PXL26, PXL27, PXL34, PXL35, and PXL36 may be pixels that emit light, and pixels PXL16, PXL17, PXL18, PXL19, PXL20, PXL21, PXL28, PXL29, PXL30, PXL31, PXL32, and PXL33 may be pixels that do not emit light.

[0169] According to the third pattern PTRN3 as described above, among the plurality of pixels PXL set in the detection area DTA, the luminous pixels and the non-luminous pixels may be repeated in a plurality of units (e.g., three units). Therefore, the overall brightness of the detection area DTA may be half the brightness of the luminous pixels in the detection area DTA. Therefore, a low grayscale image may be easily displayed in the detection area DTA.

[0170] Pattern detection block 620 (see Figure 6 ) can determine the detected pattern PTRN (see Figure 7 ) is the same as the third pattern PTRN3. When the detected pattern PTRN is the same as the third pattern PTRN3, a low grayscale image can be displayed in the detection area DTA.

[0171] Fig.11 An example of a fourth pattern PTRN4 in a display device according to an embodiment of the present disclosure is shown.

[0172] Reference Fig.11 , showing 36 pixels PXL arranged to overlap with the detection area DTA. The 36 pixels PXL may be arranged in 6 rows and 6 columns. The row direction may be the second direction DR2. The column direction may be the first direction DR1.

[0173] The layout of the first pixel PXL1 to the thirty-sixth pixel PXL36 is similar to Figure 8 The layout is the same as that of FIG. 1 , so its description is omitted.

[0174] Each of the first to thirty-sixth pixels (PXL1 to PXL36) disposed overlapping with the detection area DTA may include a plurality of sub-pixels. Fig.11 , each of the first to thirty-sixth pixels PXL1 to PXL36 may include three sub-pixels SP1, SP2, and SP3. The three sub-pixels SP1, SP2, and SP3 may be disposed adjacent to each other in the second direction DR2.

[0175] The fourth pattern PTRN4 may be a pattern in which sub-pixels that emit light and sub-pixels that do not emit light among the plurality of sub-pixels SP provided in the detection area DTA are repeated in one unit.

[0176] The fourth pattern PTRN4 is described below by taking the first and second rows as examples.

[0177] The first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 of the first pixel PXL1 may be a subpixel that emits light, a subpixel that does not emit light, and a subpixel that emits light, respectively. The first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 of the second pixel PXL2 may be a subpixel that does not emit light, a subpixel that emits light, and a subpixel that does not emit light, respectively. The first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 of the third pixel PXL3 may be a subpixel that emits light, a subpixel that does not emit light, and a subpixel that emits light, respectively. The first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 of the fourth pixel PXL4 may be a subpixel that does not emit light, a subpixel that emits light, and a subpixel that does not emit light, respectively. The first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 of the fifth pixel PXL5 may be a subpixel that emits light, a subpixel that does not emit light, and a subpixel that emits light, respectively. The first subpixel SP1 , the second subpixel SP2 , and the third subpixel SP3 of the sixth pixel PXL6 may be a subpixel that does not emit light, a subpixel that emits light, and a subpixel that does not emit light, respectively.

[0178] The first subpixel SP1, the second subpixel SP2 and the third subpixel SP3 of the seventh pixel PXL7 may be a non-luminous subpixel, a luminous subpixel and a non-luminous subpixel, respectively. The first subpixel SP1, the second subpixel SP2 and the third subpixel SP3 of the eighth pixel PXL8 may be a luminous subpixel, a non-luminous subpixel and a luminous subpixel, respectively. The first subpixel SP1, the second subpixel SP2 and the third subpixel SP3 of the ninth pixel PXL9 may be a non-luminous subpixel, a luminous subpixel and a non-luminous subpixel, respectively. The first subpixel SP1, the second subpixel SP2 and the third subpixel SP3 of the tenth pixel PXL10 may be a luminous subpixel, a non-luminous subpixel and a luminous subpixel, respectively. The first subpixel SP1, the second subpixel SP2 and the third subpixel SP3 of the eleventh pixel PXL11 may be a non-luminous subpixel, a luminous subpixel and a non-luminous subpixel, respectively. The first subpixel SP1 , the second subpixel SP2 , and the third subpixel SP3 of the twelfth pixel PXL12 may be a subpixel that emits light, a subpixel that does not emit light, and a subpixel that emits light, respectively.

[0179] The pixels of the third and fifth rows may correspond to the pixels of the first row, and the pixels of the fourth and sixth rows may correspond to the pixels of the second row.

[0180] According to the fourth pattern PTRN4 as described above, among the plurality of sub-pixels SP provided in the detection area DTA, the emitting sub-pixels and the non-emitting sub-pixels may be repeated as a unit. Therefore, the overall brightness of the detection area DTA may be half the brightness of the emitting sub-pixels in the detection area DTA. Therefore, a low grayscale image may be easily displayed in the detection area DTA.

[0181] Pattern detection block 620 (see Figure 6 ) can determine the detected pattern PTRN (see Figure 7 ) is the same as the fourth pattern PTRN4. When the detected pattern PTRN is the same as the fourth pattern PTRN4, a low grayscale image can be displayed in the detection area DTA.

[0182] Fig.12 An example of a fifth pattern PTRN5 in the display device according to an embodiment of the present disclosure is shown.

[0183] The layout of the first pixel PXL1 to the thirty-sixth pixel PXL36 is similar to Figure 8 The layout of the first sub-pixel SP1 to the third sub-pixel SP3 is the same as that of Fig.11 The layout is the same as that of FIG. 1 , so its description is omitted.

[0184] The fifth pattern PTRN5 may be a pattern in which sub-pixels that emit light and sub-pixels that do not emit light among the plurality of sub-pixels SP provided in the detection area DTA are repeated in a plurality of units (for example, two units).

[0185] The fifth pattern PTRN5 is described below by taking the first and second rows as examples.

[0186] The first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 of the first pixel PXL1 may be a subpixel that emits light, a subpixel that emits light, and a subpixel that does not emit light, respectively. The first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 of the second pixel PXL2 may be a subpixel that does not emit light, a subpixel that emits light, and a subpixel that emits light, respectively. The first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 of the third pixel PXL3 may be a subpixel that does not emit light, a subpixel that does not emit light, and a subpixel that emits light, respectively. The first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 of the fourth pixel PXL4 may be a subpixel that emits light, a subpixel that does not emit light, and a subpixel that does not emit light, respectively. The first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 of the fifth pixel PXL5 may be a subpixel that emits light, a subpixel that emits light, and a subpixel that does not emit light, respectively. The first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 of the sixth pixel PXL6 may be a subpixel that does not emit light, a subpixel that emits light, and a subpixel that emits light, respectively.

[0187] The first subpixel SP1, the second subpixel SP2 and the third subpixel SP3 of the seventh pixel PXL7 may be a non-luminous subpixel, a non-luminous subpixel and a luminous subpixel, respectively. The first subpixel SP1, the second subpixel SP2 and the third subpixel SP3 of the eighth pixel PXL8 may be a luminous subpixel, a non-luminous subpixel and a non-luminous subpixel, respectively. The first subpixel SP1, the second subpixel SP2 and the third subpixel SP3 of the ninth pixel PXL9 may be a luminous subpixel, a luminous subpixel and a non-luminous subpixel, respectively. The first subpixel SP1, the second subpixel SP2 and the third subpixel SP3 of the tenth pixel PXL10 may be a non-luminous subpixel, a luminous subpixel and a luminous subpixel, respectively. The first subpixel SP1, the second subpixel SP2 and the third subpixel SP3 of the eleventh pixel PXL11 may be a non-luminous subpixel, a non-luminous subpixel and a luminous subpixel, respectively. The first subpixel SP1 , the second subpixel SP2 , and the third subpixel SP3 of the twelfth pixel PXL12 may be a subpixel that emits light, a subpixel that does not emit light, and a subpixel that does not emit light, respectively.

[0188] The pixels of the third and fifth rows may correspond to the pixels of the first row, and the pixels of the fourth and sixth rows may correspond to the pixels of the second row.

[0189] According to the fifth pattern PTRN5, among the plurality of sub-pixels SP provided in the detection area DTA, the luminous sub-pixels and the non-luminous sub-pixels may be repeated in a plurality of units (e.g., two units). Therefore, the overall brightness of the detection area DTA may be half the brightness of the luminous sub-pixels in the detection area DTA. Therefore, a low grayscale image may be easily displayed in the detection area DTA.

[0190] Pattern detection block 620 (see Figure 6 ) can determine the detected pattern PTRN (see Figure 7 ) is the same as the fifth pattern PTRN5. When the detected pattern PTRN is the same as the fifth pattern PTRN5, a low grayscale image can be displayed in the detection area DTA.

[0191] Fig.13 is used to explain the display device 100 (see Figure 1 ) in FIG. 1 . FIG. 1 is a diagram of the panel brightness value PBV in FIG. 1 .

[0192] Reference Fig.13 , the panel brightness value PBV may represent the overall brightness of the display panel 110. For example, the panel brightness value PBV ranges from 0 to 255. In the above embodiment, when the panel brightness value PBV is 0, it may represent that an image of 0 gray level is displayed in the entire display panel 110. An image of 0 gray level may be a black image, in which all pixels PXL provided in the display panel 110 do not emit light. In the above embodiment, when the panel brightness value PBV is 255, it may represent that an image of 255 gray level is displayed in the entire display panel 110. An image of 255 gray level may be a full white image, in which all pixels PXL provided in the display panel 110 emit light at a maximum gray level. When the panel brightness value PBV is low, it may be understood that a low gray level image is displayed in the entire display panel 110. When the panel brightness value PBV is high, it may be understood that a high gray level image is displayed in the entire display panel 110.

[0193] The low grayscale image may refer to an image whose panel brightness value PBV is between 1 and 23 (or between 1 and 23 grayscale levels), for example. In some embodiments, the low grayscale image may include an image whose panel brightness value PBV is between 0 and 1 (or between 0 grayscale level and 1 grayscale level). However, the embodiments of the present disclosure are not limited thereto.

[0194] Reference Fig.13, a plurality of pixels PXL provided in the display panel 110 may be divided into luminous pixels EPXL that emit light and non-luminous pixels BPXL that do not emit light. When the panel brightness value PBV is low, the luminous pixels EPXL emit light having a relatively high brightness, and by providing non-luminous pixels BPXL between the luminous pixels EPXL, a low grayscale image may be displayed in the display area AA. The ratio of luminous pixels may be calculated by dividing the number of luminous pixels EPXL by the number of the plurality of pixels PXL provided in the display area AA. In some embodiments, the ratio of luminous pixels may be replaced by a ratio of luminous sub-pixels. For example, in order to detect the above-mentioned first to third patterns PTRN1 to PTRN3 (see Figures 8 to 10 ), the ratio of the pixels that emit light can be used. For example, in order to detect the fourth pattern PTRN4 and the fifth pattern PTRN5 (see Fig.11 and Fig.12 ), the ratio of the sub-pixels that emit light can be used. Fig.13 , the ratio of pixels that emit light may be about 80%.

[0195] For example, when real-time sensing is performed while a low grayscale image is displayed in display area AA, the corresponding pixel rows may be displayed as dark lines. This may cause horizontal lines to be visible. In order to improve display quality, real-time sensing may be stopped while a low grayscale image is displayed, and real-time sensing may be performed while a high grayscale image is displayed.

[0196] Fig.14 An example of a flowchart of a driving method 1400 of a display device according to an embodiment of the present disclosure is shown.

[0197] Reference Fig.14 According to an embodiment of the present disclosure, a driving method 1400 of a display device may include: acquiring image data corresponding to a detection area (S1410); determining whether the image data of the detection area includes a pattern (S1420); determining whether a panel brightness value is within a set range and whether a ratio of emitted pixels is greater than or equal to a first threshold value (S1430); performing real-time sensing (S1440); and stopping real-time sensing (S1450).

[0198] When acquiring image data corresponding to the detection area (S1410), the pattern detection block 620 (see Figure 6 ) can obtain image data of the detection area DTA (see Figure 7 ). The acquired image data may be the first image data DATA1 (see Figure 6 ) and one of the second image data DATA2.

[0199] When determining whether the image data of the detection area includes a pattern (S1420), the pattern detection block 620 (see Figure 6 ) can detect a pattern PTRN in the image data. The pattern detection block 620 can determine whether the detected pattern PTRN corresponds to a set pattern (eg, a preset first pattern PTRN1 to a fifth pattern PTRN5).

[0200] When it is determined that the image data of the detection area includes a pattern, the stop of the real-time sensing may be performed (S1450). In other words, the real-time sensing block 640 (see Figure 6 ) can stop real-time sensing. Therefore, when it is determined that a low grayscale image is displayed, real-time sensing is stopped to prevent the horizontal line from becoming visible.

[0201] When it is determined that the image data of the detection area does not include a pattern, it may be performed to determine whether the panel brightness value is within the set range and whether the ratio of the pixels that emit light is greater than or equal to the first threshold value (S1430). When determining whether the panel brightness value is within the set range and whether the ratio of the pixels that emit light is greater than or equal to the first threshold value (S1430), the brightness detection block 630 (see Figure 6 ) can detect the ratio of the panel brightness value PBV and the emitted pixels.

[0202] The setting range may be, for example, 1 to 23. The first threshold may be, for example, 90%.

[0203] When the detected panel brightness value PBV is within the set range and the ratio of the pixels that emit light is greater than or equal to the first threshold, the stopping of the real-time sensing may be performed (S1450). Figure 6 ) can stop real-time sensing. Therefore, by stopping real-time sensing while displaying a low grayscale image, it is possible to prevent horizontal lines from being seen.

[0204] When the detected panel brightness value PBV is outside the set range or the ratio of the pixels that emit light is less than the first threshold, the execution of real-time sensing can be performed (S1440). Figure 6 ) can perform real-time sensing. Therefore, performing real-time sensing while displaying a high grayscale image can improve display quality.

[0205] Fig.15 Another example of a flowchart of a driving method 1500 of a display device according to an embodiment of the present disclosure is shown.

[0206] Reference Fig.15According to an embodiment of the present disclosure, a driving method 1500 of a display device may include: acquiring image data corresponding to a detection area (S1510); determining whether the image data of the detection area includes a pattern (S1520); determining whether a panel brightness value is within a set range and whether a ratio of emitted pixels is greater than or equal to a first threshold value (S1530); determining whether a panel brightness value is within a set range and whether a ratio of emitted pixels is greater than or equal to a second threshold value (S1540); performing real-time sensing (S1550); and stopping real-time sensing (S1560).

[0207] When acquiring image data corresponding to the detection area (S1510), the pattern detection block 620 (see Figure 6 ) can obtain image data of the detection area DTA (see Figure 7 ). The acquired image data may be the first image data DATA1 (see Figure 6 ) and one of the second image data DATA2.

[0208] When determining whether the image data of the detection area includes a pattern (S1520), the pattern detection block 620 (see Figure 6 ) can detect a pattern PTRN in the image data. The pattern detection block 620 can determine whether the detected pattern PTRN corresponds to a set pattern (eg, a preset first pattern PTRN1 to a fifth pattern PTRN5).

[0209] When it is determined that the image data of the detection area does not include a pattern, it may be performed to determine whether the panel brightness value is within the set range and whether the ratio of the pixels that emit light is greater than or equal to the first threshold value (S1530). When determining whether the panel brightness value is within the set range and whether the ratio of the pixels that emit light is greater than or equal to the first threshold value (S1530), the brightness detection block 630 (see Figure 6 ) can detect the ratio of the panel brightness value PBV and the emitted pixels.

[0210] The setting range may be, for example, 1 to 23. The first threshold may be, for example, 90%.

[0211] When the detected panel brightness value PBV is within the set range and the ratio of the pixels that emit light is greater than or equal to the first threshold, the stopping of the real-time sensing may be performed (S1560). Figure 6 ) can stop real-time sensing. Therefore, by stopping real-time sensing while displaying a low grayscale image, it is possible to prevent horizontal lines from being seen.

[0212] When the detected panel brightness value PBV is outside the first range or the ratio of the pixels emitting light is less than the first threshold, the execution of real-time sensing may be performed (S1550). Figure 6 ) can perform real-time sensing. Therefore, performing real-time sensing while displaying a high grayscale image can improve display quality.

[0213] When it is determined that the image data of the detection area includes a pattern, it is possible to perform a determination as to whether the panel brightness value is within a set range and whether the ratio of the pixels that emit light is greater than or equal to a second threshold value (S1540). The second threshold value may be different from the first threshold value. For example, the second threshold value may be less than the first threshold value. When determining whether the panel brightness value is within a set range and whether the ratio of the pixels that emit light is greater than or equal to the second threshold value (S1540), the brightness detection block 630 (see Figure 6 ) can detect the ratio of the panel brightness value PBV and the emitted pixels.

[0214] The setting range may be, for example, 1 to 23. The second threshold may be a value less than the ratio of the pixels that emit light in the first pattern PTRN1 to the third pattern PTRN3. The second threshold may be a value less than the ratio of the sub-pixels that emit light in the fourth pattern PTRN4 and the fifth pattern PTRN5. The second threshold may be, for example, 49%.

[0215] When the detected panel brightness value PBV is within the set range and the ratio of the pixels that emit light is greater than or equal to the second threshold, the step of stopping the real-time sensing S1560 may be performed. Figure 6 ) can stop real-time sensing. Therefore, by stopping real-time sensing while displaying a low grayscale image, it is possible to prevent horizontal lines from being seen.

[0216] When the detected panel brightness value PBV is outside the set range or the ratio of the pixels that emit light is less than the second threshold, the execution of real-time sensing can be performed (S1550). Figure 6 ) can perform real-time sensing. Therefore, while displaying a high grayscale image, the display quality can be improved by performing real-time sensing.

[0217] While the disclosure has been described in connection with what are presently considered to be exemplary embodiments, it should be understood that the disclosure is not limited to the disclosed embodiments, but on the contrary, the disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

[0218] According to a processor, a display device including the processor, and a method for driving the display device, a horizontal line can be prevented from becoming visible.

Claims

1. A processor, wherein: The processor comprises: an interface circuit configured to receive first image data and convert the first image data into second image data; a pattern detection circuit configured to detect a pattern in the first image data or the second image data; a brightness detection circuit configured to detect a panel brightness value, which is a brightness value at which the plurality of pixels emit light in response to the second image data, and to detect a ratio of pixels, among a plurality of pixels, that emit light in response to the second image data; and Real-time sensing circuit, wherein, when the pattern is not detected, the real-time sensing circuit performs or stops real-time sensing of the plurality of pixels based on whether the panel brightness value is within a set range and whether the ratio of the pixels that emit light is greater than or equal to a first threshold; and When the pattern is detected, the real-time sensing circuit performs or stops the real-time sensing of the plurality of pixels based on whether the panel brightness value is within the set range and whether the ratio of the pixels emitting light is greater than or equal to a second threshold.

2. The processor according to claim 1, wherein: When the pattern is not detected, The real-time sensing circuit stops the real-time sensing of the plurality of pixels when the panel brightness value is within the set range and the ratio of the pixels emitting light is greater than or equal to the first threshold, and The real-time sensing circuit performs the real-time sensing of the plurality of pixels when the panel brightness value is outside the set range or the ratio of the pixels emitting light is less than the first threshold.

3. The processor according to claim 1, wherein: When the pattern is detected, The real-time sensing circuit stops the real-time sensing of the plurality of pixels when the panel brightness value is within the set range and the ratio of the pixels emitting light is greater than or equal to the second threshold value, and The real-time sensing circuit performs the real-time sensing of the plurality of pixels when the panel brightness value is outside the set range or the ratio of the pixels emitting light is less than the second threshold.

4. The processor according to claim 1, wherein: The first threshold is greater than the second threshold.

5. The processor according to claim 1, wherein: At least one pixel displaying the pattern among the plurality of pixels is controlled to alternate between emitting light and not emitting light as a frame progresses.

6. A processor, wherein: The processor comprises: an interface circuit configured to receive first image data and convert the first image data into second image data; a pattern detection circuit configured to detect a pattern in the first image data or the second image data; a brightness detection circuit configured to detect a panel brightness value, which is a brightness value at which the plurality of pixels emit light in response to the second image data, and to detect a ratio of pixels, among a plurality of pixels, that emit light in response to the second image data; and Real-time sensing circuit, wherein, when the pattern is not detected, the real-time sensing circuit performs or stops real-time sensing of the plurality of pixels based on whether the panel brightness value is within a set range and whether the ratio of the pixels that emit light is greater than or equal to a set threshold; and When the pattern is detected, the real-time sensing circuit stops the real-time sensing of the plurality of pixels.

7. The processor according to claim 6, wherein: When the pattern is not detected, The real-time sensing circuit stops the real-time sensing of the multiple pixels when the panel brightness value is within the set range and the ratio of the luminous pixels is greater than or equal to the set threshold, and performs the real-time sensing of the multiple pixels when the panel brightness value is outside the set range or the ratio of the luminous pixels is less than the set threshold.

8. A display device, wherein: The display device comprises: A display panel comprising a plurality of pixels, a plurality of data lines electrically connected to the plurality of pixels, and a plurality of reference voltage lines electrically connected to the plurality of pixels; an output circuit configured to supply data voltages to the plurality of data lines; a sensing circuit configured to sense the plurality of pixels through the plurality of reference voltage lines; and a timing controller configured to control the driving timing of the output circuit and the sensing circuit, wherein the timing controller receives first image data and converts the first image data into second image data to be input to the output circuit; The timing controller detects a pattern in the first image data or the second image data; The timing controller detects a panel brightness value, which is a brightness value at which the plurality of pixels emit light in response to the second image data, and detects a ratio of pixels among the plurality of pixels that emit light in response to the second image data; When the pattern is not detected, the timing controller performs or stops real-time sensing of the plurality of pixels based on whether the panel brightness value is within a set range and whether the ratio of the pixels that emit light is greater than or equal to a set first threshold; and When the pattern is detected, the timing controller performs or stops the real-time sensing of the plurality of pixels based on whether the panel brightness value is within the set range and whether the ratio of the pixels emitting light is greater than or equal to a second threshold less than the first threshold.

9. The display device according to claim 8, wherein: When the pattern is not detected, The timing controller stops the real-time sensing of the plurality of pixels when the panel brightness value is within the set range and the ratio of the pixels emitting light is greater than or equal to the first threshold, and The timing controller performs the real-time sensing of the plurality of pixels when the panel brightness value is outside the set range or the ratio of the pixels emitting light is less than the first threshold.

10. The display device according to claim 8, wherein: When the pattern is detected, The timing controller stops the real-time sensing of the plurality of pixels when the panel brightness value is within the set range and the ratio of the pixels emitting light is greater than or equal to the second threshold, and The timing controller performs the real-time sensing of the plurality of pixels when the panel brightness value is outside the set range or the ratio of the pixels emitting light is less than the second threshold.

Images