Display panel and its compensation circuit, compensation method, controller and display device

Abstract

The present disclosure provides a compensation circuit of a display panel, and relates to the technical field of display, and can improve the yield of display products. The display panel comprises a pixel circuit, a data signal line and a driving circuit, and the data signal line is used for transmitting a data signal; the compensation circuit comprises: a gating sub-circuit electrically connected between the driving circuit and the data signal line, the gating sub-circuit comprising a first path and a second path connected in series, and the first path and the second path are both electrically connected with the data signal line; one end of a compensation signal line is electrically connected with the second path, and the other end of the compensation signal line is electrically connected with the driving circuit; the gating sub-circuit is used for controlling the first path to be turned on and the second path to be turned off under the action of a compensation control signal and the data signal, so that the data signal is transmitted to the pixel circuit through the first path and / or the data signal line; or, the gating sub-circuit is used for controlling the first path to be turned off and the second path to be turned on under the action of a compensation control signal and the potential on the data signal line, so that the compensation signal is transmitted to the pixel circuit through the second path.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically, to a compensation circuit for a display panel, a display panel, a compensation method for a display panel, a controller, and a display device. Background Technology

[0002] In a display panel, the driving circuit transmits driving signals and data signals to the pixel circuit, which then presents the image information corresponding to the data signals under the drive of the driving signals. To enhance the aesthetics of the display panel and increase the display area ratio, the bezel is narrowed or the film layers are thinned through stacking. However, the display panel manufacturing process involves bending, which can easily cause data signal lines to break, affecting data signal transmission and resulting in bright lines on the display panel. Products with bright lines are deemed defective during inspection, leading to lower product yield and increased costs.

[0003] Therefore, a new technical solution is urgently needed to solve the above-mentioned technical problems. Summary of the Invention

[0004] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. The summary section of this invention is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0005] In a first aspect, a compensation circuit for a display panel is provided, the display panel including a pixel circuit, a data signal line and a driving circuit, the data signal line being electrically connected between the pixel circuit and the driving circuit, and the data signal line being used to transmit data signals;

[0006] The compensation circuit includes:

[0007] A gating sub-circuit is electrically connected between the driving circuit and the data signal line. The gating sub-circuit includes a first path and a second path connected to each other. Both the first path and the second path are electrically connected to the data signal line.

[0008] A compensation control signal line, one end of which is electrically connected to the gating sub-circuit, and the other end of which is electrically connected to the driving circuit, the compensation control signal line being used to transmit the compensation control signal output by the driving circuit;

[0009] A compensation signal line, one end of which is electrically connected to the second path, and the other end of which is electrically connected to the driving circuit, the compensation signal line being used to transmit the compensation signal output by the driving circuit;

[0010] The gating sub-circuit is used to control the first path to be turned on and the second path to be turned off under the action of the compensation control signal and the data signal, so that the data signal is transmitted to the pixel circuit via the first path and / or the data signal line; or...

[0011] The gating sub-circuit is used to control the first path to be cut off and the second path to be turned on under the action of the compensation control signal and the potential on the data signal line, so that the compensation signal is transmitted to the pixel circuit via the second path.

[0012] In some embodiments, the compensation signal line includes a compensation signal transmission line and a compensation signal connection line, the compensation signal connection line being electrically connected to the gating sub-circuit and the compensation signal transmission line respectively, and the compensation signal transmission line being electrically connected to the driving circuit;

[0013] The compensation circuit includes k groups of the gating sub-circuits, each group of the gating sub-circuits being electrically connected to the same compensation signal connection line, where k is a natural number greater than 0.

[0014] In some embodiments, the length direction of the compensation signal transmission line intersects with the length direction of the compensation signal connection line.

[0015] In some implementations, at least one set of the gating sub-circuits is electrically connected to the pixel circuits in the same row.

[0016] In some embodiments, the display area of ​​the display panel includes a first area, a second area, and a third area, the first area, the second area, and the third area are arranged along a first direction, the first direction intersects the length direction of the compensation signal transmission line, the second area is located between the first area and the third area, and the compensation signal transmission line is disposed in the second area.

[0017] In some implementations, the line width of the compensation signal transmission line is greater than the line width of the data signal line.

[0018] In some embodiments, the display area of ​​the display panel includes a fourth area, a fifth area, and a sixth area, the fourth area, the fifth area, and the sixth area are arranged along a second direction, the second direction intersecting the length direction of the compensation signal connection line, the fifth area is located between the fourth area and the sixth area, the sixth area is located between the fifth area and the driving circuit, and the gating sub-circuit is disposed in the fifth area and / or the sixth area.

[0019] In some embodiments, the gating sub-circuit includes a first unit, a second unit, and a third unit, wherein the third unit includes the first path and the second path, and the nodes connecting the first path and the second path include a fourth node and a fifth node.

[0020] The first end of the first unit is electrically connected to the compensation control signal line, which is used to transmit the compensation control signal. The second end of the first unit and the data signal line are both electrically connected to the fourth node. The third end of the first unit is electrically connected to the first end of the second unit. The second end of the second unit is electrically connected to the fifth node.

[0021] The first unit is used to control the second unit to provide a control potential signal to the third unit under the influence of the compensation control signal and the potential on the data signal line;

[0022] Both the first path and the second path are used to be turned on or off under the action of the control potential signal, wherein when the first path is turned on, the second path is turned off; when the second path is turned on, the first path is turned off.

[0023] In some embodiments, the second unit includes a third path and a fourth path, and the connection point of the third path and the fourth path includes a sixth node and a seventh node; the third end of the first unit is electrically connected to the sixth node, and the seventh node is electrically connected to the fifth node;

[0024] The third path is used to connect to the first constant voltage, and the fourth path is used to connect to the second constant voltage. When the third path is on and the fourth path is off, the control potential signal is the first constant voltage. When the third path is off and the fourth path is on, the control potential signal is the second constant voltage.

[0025] In some embodiments, the second unit includes a first transistor and a second transistor, the first unit includes a third transistor, the first path includes a fourth transistor, and the second path includes a fifth transistor;

[0026] The gates of the first transistor and the second transistor are both connected to the sixth node, the gate of the third transistor is electrically connected to the compensation control signal line, the first electrode of the third transistor is electrically connected to the sixth node, and the second electrode of the third transistor is electrically connected to the fourth node.

[0027] The first electrode of the first transistor is used to connect to a first constant voltage, the first electrode of the second transistor is used to connect to a second constant voltage, and the second electrodes of the first transistor and the second transistor are both connected to the seventh node;

[0028] The gates of the fourth transistor and the fifth transistor are both electrically connected to the fifth node. The first electrodes of the fourth transistor and the fifth transistor are both electrically connected to the fourth node. The second electrode of the fourth transistor is electrically connected to the data signal line, and the second electrode of the fifth transistor is electrically connected to the compensation signal line.

[0029] In some embodiments, the second unit includes a second capacitor, the first terminal of which is electrically connected to the seventh node, and the second terminal of which is electrically connected to the fifth node; and / or,

[0030] The first transistor and the fifth transistor are transistors of the same type, and the second transistor and the fourth transistor are transistors of the same type.

[0031] In some implementations, the effective level start point of the compensation control signal is before the start point of the test pulse of the data signal, and the effective level end point of the compensation control signal is after the end point of the test pulse of the data signal.

[0032] Secondly, a display panel is provided, comprising:

[0033] Pixel circuit, data signal line, driving circuit and the compensation circuit described in the first aspect;

[0034] The compensation circuit is electrically connected to the pixel circuit, the data signal line, and the driving circuit, respectively.

[0035] Thirdly, a compensation method for a display panel is provided, applied to a compensation circuit for the display panel as described in the first aspect, the compensation method comprising:

[0036] In the event of an abnormality in the data signal line, the drive circuit is controlled to output the compensation control signal and the compensation signal, wherein the compensation signal corresponds to the data signal transmitted by the abnormal data signal line;

[0037] Under the influence of the compensation control signal and the potential on the data signal line, the first path is cut off and the second path is turned on, so that the gating sub-circuit transmits the compensation signal to the pixel circuit.

[0038] Fourthly, a controller is provided, comprising:

[0039] Memory, which stores computer programs;

[0040] A processor for invoking the computer program in the memory, the computer program for performing the compensation method as described in the third aspect.

[0041] Fifthly, a display device is provided, comprising a display panel as described in the second aspect and / or a controller as described in the fourth aspect.

[0042] The compensation circuit for the display panel of the present invention, other advantages, objectives and features of the present invention will be apparent in part from the following description, and in part will be understood by those skilled in the art through study and practice of the present invention. Attached Figure Description

[0043] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0044] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of exemplary embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0046] Figure 1 A schematic structural diagram of a display panel provided in an embodiment of this application;

[0047] Figure 2 A schematic partial structural diagram of a display module provided in an embodiment of this application;

[0048] Figure 3 A schematic circuit diagram of a pixel circuit provided for an embodiment of this application;

[0049] Figure 4A schematic diagram of the driving timing of a pixel circuit provided in an embodiment of this application;

[0050] Figure 5 A schematic structural diagram of another display panel provided in an embodiment of this application;

[0051] Figure 6 A schematic circuit diagram of a compensation circuit for a display panel provided in an embodiment of this application;

[0052] Figure 7 A schematic structural diagram of a gating sub-circuit provided for an embodiment of this application;

[0053] Figure 8 A schematic structural diagram of another gating sub-circuit provided in an embodiment of this application;

[0054] Figure 9 A schematic diagram of the driving timing of another pixel circuit provided in an embodiment of this application;

[0055] Figure 10 A schematic flowchart illustrating a compensation method for a display panel provided in an embodiment of this application;

[0056] Figure 11 A schematic structural block diagram of a controller provided in an embodiment of this application;

[0057] Figure 12 This is a schematic structural block diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0058] To better understand the above-mentioned objectives, features, and advantages of this application, the solution of this application will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.

[0059] The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus. The technical solutions of the embodiments of this application will now be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them.

[0060] Many specific details are set forth in the following description in order to provide a full understanding of this application, but this application may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some embodiments of this application, and not all embodiments.

[0061] With the continuous development of display technology, display panels have been widely used in the mobile phone market, leading to increasingly higher requirements for product performance and cost reduction. For current ultra-narrow bezel and stacked thinning designs, data signal lines are prone to breakage during the bending process, resulting in linear defects such as bright lines. After assembling into a complete module, the products undergo inspection, and those with such linear defects are identified as defective and scrapped, resulting in reduced yield and cost losses.

[0062] The first aspect of this application proposes a compensation circuit for a display panel. Figure 1 This is a schematic structural diagram of a display panel provided in an embodiment of this application. For example, as shown... Figure 1 As shown, the display panel 100 may include a pixel circuit 110, a data signal line 120, and a driving circuit 130. The data signal line 120 is electrically connected between the pixel circuit 110 and the driving circuit 130, and is used to transmit data signal V. data .

[0063] For example, refer to Figure 1 The pixel circuit 110 can drive sub-pixel display, and the sub-pixel array is arranged in an array. Data signal lines 120 extend along the second direction Y, and multiple data signal lines 120 are arranged along the first direction X. The data signal lines 120 can provide data signals V to the pixel circuit 110. dataA single data signal line 120 can connect to one or two columns of pixel circuits arranged along the second direction Y, but this application does not specifically limit the specific connection.

[0064] For example, refer to Figure 1 The display panel 100 includes a bending portion 101, which is a portion of the display panel used for bending. A driving circuit 130 can be integrated into the display panel 100; the driving circuit 130 can also be a driving chip, which is bonded to a bonding area of ​​the display panel via a bonding method. A data signal line 120 can cross the bending portion 101 and connect to the driving circuit 130.

[0065] Figure 2 This is a schematic partial structural diagram of a display module provided in an embodiment of this application. For example, refer to... Figure 2 The display module may include a cover plate CG, optical adhesive T-OCA, polarizer T-POL, display panel 100, buffer material layer U-Film, first support layer SCF, second support layer Bending Spacer, and protective material layer MCL. The cover plate CG is provided with an ink layer CG-P, which can be black ink to block light and prevent the shape of the corresponding part of the bent portion 101 from showing through the cover plate CG. The optical adhesive T-OCA can be used to adhere the cover plate and the polarizer. The bent portion 101 of the display panel can be bent to the side of the display panel away from the display area AA. The end of the bent portion 101 away from the display area AA can be connected to a flexible circuit board, which is disposed on the side of the display panel away from the display side D. The surface of the bent portion 101 may be provided with a protective material layer MCL to enhance the stress of the bent portion. The bent portion 101 has a bending radius R, and the distance between the bent portion 101 and the edge of the cover plate CG after bending is denoted as L.

[0066] For example, refer to Figure 1 and Figure 2 When the data signal line 120 crosses the area corresponding to the bend 101, during or after the bending process of the bend 101, the lines within the bend 120 are easily damaged, such as the data signal line or other signal lines breaking, which will cause abnormal data signal transmission or other signal transmission problems.

[0067] For example, OLED (Organic Light Emitting Display) panels are currently widely used in mobile phones. Semiconductor processes include two main approaches: LTPO (Low Temperature Polycrystalline Oxide) and LTPS (Low Temperature Polycrystalline Silicon). LTPO offers lower power consumption but is also more expensive. Pixel circuits in LTPO solutions can include circuit structures such as 7T1C (7 transistors and 1 capacitor) and 8T1C circuits. The 8T1C circuit, due to its initial signal conditioning, can achieve superior frequency cutting and flicker reduction.

[0068] Figure 3 This is a schematic circuit diagram of a pixel circuit provided for an embodiment of this application. For example, refer to... Figure 3 The pixel circuit has an 8T1C circuit structure, comprising eight transistors and one capacitor. The pixel circuit includes a first capacitor C1, a first driving transistor T1, a second driving transistor T2, a third driving transistor T3, a fourth driving transistor T4, a fifth driving transistor T5, a sixth driving transistor T6, a seventh driving transistor T7, and an eighth driving transistor T8. Each driving transistor includes a gate, a first electrode, and a second electrode. The first electrode can be either the source or the drain, and the second electrode can be either the source or the drain. One end of the first capacitor C1 is connected to the first node N1, and the other end is used to connect to the first power supply signal VDD. The first node N1 is connected to the gate of the third driving transistor T3. The second driving transistor T2 is connected between the first node N1 and the third node N3, and its gate is used to connect to the second gate signal Gate_N. The third driving transistor T3 is connected between the second node N2 and the third node N3. The second electrode of the first driving transistor T1 is connected to the third node N3. The second electrode of the first driving transistor T1 is used to receive the first initial signal Vinit1, and the gate of the first driving transistor T1 is used to receive the first reset signal P-Reset. The gate of the sixth driving transistor T6 is used to receive the enable signal EM. The first electrode of the sixth driving transistor T6 is connected to the third node N3. The second electrode of the sixth driving transistor T6 is connected to the anode of the light-emitting device, and the cathode of the light-emitting device is used to receive the second power signal VSS. The gate of the seventh driving transistor T7 is used to receive the second reset signal H-Reset. The second electrode of the seventh driving transistor T7 is connected to the anode of the light-emitting device, and the first electrode of the seventh driving transistor T7 is used to receive the second initial signal Vinit2. The gate of the fourth driving transistor T4 is used to receive the fourth gate signal Gate_P, and the first electrode of the fourth driving transistor T4 is used to receive the data signal V. dataThe second electrode of the fourth driving transistor T4 is connected to the second node N2. The gate of the eighth driving transistor T8 is used to receive the second reset signal H-Reset, the first electrode of the eighth driving transistor T8 is used to receive the third initial signal Vinit3, and the second electrode of the eighth driving transistor T8 is connected to the second node N2. The first electrode of the fifth driving transistor T5 is used to receive the first power supply signal VDD, the second electrode of the fifth driving transistor T5 is connected to the second node N2, and the gate of the fifth driving transistor T5 is used to receive the enable signal EM.

[0069] For example, refer to Figure 3 The second driving transistor T2 in the pixel circuit can be of type N, while the other driving transistors can be of type P.

[0070] Figure 4 This is a schematic diagram illustrating the driving timing of a pixel circuit according to an embodiment of this application. For example, refer to... Figure 3 and Figure 4 The display panel includes a scan drive circuit, which is electrically connected to the drive circuit 130 and the pixel circuit 110. The scan drive circuit can receive drive signals from the drive circuit 130. The drive signals include a synchronization signal TE, a first drive signal ESTV-P, a second drive signal RSTV-H, a third drive signal GSTV-P, a fourth drive signal GSTV-N, and a fifth drive signal RSTV-P. The synchronization signal TE is used to limit the time synchronization of each frame. The scan driving circuit can be set on opposite sides of the display area. The scan driving circuit can process the received driving signal and output the scan driving signal. The scan driving signal can include an enable signal EM, a second reset signal H-Reset, a fourth gate signal Gate_P, a second gate signal Gate_N, and a first reset signal P-Reset. The phase of the enable signal EM is the same as the phase of the first driving signal ESTV-P, the phase of the second reset signal H-Reset is the same as the phase of the second driving signal RSTV-H, the phase of the fourth gate signal Gate_P is the same as the phase of the third driving signal GSTV-P, the phase of the second gate signal Gate_N is the same as the phase of the fourth driving signal GSTV-N, and the phase of the first reset signal P-Reset is the same as the phase of the fifth driving signal RSTV-P.

[0071] For example, refer to Figures 1 to 4 If the data signal line 120 breaks due to bending during the manufacturing process, the data signal line 120 will be unable to transmit the data signal V normally. data In V data In cases where normal transmission fails, the third driving transistor T3 in the pixel circuit cannot obtain the normal data signal V at the fourth driving transistor T4. data That is, the V received by T3 of type Pdata =0, then V data When N2 is transmitted to the gate of T3 via T2, T3 can be turned on. During the lighting stage, T5 and T6 are also turned on. VDD can reach the anode of the light-emitting device via T5, T3 and T6, and the light-emitting device can be lit. If the broken data signal line cannot provide data signal to the connected light-emitting device, the light-emitting device will remain lit, which can easily lead to display bright lines defects, resulting in display panel defects and affecting the yield of the display panel.

[0072] Figure 5 A schematic structural diagram of another display panel provided in an embodiment of this application; Figure 6 This is a schematic circuit diagram of a compensation circuit for a display panel provided in an embodiment of this application. For example,... Figure 5 and Figure 6 As shown, the compensation circuit 140 of the display panel 100 may include: a gating sub-circuit 141, a compensation control signal line 142, and a compensation signal line 143. The gating sub-circuit 141 is electrically connected between the drive circuit 130 and the data signal line 120. The gating sub-circuit 141 includes a first path 141-1 and a second path 141-2 connected to each other, both of which are electrically connected to the data signal line 120. One end of the compensation control signal line 142 is electrically connected to the gating sub-circuit 141, and the other end is electrically connected to the drive circuit 130. The compensation control signal line 142 is used to transmit the compensation control signal EN output by the drive circuit 130. One end of the compensation signal line 143 is electrically connected to the second path 141-2, and the other end is electrically connected to the drive circuit 130. The compensation signal line 143 is used to transmit the compensation signal Sr output by the drive circuit 130.

[0073] For example, refer to Figure 5 The display panel 100 includes multiple arrayed sub-pixels, including red, blue, and green sub-pixels. A row of sub-pixels arranged along a first direction X is called a row of sub-pixels, and a column of sub-pixels arranged along a second direction Y is called a column of sub-pixels. R1,1 represents the first row and first column of red sub-pixels, G1,1 represents the first row and first column of green sub-pixels, B1,1 represents the first row and first column of blue sub-pixels, Gm-1,n represents the (m-1)th row and nth column of green sub-pixels, Gm,n represents the mth row and nth column of green sub-pixels, and so on. n represents the column number of the sub-pixel, m represents the row number of the sub-pixel, and both m and n are natural numbers greater than 0.

[0074] For example, refer to Figure 5The display panel 100 also includes scan signal lines for providing scan signals to the pixel circuit 110. The first row scan signal GT1 is used to drive the first row of sub-pixels, and the m-th row scan signal GTm is used to drive the m-th row of sub-pixels. Each sub-pixel has a corresponding pixel circuit 110, which is used to drive the sub-pixel display under the action of the scan signal and the data signal.

[0075] refer to Figure 6 The selection sub-circuit 141 can be used to control the first path 141-1 to be turned on and the second path 141-2 to be turned off under the combined action of the compensation control signal EN and the data signal, so that the data signal Sn of the nth column is transmitted to the pixel circuit 110 through the first path 141-1; the data signal Sn of the nth column can also be transmitted to the pixel circuit 110 simultaneously through the data signal line 120; the data signal Sn of the nth column can also be transmitted to the pixel circuit 110 alone through the data signal line 120. Meanwhile, the second path 141-2 is turned off, the compensation signal Sr will not be transmitted to the pixel circuit 110 through the second path 141-2, or the compensation signal Sr is an invalid signal and will not affect the normal driving of the pixel circuit. At this time, all data signal lines 120 can transmit data signals normally, and the data signal is a valid high-level signal. The nth column can be any column of pixel circuits. The data signal Sn of the nth column is used to drive the pixel circuit 110 of the nth column. If no abnormality occurs in the data signal line 120, such as no breakage, the data signal line 120 can transmit data signals normally to drive the pixel circuit 110.

[0076] refer to Figure 6The selection sub-circuit 141 is used to control the first path 141-1 to be cut off and the second path 141-2 to be turned on under the combined action of the compensation control signal EN and the potential on the data signal line 120, so that the compensation signal Sr is transmitted to the pixel circuit 110 via the second path 141-2. When the data signal line 120 malfunctions, i.e., it cannot transmit data signals normally (e.g., the data signal line is broken), the nth column data signal Sn transmitted by the data signal line 120 is an invalid signal (no signal, equivalent to 0), that is, the potential on the abnormal data signal line is 0. The compensation control signal EN and the invalid nth column data signal Sn can control the first path 141-1 to be cut off and the second path 141-2 to be turned on. Then the compensation signal Sr can be transmitted to the pixel circuit 110 via the second path 141-2, that is, the compensation signal Sr can be transmitted to the corresponding nth column pixel circuit via the second path 141-2 and the data signal line. The compensation signal can have the same signal value as the data signal. It serves as a substitute for the abnormal data signal transmitted by the faulty data signal line, allowing it to drive the pixel circuit normally and ensure proper display on the display panel, thus preventing display defects caused by broken data signal lines. It should be noted that although the faulty data signal line 120 may experience breakage or other abnormalities, if the breakage occurs in the area of ​​the bend 101, the data signal lines in the pixel circuit area can still transmit the signal provided by the gating sub-circuit 141 normally.

[0077] It should be noted that the compensation circuit, by providing a compensation signal, can repair abnormal problems of abnormal data signal lines. It does not repair the abnormal data signal lines, but rather replaces the transmission of signals that the abnormal signal lines cannot transmit, thereby improving the yield of the corresponding downstream products of the display panel and avoiding cost losses.

[0078] For example, the pin connected to the driving circuit corresponding to the compensation signal Sr can be used as a replacement pin for the pin connected to the driving circuit corresponding to any abnormal data signal line, thereby achieving the repair of the bright line defect corresponding to the abnormal data signal line.

[0079] For example, in the event of a broken data signal line, the output of the pin corresponding to the abnormal data signal line will be cut off inside the drive circuit. The data signal originally sent to the abnormal data signal line will be transferred (transformed the transmission channel) to the pin corresponding to the compensation signal line and output to the corresponding pixel circuit in the form of a compensation signal to achieve the repair of bright line defects.

[0080] For example, refer to Figure 6The compensation control signal EN can be provided by the drive circuit 130. The drive circuit can generate and send the compensation control signal EN when any data signal line breakage is detected. This compensation control signal, through the compensation circuit, provides a compensation signal to the pixel circuit, preventing the corresponding pixel circuit from failing to drive properly due to abnormal breakage of the data signal line. Abnormal breakage of the data signal line can be caused by bending processes or by foreign matter in the film layer.

[0081] For example, refer to Figure 5 and Figure 6 During the driving process of each frame of the display panel, each data signal line 120 receives a pulse during the pre-charging phase of each frame, which is the test pulse of the data signal. The pre-charging phase is the pre-charging period before the lighting phase of the light-emitting device. The time segment corresponding to the effective level of the compensation control signal EN includes the test pulse period of the data signal, which ensures that each data signal line 120 has its own voltage, i.e., the voltage of the data signal. That is, the pulse amplitude of the test pulse is the voltage of the data signal provided by the driving circuit. If one of the data signal lines 120 breaks, the selection circuit 141 will not receive the high level on the data signal line, i.e., the effective voltage value of the test pulse of the data signal, i.e., Sn. Then, the driving circuit can control the pin that provides Sn to input Sn to the pin used to output the compensation signal Sr, so as to provide the compensation signal Sr to the selection circuit 141. This is a process of re-establishing the signal path, that is, cutting off the original Sn output path and establishing the output Sr path. Then, within a certain error range, Sn = Sr.

[0082] It should be noted that the driver circuit can reserve a certain number of blank pins, which can be used as pins for the output compensation signal Sr.

[0083] The compensation circuit for the display panel provided in this application embodiment includes a gating sub-circuit, a compensation control signal line, and a compensation signal line. The gating sub-circuit comprises a first path and a second path, and is connected between the data signal line and the driving circuit. When the data signal line is normal, the gating sub-circuit, under the combined action of the data signal and the compensation control signal, can ensure the normal transmission of the data signal to the pixel circuit without affecting the normal display of the display panel. When the data signal line in the bent area is broken, the gating sub-circuit, under the influence of the abnormal potential on the invalid data signal line and the compensation control signal, provides a compensation signal to the pixel circuit. This repairs the inability of the abnormal data signal line to provide a data signal, preventing display defects caused by broken data signal lines, thereby improving the yield of downstream products of the display panel and avoiding cost losses.

[0084] In some implementations, reference Figure 5 The compensation signal line 143 may include a compensation signal transmission line 143-1 and a compensation signal connection line 143-2. ​​The compensation signal connection line 143-2 is electrically connected to both the gating sub-circuit 141 and the compensation signal transmission line 143-1. The compensation signal transmission line 143-1 is electrically connected to the driving circuit 130. The compensation signal transmission line 143-1 can be used to transmit the compensation signal Sr output by the driving circuit 130 to the compensation signal connection line 143-2. ​​The compensation signal connection line 143-2 can provide the received compensation signal Sr to multiple gating sub-circuits 141.

[0085] For example, refer to Figure 5 The compensation circuit 140 may include multiple gating sub-circuits 141, which may be arranged along the length direction of the compensation signal connection line 143-2. ​​The length direction of the compensation signal transmission line 143-1 intersects the length direction of the compensation signal connection line 143-2. ​​Since the length directions of the compensation signal transmission line 143-1 and the compensation signal connection line 143-2 are not the same, it is easier to transmit the compensation signal Sr to the multiple gating sub-circuits 141 through one compensation signal transmission line 143-1 and one compensation signal connection line.

[0086] For example, refer to Figure 5 Each data signal line 120 is connected to a column of pixel circuits 110, and each scan signal line is connected to a row of pixel circuits 110. Multiple gating sub-circuits 141 are arranged in a row along the first direction X. Each gating sub-circuit 141 is connected one-to-one with a data signal line 120; that is, one gating sub-circuit 141 can compensate for one data signal line 120, and thus one gating sub-circuit 141 can compensate for one column of pixel circuits 110. The length direction of the compensation signal transmission line 143-1 can be the same as the second direction Y, and the length direction of the compensation signal connection line 143-2 can be the same as the first direction X. Therefore, the length direction of the compensation signal transmission line 143-1 can be the same as the length direction of the data signal line 120.

[0087] In some examples, the length direction of the compensation signal transmission line 143-1 can be the same as that of the data signal line 120, and both the compensation signal transmission line 143-1 and the data signal line 120 are connected to the drive circuit 130. In this case, both the compensation signal transmission line 143-1 and the data signal line 120 need to cross the area where the bend 101 is located to connect to the drive circuit. Therefore, the compensation signal transmission line 143-1 is also at risk of bending and breaking. To reduce the risk of bending and breaking of the compensation signal transmission line 143-1, its line width can be set to be greater than that of the data signal line 120. Since there are many data signal lines 120 and the wiring space is limited, the line width of the data signal lines 120 cannot be too wide. If there is only one compensation signal transmission line 143-1, its line width can be made wider to ensure it is not easily broken and to guarantee the compensation and repair effect.

[0088] In some implementations, reference Figure 5 The display panel 100 includes a first region 102, a second region 103, and a third region 104. These three regions are arranged along a first direction X, which intersects the length direction of the compensation signal transmission line 143-1. The second region 103 is located between the first region 102 and the third region 104, meaning the second region 103 is the middle region, and the first region 102 and the third region 104 are the regions on either side of the first direction. The compensation signal transmission line 143-1 is located in the second region 103. Due to the positional limitations on both sides of the display area along the first direction X, i.e.... Figure 5 As shown in the lower left and lower right corner areas, the data signal line 120 needs to be connected to the drive circuit 130 by a bend, which increases the risk of line bending damage. Therefore, the compensation signal transmission line 143-1 is set in the second area 103 to avoid the routing bends in the lower left and lower right corner areas. The compensation signal transmission line 143-1 can be without bending or with a small bending angle to avoid bending damage.

[0089] In some implementations, reference Figure 5The display area of ​​the display panel 100 may include a fourth area 105, a fifth area 106, and a sixth area 107. The fourth area 105, fifth area 106, and sixth area 107 are arranged along a second direction Y, which intersects the length direction of the compensation signal transmission line 143-2. ​​The fifth area 106 is located between the fourth area 105 and the sixth area 107, and the sixth area 107 is located between the fifth area 106 and the driving circuit 130. A selection sub-circuit 141 is disposed in the fifth area 106; the selection sub-circuit 141 may also be disposed in the sixth area 107; both the fifth area 106 and the sixth area 107 may contain a selection sub-circuit 141. The fifth area 106 and the sixth area 107 are closer to the driving circuit 130 than the fourth area 105. Placing the selection sub-circuit 141 close to the driving circuit 130 avoids signal attenuation caused by excessive length of the compensation signal transmission line 143-1.

[0090] In some implementations, the compensation circuit 140 includes k groups of gating sub-circuits, each group of gating sub-circuits being electrically connected to the same compensation signal connection line 143-2, where k is a natural number greater than 0 and k≤m.

[0091] In some examples, reference Figure 5 With k=1, a set of gating sub-circuits is set in the display panel. The number of gating sub-circuits 141 in this set of gating sub-circuits is equal to the total number of data signal lines. This set of gating sub-circuits is arranged in a row, and this row of gating sub-circuits 141 can be set between the pixel circuits of adjacent rows.

[0092] In some examples, the number of gating sub-circuits in each group of gating sub-circuits may be different or the same. For example, the number of gating sub-circuits in the first group is p1, the number of gating sub-circuits in the second group is p2, and so on. The sum of p1, p2, ..., pk-1 and pk can be equal to the number of data signal lines 120. This ensures that each data signal line 120 is connected to a gating sub-circuit 141, which can drive and repair abnormal data signal lines. The data signal corresponding to the abnormal data signal line is then provided to the corresponding pixel circuit through the gating sub-circuit 141 to obtain a normal display image and reduce display product defects.

[0093] In some examples, at least one set of gating sub-circuits is electrically connected to the pixel circuitry in the same row.

[0094] For example, k=m, each row of pixel circuits corresponds to a set of gating sub-circuits, and each gating sub-circuit 141 of each set of gating sub-circuits is connected to a data signal line 120, which can ensure that the compensation signal is provided to the corresponding pixel circuit.

[0095] In some implementations... Figure 7This is a schematic structural diagram of a gating sub-circuit provided in an embodiment of this application. For example... Figure 7 As shown, the selection sub-circuit 141 includes a first unit 144, a second unit 145, and a third unit 146. The third unit 146 includes a first path 141-1 and a second path 141-2. The nodes connecting the first path 141-1 and the second path 141-2 include a fourth node N4 and a fifth node N5. The first terminal 401 of the first unit 144 is electrically connected to the compensation control signal line 142, which is used to transmit the compensation control signal EN. The second terminal 402 of the first unit 144 and the data signal line 120 are both electrically connected to the fourth node N4. The third terminal 403 of the first unit 144 is electrically connected to the first terminal 501 of the second unit 145, and the second terminal 502 of the second unit 145 is electrically connected to the fifth node N5. The first unit 144 is used to control the second unit 145 to provide a control potential signal to the third unit 146 under the action of the compensation control signal EN and the potential on the data signal line 120. Both the first path 141-1 and the second path 141-2 are used to turn on or off under the action of the control potential signal. When the first path 141-1 is on, the second path 141-2 is off; when the second path 141-2 is on, the first path 141-1 is off. When the first path 141-1 is on and the second path 141-2 is off, the compensation signal Sr will not be transmitted to the fourth node N4, meaning the compensation signal Sr will not be transmitted to the data signal line 120. The nth column data signal Sn on the data signal line 120 can be transmitted to the fourth node N4 through the first path 141-1. In other words, the data signal line 120 can short-circuit the first path 141-1 without affecting the data signal's driving of the pixel circuit. When the first path 141-1 is off and the second path 141-2 is on, the compensation signal Sr can be transmitted to the fourth node N4 via the second path 141-2, and then to the data signal line. Therefore, the compensation signal Sr can replace the data signal that the abnormal data signal line cannot transmit, thus driving the pixel circuit normally.

[0096] In some implementations, reference Figure 7The second unit 145 includes a third path 145-1 and a fourth path 145-2. The connection points of the third path 145-1 and the fourth path 145-2 include a sixth node N6 and a seventh node N7. The third path 145-1 is used to connect to a first constant voltage VGL, and the fourth path 145-2 is used to connect to a second constant voltage VGH. The potential of the second constant voltage VGH is greater than that of the first constant voltage VGL. The second constant voltage VGH is a high-level signal, and the first constant voltage VGL is a low-level signal. The third terminal 403 of the first unit 144 is electrically connected to the sixth node N6, and the seventh node N7 is electrically connected to the fifth node N5. The first unit 144 can transmit signals to the sixth node N6 of the second unit 145 under the influence of the compensation control signal EN and the potential of the data signal line 120. The first unit 144 can control the conduction or cutoff of the third path 145-1 and the fourth path 145-2; when the third path 145-1 is on, the fourth path 145-2 is off. When the third pathway 145-1 is blocked, the fourth pathway 145-2 is activated.

[0097] refer to Figure 7 When the third path 145-1 is on and the fourth path 145-2 is off, the first constant voltage VGL is transmitted to the fifth node N5 via the third path 145-1, and the control potential signal is the first constant voltage VGL. When the third path 145-1 is off and the fourth path 145-2 is on, the second constant voltage VGH is transmitted to the fifth node N5 via the fourth path 145-2, and the control potential signal is the second constant voltage VGH.

[0098] In some examples, Figure 8 A schematic structural diagram of another gating sub-circuit provided in an embodiment of this application. (Refer to...) Figure 8The second unit 145 includes a first transistor T01 and a second transistor T02. The first unit 144 includes a third transistor T03. The first path 141-1 includes a fourth transistor T04, and the second path 141-2 includes a fifth transistor T05. The gates of the first transistor T01 and the second transistor T02 are both connected to the sixth node N6. The gate of the third transistor T03 is electrically connected to the compensation control signal line 142. The first electrode of the third transistor T03 is electrically connected to the sixth node N6, and the second electrode of the third transistor T03 is electrically connected to the fourth node N4. The first electrode of the transistor is one of the source and the drain, and the second electrode is the other of the source and the drain. The first electrode of the first transistor T01 is used to connect to the first constant voltage VGL, and the first electrode of the second transistor T02 is used to connect to the second constant voltage VGH. The second electrodes of both the first transistor T01 and the second transistor T02 are connected to the seventh node N7. The gates of the fourth transistor T04 and the fifth transistor T05 are both electrically connected to the fifth node N5. The first electrodes of the fourth transistor T04 and the fifth transistor T05 are both electrically connected to the fourth node N4. The second electrode of the fourth transistor T04 is electrically connected to the data signal line 120. The second electrode of the fifth transistor T05 is electrically connected to the compensation signal line 143.

[0099] In some examples, reference Figure 8 The second unit 145 includes a second capacitor Cst, the first end of the second capacitor Cst is electrically connected to the seventh node N7, and the second end of the second capacitor Cst is electrically connected to the fifth node N5.

[0100] In some examples, the first transistor T01 and the fifth transistor T05 are transistors of the same type, and the second transistor T02 and the fourth transistor T04 are transistors of the same type.

[0101] It should be noted that the third transistor T03 can be either P-type or N-type, without any specific limitation.

[0102] For example, refer to Figure 8 The first transistor T01 and the fifth transistor T05 are both P-type transistors (Pmos), and the second transistor T02 and the fourth transistor T04 are both N-type transistors (Nmos).

[0103] In some implementations, the effective level start point of the compensation control signal is before the start point of the test pulse of the data signal, and the effective level end point of the compensation control signal is after the end point of the test pulse of the data signal.

[0104] Figure 9 This is a schematic diagram illustrating the driving timing of another pixel circuit provided in an embodiment of this application. For example, refer to... Figure 9When all data signal lines are intact, during the pre-charge phase T0 of each frame display, the compensation control signal EN is pulled low, causing the P-type third transistor T03 to turn on. The high level of the test pulse pulse for the nth column data signal Sn enters the gates of the first transistor T01 and the second transistor T02, causing T02 of NMOS to turn on and T01 to turn off. This allows Cst to be charged with a high voltage, causing T04 to turn on and T05 to turn off. Therefore, Sr does not enter N4, meaning Sr does not enter the N4 data signal line 120. The normal Sn is unaffected, and the pixel circuit drives normally. If a data signal line breaks, specifically the nth column data signal line, there is no test pulse during the pre-charge phase T0 of each frame display. At this time, T01 and T05 turn on, and Sr enters the nth column data signal line, completing the repair.

[0105] For example, when all data signal lines are intact, during the pre-charge phase T0 of each frame display, the compensation control signal EN is pulled high. This turns on the third N-type transistor T03, and the high level of the test pulse pulse for the nth column data signal Sn enters the gates of the first transistor T01 and the second transistor T02, causing T02 of NMOS to turn on and T01 to turn off. This allows Cst to be charged with a high voltage, causing T04 to turn on and T05 to turn off. Therefore, Sr does not enter N4, meaning Sr does not enter the N4 data signal line 120. The normal Sn is unaffected, and the pixel circuit drives normally. When a data signal line breaks, specifically the nth column data signal line, there is no test pulse during the pre-charge phase T0 of each frame display. At this time, T01 and T05 turn on, and Sr enters the nth column data signal line, completing the repair.

[0106] For example, refer to Figure 8 The effective level start point a2 (falling edge start point of low level) of the compensation control signal EN precedes the test pulse start point a1 (rising edge start point of high level) of the nth column data signal Sn, and the effective level end point b2 (rising edge end point of low level) of the compensation control signal EN follows the test pulse end point b1 (falling edge end point of high level) of the nth column data signal Sn. During display driving, the effective level period of the compensation control signal EN includes the effective level period of the data signal test pulse, ensuring that the test pulse enters the gating sub-circuit.

[0107] Secondly, embodiments of this application provide a display panel, referencing Figure 5 The display panel includes: a pixel circuit 110, a data signal line 120, a driving circuit 130, and a compensation circuit 140 as described in the first aspect; the compensation circuit 140 is electrically connected to the pixel circuit 110, the data signal line 120, and the driving circuit 130, respectively.

[0108] The display panel provided in this application embodiment includes a compensation circuit. This compensation circuit comprises a gating sub-circuit, a compensation control signal line, and a compensation signal line. The gating sub-circuit includes a first path and a second path, and is connected between the data signal line and the driving circuit. When the data signal line is normal, the gating sub-circuit, under the combined action of the data signal and the compensation control signal, can ensure the normal transmission of the data signal to the pixel circuit without affecting the normal display of the display panel. When the data signal line in the bent area is broken, the gating sub-circuit, under the influence of the abnormal potential on the invalid data signal line and the compensation control signal, provides a compensation signal to the pixel circuit. This repairs the inability of the abnormal data signal line to provide a data signal, preventing display defects caused by broken data signal lines, thereby improving the yield of downstream products of the display panel and avoiding cost losses.

[0109] Thirdly, embodiments of this application provide a compensation method for a display panel, applied to the compensation circuit of the display panel as described in the first aspect. Figure 10 This is a schematic flowchart illustrating a compensation method for a display panel provided in an embodiment of this application. Figure 10 As shown, the compensation method includes:

[0110] S201: In the event of an abnormality in the data signal line, the control drive circuit outputs a compensation control signal and a compensation signal, wherein the compensation signal corresponds to the data signal transmitted by the abnormal data signal line.

[0111] S202: Under the influence of the potential on the compensation control signal and data signal lines, the first path is cut off and the second path is turned on, so that the gating sub-circuit transmits the compensation signal to the pixel circuit.

[0112] For example, refer to Figure 5 and Figure 6During the driving process of each frame of the display panel, each data signal line 120 receives a pulse during the pre-charging phase of each frame, which is the test pulse of the data signal. The pre-charging phase is the pre-charging period before the lighting phase of the light-emitting device. The time segment corresponding to the effective level of the compensation control signal EN includes the test pulse period of the data signal, which ensures that each data signal line 120 has its own voltage, i.e., the voltage of the data signal. That is, the pulse amplitude of the test pulse is the voltage of the data signal provided by the driving circuit. If one of the data signal lines 120 breaks, the selection circuit 141 will not receive the high level on the data signal line, i.e., the effective voltage value of the test pulse of the data signal, i.e., Sn. Then, the driving circuit can control the pin that provides Sn to input Sn to the pin used to output the compensation signal Sr, so as to provide the compensation signal Sr to the selection circuit 141. This is a process of re-establishing the signal path, that is, cutting off the original Sn output path and establishing the output Sr path. Then, within a certain error range, Sn = Sr.

[0113] In some examples, the compensation method for the display panel also includes:

[0114] Automatic optical inspection is performed on the illuminated display panel or display module to confirm whether there are any display defects. Display defects may include bright lines caused by abnormal breakage of data signal lines. Bright lines can be detected in the detection results of automatic optical inspection.

[0115] If a display defect is detected, and the defect is a linear defect in the column direction, the data signal of that column can be continued to be transmitted to the pixel circuit of that column through the compensation circuit, so as to drive the pixel circuit of that column normally for display driving, thereby repairing the defect caused by the data signal line.

[0116] Fourthly, Figure 11 This is a schematic structural block diagram of a controller provided in an embodiment of this application. Figure 11 As shown, a controller 300 includes: a memory 310 storing a computer program; and a processor 320 for calling the computer program in the memory 310, the computer program being used to execute the compensation method as described in the third aspect.

[0117] For example, the controller 300 may be integrated into the drive circuit or into the control motherboard connected to the display panel.

[0118] Fifthly, Figure 12 This is a schematic structural block diagram of a display device provided in an embodiment of this application. Figure 12 As shown, a display device includes a display panel 1000 as described in the second aspect.

[0119] In some examples, the display device includes a controller as described in the fourth aspect.

[0120] The display device provided in this application embodiment includes a compensation circuit within the display panel. This compensation circuit comprises a gating sub-circuit, a compensation control signal line, and a compensation signal line. The gating sub-circuit includes a first path and a second path, and is connected between the data signal line and the driving circuit. When the data signal line is normal, the gating sub-circuit, under the combined action of the data signal and the compensation control signal, can ensure the normal transmission of the data signal to the pixel circuit without affecting the normal display of the display panel. When the data signal line in the bent area is broken, the gating sub-circuit, under the influence of the abnormal potential on the invalid data signal line and the compensation control signal, provides a compensation signal to the pixel circuit. This repairs the inability of the abnormal data signal line to provide a data signal, preventing display defects caused by broken data signal lines, thereby improving the yield of subsequent products in the display panel and avoiding cost losses.

[0121] The display devices provided in this application embodiment may include televisions, computers, smartphones, smart wearable devices, laptops, and tablets, etc. Smart wearable devices may include smartwatches, AR (augmented reality) devices, and VR (virtual reality) devices, etc.

[0122] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and / or device can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0123] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0124] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0125] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0126] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A compensation circuit of a display panel, characterized by, The display panel comprises pixel circuits, a data signal line and a driving circuit, the data signal line is electrically connected between the pixel circuits and the driving circuit, and the data signal line is used for transmitting a data signal; The compensation circuit comprises: A gate sub-circuit, which is electrically connected between the driving circuit and the data signal line, and comprises a first path and a second path connected in series, and the first path and the second path are both electrically connected with the data signal line; A compensation control signal line, one end of which is electrically connected with the gate sub-circuit, and the other end of which is electrically connected with the driving circuit, and the compensation control signal line is used for transmitting a compensation control signal output by the driving circuit; A compensation signal line, one end of which is electrically connected with the second path, and the other end of which is electrically connected with the driving circuit, and the compensation signal line is used for transmitting a compensation signal output by the driving circuit; The gate sub-circuit is used for controlling the first path to be turned on and the second path to be turned off under the action of the compensation control signal and the data signal, so that the data signal is transmitted to the pixel circuit via the first path and / or the data signal line; or The gate sub-circuit is used for controlling the first path to be turned off and the second path to be turned on under the action of the compensation control signal and the potential on the data signal line, so that the compensation signal is transmitted to the pixel circuit via the second path.

2. The compensation circuit of the display panel according to claim 1, wherein The compensation signal line comprises a compensation signal transmission line and a compensation signal connection line, the compensation signal connection line is electrically connected with the gate sub-circuit and the compensation signal transmission line respectively, and the compensation signal transmission line is electrically connected with the driving circuit; The compensation circuit comprises k groups of the gate sub-circuit, each group of the gate sub-circuit is electrically connected with the same compensation signal connection line, and k is a natural number greater than 0.

3. The compensation circuit of the display panel according to claim 2, wherein, The length direction of the compensation signal transmission line intersects with the length direction of the compensation signal connection line.

4. The compensation circuit of the display panel according to claim 3, wherein, At least one group of the gate sub-circuit is electrically connected with the pixel circuits in the same row.

5. The compensation circuit of the display panel according to any one of claims 2 to 4, characterized in that, The display area of the display panel comprises a first area, a second area and a third area, the first area, the second area and the third area are arranged along a first direction, the first direction intersects with the length direction of the compensation signal transmission line, the second area is located between the first area and the third area, and the compensation signal transmission line is arranged in the second area.

6. The compensation circuit of the display panel according to any one of claims 2 to 4, wherein, The line width of the compensation signal transmission line is greater than the line width of the data signal line.

7. The compensation circuit of the display panel according to any one of claims 2 to 4, characterized in that, The display panel further includes a fourth region, a fifth region and a sixth region, the fourth region, the fifth region and the sixth region are arranged along a second direction intersecting with a length direction of the compensation signal connection line, the fifth region is located between the fourth region and the sixth region, and the sixth region is located between the fifth region and the driving circuit.

8. The compensation circuit of the display panel according to claim 1, wherein, The gate electrode of the first transistor and the gate electrode of the second transistor are connected to the sixth node, the gate electrode of the third transistor is electrically connected to the compensation control signal line, the first electrode of the third transistor is electrically connected to the sixth node, and the second electrode of the third transistor is electrically connected to the fourth node. The first unit is configured to control the second unit to provide a control potential signal to the third unit under the action of potentials on the compensation control signal and the data signal line. The first path and the second path are configured to be turned on or turned off under the action of the control potential signal, wherein the second path is turned off when the first path is turned on, and the first path is turned off when the second path is turned on. The third path is configured to be connected to a first constant voltage, and the fourth path is configured to be connected to a second constant voltage, wherein the control potential signal is the first constant voltage when the third path is turned on and the fourth path is turned off, and the control potential signal is the second constant voltage when the third path is turned off and the fourth path is turned on.

9. The compensation circuit of the display panel according to claim 8, wherein, The second unit includes a first transistor and a second transistor, the first unit includes a third transistor, the first path includes a fourth transistor, and the second path includes a fifth transistor. The gate electrode of the first transistor and the gate electrode of the second transistor are connected to the sixth node, the gate electrode of the third transistor is electrically connected to the compensation control signal line, the first electrode of the third transistor is electrically connected to the sixth node, and the second electrode of the third transistor is electrically connected to the fourth node.

10. The compensation circuit of the display panel according to claim 9, characterized in that, The first electrode of the first transistor is configured to be connected to a first constant voltage, the first electrode of the second transistor is configured to be connected to a second constant voltage, and the second electrode of the first transistor and the second electrode of the second transistor are connected to the seventh node. ​ ​ The gate of the fourth transistor and the gate of the fifth transistor are electrically connected with the fifth node, the first electrode of the fourth transistor and the first electrode of the fifth transistor are electrically connected with the fourth node, the second electrode of the fourth transistor is electrically connected with the data signal line, and the second electrode of the fifth transistor is electrically connected with the compensation signal line.

11. The compensation circuit of the display panel according to claim 10, wherein, The second unit comprises a second capacitor, a first end of the second capacitor is electrically connected with a seventh node, and a second end of the second capacitor is electrically connected with the fifth node; and / or, The first transistor and the fifth transistor are the same type of transistor, and the second transistor and the fourth transistor are the same type of transistor.

12. The compensation circuit of the display panel according to claim 1, wherein, The starting point of the effective level of the compensation control signal is before the starting point of the test pulse of the data signal, and the ending point of the effective level of the compensation control signal is after the ending point of the test pulse of the data signal.

13. A display panel, characterized by The compensation circuit comprises: The pixel circuit, the data signal line, the driving circuit and the compensation circuit according to any one of claims 1 to 12; The compensation circuit is electrically connected with the pixel circuit, the data signal line and the driving circuit respectively.

14. A compensation method of a display panel, characterized by, The compensation method comprises: In the case that the data signal line is abnormal, the driving circuit outputs the compensation control signal and a compensation signal, wherein the compensation signal corresponds to the data signal transmitted by the abnormal data signal line; Under the action of the potential of the compensation control signal and the data signal line, the first path is cut off and the second path is turned on, so that the gate sub-circuit transmits the compensation signal to the pixel circuit.

15. A controller characterized by comprising: The compensation method comprises: The memory stores a computer program; The processor is configured to invoke the computer program in the memory, and the computer program is configured to execute the compensation method according to claim 14.

16. A display device comprising: The display panel according to claim 13 and / or the controller according to claim 15.

Images