Mixed bit read-write device of ferroelectric memory based on SPI (Serial Peripheral Interface)

Abstract

The invention discloses a mixed bit read-write device of a ferroelectric memory based on an SPI (Serial Peripheral Interface), which is characterized in that a data register file, an address CAM (Content Address Memory) and an arbiter are arranged to temporarily store single 8-bit input data, and the input data with the same input address are stored in the same address in the data register file so as to merge the input data, and finally, the mixed bit read-write device of the ferroelectric memory based on the SPI is stored in the data register file. When the data is written into the data register file, the storage data corresponding to the storage address can be directly read from the data register file and written into the ferroelectric memory, so that the simultaneous writing of multi-byte data can be completed; based on this, the method supports the writing of mixed bits of 8-32 bits, and the writing efficiency of the ferroelectric memory can be remarkably improved, so that the method is very suitable for large-scale application and popularization.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor integrated circuit design, and in particular relates to a mixed bit reading and writing device of a ferroelectric memory based on SPI. Background Art

[0002] Ferroelectric memory can be used as a slave device of I2C (serial bus) or SPI (serial peripheral interface), and the required interface circuit functions are as follows: when in the opcode recognition state, the interface circuit will identify whether the 8-bit opcode input from SI is among the 9 defined opcodes. If so, it will jump to the opcode execution state, otherwise, it will jump to the opcode mismatch state; among them, for the opcode execution state, there will be different execution methods and execution states for different opcodes.

[0003] Currently, see Figure 1 As shown, the communication between the SPI host and the ferroelectric memory is usually realized based on a single-channel SPI interface. In the single-channel SPI interface described in the technology, the DATA bus connected to the FRAM (ferroelectric memory) is 8 bits per byte. Therefore, when writing data, only 8 bits of writing are supported. For large-capacity ferroelectric memories, continuous address data is usually read and written. In this way, the internal structure of FRAM is more inclined to multi-byte reading and writing. Based on this, the existing technology does not support multi-byte writing to the ferroelectric memory, and its writing efficiency is low. Therefore, how to provide a mixed bit reading and writing device that supports multi-byte writing to improve writing efficiency has become a problem to be solved urgently. Summary of the invention

[0004] The purpose of the present invention is to provide a hybrid bit reading and writing device of a ferroelectric memory based on SPI, so as to solve the problem of low writing efficiency existing in the prior art.

[0005] In order to achieve the above object, the present invention adopts the following technical solutions:

[0006] In a first aspect, a hybrid bit reading and writing device of a ferroelectric memory based on SPI is provided, comprising:

[0007] A mixed bit writing unit, the mixed bit writing unit comprising: a first arbitrator, a first address CAM, a second arbitrator and a first data register stack, wherein the second arbitrator is used to obtain input data from the SPI host, the first arbitrator is used to obtain an input address corresponding to the input data from the SPI host and perform address counting, and the length of the input data is 8 bits;

[0008] a first arbitrator, electrically connected to the first address CAM and the second arbitrator, respectively, wherein the first address CAM is used to determine a first storage address of the input data in the first data register file according to the input address, and transmit the first storage address to the second arbitrator through the first arbitrator;

[0009] a second arbiter, configured to store the input data into a first data register file according to the first storage address;

[0010] A first arbitrator, used to determine whether the address counting result is greater than a preset value;

[0011] If the counting result is less than or equal to the preset value, the first arbitrator is used to obtain the next input data and the input address corresponding to the next input data from the SPI host, and re-determine the first storage address of the next input data in the first data register stack according to the input address of the next input data, until the counting result is greater than the preset value, the data read instruction is sent to the first data register stack through the second arbitrator, wherein, when the input address of the next input data is the same as the input address of the input data, the first storage address of the next input data is the same as the first storage address of the input data;

[0012] A first data register file, used for reading the storage data corresponding to the first storage address based on the data read instruction, and writing the read storage data into the ferroelectric memory to complete the writing of the current round of data;

[0013] The first arbiter and the first data register stack are further used to clear the address counting result and the storage data corresponding to the first storage address after completing the writing of the storage data, so as to write the next round of data.

[0014] Based on the above disclosed content, the mixed bit reading and writing device provided by the present invention, after obtaining the input data and the corresponding input address transmitted by the SPI host, will first determine the first storage address of the input data in the first data register stack according to the input address, and then, the input data can be stored in the first data register stack according to the aforementioned first storage address; then, the next input data and the corresponding input address can be obtained; then, based on the aforementioned principle, the next input data is temporarily stored in the first data register stack, and when the input address of the next input data is the same as the input address of the previous input data, the storage addresses of the two in the first data register stack are the same; in this way, multiple input data with the same address can be stored in the same address in the first data register stack, thereby completing the merging of multiple input data, and finally, when the result of the address counting by the mixed bit reading and writing device is greater than the preset value, the storage data corresponding to the first storage address in the first data register stack can be directly written into the ferroelectric memory, thereby realizing the writing of multi-byte data.

[0015] Through the above design, the mixed bit reading and writing device provided by the present invention realizes the temporary storage of a single 8-bit input data by setting a data register stack, an address CAM and an arbiter, and stores the input data with the same input address in the same address in the data register stack, thereby realizing the merging of the input data. Finally, the storage data corresponding to the storage address can be directly read from the data register stack and written into the ferroelectric memory. In this way, the simultaneous writing of multi-byte data can be completed. Based on this, the present invention supports the writing of mixed bits of 8bit to 32bit, which can significantly improve the writing efficiency of the ferroelectric memory, and is therefore very suitable for large-scale application and promotion.

[0016] In a possible design, the length of the input address corresponding to the input data is 19 bits, wherein the first address CAM is provided with four address units, and the four address units include address 0, address 1, address 2 and address 3;

[0017] The first address CAM is used to filter out a first address bit from the input address corresponding to the input data, and use the first address bit as the first data to be checked to perform a matching query in the first address CAM, wherein the first address bit is the third to eighteenth bits in the input address of the input data, and the first bit of the input address of the input data is the zeroth bit;

[0018] If the first data to be checked is stored in the first address CAM, the first address CAM is used to use the address where the first data to be checked is stored in the first address CAM as the first storage address of the input data in the first data register stack, wherein the first storage address is address 0, address 1, address 2 or address 3.

[0019] In a possible design, the first data register file is provided with 4 storage units, wherein the bit width of each storage unit is 32 bits, and each storage unit is divided into 4 storage bytes;

[0020] A second arbiter, used to determine a storage bit from an input address corresponding to the input data, wherein the storage bit is from the zeroth bit to the first bit of the input address corresponding to the input data;

[0021] a second arbiter, for determining a storage unit of the input data in the first data register file as a target unit according to a first storage address corresponding to the input data, and for determining a storage byte of the input data in the target unit as a target byte according to the storage bit;

[0022] The second arbiter is further used to store the input data into the target byte corresponding to the target unit.

[0023] In one possible design, when the first address bit in the input address of the next input data is the same as the first address bit in the input address of the input data, the first storage address of the next input data is the same as the first storage address of the input data, wherein the first address bit in the input address of the input data is: the third to eighteenth bits in the input address of the input data.

[0024] In a possible design, the mixed bit writing unit further includes: a data trigger and a first address trigger;

[0025] A data trigger, used for acquiring the input data from the SPI host, and the data trigger is electrically connected to the second arbitrator and the first data register file, respectively, and is used for transmitting the input data to the second arbitrator and the first data register file;

[0026] The first address trigger is used to obtain the input address corresponding to the input data, and the first address trigger is electrically connected to the first arbitrator and the first address CAM respectively, and is used to transmit the input address corresponding to the input data to the first arbitrator and the first address CAM.

[0027] In one possible design, the mixed bit writing unit further includes: an input clock counter and an input clock trigger;

[0028] Among them, the input clock counter is electrically connected to the input clock trigger, used to obtain the clock signal of the SPI host and transmit the clock signal to the input clock trigger, and the input clock trigger is electrically connected to the first data register stack and the first address CAM respectively to perform timing alignment on the first data register stack and the first address CAM based on the clock signal.

[0029] In a possible design, the mixed bit writing unit further includes: a data counter and an address counter;

[0030] The first data register stack is electrically connected to the ferroelectric memory through the data counter, and the first address CAM is electrically connected to the ferroelectric memory through the address counter.

[0031] In a possible design, the device further includes: a mixed bit reading unit, wherein the mixed bit reading unit includes: a third arbitrator, a fourth arbitrator, a second address CAM and a second data register file, and the third arbitrator is electrically connected to the second address CAM and the fourth arbitrator, and the fourth arbitrator is electrically connected to the second data register file;

[0032] A third arbitrator is used to obtain a read address of the data to be read when the chip selection signal is at a high level, and transmit the read address of the data to be read to the second address CAM;

[0033] A second address CAM, used for determining a second storage address of the data to be read in the second data register stack based on a read address of the data to be read, and sending the second storage address to the fourth arbitrator through the third arbitrator;

[0034] A second data register stack, used to read the data to be read from the ferroelectric memory according to the read address of the data to be read, and store the data to be read according to the second storage address, wherein the length of the data to be read is an integer multiple of 8;

[0035] a fourth arbiter, configured to determine a data read bit according to a read address of the data to be read, and extract data at the data read bit in target data in the second data register stack as actual read data, wherein the target data is the data to be read stored in the second storage address in the second data register stack, and the length of the actual read data is 8 bits;

[0036] A fourth arbitrator, used for transmitting the actual read data to the SPI host;

[0037] The third arbiter is used to determine whether the chip select signal is still at a high level;

[0038] If yes, the third arbitrator is used to obtain the read address of the next data to be read, and determine whether the target bit in the read address of the next data to be read is the same as the target bit in the read address of the data to be read;

[0039] If so, the third arbitrator is used to send a first read instruction to the fourth arbitrator, so that after receiving the first read instruction, the fourth arbitrator reuses the read address of the next data to be read to determine the data read bit, until the target bit in the read address of the next data to be read is different from the target bit in the read address of the data to be read, and then sends a second read instruction to the second data register stack, so that after receiving the second read instruction, the second data register stack re-reads the next data to be read from the ferroelectric memory according to the read address of the next data to be read, until the chip select signal is at a low level, the data reading process is terminated.

[0040] In a possible design, the length of the read address corresponding to the to-be-read data is 19 bits;

[0041] The second address CAM is used to determine a second address bit from the read address of the data to be read, and use the second address bit as the second data to be checked to perform a matching query in the second address CAM, wherein the second address bit is the third to eighteenth bits in the read address of the data to be read, and the first bit of the read address of the data to be read is the zeroth bit;

[0042] If the second data to be checked is stored in the second address CAM, the second address CAM is used to use the address where the second data to be checked is stored in the second address CAM as the second storage address of the data to be read in the second data register stack.

[0043] In one possible design, a second data register stack is used to read the data to be read from the ferroelectric memory according to the second address bit in the read address of the data to be read; wherein the target bit in the read address of the data to be read is: the third to eighteenth bits in the read address of the data to be read.

[0044] Beneficial effects:

[0045] (1) The mixed bit reading and writing device provided by the present invention realizes the temporary storage of a single 8-bit input data by setting a data register stack, an address CAM and an arbiter, and stores the input data with the same input address in the same address in the data register stack, thereby realizing the merging of the input data. Finally, the storage data corresponding to the storage address can be directly read from the data register stack and written into the ferroelectric memory. In this way, the simultaneous writing of multi-byte data can be completed. Based on this, the present invention supports the writing of mixed bits of 8-bit to 32-bit, which can significantly improve the writing efficiency of the ferroelectric memory. Therefore, it is very suitable for large-scale application and promotion.

[0046] (2) Since the input data is merged when writing data, multiple bytes of data can be read at one time when reading. Based on this, the number of read operations can be reduced, thereby improving the reading efficiency.

[0047] (3) The present invention is also provided with a mixed bit reading unit, which first reads data from the ferroelectric memory according to the read address and temporarily stores it in the data register stack; at the same time, the data read from the ferroelectric memory is merged data, that is, multi-byte data. Based on this, when the target bit in the read address of the data to be read next time is the same as the target bit read last time, the data can be directly read from the register stack without reading from the ferroelectric memory; based on this, the number of erase and write times of the FRAM array can be reduced, thereby extending the service life of the FRAM and improving its durability.

[0048] (4) The present invention combines multiple input data into multi-byte data, so that the access of large data blocks can be processed more efficiently, thereby improving the overall data transmission rate of the large-capacity storage array and reducing the delay in the transmission process. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 A communication schematic diagram of a conventional ferroelectric memory based on a single-channel SPI interface provided by an embodiment of the present invention;

[0050] Figure 2 A communication architecture diagram of a hybrid bit reading and writing device of a ferroelectric memory based on SPI provided in an embodiment of the present invention;

[0051] Figure 3 A schematic diagram of the structure of a mixed bit writing unit provided in an embodiment of the present invention;

[0052] Figure 4 A schematic diagram of the structure of a mixed bit reading unit provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the present invention will be briefly introduced below in combination with the drawings and the description of the embodiments or the prior art. Obviously, the following description of the structure of the drawings is only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. It should be noted that the description of these embodiments is used to help understand the present invention, but does not constitute a limitation of the present invention.

[0054] It should be understood that although the terms first, second, etc. may be used herein to describe various units, these units should not be limited by these terms. These terms are only used to distinguish one unit from another unit. For example, a first unit can be referred to as a second unit, and similarly, a second unit can be referred to as a first unit without departing from the scope of the exemplary embodiments of the present invention.

[0055] It should be understood that the term "and / or" that may appear in this article is merely a description of the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B can represent three situations: A exists alone, B exists alone, and A and B exist at the same time. The term " / and" that may appear in this article describes another type of association object relationship, indicating that two relationships may exist. For example, A / and B can represent two situations: A exists alone, and A and B exist alone. In addition, the character " / " that may appear in this article generally indicates that the previous and next associated objects are in an "or" relationship.

[0056] Example:

[0057] See also Figure 2 As shown, the mixed bit read-write device of the SPI-based ferroelectric memory provided in this embodiment is arranged between the single-channel SPI interface circuit and the ferroelectric memory, that is, the mixed bit read-write device is electrically connected to the SPI host through the single-channel SPI interface circuit, and it is also electrically connected to the ferroelectric memory, so as to realize the writing and reading of multi-byte data of the ferroelectric memory based on the mixed bit read-write device.

[0058] The mixed bit reading and writing device may include, but is not limited to, a mixed bit writing unit, that is, the mixed bit writing unit is used to write multiple bytes of data transmitted by SPI into the ferroelectric memory.

[0059] See also Figure 3 As shown, for example, the mixed bit writing unit may include but is not limited to: a first arbitrator ( Figure 3 ARBI TER1 in), the first address CAM ( Figure 3 ADDR_CAM1 in), the second arbiter ( Figure 3ARBI TER2) ​​and the first data register file ( Figure 3 DATA_REGFI LE1 in the SPI host), wherein the second arbitrator is used to obtain input data from the SPI host, and the first arbitrator is used to obtain the input address corresponding to the input data from the SPI host and perform address counting, and the length of the input data is 8 bits; that is, the data obtained by the mixed bit write unit is still 8 bits, but after being temporarily stored in the write unit, the input data can be merged, thereby realizing the writing of 16-32 bit data.

[0060] Specifically, the first arbitrator is electrically connected to the first address CAM and the second arbitrator, respectively, wherein the first address CAM is used to determine the first storage address of the input data in the first data register stack according to the input address, and transmit the first storage address to the second arbitrator through the first arbitrator.

[0061] In specific applications, the length of the aforementioned input address is 19 bits, that is, the input address is A0-A18, and the first bit is the zeroth bit, that is, the A0 bit; at the same time, the first address CAM is provided with four address units (that is, the depth is 4), and the four address units include address 0, address 1, address 2 and address 3 (the bit width of each address unit is 17); in this way, the first address CAM is used to filter out the first address bit from the input address corresponding to the input data, and use the first address bit as the first data to be checked, and perform a matching query in the first address CAM; in this embodiment, for example, the first address bit can be but is not limited to the third to eighteenth bits in the input address of the input data, that is, the high 17 bits of the input address corresponding to the input data.

[0062] Based on this, when the first data to be checked is stored in the first address CAM, that is, the first data to be checked can be queried in the first address CAM, then the first address CAM is used to use the address where the first data to be checked is stored in the first address CAM as the first storage address of the input data in the first data register stack; wherein, the first storage address is address 0, address 1, address 2 or address 3; for example, assuming that the first address bit (that is, bits A2-A8) is stored in address 0 in the first address CAM, then the first storage address of the input address in the first data register stack is address 0; of course, when the storage location of the first data to be checked is different, the process of determining the first storage address is the same as the aforementioned example, and will not be repeated here.

[0063] Furthermore, if the first data to be checked is not stored in the first address CAM, the first address bit can be stored in address 0 of the first address CAM, and then the storage position of the first address bit can be used as the first storage address corresponding to the input data, that is, address 0 can be used as the storage address of the input data in the first data register stack.

[0064] After determining the first storage address of the input data in the first data register stack, the input data can be temporarily stored, that is, the second arbitrator is used to store the input data in the first data register stack according to the first storage address; in this embodiment, the first data register stack is provided with 4 storage units (that is, the depth is also 4, corresponding to address 0, address 1, address 2 and address 3 respectively), wherein the bit width of each storage unit is 32 bits, and each storage unit is divided into 4 storage bytes (represented by 00, 01, 10 and 11 respectively), that is, one storage byte stores 8 bits of data; thus, the second arbitrator actually determines two storage locations of the input data, one is the storage unit in the first data register stack, and the other is the storage byte in the storage unit.

[0065] Specifically, the second arbitrator is used to determine the storage bit from the input address corresponding to the input data; in this embodiment, the storage bit is taken as the zeroth to first bits of the input address corresponding to the input data, that is, bits A0 and A1. Based on this, the second arbitrator is used to determine the storage unit of the input data in the first data register stack as the target unit according to the first storage address corresponding to the input data, and to determine the storage byte of the input data in the target unit as the target byte according to the storage bit; finally, the second arbitrator is used to store the input data in the target byte corresponding to the target unit.

[0066] The following example illustrates the temporary storage process of the input data:

[0067] Assuming that the first storage address bit of the input data is address 0, and its A0-A1 bits are 00, then the storage unit corresponding to address 0 in the first data register stack is used as the target unit, and then the storage byte corresponding to the lower eight bits of the 32 bits in address 0 is used as the target byte, that is, the input data is stored in address 0 in the first data register, and the lower eight bits of the 32-bit data in address 0 are updated to the aforementioned input data; at this time, the temporary storage of the input data can be completed.

[0068] After completing the temporary storage of an input data, the first arbitrator is used to determine whether the address counting result is greater than the preset value; in this embodiment, the preset value can be, but is not limited to, set to 2, 3 or 4. In this embodiment, it is preferably set to 4, that is, 32-bit data is written in one round, that is, 4 input data are merged.

[0069] Among them, if the address counting result is less than or equal to the preset value, it means that one round of data has not been written. At this time, the first arbitrator is used to obtain the next input data and the input address corresponding to the next input data from the SPI host, and re-determine the first storage address of the next input data in the first data register stack according to the input address of the next input data; then, the aforementioned temporary storage operation is re-executed until the counting result is greater than the preset value, and the data read instruction is sent to the first data register stack through the second arbitrator; in this way, in the process of continuously obtaining input data, when the input address of the next input data (referring to the first address bit in the input address) is the same as the input address of the input data (that is, the input address of the previous input data The first storage address of the next input data is the same as the first storage address of the input data; that is, when the A2-A18 bits in the input address of the next input data are the same as the A0-A18 bits in the previous input address, the two are stored in the same storage unit, such as both are stored in the 32-bit data corresponding to address 0; at the same time, the two are only different in the target bytes stored, that is, the A0 and A1 bits of the input address of the previous input data are 0,0, then, they are stored in the lower eight bits of the 32 bits of address 0, and if the A0 and A1 bits of the input address of the next input data are 1 and 1 respectively, then, they are stored in the upper eight bits of the 32 bits of address 0.

[0070] Based on this, during a round of data writing, input data with the same high 17-bit address in the input address can be stored in the same storage unit in the first data register stack, so that multiple input data can be merged.

[0071] Finally, the first data register stack is used to read the storage data corresponding to the first storage address based on the data read instruction, and write the read storage data into the ferroelectric memory to complete the writing of the current round of data; based on this, when the preset value is 4, and the high 17 bits of the input addresses of the 4 input data are the same, at this time, the 4 data can be merged into 32-bit data and written into the ferroelectric memory at one time.

[0072] Of course, if the upper 17 bits of the input address of the input data are different, then the 32-bit data in each storage unit in the first data register stack is output; and if the upper 17 bits of the input addresses of the four input data are all different, then they are integrated into 4 32-bit data together with 4 address outputs and written into the ferroelectric memory; at this point, the write merging function of the mixed bits can be completed.

[0073] Furthermore, after completing the writing of storage data of a round of data, the first arbitrator and the first data register stack are also used to clear the address counting result and the storage data corresponding to the first storage address respectively, and the first arbitrator is also used to clear the data stored in the first address CAM so as to write the next round of data, that is, to perform initialization processing so as to perform the next counting and temporary storage.

[0074] Thus, through the aforementioned explanation of the mixed bit writing unit, the present invention supports the writing of mixed bits of 8-bit to 32-bit, which can significantly improve the writing efficiency of the ferroelectric memory; at the same time, since the input data is merged when writing data, multiple bytes of data can be read at one time when reading. Based on this, the number of read operations each time can be reduced, thereby improving the reading efficiency; therefore, the present invention is very suitable for large-scale application and promotion.

[0075] In a specific implementation, the mixed bit writing unit may also include, but is not limited to: a data trigger, a first address trigger, an input clock counter, an input clock trigger, a data counter, and an address counter.

[0076] Among them, see Figure 3 As shown, the data trigger (i.e. Figure 3 DATA_FF in ), used to obtain the input data from the SPI host, and the data trigger is electrically connected to the second arbitrator and the first data register stack, respectively, to transmit the input data to the second arbitrator and the first data register stack, so that the second arbitrator and the first data register stack can realize the storage of the input data; similarly, the first address trigger ( Figure 3 ADDR_FF in the input data) is used to obtain the input address corresponding to the input data, and the first address trigger is electrically connected to the first arbitrator and the first address CAM, respectively, for transmitting the input address corresponding to the input data to the first arbitrator and the first address CAM; based on this, the first arbitrator and the first address CAM can match the addresses to obtain the first storage address corresponding to the input data.

[0077] Furthermore, the input clock counter ( Figure 3CNT_IN_4 in the figure is electrically connected to the input clock trigger (CNT_IN_FF) for obtaining the clock signal of the SPI host and transmitting the clock signal to the input clock trigger, and the input clock trigger is electrically connected to the first data register stack and the first address CAM, respectively, for performing timing alignment on the first data register stack and the first address CAM based on the clock signal; in this way, the mixed bit write unit uses the SCK of the SPI host as the clock of the device to realize data writing.

[0078] In addition, the first data register file is connected to the data counter (i.e. Figure 3 The DATA_CNT in the ferroelectric memory is electrically connected to realize the writing of multi-byte data, and the first address CAM is connected to the ferroelectric memory through the address counter ( Figure 3 ADDR_CNT in the ferroelectric memory is electrically connected to the ferroelectric memory to achieve the output of the input address, that is, when the data in the first data register stack is written into the ferroelectric memory, the write address of each stored data in the ferroelectric memory is still the aforementioned first storage address.

[0079] Thus, through the above detailed structural description of the mixed bit writing unit, the write merging function of the mixed bits of the ferroelectric memory can be realized, thereby greatly improving the data writing efficiency.

[0080] In a possible design, the second aspect of this embodiment is optimized based on the first aspect of the embodiment to provide a hybrid bit reading unit to achieve fast reading of data in a ferroelectric memory.

[0081] In the specific implementation, see Figure 4 As shown, for example, the mixed bit reading unit may include but is not limited to: a third arbitrator ( Figure 4 ARBI TER3 in), the fourth arbitrator ( Figure 4 ARBI TER4 in), the second address CAM ( Figure 4 ADDR_CAM2 in the second data register file ( Figure 4 DATA_REGFI LE2 in the arbitrator, and the third arbitrator is electrically connected to the second address CAM and the fourth arbitrator, and the fourth arbitrator is electrically connected to the second data register stack.

[0082] In a specific implementation, when the SPI host reads data from the ferroelectric memory, it can continuously read in an automatic address increment manner, and the mixed bit reading unit provided in this embodiment implements fast data reading according to this logic, and the process is as follows:

[0083] The third arbitrator is used to obtain the read address of the data to be read when the chip select signal is at a high level, and transmit the read address of the data to be read to the second address CAM; that is, when reading data, by inputting the address of the data to be read, the data at the address is returned to the SPI host; in this embodiment, the length of the read address corresponding to the data to be read is also 19 bits, that is, it is still A0-A18; therefore, the second address CAM is used to determine the second storage address of the data to be read in the second data register stack based on the read address of the data to be read, and send the second storage address to the fourth arbitrator through the third arbitrator.

[0084] In this embodiment, the process of determining the second storage address is the same as the process of determining the first storage address, both of which are: first determine the second address bit from the read address of the data to be read, and use the second address bit as the second data to be checked, and perform a matching query in the second address CAM (of course, the second address bit is still the third to eighteenth bits in the read address of the data to be read, and the first bit of the read address of the data to be read is still the zeroth bit); wherein, if the second data to be checked is stored in the second address CAM, the second address CAM is used to use the address where the second data to be checked is stored in the second address CAM as the second storage address of the data to be read in the second data register stack; in this way, the storage address of the data read from the ferroelectric memory in the second data register stack can be determined.

[0085] Then, the data can be read and temporarily stored, and the process is as follows: the second data register stack is used to read the data to be read from the ferroelectric memory according to the read address of the data to be read (that is, according to the aforementioned second address bit), and store the data to be read according to the second storage address, wherein the length of the data to be read is an integer multiple of 8.

[0086] In this embodiment, the third to eighteenth bits in the read address of the data to be read are still taken as outputs, and then the data corresponding to the third to eighteenth bits of the address are obtained in the ferroelectric memory (the data is actually a multi-byte data, such as a 32-bit data based on the first aspect of the embodiment), and then the multi-byte data read out is stored in the second data register stack; specifically, assuming that the storage position of the second address bit in the second address CAM is address 0, then the aforementioned 32-bit data read out from the ferroelectric memory is stored in the storage unit corresponding to address 0 in the second data register stack; at this time, the reading of the data to be read corresponding to a read address can be completed.

[0087] At this time, it is necessary to extract data from the second data register stack and output it to the SPI host to realize the actual reading of the data; specifically, the fourth arbitrator is used to determine the data reading bit according to the read address of the data to be read, and extract the data on the data reading bit in the target data in the second data register stack as the actual read data; in this embodiment, the target data is taken as the data to be read stored in the second storage address in the second data register stack, and the data reading bit is the first two bits of the read address, that is, A0 and A1 bits, and the length of the actual read data is 8 bits.

[0088] Optionally, the following is explained using an example. Assuming that the second storage address of the data to be read is address 0, and the first two bits of the read address are 00, then the data on the lower eight bits (i.e., the data on the byte corresponding to binary 00) is extracted from the 32-bit data stored at address 0 in the second data register stack (the data is the data read from the ferroelectric memory) as the actual read data, and then the fourth arbitrator transmits the actual read data to the SPI host.

[0089] At this time, an 8-bit data read output can be completed; then, the third arbitrator needs to determine whether the chip select signal is still at a high level; if it is still at a high level, it means that data reading needs to be continued at this time; therefore, it is necessary to continuously read data in an automatic address increment manner.

[0090] Specifically, the automatic address increment is actually the increment of the read address of the data to be read by SPI, that is, an overall increase of 1. At this time, the read address obtained by the third arbitrator has changed, which is equivalent to obtaining the read address of the next data to be read; based on this, the third arbitrator needs to determine whether the target bit in the read address of the next data to be read is the same as the target bit in the read address of the data to be read, so as to determine whether it is necessary to re-pull data from the ferroelectric memory based on the judgment result.

[0091] In a specific implementation, the target bits in the read address of the aforementioned data to be read are: the third to eighteenth bits in the read address of the data to be read; in this way, it is determined whether the upper 17 bits of the read addresses obtained twice are the same. If they are the same, it means that the data can be read in the same second storage address. Otherwise, it is necessary to pull data from the ferroelectric memory again based on the read address of the next data to be read.

[0092] Optionally, if the target bit in the read address of the next data to be read is the same as the target bit in the read address of the data to be read, then the third arbitrator is used to send a first read instruction to the fourth arbitrator, so that after receiving the first read instruction, the fourth arbitrator reuses the read address of the next data to be read to determine the data read bit, until the target bit in the read address of the next data to be read is different from the target bit in the read address of the data to be read, then send a second read instruction to the second data register stack, so that after receiving the second read instruction, the second data register stack re-reads the next data to be read from the ferroelectric memory according to the read address of the next data to be read, until the chip select signal is at a low level, the data reading process is terminated.

[0093] In this embodiment, an example is used to illustrate the aforementioned reading process:

[0094] Assuming that the second storage address corresponding to the first read address is address 0, and the first two bits of the read address are 00, then the data on the lower eight bits (that is, the data on the byte corresponding to binary 00) are extracted from the 32-bit data stored at address 0 in the second data register stack (the data is the data read from the ferroelectric memory) as the actual read data. Finally, the fourth arbitrator transmits the actual read data to the SPI host.

[0095] Then, if the chip select signal is still at a high level, data is read in an address-automatic increment manner. Therefore, the third arbitrator obtains a second read address (the address is the address after the address is automatically incremented); then, it is determined whether the second to eighteenth bits in the second read address are the same as the second to eighteenth bits in the first read address.

[0096] If they are the same, data is still read from the 32-bit data stored at address 0 in the second data register stack. At this time, assuming that the first two bits of the second read address are 01, then the 8-bit data on the byte corresponding to 01 in the 32-bit data is output as the actual read data.

[0097] Next, it is determined again whether the chip select signal is at a high level; if so, data is read in an automatic address increment manner; that is, the third arbitrator obtains the third read address; then, it is determined whether the second to eighteenth bits in the third read address are the same as the second to eighteenth bits in the second read address.

[0098] Among them, if they are the same, data is still read from the 32-bit data stored at address 0 in the second data register stack. At this time, assuming that the first two bits of the third read address are 10, then the 8-bit data on the byte corresponding to 10 in the 32-bit data is output as the actual read data; in this way, all the data corresponding to the four bytes in the 32-bit data stored at address 0 in the second data register stack can be read out.

[0099] Then, if the chip select signal is still at a high level, and the second to eighteenth bits of the fourth read address obtained are different from the second to eighteenth bits in the third read address, this means that the address has changed, and the 32-bit data corresponding to the fourth address needs to be pulled out from the ferroelectric memory again and stored in the second data register stack (assuming it is stored in address 1); then, based on the A0 and A1 bits in the fourth address, determine which eight bits of the 32-bit data stored in address 1 are output as the actual read data.

[0100] Based on this, with the aforementioned principle, the data in the ferroelectric memory can be quickly read, and when the chip select signal is at a low level, the data reading process can be ended; of course, in the first and second data register stacks, the data stored in both will be stored until power is lost.

[0101] In addition, in this embodiment, the example mixed bit read unit also includes an address trigger, a data counter, an address counter, an input clock counter and an input clock trigger, etc. The names of the aforementioned devices in the figure are the same as the names in the aforementioned mixed bit write unit, and they are not repeated here.

[0102] Thus, through the above-mentioned design, when reading, the present invention first reads data from the ferroelectric memory according to the read address, and temporarily stores it in the data register stack; at the same time, the data read from the ferroelectric memory is merged data, that is, multi-byte data. Based on this, when the target bit in the read address of the data to be read next time is the same as the target bit read last time, the data can be directly read in the register stack without going to the ferroelectric memory; based on this, the number of erase and write times of the FRAM array can be reduced, thereby extending the service life of the FRAM and improving its durability.

[0103] Therefore, through the above detailed description of the hybrid bit reading and writing device of the ferroelectric memory based on SPI, the present invention has the following advantages:

[0104] Beneficial effects:

[0105] (1) Improved access efficiency: By supporting 16-bit-32-bit mixed bit reading and writing, the present invention can significantly improve the efficiency of data reading and writing for large-capacity FRAM (above 2M), especially in scenarios requiring continuous reading and writing, thereby reducing the number of read and write operations each time.

[0106] (2) Reducing the number of erasures and writes to the FRAM array: The present invention reduces the frequency of erasing and writing to the storage unit by reducing the destructive reading of the FRAM, thereby extending the service life of the FRAM, improving its durability, and reducing the fatigue effect caused by repeated erasures and writes.

[0107] (3) More suitable for large-capacity data transmission: The present invention can more effectively handle the access of large data blocks by combining multiple bytes of data into 32-bit long words, thereby improving the overall data transmission rate of the large-capacity storage array and reducing the delay in the transmission process.

[0108] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A hybrid bit reading and writing device for ferroelectric memory based on SPI, characterized in that: include: A mixed bit writing unit, the mixed bit writing unit comprising: a first arbitrator, a first address CAM, a second arbitrator and a first data register stack, wherein the second arbitrator is used to obtain input data from the SPI host, the first arbitrator is used to obtain an input address corresponding to the input data from the SPI host and perform address counting, and the length of the input data is 8 bits; a first arbitrator, electrically connected to the first address CAM and the second arbitrator, respectively, wherein the first address CAM is used to determine a first storage address of the input data in the first data register file according to the input address, and transmit the first storage address to the second arbitrator through the first arbitrator; a second arbiter, configured to store the input data into a first data register file according to the first storage address; A first arbitrator, used to determine whether the address counting result is greater than a preset value; If the counting result is less than or equal to the preset value, the first arbitrator is used to obtain the next input data and the input address corresponding to the next input data from the SPI host, and re-determine the first storage address of the next input data in the first data register stack according to the input address of the next input data, until the counting result is greater than the preset value, the data read instruction is sent to the first data register stack through the second arbitrator, wherein, when the input address of the next input data is the same as the input address of the input data, the first storage address of the next input data is the same as the first storage address of the input data; A first data register file, used for reading the storage data corresponding to the first storage address based on the data read instruction, and writing the read storage data into the ferroelectric memory to complete the writing of the current round of data; The first arbiter and the first data register stack are further used to clear the address counting result and the storage data corresponding to the first storage address after completing the writing of the storage data, so as to write the next round of data.

2. A hybrid bit reading and writing device of a ferroelectric memory based on SPI according to claim 1, characterized in that: The length of the input address corresponding to the input data is 19 bits, wherein the first address CAM is provided with four address units, and the four address units include address 0, address 1, address 2 and address 3; The first address CAM is used to filter out a first address bit from the input address corresponding to the input data, and use the first address bit as the first data to be checked to perform a matching query in the first address CAM, wherein the first address bit is the third to eighteenth bits in the input address of the input data, and the first bit of the input address of the input data is the zeroth bit; If the first data to be checked is stored in the first address CAM, the first address CAM is used to use the address where the first data to be checked is stored in the first address CAM as the first storage address of the input data in the first data register stack, wherein the first storage address is address 0, address 1, address 2 or address 3.

3. A hybrid bit reading and writing device of a ferroelectric memory based on SPI according to claim 2, characterized in that: The first data register file is provided with 4 storage units, wherein the bit width of each storage unit is 32 bits, and each storage unit is divided into 4 storage bytes; A second arbiter, used to determine a storage bit from an input address corresponding to the input data, wherein the storage bit is from the zeroth bit to the first bit of the input address corresponding to the input data; a second arbiter, for determining a storage unit of the input data in the first data register file as a target unit according to a first storage address corresponding to the input data, and for determining a storage byte of the input data in the target unit as a target byte according to the storage bit; The second arbiter is further used to store the input data into the target byte corresponding to the target unit.

4. The hybrid bit reading and writing device of the SPI-based ferroelectric memory according to claim 1, characterized in that: When the first address bit in the input address of the next input data is the same as the first address bit in the input address of the input data, the first storage address of the next input data is the same as the first storage address of the input data, wherein the first address bit in the input address of the input data is: the third to eighteenth bits in the input address of the input data.

5. The hybrid bit reading and writing device of the SPI-based ferroelectric memory according to claim 1, wherein the hybrid bit writing unit further comprises: a data trigger and a first address trigger; A data trigger, used for acquiring the input data from the SPI host, and the data trigger is electrically connected to the second arbitrator and the first data register file, respectively, and is used for transmitting the input data to the second arbitrator and the first data register file; The first address trigger is used to obtain the input address corresponding to the input data, and the first address trigger is electrically connected to the first arbitrator and the first address CAM respectively, and is used to transmit the input address corresponding to the input data to the first arbitrator and the first address CAM.

6. The hybrid bit reading and writing device of ferroelectric memory based on SPI according to claim 1, characterized in that: The mixed bit writing unit further includes: an input clock counter and an input clock trigger; Among them, the input clock counter is electrically connected to the input clock trigger, used to obtain the clock signal of the SPI host and transmit the clock signal to the input clock trigger, and the input clock trigger is electrically connected to the first data register stack and the first address CAM respectively to perform timing alignment on the first data register stack and the first address CAM based on the clock signal.

7. The hybrid bit reading and writing device of ferroelectric memory based on SPI according to claim 1, characterized in that: The mixed bit writing unit further includes: a data counter and an address counter; The first data register stack is electrically connected to the ferroelectric memory through the data counter, and the first address CAM is electrically connected to the ferroelectric memory through the address counter.

8. The hybrid bit reading and writing device of ferroelectric memory based on SPI according to claim 1, characterized in that: Also includes: A mixed bit reading unit, wherein the mixed bit reading unit comprises: a third arbitrator, a fourth arbitrator, a second address CAM and a second data register file, and the third arbitrator is electrically connected to the second address CAM and the fourth arbitrator, and the fourth arbitrator is electrically connected to the second data register file; A third arbitrator is used to obtain a read address of the data to be read when the chip selection signal is at a high level, and transmit the read address of the data to be read to the second address CAM; A second address CAM, used for determining a second storage address of the data to be read in the second data register stack based on a read address of the data to be read, and sending the second storage address to the fourth arbitrator through the third arbitrator; A second data register stack, used to read the data to be read from the ferroelectric memory according to the read address of the data to be read, and store the data to be read according to the second storage address, wherein the length of the data to be read is an integer multiple of 8; a fourth arbiter, configured to determine a data read bit according to a read address of the data to be read, and extract data at the data read bit in target data in the second data register stack as actual read data, wherein the target data is the data to be read stored in the second storage address in the second data register stack, and the length of the actual read data is 8 bits; A fourth arbitrator, used for transmitting the actual read data to the SPI host; The third arbiter is used to determine whether the chip select signal is still at a high level; If yes, the third arbitrator is used to obtain the read address of the next data to be read, and determine whether the target bit in the read address of the next data to be read is the same as the target bit in the read address of the data to be read; If so, the third arbitrator is used to send a first read instruction to the fourth arbitrator, so that after receiving the first read instruction, the fourth arbitrator reuses the read address of the next data to be read to determine the data read bit, until the target bit in the read address of the next data to be read is different from the target bit in the read address of the data to be read, and then sends a second read instruction to the second data register stack, so that after receiving the second read instruction, the second data register stack re-reads the next data to be read from the ferroelectric memory according to the read address of the next data to be read, until the chip select signal is at a low level, the data reading process is terminated.

9. The hybrid bit reading and writing device of ferroelectric memory based on SPI according to claim 8, characterized in that: The length of the read address corresponding to the data to be read is 19 bits; The second address CAM is used to determine a second address bit from the read address of the data to be read, and use the second address bit as the second data to be checked to perform a matching query in the second address CAM, wherein the second address bit is the third to eighteenth bits in the read address of the data to be read, and the first bit of the read address of the data to be read is the zeroth bit; If the second data to be checked is stored in the second address CAM, the second address CAM is used to use the address where the second data to be checked is stored in the second address CAM as the second storage address of the data to be read in the second data register stack.

10. The hybrid bit reading and writing device of ferroelectric memory based on SPI according to claim 9, characterized in that: The second data register stack is used to read the data to be read from the ferroelectric memory according to the second address bit in the read address of the data to be read; wherein the target bit in the read address of the data to be read is: the third to eighteenth bits in the read address of the data to be read.

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