A hybrid bit read-write device for ferroelectric memory based on SPI

Abstract

The application discloses a hybrid bit read-write device of ferroelectric memory based on SPI, which realizes the temporary storage of single 8bit input data by setting a data register stack, an address CAM and an arbitrator, and stores the input data with the same input address into the same address in the data register stack, so as to realize the merging of the input data, finally, the storage data corresponding to the storage address can be directly read from the data register stack and written into the ferroelectric memory, so that the simultaneous writing of multi-byte data can be completed; based on this, the application supports the writing of 8bit-32bit hybrid bits, can significantly improve the writing efficiency of the ferroelectric memory, and is very suitable for large-scale application and popularization.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor integrated circuit design, and particularly relates to a hybrid bit read-write device of a ferroelectric memory based on SPI. BACKGROUND

[0002] The ferroelectric memory can be a slave device of I2C (serial bus) or SPI (serial peripheral interface), and the required interface circuit functions are as follows: when in an operation code identification state, the interface circuit identifies whether the 8-bit operation code input from SI is in the defined 9 operation codes, if yes, the operation code execution state is jumped to, otherwise, the operation code mismatch state is jumped to; wherein, for the operation code execution state, different execution modes and execution states are provided for different operation codes.

[0003] At present, as shown in the figure, the communication between the SPI host and the ferroelectric memory is usually realized based on a single-channel SPI interface, wherein, in the single-channel SPI interface described by the technology, the DATA bus of the FRAM (ferroelectric memory) is 8 bits, so that only 8-bit writing can be supported when writing data. Figure 1 For a large-capacity ferroelectric memory, continuous address data is usually read and written, so the FRAM internal structure is more inclined to multi-byte reading and writing. Therefore, the prior art does not support multi-byte writing of the ferroelectric memory, and the writing efficiency is low. Therefore, how to provide a hybrid bit read-write device supporting multi-byte writing to improve the writing efficiency has become a problem to be solved. SUMMARY

[0004] The application aims to provide a hybrid bit read-write device of a ferroelectric memory based on SPI to solve the problem of low writing efficiency in the prior art.

[0005] In order to achieve the above-mentioned purpose, the application adopts the following technical scheme:

[0006] In a first aspect, a hybrid bit read-write device of a ferroelectric memory based on SPI is provided, comprising:

[0007] The hybrid bit write unit comprises a first arbiter, a first address CAM, a second arbiter and a first data register stack, wherein the second arbiter is used to obtain input data from the SPI host, the first arbiter is used to obtain input addresses corresponding to the input data from the SPI host and perform address counting, and the length of the input data is 8 bits.

[0008] a first arbitrator, electrically connected with the first address CAM and the second arbitrator respectively, wherein the first address CAM is configured to determine a first storage address of the input data in the first data register stack according to the input address, and transmit the first storage address to the second arbitrator through the first arbitrator;

[0009] a second arbitrator, configured to store the input data into the first data register stack according to the first storage address;

[0010] the first arbitrator is configured to determine whether the address count result is greater than a preset value;

[0011] if the count result is less than or equal to the preset value, the first arbitrator is configured to acquire a next input data and an input address corresponding to the next input data from the SPI host, and determine a first storage address of the next input data in the first data register stack according to the input address of the next input data, until the count result is greater than the preset value, and then send a data read instruction to the first data register stack through the second arbitrator, wherein when the input address of the next input data is the same as the input address of the input data, the first storage address of the next input data is the same as the first storage address of the input data;

[0012] the first data register stack is configured to read the storage data corresponding to the first storage address based on the data read instruction, and write the read storage data into the ferroelectric memory, so as to complete the writing of the current round of data;

[0013] the first arbitrator and the first data register stack are further configured to, after completing the writing of the storage data, clear the address count result and the storage data corresponding to the first storage address respectively, so as to perform the writing of the next round of data.

[0014] Based on the above disclosure, the mixed bit read-write device provided by the application, after obtaining the input data transmitted by the SPI host and the corresponding input address, determines the first storage address of the input data in the first data register stack according to the input address, and then stores the input data into the first data register stack according to the first storage address; then, the next input data and the corresponding input address are obtained; then, the next input data is temporarily stored in the first data register stack according to the above principle, and when the input address of the next input data is the same as the input address of the previous input data, the storage addresses of the two in the first data register stack are the same; in this way, the multiple input data with the same address can be stored in the same address in the first data register stack, thereby completing the merging of the multiple input data; finally, when the result of the address counting of the mixed bit read-write device is greater than the preset value, the storage data corresponding to the first storage address in the first data register stack can be directly written into the ferroelectric memory, thereby realizing the writing of the multi-byte data.

[0015] Through the above design, the mixed bit read-write device provided by the application realizes the temporary storage of a single 8bit input data by setting the data register stack, the address CAM and the arbitrator, and stores the input data with the same input address into the same address in the data register stack, thereby realizing the merging of the input data; finally, the storage data corresponding to the storage address can be directly read from the data register stack and written into the ferroelectric memory, so that the simultaneous writing of the multi-byte data can be completed; based on this, the application supports the writing of 8bit-32bit mixed bits, which can significantly improve the writing efficiency of the ferroelectric memory, and is therefore very suitable for large-scale application and promotion.

[0016] In one possible design, the length of the input address corresponding to the input data is 19bit, wherein the first address CAM is provided with four address units, and the four address units include address 0, address 1, address 2 and address 3;

[0017] The first address CAM is used to filter out the first address bit from the input address corresponding to the input data, and the first address bit is used as the first data to be searched for in the matching query in the first address CAM, wherein the first address bit is the third to eighteenth bit in the input address of the input data, and the first bit in the input address of the input data is the zeroth bit.

[0018] If the first address CAM stores the first search data, the first address CAM is configured to store the address of the first search data in the first address CAM as the first storage address of the input data in the first data register stack, wherein the first storage address is address 0, address 1, address 2 or address 3.

[0019] In a possible design, the first data register stack is provided with four storage units, wherein each storage unit has a bit width of 32 bits, and each storage unit is divided into four storage bytes;

[0020] The second arbitrator is configured to determine a storage bit from the input address corresponding to the input data, wherein the storage bit is the zeroth bit to the first bit of the input address corresponding to the input data.

[0021] The second arbitrator is configured to determine, according to the first storage address corresponding to the input data, a storage unit of the input data in the first data register stack as a target unit, and to determine, according to the storage bit, a storage byte of the input data in the target unit as a target byte.

[0022] The second arbitrator is further configured to store the input data into the target byte corresponding to the target unit.

[0023] In a possible design, when the first address bit in the input address of the next input data is the same as the first address bit in the input address of the input data, the first storage address of the next input data is the same as the first storage address of the input data, wherein the first address bit in the input address of the input data is the third bit to the eighteenth bit in the input address of the input data.

[0024] In a possible design, the mixed-bit write unit further includes a data flip-flop and a first address flip-flop.

[0025] The data flip-flop is configured to obtain the input data from the SPI host, and is electrically connected to the second arbitrator and the first data register stack respectively, and configured to transmit the input data to the second arbitrator and the first data register stack.

[0026] The first address flip-flop is configured to obtain the input address corresponding to the input data, and is electrically connected to the first arbitrator and the first address CAM respectively, and configured to transmit the input address corresponding to the input data to the first arbitrator and the first address CAM.

[0027] In a possible design, the mixed-bit write unit further includes an input clock counter and an input clock flip-flop.

[0028] The input clock counter is electrically connected with the input clock flip-flop, used to acquire the clock signal of the SPI host and transmit the clock signal to the input clock flip-flop, and the input clock flip-flop is electrically connected with the first data register stack and the first address CAM respectively, so as to perform timing alignment on the first data register stack and the first address CAM based on the clock signal.

[0029] In a possible design, the mixed-bit write unit further includes a data counter and an address counter.

[0030] The first data register stack is electrically connected with the ferroelectric memory through the data counter, and the first address CAM is electrically connected with the ferroelectric memory through the address counter.

[0031] In a possible design, the mixed-bit read unit further includes a third arbiter, a fourth arbiter, a second address CAM and a second data register stack, and the third arbiter is electrically connected with the second address CAM and the fourth arbiter, and the fourth arbiter is electrically connected with the second data register stack.

[0032] The third arbiter is used to acquire the read address of the to-be-read data when the chip select signal is at a high level, and transmit the read address of the to-be-read data to the second address CAM.

[0033] The second address CAM is used to determine the second storage address of the to-be-read data in the second data register stack based on the read address of the to-be-read data, and transmit the second storage address to the fourth arbiter through the third arbiter.

[0034] The second data register stack is used to read the to-be-read data from the ferroelectric memory according to the read address of the to-be-read data, and store the to-be-read data according to the second storage address, and the length of the to-be-read data is an integer multiple of 8.

[0035] The fourth arbiter is used to determine the data read bit according to the read address of the to-be-read data, and extract the data on the data read bit in the target data in the second data register stack as actual read data, and the length of the actual read data is 8 bits.

[0036] The fourth arbiter is used to transmit the actual read data to the SPI host.

[0037] The third arbiter is used to determine whether the chip select signal is still at a high level.

[0038] If yes, the third arbiter is configured to acquire a read address of the next to-be-read data, and determine whether a target bit in the read address of the next to-be-read data is same as a target bit in the read address of the to-be-read data.

[0039] If yes, the third arbiter is configured to send a first read instruction to the fourth arbiter, so that the fourth arbiter determines a data read bit by using the read address of the next to-be-read data again after receiving the first read instruction, until the target bit in the read address of the next to-be-read data is different from the target bit in the read address of the to-be-read data, and sends a second read instruction to the second data register stack, so that the second data register stack reads the next to-be-read data from the ferroelectric memory according to the read address of the next to-be-read data again after receiving the second read instruction, until the chip select signal is low, and the data read process is ended.

[0040] In a possible design, the read address corresponding to the to-be-read data has a length of 19 bits.

[0041] The second address CAM is configured to determine a second address bit from the read address of the to-be-read data, and match the second address bit as second to-be-searched data in the second address CAM, where the second address bit is a third bit to an eighteenth bit in the read address of the to-be-read data, and a first bit in the read address of the to-be-read data is a zeroth bit.

[0042] If the second to-be-searched data is stored in the second address CAM, the second address CAM is configured to take an address at which the second to-be-searched data is stored in the second address CAM as a second storage address of the to-be-read data in the second data register stack.

[0043] In a possible design, the second data register stack is configured to read the to-be-read data from the ferroelectric memory according to the second address bit in the read address of the to-be-read data, where the target bit in the read address of the to-be-read data is a third bit to an eighteenth bit in the read address of the to-be-read data.

[0044] Beneficial effects:

[0045] (1) The mixed bit read-write device provided by the application realizes the temporary storage of single 8bit input data, and stores the input data with the same input address into the same address in the data register stack, thereby realizing the merging of input data, and finally, the stored data corresponding to the storage address can be directly read from the data register stack and written into the ferroelectric memory, so that the simultaneous writing of multi-byte data can be completed; based on this, the application supports the writing of 8bit-32bit mixed bits, which can significantly improve the writing efficiency of the ferroelectric memory, and therefore, is very suitable for large-scale application and promotion.

[0046] (2) Since the merging of input data is realized during data writing, multi-byte data can be read at a time during reading, and based on this, the number of read operations can be reduced, thereby improving the reading efficiency.

[0047] (3) The application also provides a mixed bit read unit, which first reads data from the ferroelectric memory according to the read address and temporarily stores it in the data register stack; at the same time, the data read from the ferroelectric memory is merged data, that is, multi-byte data, and based on this, when the target bit in the read address of the next to-be-read data is the same as the target bit of the last read data, the data can be directly read in the register stack without reading from the ferroelectric memory; based on this, the number of erase and write operations on the FRAM array can be reduced, thereby prolonging the service life of the FRAM and improving its durability.

[0048] (4) The application merges multiple input data into multi-byte data, which can more effectively process the access of large data blocks, thereby improving the overall data transmission rate of the large-capacity storage array and reducing the delay in the transmission process. BRIEF DESCRIPTION OF DRAWINGS

[0049] Figure 1 The traditional ferroelectric memory provided by the embodiment of the application is based on a single-channel SPI interface communication schematic diagram;

[0050] Figure 2 The communication architecture diagram of the mixed bit read-write device of the ferroelectric memory based on SPI provided by the embodiment of the application;

[0051] Figure 3 The structure schematic diagram of the mixed bit write unit provided by the embodiment of the application;

[0052] Figure 4 The structure schematic diagram of the mixed bit read unit provided by the embodiment of the application. DETAILED DESCRIPTION

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the present application will be briefly introduced below in combination with the drawings and the description of the embodiments or the prior art. Obviously, the following description of the drawings is only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative effort on the basis of these drawings. It should be noted that the description of these embodiments is used to help understand the present application, but does not constitute a limitation on the present application.

[0054] It should be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element can be called a second element, and similarly, a second element can be called a first element without departing from the scope of the example embodiments of the present application.

[0055] It should be understood that for the term "and / or" that may appear herein, it only describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which means that there are three cases of A alone, B alone, and A and B together. For the term "and" that may appear herein, it describes another association object relationship, which means that there can be two relationships, for example, A and B, which means that there are two cases of A alone and A and B together. In addition, for the character " / " that may appear herein, it generally means that the associated objects before and after are an "or" relationship.

[0056] Embodiments:

[0057] Referring to Figure 2 As shown in the figure, the hybrid bit read-write device based on the ferroelectric memory provided by the embodiment is arranged between the single-channel SPI interface circuit and the ferroelectric memory, that is, the hybrid bit read-write device is electrically connected to the SPI host through the single-channel SPI interface circuit, and it is also electrically connected to the ferroelectric memory, so as to realize the writing and reading of multi-byte data of the ferroelectric memory based on the hybrid bit read-write device.

[0058] Among them, for example, the hybrid bit read-write device can but is not limited to include: a hybrid bit write unit, that is, through the hybrid bit write unit, the data transmitted by the SPI is written into the ferroelectric memory in multiple bytes.

[0059] Referring to Figure 3 As shown in the figure, for example, the hybrid bit write unit can but is not limited to include: a first arbiter (ARBITER1) in Figure 3 , a first address CAM (ADDR_CAM1) in Figure 3 , a second arbiter (ARBITER2) in Figure 3ARBI TER2) ​​and the first data register file ( Figure 3 In the DATA_REGFILE1, the second arbiter is used to obtain input data from the SPI host, and the first arbiter is used to obtain the input address corresponding to the input data from the SPI host and perform address counting, and the length of the input data is 8 bits; that is, the data obtained by the mixed bit write unit is still 8 bits, but after temporary storage by the write unit, the input data can be merged, thereby realizing the writing of 16-32 bit data.

[0060] Specifically, the first arbitrator is electrically connected to the first address CAM and the second arbitrator, respectively, wherein the first address CAM is used to determine the first storage address of the input data in the first data register stack based on the input address, and transmit the first storage address to the second arbitrator through the first arbitrator.

[0061] In specific applications, the length of the aforementioned input address is 19 bits, that is, the input address is A0-A18, and the first bit is the zeroth bit, that is, the A0 bit; at the same time, the first address CAM is provided with four address units (that is, the depth is 4), and the four address units include address 0, address 1, address 2 and address 3 (the bit width of each address unit is 17); in this way, the first address CAM is used to filter out the first address bit from the input address corresponding to the input data, and use the first address bit as the first data to be checked, and perform a matching query in the first address CAM; in this embodiment, for example, the first address bit can be but is not limited to the third to eighteenth bits in the input address of the input data, that is, the high 17 bits of the input address corresponding to the input data.

[0062] Based on this, when the first data to be checked is stored in the first address CAM, that is, the first data to be checked can be queried in the first address CAM, then the first address CAM is used to use the address where the first data to be checked is stored in the first address CAM as the first storage address of the input data in the first data register stack; wherein, the first storage address is address 0, address 1, address 2 or address 3; for example, assuming that the first address bit (that is, A2-A8 bits) is stored in address 0 in the first address CAM, then the first storage address of the input address in the first data register stack is address 0; of course, when the storage location of the first data to be checked is different, the process of determining the first storage address is the same as the above example, and will not be repeated here.

[0063] Further, if the first address CAM does not store the first data to be searched, the first address bit can be stored in address 0 of the first address CAM, and then the storage position of the first address bit is used as the first storage address of the input data, that is, address 0 is used as the storage address of the input data in the first data register stack.

[0064] After determining the first storage address of the input data in the first data register stack, the input data can be temporarily stored, that is, the second arbiter is configured to store the input data in the first data register stack according to the first storage address. In this embodiment, the first data register stack is provided with four storage units (that is, the depth is also 4, corresponding to address 0, address 1, address 2 and address 3 respectively), wherein the bit width of each storage unit is 32 bits, and each storage unit is divided into four storage bytes (represented by 00, 01, 10 and 11 respectively), that is, one storage byte stores 8 bits of data. Therefore, the second arbiter is essentially to determine two storage positions of the input data, one in the storage unit in the first data register stack, and the other in the storage byte in the storage unit.

[0065] Specifically, the second arbiter is configured to determine a storage bit from the input address corresponding to the input data. In this embodiment, the storage bit is the zeroth bit to the first bit of the input address corresponding to the input data, that is, the A0 and A1 bits. Based on this, the second arbiter is configured to determine a storage unit of the input data in the first data register stack as a target unit according to the first storage address of the input data, and to determine a storage byte of the input data in the target unit as a target byte according to the storage bit. Finally, the second arbiter is configured to store the input data in the target byte corresponding to the target unit.

[0066] The following describes the temporary storage process of the input data by taking an example:

[0067] Suppose the first storage address bit of the input data is address 0, and the A0-A1 bits are 00. Then, the storage unit corresponding to address 0 in the first data register stack is used as the target unit, and the storage byte corresponding to the lower eight bits in the 32 bits of address 0 is used as the target byte, that is, the input data is stored in address 0 in the first data register, and the lower eight bits of the 32 bits of data in address 0 are updated to the input data. At this time, the temporary storage of the input data can be completed.

[0068] After the temporary storage of one input data is completed, the first arbitrator is configured to determine whether the address count result is greater than a preset value; in the embodiment, the preset value can be set as 2, 3 or 4, but is not limited to, and the preset value is preferably set as 4, that is, one round of writing of 32-bit data is implemented, that is, four input data are merged.

[0069] If the address count result is less than or equal to the preset value, it indicates that one round of data writing is not completed, at this time, the first arbitrator is configured to obtain the next input data and the input address corresponding to the next input data from the SPI host, and determine the first storage address of the next input data in the first data register stack according to the input address of the next input data; then, the temporary storage operation is re-executed until the count result is greater than the preset value, and the data reading instruction is sent to the first data register stack through the second arbitrator; in this way, in the process of continuously obtaining input data, when the input address (the first address bit in the input address) of the next input data is the same as the input address of the input data (the first address bit in the input address of the previous input data), the first storage address of the next input data is the same as the first storage address of the input data; that is, when the A2-A18 bits in the input address of the next input data are the same as the A0-A18 bits in the input address of the previous input data, the two are stored in the same storage unit, for example, are stored in 32-bit data corresponding to address 0; at the same time, the two only differ in the target byte to be stored, that is, the A0 and A1 bits in the input address of the previous input data are 0, 0, and then the low eight bits of 32-bit data at address 0 are stored, and if the A0 and A1 bits in the input address of the next input data are 1 and 1 in turn, then the high eight bits of 32-bit data at address 0 are stored.

[0070] Based on this, in one round of data writing, input data with the same high 17-bit address in the input address can be stored in the same storage unit in the first data register stack, so that the merging of multiple input data can be implemented.

[0071] Finally, the first data register stack is configured to read the storage data corresponding to the first storage address based on the data reading instruction, and write the read storage data into the ferroelectric memory to complete the writing of the current round of data; based on this, when the preset value is 4 and the high 17 bits of the input addresses of the four input data are the same, the four input data can be merged into 32-bit data and written into the ferroelectric memory at one time.

[0072] Of course, if the upper 17 bits of the input address of the input data are different, then the 32-bit data in each storage unit in the first data register stack is output; and if the upper 17 bits of the input addresses of the four input data are all different, then they are integrated into 4 32-bit data together with 4 address outputs and written into the ferroelectric memory; at this point, the write merging function of the mixed bits can be completed.

[0073] Furthermore, after completing the writing of the storage data of a round of data, the first arbitrator and the first data register stack are also used to clear the address counting result and the storage data corresponding to the first storage address respectively, and the first arbitrator is also used to clear the data stored in the first address CAM so as to write the next round of data, that is, to perform initialization processing so as to perform the next counting and temporary storage.

[0074] Thus, through the above explanation of the mixed bit writing unit, the present invention supports the writing of mixed bits of 8 bits to 32 bits, which can significantly improve the writing efficiency of the ferroelectric memory; at the same time, since the input data is merged when writing data, multiple bytes of data can be read at one time when reading. Based on this, the number of read operations each time can be reduced, thereby improving the reading efficiency; therefore, the present invention is very suitable for large-scale application and promotion.

[0075] In a specific embodiment, the mixed bit writing unit may also include, but is not limited to: a data trigger, a first address trigger, an input clock counter, an input clock trigger, a data counter, and an address counter.

[0076] Among them, see Figure 3 As shown, the data trigger (ie Figure 3 DATA_FF in the SPI register), is used to obtain the input data from the SPI host, and the data trigger is electrically connected to the second arbitrator and the first data register file, respectively, for transmitting the input data to the second arbitrator and the first data register file, so that the second arbitrator and the first data register file can realize the storage of the input data; similarly, the first address trigger ( Figure 3 ADDR_FF in the first address trigger is used to obtain the input address corresponding to the input data, and the first address trigger is electrically connected to the first arbiter and the first address CAM, respectively, for transmitting the input address corresponding to the input data to the first arbiter and the first address CAM; based on this, the first arbiter and the first address CAM can match the addresses to obtain the first storage address corresponding to the input data.

[0077] Furthermore, the input clock counter ( Figure 3CNT_IN_4 in the SPI host), electrically connected to the input clock trigger (CNT_IN_FF), for obtaining the clock signal of the SPI host and transmitting the clock signal to the input clock trigger, and the input clock trigger is electrically connected to the first data register stack and the first address CAM, respectively, for performing timing alignment on the first data register stack and the first address CAM based on the clock signal; in this way, the mixed bit write unit uses the SCK of the SPI host as the clock of the device to realize data writing.

[0078] In addition, the first data register file is configured to receive the data through the data counter (ie Figure 3 The DATA_CNT in the ferroelectric memory is electrically connected to realize the writing of multi-byte data, and the first address CAM is connected to the ferroelectric memory through the address counter ( Figure 3 ADDR_CNT in the ferroelectric memory is electrically connected to the ferroelectric memory, thereby realizing the output of the input address, that is, when the data in the first data register stack is written into the ferroelectric memory, the write address of each stored data in the ferroelectric memory is still the aforementioned first storage address.

[0079] Thus, through the above detailed description of the structure of the mixed bit writing unit, the write merging function of the mixed bits of the ferroelectric memory can be realized, thereby greatly improving the data writing efficiency.

[0080] In a possible design, the second aspect of this embodiment is optimized based on the first aspect of the embodiment, and provides a hybrid bit reading unit to achieve fast reading of data in the ferroelectric memory.

[0081] In the specific implementation, see Figure 4 As shown, for example, the mixed bit reading unit may include but is not limited to: a third arbitrator ( Figure 4 ARBI TER3 in), the fourth arbitrator ( Figure 4 ARBI TER4 in), the second address CAM ( Figure 4 ADDR_CAM2 in) and the second data register file ( Figure 4 DATA_REGFI LE2 in the arbitrator, and the third arbitrator is electrically connected to the second address CAM and the fourth arbitrator, and the fourth arbitrator is electrically connected to the second data register file.

[0082] In a specific implementation, when the SPI host reads data from the ferroelectric memory, it can continuously read in an automatic address increment manner. The mixed bit reading unit provided in this embodiment implements fast data reading according to this logic. The process is as follows:

[0083] The third arbiter is configured to obtain a read address of the to-be-read data when a chip select signal is high, and transmit the read address of the to-be-read data to the second address CAM; that is, when data is read, the address of the to-be-read data is input to return data on the address to the SPI host; in this embodiment, the length of the read address corresponding to the to-be-read data is also 19 bits, that is, A0-A18; therefore, the second address CAM is configured to determine a second storage address of the to-be-read data in the second data register stack based on the read address of the to-be-read data, and transmit the second storage address to the fourth arbiter through the third arbiter.

[0084] In this embodiment, the determination process of the second storage address is the same as that of the first storage address, that is, the second address bit is first determined from the read address of the to-be-read data, and the second address bit is taken as second search data to perform matching query in the second address CAM (of course, the second address bit is the third bit to the eighteenth bit in the read address of the to-be-read data, and the first bit of the read address of the to-be-read data is still the zeroth bit); if the second search data is stored in the second address CAM, the second address CAM is configured to take the address at which the second search data is stored in the second address CAM as the second storage address of the to-be-read data in the second data register stack; in this way, the storage address of the data read from the ferroelectric memory in the second data register stack can be determined.

[0085] Then, data reading and temporary storage can be performed, and the process is as follows: the second data register stack is configured to read the to-be-read data from the ferroelectric memory according to the read address of the to-be-read data (that is, according to the second address bit), and store the to-be-read data according to the second storage address, where the length of the to-be-read data is an integer multiple of 8.

[0086] In this embodiment, the third bit to the eighteenth bit in the read address of the to-be-read data is taken as output, then the data corresponding to the third bit to the eighteenth bit address in the ferroelectric memory is obtained (the data is actually a multi-byte data, for example, a 32-bit data based on the first aspect of the embodiment), and then the read multi-byte data is stored in the second data register stack; specifically, assuming that the storage position of the second address bit in the second address CAM is address 0, the 32-bit data read from the ferroelectric memory is stored in the storage unit corresponding to the address 0 in the second data register stack; at this time, the reading of the to-be-read data corresponding to one read address can be completed.

[0087] At this time, data needs to be extracted from the second data register stack and output to the SPI host to realize actual reading out of data. Specifically, the fourth arbitrator is configured to determine a data reading bit according to the reading address of the data to be read, and extract data on the data reading bit in the target data in the second data register stack as actual read data. In this embodiment, the target data is the data to be read stored in the second storage address in the second data register stack, the data reading bit is the first two bits of the reading address, that is, the A0 and A1 bits, and the length of the actual read data is 8 bits.

[0088] Alternatively, the following is described by taking an example. Assuming that the second storage address of the data to be read is address 0, and the first two bits of the reading address are 00, then the lower eight bits of the 32-bit data stored in address 0 in the second data register stack (the data is read from the ferroelectric memory) are extracted as the actual read data, and then the fourth arbitrator transmits the actual read data to the SPI host.

[0089] At this time, the reading and output of an 8-bit data can be completed. Then, the third arbitrator needs to determine whether the chip select signal is still at a high level. If it is still at a high level, it means that data reading still needs to be continued. Therefore, the automatic address increment mode needs to be used to continuously read data.

[0090] Specifically, the automatic address increment is essentially the increment of the reading address of the data to be read by SPI, that is, the whole is increased by 1. At this time, the reading address obtained by the third arbitrator changes, that is, the reading address of the next data to be read is obtained. Based on this, the third arbitrator needs to determine whether the target bit in the reading address of the next data to be read is the same as the target bit in the reading address of the data to be read, so as to determine whether data needs to be pulled from the ferroelectric memory again based on the determination result.

[0091] In specific implementation, the target bit in the reading address of the data to be read is the third bit to the eighteenth bit in the reading address of the data to be read. In this way, it is determined whether the high 17 bits in the reading addresses obtained at the two times are the same. If they are the same, it means that data reading can be performed in the same second storage address. Otherwise, data needs to be pulled from the ferroelectric memory again based on the reading address of the next data to be read.

[0092] Optionally, if the target bit in the read address of the next data to be read is the same as the target bit in the read address of the data to be read, the third arbitrator is configured to send a first read instruction to the fourth arbitrator, so that the fourth arbitrator determines the data read bit by using the read address of the next data to be read again after receiving the first read instruction, until the target bit in the read address of the next data to be read is different from the target bit in the read address of the data to be read, and sends a second read instruction to the second data register stack, so that the second data register stack reads the next data to be read from the ferroelectric memory according to the read address of the next data to be read again after receiving the second read instruction, until the chip select signal is low, and the data reading process is ended.

[0093] In this embodiment, the foregoing reading process is described by taking an example.

[0094] Suppose that the second storage address corresponding to the first read address is address 0, and the first two bits of the read address are 00, then the data on the low eight bits (i.e. the data on the byte corresponding to binary 00) in the 32-bit data stored in the address 0 in the second data register stack (the data is read from the ferroelectric memory) is extracted as the actual read data, and finally the fourth arbitrator transmits the actual read data to the SPI host.

[0095] Then, if the chip select signal is still high, the data reading is performed in the address automatic increment mode, so that the third arbitrator obtains the second read address (the address is the address after the address automatic increment); then, it is judged whether the second bit to the eighteenth bit in the second read address is the same as the second bit to the eighteenth bit in the first read address.

[0096] If they are the same, the data is read from the 32-bit data stored in the address 0 in the second data register stack, and at this time, suppose that the first two bits of the second read address are 01, then the 8-bit data on the byte corresponding to 01 in the 32-bit data is taken as the actual read data and output.

[0097] Next, it is judged again whether the chip select signal is high; if yes, the data reading is performed in the address automatic increment mode; that is, the third arbitrator obtains the third read address; then, it is judged again whether the second bit to the eighteenth bit in the third read address is the same as the second bit to the eighteenth bit in the second read address.

[0098] If the same, the 32-bit data stored in the address 0 of the second data register stack is read, and the 8-bit data in the 10 corresponding byte of the 32-bit data is output as the actual read data, assuming that the first two bits of the third read address are 10.

[0099] If the chip select signal is still at a high level and the second bit to the eighteenth bit of the fourth read address is different from the second bit to the eighteenth bit of the third read address, the address changes, and the 32-bit data corresponding to the fourth address is pulled from the ferroelectric memory and stored in the second data register stack (assuming that it is stored in the address 1). Then, the A0 and A1 bits of the fourth address are used to determine which eight bits of the 32-bit data stored in the address 1 are output as the actual read data.

[0100] Based on the foregoing principle, the data in the ferroelectric memory can be quickly read, and the data reading process can be ended when the chip select signal is at a low level. Of course, the data stored in the first and second data register stacks will be stored until power failure.

[0101] In addition, in the embodiment, the mixed bit read unit also includes address flip-flops, data counters, address counters, input clock counters, and input clock flip-flops. The names of the foregoing devices in the figure are the same as those in the mixed bit write unit, and will not be described again.

[0102] In this way, through the foregoing design, when reading, the data is first read from the ferroelectric memory according to the read address and temporarily stored in the data register stack. The data read from the ferroelectric memory is merged data, that is, multi-byte data. When the target bit of the next read address is the same as the target bit of the last read, the data can be directly read from the register stack without reading from the ferroelectric memory. In this way, the number of erasing and writing operations on the FRAM array is reduced, the service life of the FRAM is prolonged, and the durability is improved.

[0103] Through the foregoing detailed description of the mixed bit read-write device for the SPI-based ferroelectric memory, the present application has the following advantages

[0104] Advantages:

[0105] (1) Can improve access efficiency: by supporting 16bit-32bit mixed bit read and write, the application can significantly improve the efficiency of data reading and writing of large capacity FRAM (2M above), especially in the scene of continuous read and write, reducing the number of read and write operation each time.

[0106] (2) Reduce the erase-write frequency of FRAM array: by reducing the destructive reading of FRAM, the application reduces the erase-write frequency of the storage unit, prolongs the service life of FRAM, improves its durability, and reduces the fatigue effect caused by repeated erase-write.

[0107] (3) More suitable for large capacity data transmission: by combining multiple bytes of data into 32bit long word, the application can more effectively handle the access of large data block, thereby improving the overall data transmission rate of large capacity storage array and reducing the delay in the transmission process.

[0108] Finally, it should be pointed out that: the above only for the preferred embodiments of the application, and not for limiting the protection scope of the application. Any modification, equivalent replacement, improvement, etc. within the spirit and principles of the application shall be included in the protection scope of the application.

Claims

1. A hybrid bit read-write device for ferroelectric memory based on SPI, characterized by, The application relates to a mixed bit write unit, which comprises a first arbitrator, a first address CAM, a second arbitrator and a first data register stack, wherein the second arbitrator is used for obtaining input data from an SPI host, the first arbitrator is used for obtaining an input address corresponding to the input data from the SPI host and performing address counting, and the length of the input data is 8 bits. The first arbitrator is electrically connected with the first address CAM and the second arbitrator respectively, wherein the first address CAM is used for determining a first storage address of the input data in the first data register stack according to the input address, and the first storage address is transmitted to the second arbitrator through the first arbitrator. The second arbitrator is used for storing the input data into the first data register stack according to the first storage address. The first arbitrator is used for judging whether the address counting result is greater than a preset value. If the counting result is less than or equal to the preset value, the first arbitrator is used for obtaining next input data and an input address corresponding to the next input data from the SPI host, and a first storage address of the next input data in the first data register stack is determined again according to the input address of the next input data until the counting result is greater than the preset value, and a data reading instruction is sent to the first data register stack through the second arbitrator, wherein when the input address of the next input data is the same as that of the previous input data, the first storage address of the next input data is the same as that of the previous input data. The first data register stack is used for reading storage data corresponding to the first storage address based on the data reading instruction, and the read storage data is written into a ferroelectric memory to complete the writing of current round data. The first arbitrator and the first data register stack are also used for performing emptying processing on the address counting result and the storage data corresponding to the first storage address respectively after completing the writing of the storage data, so as to perform the writing of next round data. The length of the input address corresponding to the input data is 19 bits, wherein the first address CAM is provided with four address units, and the four address units comprise address 0, address 1, address 2 and address 3.

2. The hybrid bit read / write device for ferroelectric memory based on SPI according to claim 1, wherein, The first address CAM is used for screening a first address bit from the input address corresponding to the input data, and the first address bit is taken as first search data for matching and searching in the first address CAM, wherein the first address bit is the third bit to the eighteenth bit in the input address of the input data, and the first bit of the input address of the input data is the zeroth bit. If the first search data is stored in the first address CAM, the first address CAM is used for taking the address of the first search data stored in the first address CAM as the first storage address of the input data in the first data register stack, wherein the first storage address is address 0, address 1, address 2 or address 3. ​ 3. The hybrid bit read / write device for ferroelectric memory based on SPI according to claim 2, wherein, The first data register stack is provided with 4 storage units, each of which has a bit width of 32 bits, and each of which is divided into 4 storage bytes; The second arbiter is configured to determine a storage bit from the input address corresponding to the input data, wherein the storage bit is the zeroth bit to the first bit of the input address corresponding to the input data; The second arbiter is configured to determine, according to the first storage address corresponding to the input data, a storage unit of the first data register stack in which the input data is stored as a target unit, and to determine, according to the storage bit, a storage byte of the target unit in which the input data is stored as a target byte; The second arbiter is further configured to store the input data into the target byte corresponding to the target unit.

4. The hybrid bit read / write device for ferroelectric memory based on SPI according to claim 1, wherein, When the first address bit in the input address of the next input data is the same as the first address bit in the input address of the previous input data, the first storage address of the next input data is the same as the first storage address of the previous input data, wherein the first address bit in the input address of the previous input data is the third bit to the eighteenth bit in the input address of the previous input data.

5. The hybrid bit read / write device for a ferroelectric memory based on SPI of claim 1, the hybrid bit write unit further comprising: Data flip-flop and first address flip-flop; The data flip-flop is configured to obtain the input data from the SPI host, and is electrically connected to the second arbiter and the first data register stack respectively, and is configured to transmit the input data to the second arbiter and the first data register stack; The first address flip-flop is configured to obtain the input address corresponding to the input data, and is electrically connected to the first arbiter and the first address CAM respectively, and is configured to transmit the input address corresponding to the input data to the first arbiter and the first address CAM.

6. The hybrid bit read / write device for ferroelectric memory based on SPI according to claim 1, wherein, The mixed bit write unit further comprises an input clock counter and an input clock flip-flop; The input clock counter is electrically connected to the input clock flip-flop, configured to obtain a clock signal of the SPI host and transmit the clock signal to the input clock flip-flop, and the input clock flip-flop is electrically connected to the first data register stack and the first address CAM respectively, so as to perform timing alignment on the first data register stack and the first address CAM based on the clock signal.

7. The hybrid bit read / write device for ferroelectric memory based on SPI according to claim 1, wherein, The mixed bit write unit further comprises a data counter and an address counter; The first data register stack is electrically connected to the ferroelectric memory through the data counter, and the first address CAM is electrically connected to the ferroelectric memory through the address counter.

8. The hybrid bit read / write device for a ferroelectric memory based on SPI according to claim 1, wherein, Further comprising: A mixed bit read unit, wherein the mixed bit read unit comprises a third arbiter, a fourth arbiter, a second address CAM and a second data register stack, and the third arbiter is electrically connected to the second address CAM and the fourth arbiter, and the fourth arbiter is electrically connected to the second data register stack; The third arbiter is configured to obtain a read address of to-be-read data when a chip select signal is high, and transmit the read address of the to-be-read data to the second address CAM; a second address CAM, configured to determine a second storage address of the to-be-read data in the second data register stack based on a read address of the to-be-read data, and send the second storage address to the fourth arbitrator through a third arbitrator; a second data register stack, configured to read the to-be-read data from the ferroelectric memory according to the read address of the to-be-read data, and store the to-be-read data according to a second storage address, wherein the length of the to-be-read data is an integer multiple of 8; the fourth arbitrator is configured to determine a data read bit according to the read address of the to-be-read data, and extract data on the data read bit in target data in the second data register stack as actual read data, wherein the target data is the to-be-read data stored in the second storage address in the second data register stack, and the length of the actual read data is 8 bits; the fourth arbitrator is configured to transmit the actual read data to the SPI host; the third arbitrator is configured to determine whether the chip select signal is still at a high level; if yes, the third arbitrator is configured to obtain a read address of a next to-be-read data, and determine whether a target bit in the read address of the next to-be-read data is same as a target bit in the read address of a previous to-be-read data; if yes, the third arbitrator is configured to send a first read instruction to the fourth arbitrator, so that the fourth arbitrator determines the data read bit by using the read address of the next to-be-read data again until the target bit in the read address of the next to-be-read data is different from the target bit in the read address of the previous to-be-read data, and sends a second read instruction to the second data register stack, so that the second data register stack reads the next to-be-read data from the ferroelectric memory again according to the read address of the next to-be-read data until the chip select signal is at a low level, and ends the data reading process.

9. The hybrid bit read / write device for ferroelectric memory based on SPI according to claim 8, wherein, the length of the read address corresponding to the to-be-read data is 19 bits; the second address CAM is configured to determine a second address bit from the read address of the to-be-read data, and match the second address bit as second search data in the second address CAM, wherein the second address bit is the third bit to the eighteenth bit in the read address of the to-be-read data, and the first bit in the read address of the to-be-read data is the zeroth bit; if the second search data is stored in the second address CAM, the second address CAM is configured to take an address at which the second search data is stored in the second address CAM as the second storage address of the to-be-read data in the second data register stack.

10. The hybrid bit read / write device for a ferroelectric memory based on SPI according to claim 9, wherein, the second data register stack is configured to read the to-be-read data from the ferroelectric memory according to the second address bit in the read address of the to-be-read data, wherein the target bit in the read address of the to-be-read data is the third bit to the eighteenth bit in the read address of the to-be-read data.

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