NOR type flash memory and write-in control method and write-in control system thereof

Abstract

The invention provides a NOR type flash memory and a write-in control method and system thereof, the NOR type flash memory is a flash memory with a page write-in function, the write-in control method comprises the steps that a target page write-in instruction is acquired, and the target page write-in instruction comprises a target page address; and based on the target page write-in instruction, controlling a target page corresponding to the target page address in the NOR type flash memory to execute page write-in operation. According to the method and the device, based on the NOR type flash memory with the page writing function, the direct page writing operation is supported, the direct writing function is realized, the operation process of the NOR type flash memory is greatly simplified, and the data writing time of the flash memory is effectively shortened; when the power failure occurs, only the target page of the data to be written is influenced, and the data of other pages is not influenced, so that the reliability of the writing function is higher; in addition, the whole process is simple and easy to operate, and the user experience is effectively improved.

Description

Technical Field

[0001] The present disclosure relates to the field of chip technology, and in particular to a NOR flash memory (a flash memory chip) and a write control method and a write control system thereof. Background Art

[0002] Traditional flash memory (such as NOR flash memory) must first perform an erase operation to change the stored data to 1 before performing a programming operation to write data 0. The erase area is usually large and is operated in sectors or blocks. NOR flash memory is generally erased in units of 4K bytes or 64K bytes. In order to allow users to flexibly select area programming, the programming operation area is usually smaller and is operated in bytes or pages, generally 1 byte to 256 bytes. The storage space hierarchy is as follows Figure 1 As shown in the figure, different instruction types and operation areas are divided according to process characteristics, design considerations and application requirements. The storage space is generally divided into 64K-byte blocks, 32K-byte half blocks, 4K-byte sectors and 256-byte pages in order of size from large to small.

[0003] Since erasing changes the entire erase area to data 1, programming can only change the storage unit in the target area to data 0. In this way, if the user expects a bit that has been programmed as data 0 to change back to 1, it is necessary to first perform an erase operation of at least 4K bytes to change all the data to 1, and then program the storage unit that needs to be written to 0. At the same time, since the erase area is much larger than the programming area, if there is previously written data in the erase range, it is also necessary to read and record the written data in the original 4K byte area before erasing, and save it in the RAM (random access memory) and other storage space outside the flash memory. After the erasure is completed, these data need to be rewritten. Figure 2 FIG. 1 is a schematic diagram showing the operation of the flash memory storage space in the above process. Figure 2 State (1) is the state of a block full of data, state (2) is the state of a block after sector erasure, state (3) is the state of writing the original data of the sector, and state (4) is the state after writing the target page data.

[0004] like Figure 3As shown, the process of the existing flash memory type memory being controlled by the external main control chip includes: the main control reads the storage data as 0, and when encountering the data that needs to be changed from 0 to 1, the main control obtains the sector address, the page address is set to 0, the main control reads the data in the page and stores it in RAM, and determines whether the current page is the last page of data. If not, the page address is increased by one and the step of the main control reading the data in the page and storing it in RAM is re-executed; if so, the main control outputs a sector erase operation instruction, the main control outputs the sector address, and the page address is set to 0; the main control reads the RAM data for page programming, the target data remains at 1, and other data remain, and continues to determine whether the current page is the last page of data. If not, the page address is increased by one and the step of the main control reading the RAM data for page programming is re-executed, the target data remains at 1, and other data remain, and if so, the control process ends. That is to say, when the master controller encounters a situation where data needs to be changed from 0 to 1, it needs to first save the data already written in the flash memory sector to the outside of the flash memory, then perform an erase operation on the flash memory, and then write the saved flash memory data back to the flash memory, and write the target page data back to the flash memory; when the master controller operates the above process, it may first complete the operation of changing data from 0 to 1 in the RAM storage space of the master controller, and after merging multiple data operations, it will finally perform the above operation process on the flash memory to complete the storage state after power failure. Figure 4 As shown, the existing flash memory page programming process includes: the flash memory receives a page programming instruction, an address and data; and the flash memory internally programs the selected page according to the address decoding to complete the page programming process.

[0005] Based on the above content, it can be seen that such an operation process is extremely complicated and takes a lot of time. In addition, the demand for RAM capacity will also increase the chip cost, and the data stored in the RAM will also be lost if there is a sudden power outage. In addition, there is also the problem of inconvenience for users to use, resulting in a poor user experience. Summary of the invention

[0006] The technical problem to be solved by the present disclosure is to overcome the above-mentioned defects in the prior art and to provide a NOR flash memory and a write control method and a write control system thereof.

[0007] The present invention solves the above technical problems through the following technical solutions:

[0008] In a first aspect of the present disclosure, a write control method for a NOR flash memory is provided, wherein the NOR flash memory is a flash memory with a page write function, and the write control method comprises:

[0009] Obtaining a target page write instruction, wherein the target page write instruction includes a target page address;

[0010] Based on the target page write instruction, a page write operation is controlled to be performed on the target page corresponding to the target page address in the NOR flash memory.

[0011] Preferably, the NOR flash memory with page write function is prepared based on SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) process.

[0012] Preferably, the target page write instruction further includes at least one target page write position under the target page and target write data at each target page write position;

[0013] The step of controlling, based on the target page write instruction, to perform a page write operation on the target page corresponding to the target page address in the NOR flash memory comprises:

[0014] Based on the target page write position and the corresponding target write data, a page write operation is controlled to be performed on the target page corresponding to the target page address in the NOR flash memory.

[0015] Preferably, the step of controlling the execution of a page write operation on the target page corresponding to the target page address in the NOR flash memory based on the target page write position and the corresponding target write data includes:

[0016] Controlling to perform a page erase operation on the target page corresponding to the target page address in the NOR flash memory;

[0017] In response to a page erase operation having been completed in the target page, based on the target page write position and the corresponding target write data, controlling writing of the target write data at the target page write position on the target page;

[0018] The page erase operation is an operation of writing 1 at a corresponding position in the target page, and the target write data written is 0.

[0019] Preferably, before the step of controlling the page erasing operation on the target page corresponding to the target page address in the NOR flash memory, the method further comprises:

[0020] Reading current page data in the target page corresponding to the target page address in the NOR flash memory;

[0021] In response to the current page data indicating that the target page is in an erased state, determining that a page erase operation has been completed in the target page, and executing the step of controlling writing the target write data at the target page write position on the target page based on the target page write position and the corresponding target write data;

[0022] In response to the current page data indicating that the target page is in an uncompleted erase state, the step of controlling to perform a page erase operation on the target page corresponding to the target page address in the NOR flash memory is performed.

[0023] Preferably, the step of controlling the execution of a page write operation on the target page corresponding to the target page address in the NOR flash memory based on the target page write position and the corresponding target write data includes:

[0024] Reading currently written data at each write position of the target page in the target page corresponding to the target page address in the NOR flash memory;

[0025] Obtaining a comparison result between the current write data and the corresponding target write data at each write position of the target page;

[0026] In response to the comparison result, a page write operation is controlled to be performed on each of the target page write locations on the target page.

[0027] Preferably, the target page write instruction includes a plurality of target page write locations;

[0028] The step of controlling, in response to the comparison result, to perform a page write operation on each of the target page write positions on the target page comprises:

[0029] In response to the comparison result, simultaneously controlling to perform a page write operation on each of the target page write positions on the target page;

[0030] and / or,

[0031] The step of reading the currently written data at each write position of the target page in the target page corresponding to the target page address in the NOR flash memory comprises:

[0032] According to the position sequence of different target page write positions, the currently written data at a preset number of the target page write positions are read in each batch until the currently written data at the remaining number of the target page write positions in the last batch are read; wherein the remaining number is greater than 1 and less than or equal to the preset number;

[0033] Or, in response to the total number of all target page write positions corresponding to the target page write instruction being less than a preset number, the current write data at the total number of target page write positions are acquired in the same batch.

[0034] Preferably, in response to the comparison result, the step of controlling the execution of a page write operation on each target page write position on the target page comprises:

[0035] In response to the current write data at the write position of the target page being inconsistent with the target write data, controlling writing of the target write data at the corresponding write position of the target page on the target page;

[0036] In response to the current write data at the target page write position being consistent with the target write data, it is determined not to perform a corresponding page write operation at the target page write position.

[0037] Preferably, in response to the comparison result, the step of controlling the execution of a page write operation on each target page write position on the target page comprises:

[0038] In response to the existence of at least one comparison result indicating that the current write data at the write position of the target page is 0 and the target write data is 1, controlling to perform a page erase operation on the target page corresponding to the target page address in the NOR flash memory, and after the page erase operation is completed in the target page, controlling to write the target write data at each of the target page write positions on the target page;

[0039] Wherein, the page erase operation is an operation of writing 1 at the corresponding position in the target page, and the target write data written is 0;

[0040] In response to the absence of the comparison result indicating that the current write data at the target page write position is 0 and the target write data is 1, writing the target write data at each of the target page write positions on the target page is controlled.

[0041] Preferably, the total operation durations of the page write operations corresponding to the different target page write instructions are all the same;

[0042] and / or,

[0043] The storage unit in the NOR flash memory includes a storage tube and a selection tube.

[0044] In a second aspect of the present disclosure, a write control system of a NOR flash memory is further provided, wherein the NOR flash memory is a flash memory with a page write function, and the write control system comprises:

[0045] A write instruction acquisition module, used to acquire a target page write instruction, wherein the target page write instruction includes a target page address;

[0046] A write control module is used to control the execution of a page write operation on a target page corresponding to the target page address in the NOR flash memory based on the target page write instruction.

[0047] Preferably, the NOR flash memory with page write function is prepared based on SONOS process.

[0048] Preferably, the target page write instruction further includes at least one target page write position under the target page and target write data at each target page write position;

[0049] The write control module is further used to control a page write operation to be performed on the target page corresponding to the target page address in the NOR flash memory based on the target page write position and the corresponding target write data.

[0050] Preferably, the write control module is further used to control the execution of a page erase operation on the target page corresponding to the target page address in the NOR flash memory; in response to the completion of the page erase operation in the target page, based on the target page write position and the corresponding target write data, control the writing of the target write data at the target page write position on the target page;

[0051] The page erase operation is an operation of writing 1 at a corresponding position in the target page, and the target write data written is 0.

[0052] Preferably, the write control system further includes:

[0053] A data reading module, used for reading the current page data in the target page corresponding to the target page address in the NOR flash memory;

[0054] a state determination module, configured to determine that a page erase operation has been completed in the target page in response to the current page data indicating that the target page is in an erased state, and to call the write control module to control writing of the target write data at the target page write position on the target page based on the target page write position and the corresponding target write data;

[0055] The state determination module is further configured to call the write control module to control a page erase operation on the target page corresponding to the target page address in the NOR flash memory in response to the current page data indicating that the target page is in an uncompleted erase state.

[0056] Preferably, the write control module includes:

[0057] A current data reading unit, used for reading the current written data at each write position of the target page in the target page corresponding to the target page address in the NOR flash memory;

[0058] A comparison result acquisition unit, used for acquiring a comparison result between the current write data and the corresponding target write data at each write position of the target page;

[0059] A write control unit is used for controlling, in response to the comparison result, to perform a page write operation on each of the target page write positions on the target page.

[0060] Preferably, the target page write instruction includes a plurality of target page write locations;

[0061] The write control unit is used for controlling, in response to the comparison result, to perform a page write operation on each of the target page write positions on the target page at the same time;

[0062] and / or,

[0063] The current data reading unit is used to read the current written data at a preset number of the target page write positions in each batch according to the position sequence of the different target page write positions, until the current written data at the remaining number of the target page write positions in the last batch is read; wherein the remaining number is greater than 1 and less than or equal to the preset number;

[0064] Or, in response to the total number of all target page write positions corresponding to the target page write instruction being less than a preset number, the current write data at the total number of target page write positions are acquired in the same batch.

[0065] Preferably, the write control unit is used for controlling the writing of the target write data at the corresponding target page write position on the target page in response to the current write data at the target page write position being inconsistent with the target write data;

[0066] The write control unit is further configured to determine not to perform a page write operation at the corresponding target page write position in response to the current write data at the target page write position being consistent with the target write data.

[0067] Preferably, the write control unit is used for controlling, in response to the existence of at least one comparison result indicating that the current write data at the write position of the target page is 0 and the target write data is 1, to perform a page erase operation on the target page corresponding to the target page address in the NOR flash memory, and after the page erase operation has been completed in the target page, to control writing of the target write data at each of the target page write positions on the target page;

[0068] Wherein, the page erase operation is an operation of writing 1 at the corresponding position in the target page, and the target write data written is 0;

[0069] The write control unit is further configured to control writing of the target write data at each of the target page write positions on the target page in response to the absence of the comparison result indicating that the current write data at the target page write position is 0 and the target write data is 1.

[0070] Preferably, the total operation durations of the page write operations corresponding to the different target page write instructions are all the same;

[0071] and / or,

[0072] The storage unit in the NOR flash memory includes a storage tube and a selection tube.

[0073] According to a third aspect of the present disclosure, a NOR flash memory is further provided, wherein the NOR flash memory includes the write control system of the NOR flash memory as described above.

[0074] On the basis of being in accordance with the common sense in the art, the above-mentioned preferred conditions can be arbitrarily combined to obtain the preferred embodiments of the present disclosure.

[0075] The positive and progressive effects of this disclosure are:

[0076] In the present disclosure, based on a NOR flash memory with a page write function, direct page write operation is supported, the direct write function is realized, the NOR flash memory operation process is greatly simplified, and the time for writing data in the flash memory is effectively reduced; at the same time, 0 or 1 is directly written in a page of the NOR flash memory, and there is no need to operate other pages in the same sector or the same area, so that even if power failure occurs during the operation, only the target page to which data is to be written is affected, and the data of other pages is not affected, thereby ensuring that the reliability of the write function is higher, and improving the reliability of the flash memory product and the overall product performance; in addition, for users of flash memory products, the whole process is simple and easy to operate, thereby improving the user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0077] Figure 1 A schematic diagram of a storage space hierarchy structure of an existing flash memory;

[0078] Figure 2 It is a schematic diagram of the operation of the storage space of the existing flash memory;

[0079] Figure 3 A flowchart of the writing control of the existing flash memory;

[0080] Figure 4 A flow chart for programming a flash page of an existing flash memory;

[0081] Figure 5 It is a flowchart of a write control method of a NOR flash memory according to Embodiment 1 of the present disclosure;

[0082] Figure 6 A schematic diagram of a storage space hierarchy structure of a NOR flash memory according to Embodiment 1 of the present disclosure;

[0083] Figure 7 This is a first flow chart of a write control method for a NOR flash memory according to Embodiment 2 of the present disclosure;

[0084] Figure 8 A second flow chart of the write control method of the NOR flash memory according to the second embodiment of the present disclosure;

[0085] Fig. 9 A third flow chart of the write control method of the NOR flash memory according to the second embodiment of the present disclosure;

[0086] Fig.10 This is a module schematic diagram of a write control system of a NOR flash memory according to Embodiment 3 of the present disclosure;

[0087] Fig.11 This is a module diagram of a write control system for a NOR flash memory according to Embodiment 4 of the present disclosure;

[0088] Fig.12 This is a module diagram of the NOR flash memory of Embodiment 5 of the present disclosure. DETAILED DESCRIPTION

[0089] The present disclosure is further described below by way of examples, but the present disclosure is not limited to the scope of the examples.

[0090] Prefixes such as "first" and "second" are used in the embodiments of the present disclosure only to distinguish different description objects, and have no limiting effect on the position, order, priority, quantity or content of the described objects. The use of prefixes such as ordinal numbers to distinguish description objects in the embodiments of the present disclosure does not constitute a limitation on the described objects. For the statement of the described objects, please refer to the description in the context of the embodiments, and no unnecessary limitation should be constituted due to the use of such prefixes. In addition, in the description of the present embodiment, unless otherwise specified, the meaning of "plurality" is two or more.

[0091] Based on the existing NOR flash memory write control scheme, the write process is complicated, time-consuming, easy to cause data loss when power is off, poor reliability and other problems, a new NOR flash memory write control scheme is proposed to solve these problems, specifically:

[0092] Example 1

[0093] The NOR flash memory of the present embodiment is a flash memory with a page writing function.

[0094] Preferably, the NOR flash memory with page write function is manufactured based on the SONOS process. Specifically, the storage unit in the NOR flash memory manufactured based on the SONOS process is composed of a storage tube and a selection tube.

[0095] Among them, the NOR flash memory prepared based on the SONOS process has a direct write function, which can directly operate the data in a page from 0 to 1 or from 1 to 0, that is, the NOR flash memory supports page write operations and can perform page erase operations without using a larger range of sector erase or block erase.

[0096] like Figure 5 As shown, the write control method of the NOR flash memory of this embodiment includes:

[0097] S101, obtaining a target page write instruction, where the target page write instruction includes a target page address;

[0098] S102 . Based on the target page write instruction, control the execution of a page write operation on the target page corresponding to the target page address in the NOR flash memory.

[0099] Among them, the NOR flash memory with direct write function is simple to operate. It only needs to write to the target page, and the data of other pages does not need to be erased and written, and will not be affected.

[0100] Specifically, Figure 6 FIG. 1 is a schematic diagram of the storage space operation of the NOR flash memory in this embodiment. Figure 6 The block state of the storage space of the NOR flash memory for direct write operation is shown, specifically the state after data is directly written to page 15 in sector 15. It can be seen that only page 15 of sector 15 is operated, and other pages are not operated and will not be affected.

[0101] In addition, since the erasing and programming areas of the NOR flash memory can both be selected as 256 bytes, the NOR flash memory can perform a 256-byte page operation to change the storage unit to both 0 and 1. If the user only wants to modify one bit of storage content, there is no need to first erase the sector or block and then perform a page write operation (corresponding to a programming operation) as in the prior art, but it can be completed directly with a write operation. Therefore, for NOR flash memory users, the entire implementation process is simple and easy to operate.

[0102] The content stored in the flash memory is divided into code type and data type content. Code type content generally only needs to be read frequently, and data type content often needs to be written 0 or 1 frequently. The write control scheme in this solution can well support the writing needs of data type content.

[0103] In this embodiment, based on a NOR flash memory with a page write function, direct page write operations are supported, and the direct write function is realized, which greatly simplifies the NOR flash memory operation process and effectively reduces the time for writing data in the flash memory; at the same time, 0 or 1 is directly written in a page in the NOR flash memory, and there is no need to operate other pages in the same sector or the same area, so that even if a power failure occurs during the operation, only the target page to which data is to be written is affected, and the data on other pages is not affected, thereby ensuring that the reliability of the write function is higher, and improving the reliability of the flash memory product and the overall product performance; in addition, for users of flash memory products, the entire process is simple and easy to operate, thereby improving the user experience.

[0104] Example 2

[0105] The write control method of the NOR flash memory of this embodiment is a further improvement of the embodiment 1, specifically:

[0106] In an implementable solution, the target page write instruction further includes at least one target page write position under the target page and target write data at each target page write position;

[0107] like Figure 7 As shown, step S102 includes:

[0108] S1021. Based on the target page write position and the corresponding target write data, control the execution of a page write operation on the target page corresponding to the target page address in the NOR flash memory.

[0109] In this solution, during page write control, the specified write data is written to corresponding different write locations, thereby ensuring the write speed and the write accuracy, thereby effectively ensuring the reliability and efficiency of the page write operation.

[0110] In one feasible solution, Figure 8 As shown, step S1021 includes:

[0111] S102111, controlling to perform a page erase operation on a target page corresponding to a target page address in a NOR flash memory;

[0112] Among them, the erasure time of the page erase operation only takes about 0.5 milliseconds, and the erase time can be increased according to actual needs (for example, the erase time can be increased to about 10 milliseconds), so that the effect of a full erase operation can be achieved. In this way, the erase plus program operation becomes a complete operation that can write both 0 and 1 at the same time.

[0113] S102112, in response to the page erase operation being completed in the target page, based on the target page write position and the corresponding target write data, controlling writing of the target write data at the target page write position on the target page;

[0114] The page erase operation is an operation of writing 1 at a corresponding position in the target page, and the target write data is 0.

[0115] In this scheme, during the page programming operation, a short page erase operation (i.e., pre-erase) is required before a page write operation (i.e., programming operation) is performed, so that the stored data after programming will not be over-programmed, and at the same time can be maintained in a narrow voltage Vt distribution range to ensure the reliability and rationality of write control.

[0116] In an implementable solution, before step S102111, the method further includes:

[0117] Read the current page data in the target page corresponding to the target page address in the NOR flash memory;

[0118] In response to the current page data indicating that the target page is in an erased state, determining that a page erase operation has been completed in the target page, and executing the step of controlling writing the target write data at the target page write position on the target page based on the target page write position and the corresponding target write data;

[0119] In response to the current page data indicating that the target page is in an uncompleted erase state, a step of controlling a page erase operation to be performed on the target page corresponding to the target page address in the NOR flash memory is executed.

[0120] Considering a special case, such as when the data in the target page is already in a blank page state of all 1s, it is unnecessary to perform an erase process on the target page, and the internal page programming operation can be performed directly, because an erase verification process is performed before erasing.

[0121] In this scheme, an erase verification process is introduced. When entering the erase verification process, the data in the page is read. If the data in the page is all 1, it is determined that the page is already in an erased state, and it is determined to skip the subsequent erase phase with a longer time; that is, once it is verified that the data in the current page is all 1, the erase operation is skipped, and the internal page programming operation is directly performed to avoid performing unnecessary erase operations and wasting unnecessary operation time. The erase operation is only performed in time when it is determined that the data in the current page is not all 1, thereby reasonably and effectively completing the corresponding write control process, further shortening the time for flash memory to write data, improving the rationality, reliability and efficiency of the overall processing, while also further improving the user experience and reducing unnecessary energy consumption.

[0122] In one feasible solution, Fig. 9As shown, step S1021 includes:

[0123] S102121, reading the current write data at each target page write position in the target page corresponding to the target page address in the NOR flash memory;

[0124] S102122, obtaining a comparison result between the current write data and the corresponding target write data at each target page write position;

[0125] S102123. In response to the comparison result, control the execution of a page write operation on each target page write position on the target page.

[0126] In this scheme, even if the data in the target page is not all 1 (non-blank page state), the data writing in the target page can still be completed. Specifically, the data in the target page is read and verified, and the current write data at the read target page write position is compared with the target write data to be written. Based on the comparison result, the data writing control of each local target page write position in the entire target page is performed to finally complete the write control operation of all data in the target page. That is, this process does not require the erasing operation of the entire page, and does not require the execution of a long erasing phase, which further shortens the time for flash memory to write data.

[0127] In one practicable solution, the target page write instruction includes a plurality of target page write locations;

[0128] Step S102123 includes:

[0129] In response to the comparison result, simultaneously controlling to perform a page write operation on each target page write position on the target page;

[0130] In this scheme, after obtaining the corresponding comparison results at each target page write position, the write operations at these target page write positions are controlled to be performed synchronously. While meeting the write control requirements in the NOR flash memory, the write control operation is simplified, making the write process orderly, and ensuring the processing efficiency and rationality of the entire write control process.

[0131] In one feasible solution, step S102121 includes:

[0132] According to the position sequence of different target page write positions, currently written data at a preset number of target page write positions are read in each batch until currently written data at the remaining number of target page write positions in the last batch are read; wherein the remaining number is greater than 1 and less than or equal to the preset number;

[0133] Or, in response to the total number of all target page write positions corresponding to the target page write instruction being less than a preset number, current write data at the total number of target page write positions are acquired in the same batch.

[0134] For example, the preset number is 4, and according to the address of the write position of the target page, the current write data corresponding to the 4 positions are read in sequence and each batch is read until the reading of the current write data at all positions is completed; for the last batch, the corresponding read number can be 4, or 1, 2 or 3;

[0135] Taking the case where there are 27 target page write locations in the target page that need to write data as an example, 7 batches of data reading processes need to be performed in sequence. The first 6 batches read the current write data of 4 target page write locations each time, and the 7th batch reads the current write data of the last 3 target page write locations.

[0136] Taking the case where there are 3 target page write locations in the target page that need to write data as an example, only one batch is needed to read the current write data of the 3 target page write locations.

[0137] In this scheme, when reading the current write data of different target page write positions in the target page, the pre-set reading rules are used for reading. While meeting the write control requirements in the NOR flash memory, the data reading process is orderly and reliable, thereby ensuring the reliability of the entire write control operation and ensuring the processing efficiency and rationality of the entire write control process.

[0138] In one feasible solution, step S102123 includes:

[0139] In response to the current write data at the target page write position being inconsistent with the target write data, controlling the target write data to be written at the corresponding target page write position on the target page;

[0140] In response to the current write data at the target page write position being consistent with the target write data, it is determined not to perform a page write operation at the corresponding target page write position.

[0141] For example, if the current write data at the write position of the target page is 1 and the corresponding target write data is 0, the comparison result is that the two are inconsistent. In this case, the current write data 1 at the write position of the target page is changed to 0;

[0142] On the contrary, if the current write data at the write position of the target page is 1 and the corresponding target write data is 1, the comparison result is that the two are consistent, and the current write data at the write position of the target page remains unchanged. Specifically, the storage unit of the NOR flash memory prepared based on the SONOS process has only the case of 1 changing to 0 by default; that is, the original storage data in the page is not all 1, and the newly written data has both 0 and 1, but because the storage unit only has the case of 1 changing to 0, that is, the user only changes part of the data 1 to 0 based on the original stored data, the process does not need to perform the erase operation in the process, only the programming operation is required.

[0143] In this solution, the data stored in the flash memory is read out and compared with the data to be written, and the data writing control of each local target page writing position in the entire target page is performed based on the comparison result, so as to finally complete the writing control operation of all data in the target page. That is, this process does not need to perform the erasing operation of the entire page, and does not need to execute the long erasing phase, which further shortens the time for flash memory to write data.

[0144] In one feasible solution, step S102123 includes:

[0145] In response to at least one comparison result indicating that the current write data at the target page write position is 0 and the target write data is 1, controlling to perform a page erase operation on the target page corresponding to the target page address in the NOR flash memory, and after the page erase operation has been completed in the target page, controlling to write the target write data at each target page write position on the target page;

[0146] Among them, the page erase operation is an operation of writing 1 at the corresponding position in the target page, and the target write data written is 0; in response to the absence of a comparison result indicating that the current write data at the target page write position is 0 and the target write data is 1, the target write data is controlled to be written at each target page write position on the target page.

[0147] In this scheme, the data stored in the flash memory is read out and compared with the data to be written. Only when the data needs to be changed from 0 to 1 (that is, the current written data is 0 and the new written data is 1) is it necessary to perform an erase operation. At this time, the page erase operation is triggered, and after the page erase operation is completed, the target write data at each target page write position in the target page is completely written;

[0148] When data needs to be changed from 1 to 0 (i.e., the current written data is 1 and the new written data is 0), the data at the write position of the target page can be directly changed to 0 without performing an erase operation, only a programming operation is required;

[0149] If the current written data is 1 and the newly written data is 1, it is determined that no operation needs to be performed;

[0150] In the case where the currently written data is 0 and the newly written data is 0, it is determined that no operation needs to be performed.

[0151] That is to say, even if the data in the page is not in a blank state of all 1s, the newly written data is based on the original data with some data 1 changed to 0, and the other data are 1 remains 1, or 0 remains 0. The above situation is the situation where the data does not change from 0 to 1. In this case, the page erase operation can be skipped and only the programming operation is required.

[0152] In this scheme, by comparing the current write data at the target page write position with the target write data, it is checked whether there is a need to change the data from 0 to 1. If so, a page erase operation is triggered. Compared with triggering the page erase operation based on whether the data in the target page is not all 1, it can more reasonably and accurately determine whether the flash memory needs to perform an erase operation, thereby further improving the accuracy and reliability of the entire write control.

[0153] In an implementable solution, the total operation durations of the page write operations corresponding to different target page write instructions are all the same;

[0154] In this solution, the NOR flash memory prepared based on the SONOS process determines that no matter how much data is written to any page, the corresponding total write time is equal, while meeting the write control requirements in the NOR flash memory, achieving the controllability and reliability of the overall write operation.

[0155] Example 3

[0156] The NOR flash memory of the present embodiment is a flash memory with a page writing function.

[0157] Preferably, the NOR flash memory with page write function is manufactured based on the SONOS process. Specifically, the storage unit in the NOR flash memory manufactured based on the SONOS process is composed of a storage tube and a selection tube.

[0158] Among them, the NOR flash memory prepared based on the SONOS process has a direct write function, which can directly operate the data in a page from 0 to 1 or from 1 to 0, that is, the NOR flash memory supports page write operations and can perform page erase operations without using a larger range of sector erase or block erase.

[0159] like Fig.10 As shown, the write control system of the NOR flash memory of this embodiment includes:

[0160] A write instruction acquisition module 1 is used to acquire a target page write instruction, where the target page write instruction includes a target page address;

[0161] The write control module 2 is used to control the execution of a page write operation on a target page corresponding to a target page address in a NOR flash memory based on a target page write instruction.

[0162] Among them, the NOR flash memory with direct write function is simple to operate. It only needs to write to the target page, and the data of other pages does not need to be erased and written, and will not be affected.

[0163] Specifically, Figure 6 FIG. 1 is a schematic diagram of the storage space operation of the NOR flash memory in this embodiment. Figure 6 The block state of the storage space of the NOR flash memory for direct write operation is shown, specifically the state after data is directly written to page 15 in sector 15. It can be seen that only page 15 of sector 15 is operated, and other pages are not operated and will not be affected.

[0164] In addition, since the erasing and programming areas of the NOR flash memory can both be selected as 256 bytes, the NOR flash memory can perform a 256-byte page operation to change the storage unit to both 0 and 1. If the user only wants to modify one bit of storage content, there is no need to first erase the sector or block and then perform a page write operation (corresponding to a programming operation) as in the prior art, but it can be completed directly with a write operation. Therefore, for NOR flash memory users, the entire implementation process is simple and easy to operate.

[0165] The content stored in the flash memory is divided into code type and data type content. Code type content generally only needs to be read frequently, and data type content often needs to be written 0 or 1 frequently. The write control scheme in this solution can well support the writing needs of data type content.

[0166] In this embodiment, based on a NOR flash memory with a page write function, direct page write operations are supported, and the direct write function is realized, which greatly simplifies the NOR flash memory operation process and effectively reduces the time for writing data in the flash memory; at the same time, 0 or 1 is directly written in a page in the NOR flash memory, and there is no need to operate other pages in the same sector or the same area, so that even if a power failure occurs during the operation, only the target page to which data is to be written is affected, and the data on other pages is not affected, thereby ensuring that the reliability of the write function is higher, and improving the reliability of the flash memory product and the overall product performance; in addition, for users of flash memory products, the entire process is simple and easy to operate, thereby improving the user experience.

[0167] Example 4

[0168] The write control system of the NOR flash memory of this embodiment is a further improvement of the embodiment 3, specifically:

[0169] In an implementable solution, the target page write instruction further includes at least one target page write position under the target page and target write data at each target page write position;

[0170] The write control module 2 is further used to control the execution of a page write operation on a target page corresponding to a target page address in the NOR flash memory based on the target page write position and the corresponding target write data.

[0171] In this solution, during page write control, the specified write data is written to corresponding different write locations, thereby ensuring the write speed and the write accuracy, thereby effectively ensuring the reliability and efficiency of the page write operation.

[0172] In an implementable solution, the write control module 2 is further used to control the execution of a page erase operation on a target page corresponding to a target page address in the NOR flash memory;

[0173] In response to a page erase operation being completed in the target page, based on the target page write position and the corresponding target write data, controlling writing of the target write data at the target page write position on the target page;

[0174] The page erase operation is an operation of writing 1 at a corresponding position in the target page, and the target write data is 0.

[0175] Among them, the erasure time of the page erase operation only takes about 0.5 milliseconds, and the erase time can be increased according to actual needs (for example, the erase time can be increased to about 10 milliseconds), so that the effect of a full erase operation can be achieved. In this way, the erase plus program operation becomes a complete operation that can write both 0 and 1 at the same time.

[0176] In this scheme, during the page programming operation, a short page erase operation (i.e., pre-erase) is required before a page write operation (i.e., programming operation) is performed, so that the stored data after programming will not be over-programmed, and at the same time can be maintained in a narrow voltage Vt distribution range to ensure the reliability and rationality of write control.

[0177] In one feasible solution, Fig.11 As shown, the write control system also includes:

[0178] The data reading module 3 is used to read the current page data in the target page corresponding to the target page address in the NOR flash memory;

[0179] The state determination module 4 is used for determining that the page erase operation has been completed in the target page in response to the current page data indicating that the target page is in the erased state, and calling the write control module 2 to control the writing of the target write data at the target page write position on the target page based on the target page write position and the corresponding target write data;

[0180] The state determination module 4 is further configured to call the write control module 2 to control the execution of a page erase operation on the target page corresponding to the target page address in the NOR flash memory in response to the current page data indicating that the target page is in an uncompleted erase state.

[0181] Considering a special case, such as when the data in the target page is already in a blank page state of all 1s, it is unnecessary to perform an erase process on the target page, and the internal page programming operation can be performed directly, because an erase verification process is performed before erasing.

[0182] In this scheme, an erase verification process is introduced. When entering the erase verification process, the data in the page is read. If the data in the page is all 1, it is determined that the page is already in an erased state, and it is determined to skip the subsequent erase phase with a longer time; that is, once it is verified that the data in the current page is all 1, the erase operation is skipped, and the internal page programming operation is directly performed to avoid performing unnecessary erase operations and wasting unnecessary operation time. The erase operation is only performed in time when it is determined that the data in the current page is not all 1, thereby reasonably and effectively completing the corresponding write control process, further shortening the time for flash memory to write data, improving the rationality, reliability and efficiency of the overall processing, while also further improving the user experience and reducing unnecessary energy consumption.

[0183] In an implementable solution, the write control module 2 includes:

[0184] A current data reading unit, used for reading the current written data at each target page write position in the target page corresponding to the target page address in the NOR flash memory;

[0185] A comparison result acquisition unit, used to acquire a comparison result between the current write data and the corresponding target write data at each target page write position;

[0186] The write control unit is used for controlling the execution of a page write operation on each target page write position on the target page in response to the comparison result.

[0187] In this scheme, even if the data in the target page is not all 1 (non-blank page state), the data writing in the target page can still be completed. Specifically, the data in the target page is read and verified, and the current write data at the read target page write position is compared with the target write data to be written. Based on the comparison result, the data writing control of each local target page write position in the entire target page is performed to finally complete the write control operation of all data in the target page. That is, this process does not require the erasing operation of the entire page, and does not require the execution of a long erasing phase, which further shortens the time for flash memory to write data.

[0188] In one practicable solution, the target page write instruction includes a plurality of target page write locations;

[0189] The write control unit is used to control the execution of a page write operation on each target page write position on the target page in response to the comparison result;

[0190] In this scheme, after obtaining the corresponding comparison results at each target page write position, the write operations at these target page write positions are controlled to be performed synchronously. While meeting the write control requirements in the NOR flash memory, the write control operation is simplified, making the write process orderly, and ensuring the processing efficiency and rationality of the entire write control process.

[0191] In an practicable solution, the current data reading unit is used to read the current written data at the target page write positions of a preset number in each batch according to the position sequence of different target page write positions, until the current written data at the target page write positions of the remaining number in the last batch are read; wherein the remaining number is greater than 1 and less than or equal to the preset number;

[0192] Or, in response to the total number of all target page write positions corresponding to the target page write instruction being less than a preset number, current write data at the total number of target page write positions are acquired in the same batch.

[0193] For example, the preset number is 4, and according to the address of the write position of the target page, the current write data corresponding to the 4 positions are read in sequence and each batch is read until the reading of the current write data at all positions is completed; for the last batch, the corresponding read number can be 4, or 1, 2 or 3;

[0194] Taking the case where there are 27 target page write locations in the target page that need to write data as an example, 7 batches of data reading processes need to be performed in sequence. The first 6 batches read the current write data of 4 target page write locations each time, and the 7th batch reads the current write data of the last 3 target page write locations.

[0195] Taking the case where there are 3 target page write locations in the target page that need to write data as an example, only one batch is needed to read the current write data of the 3 target page write locations.

[0196] In this scheme, when reading the current write data of different target page write positions in the target page, the pre-set reading rules are used for reading. While meeting the write control requirements in the NOR flash memory, the data reading process is orderly and reliable, thereby ensuring the reliability of the entire write control operation and ensuring the processing efficiency and rationality of the entire write control process.

[0197] In an implementable solution, the write control unit is used to control writing of the target write data at the corresponding target page write position on the target page in response to the inconsistency between the current write data at the target page write position and the target write data;

[0198] The write control unit is further configured to determine not to perform a page write operation at the corresponding target page write position in response to the current write data at the target page write position being consistent with the target write data.

[0199] For example, if the current write data at the write position of the target page is 1 and the corresponding target write data is 0, the comparison result is that the two are inconsistent. In this case, the current write data 1 at the write position of the target page is changed to 0;

[0200] On the contrary, if the current write data at the write position of the target page is 1 and the corresponding target write data is 1, the comparison result is that the two are consistent, and the current write data at the write position of the target page remains unchanged. Specifically, the storage unit of the NOR flash memory prepared based on the SONOS process has only the case of 1 changing to 0 by default; that is, the original storage data in the page is not all 1, and the newly written data has both 0 and 1, but because the storage unit only has the case of 1 changing to 0, that is, the user only changes part of the data 1 to 0 based on the original stored data, the process does not need to perform the erase operation in the process, only the programming operation is required.

[0201] In this solution, the data stored in the flash memory is read out and compared with the data to be written, and the data writing control of each local target page writing position in the entire target page is performed based on the comparison result, so as to finally complete the writing control operation of all data in the target page. That is, this process does not need to perform the erasing operation of the entire page, and does not need to execute the long erasing phase, which further shortens the time for flash memory to write data.

[0202] In an practicable solution, the write control unit is used to control the execution of a page erase operation on a target page corresponding to a target page address in a NOR flash memory in response to the existence of at least one comparison result indicating that the current write data at the target page write position is 0 and the target write data is 1, and after the page erase operation has been completed in the target page, control the writing of the target write data at each target page write position on the target page;

[0203] Wherein, the page erase operation is an operation of writing 1 at the corresponding position in the target page, and the target write data written is 0;

[0204] The write control unit is further configured to control writing of the target write data at each target page write position on the target page in response to the absence of a comparison result indicating that the current write data at the target page write position is 0 and the target write data is 1.

[0205] In this scheme, the data stored in the flash memory is read out and compared with the data to be written. Only when the data needs to be changed from 0 to 1 (that is, the current written data is 0 and the new written data is 1) is it necessary to perform an erase operation. At this time, the page erase operation is triggered, and after the page erase operation is completed, the target write data at each target page write position in the target page is completely written;

[0206] When data needs to be changed from 1 to 0 (i.e., the current written data is 1 and the new written data is 0), the data at the write position of the target page can be directly changed to 0 without performing an erase operation, only a programming operation is required;

[0207] If the current written data is 1 and the newly written data is 1, it is determined that no operation needs to be performed;

[0208] In the case where the currently written data is 0 and the newly written data is 0, it is determined that no operation needs to be performed.

[0209] That is to say, even if the data in the page is not in a blank state of all 1s, the newly written data is based on the original data with some data 1 changed to 0, and the other data are 1 remains 1, or 0 remains 0. The above situation is the situation where the data does not change from 0 to 1. In this case, the page erase operation can be skipped and only the programming operation is required.

[0210] In this scheme, by comparing the current write data at the target page write position with the target write data, it is checked whether there is a need to change the data from 0 to 1. If so, a page erase operation is triggered. Compared with triggering the page erase operation based on whether the data in the target page is not all 1, it can more reasonably and accurately determine whether the flash memory needs to perform an erase operation, thereby further improving the accuracy and reliability of the entire write control.

[0211] In an implementable solution, the total operation durations of the page write operations corresponding to different target page write instructions are all the same.

[0212] In this solution, the NOR flash memory prepared based on the SONOS process determines that no matter how much data is written to any page, the corresponding total write time is equal, while meeting the write control requirements in the NOR flash memory, achieving the controllability and reliability of the overall write operation.

[0213] As for the system embodiment, since it basically corresponds to the method embodiment, the relevant parts can refer to the partial description of the method embodiment. The system embodiment described above is only illustrative, in which the units described as separate components may or may not be physically separated, and the components as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the disclosed solution.

[0214] Example 5

[0215] like Fig.12 As shown, the NOR flash memory 100 of this embodiment includes the write control system 200 of the NOR flash memory of the third or fourth embodiment.

[0216] The NOR flash memory of the present embodiment is integrated with the above-mentioned write control system, can support page write operations, realizes direct write function, greatly simplifies the operation process of the NOR flash memory, effectively reduces the time of writing data in the flash memory, and in the event of power failure, only the target page to be written is affected, and the data of other pages are not affected, thereby ensuring that the reliability of the write function is higher, thereby effectively improving the overall product performance of the NOR flash memory.

[0217] Although the specific embodiments of the present disclosure are described above, those skilled in the art should understand that this is only an example, and the protection scope of the present disclosure is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present disclosure, but these changes and modifications all fall within the protection scope of the present disclosure.

Claims

1. A method for controlling writing of a NOR flash memory, characterized in that: The NOR flash memory is a flash memory with a page write function, and the write control method includes: Obtaining a target page write instruction, wherein the target page write instruction includes a target page address; Based on the target page write instruction, a page write operation is controlled to be performed on the target page corresponding to the target page address in the NOR flash memory.

2. The writing control method according to claim 1, characterized in that: The NOR flash memory with page writing function is prepared based on the SONOS process.

3. The writing control method according to claim 1 or 2, characterized in that: The target page write instruction further includes at least one target page write position under the target page and target write data at each target page write position; The step of controlling the execution of a page write operation on a target page corresponding to the target page address in the NOR flash memory based on the target page write instruction comprises: Based on the target page write position and the corresponding target write data, a page write operation is controlled to be performed on the target page corresponding to the target page address in the NOR flash memory.

4. The writing control method according to claim 3, characterized in that: The step of controlling the execution of a page write operation on the target page corresponding to the target page address in the NOR flash memory based on the target page write position and the corresponding target write data comprises: Controlling to perform a page erase operation on the target page corresponding to the target page address in the NOR flash memory; In response to a page erase operation having been completed in the target page, based on the target page write position and the corresponding target write data, controlling writing of the target write data at the target page write position on the target page; The page erase operation is an operation of writing 1 at a corresponding position in the target page, and the target write data written is 0.

5. The writing control method according to claim 4, characterized in that: Before the step of controlling the page erasing operation on the target page corresponding to the target page address in the NOR flash memory, the method further includes: Reading current page data in the target page corresponding to the target page address in the NOR flash memory; In response to the current page data indicating that the target page is in an erased state, determining that a page erase operation has been completed in the target page, and executing the step of controlling writing the target write data at the target page write position on the target page based on the target page write position and the corresponding target write data; In response to the current page data indicating that the target page is in an uncompleted erase state, the step of controlling to perform a page erase operation on the target page corresponding to the target page address in the NOR flash memory is performed.

6. The writing control method according to claim 3, characterized in that: The step of controlling the execution of a page write operation on the target page corresponding to the target page address in the NOR flash memory based on the target page write position and the corresponding target write data comprises: Reading currently written data at each write position of the target page in the target page corresponding to the target page address in the NOR flash memory; Obtaining a comparison result between the current write data and the corresponding target write data at each write position of the target page; In response to the comparison result, a page write operation is controlled to be performed on each of the target page write locations on the target page.

7. The writing control method according to claim 6, characterized in that: The target page write instruction includes a plurality of target page write locations; The step of controlling, in response to the comparison result, to perform a page write operation on each of the target page write positions on the target page comprises: In response to the comparison result, simultaneously controlling to perform a page write operation on each of the target page write positions on the target page; and / or, The step of reading the currently written data at each write position of the target page in the target page corresponding to the target page address in the NOR flash memory comprises: According to the position sequence of different target page write positions, the currently written data at a preset number of the target page write positions are read in each batch until the currently written data at the remaining number of the target page write positions in the last batch are read; wherein the remaining number is greater than 1 and less than or equal to the preset number; Or, in response to the total number of all target page write positions corresponding to the target page write instruction being less than a preset number, the current write data at the total number of target page write positions are acquired in the same batch.

8. The writing control method according to claim 7, characterized in that: The step of controlling, in response to the comparison result, to perform a page write operation on each of the target page write positions on the target page comprises: In response to the current write data at the write position of the target page being inconsistent with the target write data, controlling writing of the target write data at the corresponding write position of the target page on the target page; In response to the current write data at the target page write position being consistent with the target write data, it is determined not to perform a corresponding page write operation at the target page write position.

9. The writing control method according to claim 7, characterized in that: The step of controlling, in response to the comparison result, to perform a page write operation on each of the target page write positions on the target page comprises: In response to at least one comparison result indicating that the current write data at the write position of the target page is 0 and the target write data is 1, controlling to perform a page erase operation on the target page corresponding to the target page address in the NOR flash memory, and after the page erase operation is completed in the target page, controlling to write the target write data at each of the target page write positions on the target page; Wherein, the page erase operation is an operation of writing 1 at the corresponding position in the target page, and the target write data written is 0; In response to the absence of the comparison result indicating that the current write data at the target page write position is 0 and the target write data is 1, writing the target write data at each of the target page write positions on the target page is controlled.

10. The writing control method according to claim 1 or 2, characterized in that: The total operation durations of the page write operations corresponding to the different target page write instructions are all the same; and / or, The storage unit in the NOR flash memory includes a storage tube and a selection tube.

11. A write control system for a NOR flash memory, characterized in that: The NOR flash memory is a flash memory with a page write function, and the write control system includes: A write instruction acquisition module, used to acquire a target page write instruction, wherein the target page write instruction includes a target page address; A write control module is used to control the execution of a page write operation on a target page corresponding to the target page address in the NOR flash memory based on the target page write instruction.

12. A NOR flash memory, characterized in that: The NOR flash memory includes the write control system of the NOR flash memory as claimed in claim 11.

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