Memory device and operating method thereof

Abstract

The invention relates to a memory device and an operating method thereof. A memory device and a method of operating a memory device include a memory block including a cell plug extending between a first line and a second line, in which a first select line, a first word line group, a first transfer word line, a second word line group, and a second select line are arranged between the first line and the second line along the cell plug. The memory device further includes a peripheral circuit configured to apply an erase voltage to the first line or the second line, apply an auxiliary voltage to the first transfer word line when the erase voltage is applied, and lower a potential of the first transfer word line when the erase voltage is maintained at a target level.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate to a memory device and a method of operating the memory device, and more particularly, to a memory device capable of performing an erase operation and a method of operating the memory device. Background Art

[0002] The memory device may include a memory cell array in which data is stored and a peripheral circuit that performs a program operation, a read operation, or an erase operation on the memory cell array.

[0003] The memory cell array may include a plurality of memory blocks disposed between bit lines and source lines, and each memory block may include a cell plug extending in a vertical direction from a substrate. Each cell plug may include a source selection transistor, a memory cell, and a drain selection transistor.

[0004] The erase operation of the memory device can be performed using a method of directly applying an erase voltage to a cell plug through a source line or a bit line or a method of using a gate induced drain leakage (GIDL). In these methods, since interference from a voltage applied to peripheral elements is reduced, an erase operation using GIDL can be stably performed, but the time required for the erase operation may be longer. Summary of the invention

[0005] According to an embodiment of the present disclosure, a first memory device is provided. The first memory device may include a memory block including a cell plug extending between a source line and a bit line, wherein a source selection line, a first word line group, a first transmission word line, a second word line group, and a drain selection line are arranged between the source line and the bit line along the cell plug. The first memory device may also include a peripheral circuit configured to apply an erase voltage to a source line or a bit line, apply an auxiliary voltage to a first transmission word line when applying the erase voltage, and reduce a potential of the first transmission word line when the erase voltage is maintained at a target level.

[0006] According to an embodiment of the present disclosure is a second memory device. The second memory device may include a first sub-block, a second sub-block, and a third sub-block disposed between a source line and a bit line; a first connection region disposed between the first sub-block and the second sub-block; a second connection region disposed between the second sub-block and the third sub-block; a first transmission word line adjacent to the first connection region; and a second transmission word line adjacent to the second connection region. The second memory device may also include a peripheral circuit configured to apply an auxiliary voltage to the first transmission word line or the second transmission word line when an erase voltage is applied to the source line or the bit line, and configured to reduce the potential of the first transmission word line or the second transmission word line to which the auxiliary voltage is applied when the erase voltage is maintained at a target level.

[0007] According to an embodiment of the present disclosure, a method for operating a memory device may include: during an erase operation performed on a memory block including a cell plug extending between a source line and a bit line, wherein a source select line, a first word line group, a first transmission word line, a second word line group, and a drain select line are arranged between the source line and the bit line along the cell plug, applying an erase voltage to the source line or the bit line, applying an auxiliary voltage to the first transmission word line when the erase voltage is applied to the source line or the bit line, and reducing the potential of the first transmission word line when the erase voltage is maintained at a target level. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a diagram illustrating a memory device.

[0009] Figure 2A and Figure 2B is a diagram illustrating a memory cell array.

[0010] Figure 3 is a diagram illustrating a storage block.

[0011] FIG. 4A to FIG. 4G The diagrams illustrate various structures of storage blocks.

[0012] Figure 5 This is a diagram illustrating GIDL.

[0013] Figure 6 is a diagram illustrating a principle of an erase operation according to an embodiment of the present disclosure.

[0014] Figure 7 is a timing chart illustrating an erase operation according to the first embodiment of the present disclosure.

[0015] Figure 8 is a timing chart showing an erase operation according to the second embodiment of the present disclosure.

[0016] Fig. 9 is a flowchart illustrating an erase operation according to the third embodiment of the present disclosure.

[0017] Fig.10 is a timing chart illustrating an erase operation according to the third embodiment of the present disclosure.

[0018] Fig.11 is a diagram illustrating a structure of a unit plug according to an embodiment of the present disclosure.

[0019] Fig.12 is a diagram illustrating the principle of an erase operation according to a fourth embodiment of the present disclosure.

[0020] Fig.13 is a timing chart illustrating an erase operation according to the fourth embodiment of the present disclosure.

[0021] Fig.14 is a diagram illustrating the principle of an erase operation according to a fifth embodiment of the present disclosure.

[0022] Fig.15 is a timing chart illustrating an erase operation according to the fifth embodiment of the present disclosure.

[0023] Fig.16 is a diagram illustrating the principle of an erase operation according to a sixth embodiment of the present disclosure.

[0024] Fig.17 is a timing chart illustrating an erase operation according to a sixth embodiment of the present disclosure.

[0025] Fig.18 is a diagram illustrating a memory card system to which a memory device according to the present disclosure is applied.

[0026] Fig.19 is a diagram illustrating a solid state drive (SSD) system to which a memory device according to the present disclosure is applied. DETAILED DESCRIPTION

[0027] The specific structural or functional description disclosed herein is exemplified to describe the embodiments according to the concept of the present disclosure. The embodiments according to the concept of the present disclosure should not be interpreted as being limited to the embodiments described below, and may be modified in various forms and replaced with other equivalent embodiments.

[0028] Hereinafter, it will be understood that although the terms "first" and "second" may be used herein to describe various elements, these elements should not be limited by these terms. The terms are used to distinguish one element from other elements, rather than implying the number or order of the elements.

[0029] Various embodiments of the present disclosure are directed to a memory device capable of reducing the time required for an erase operation and a method of operating the memory device.

[0030] Figure 1 is a diagram illustrating a memory device.

[0031] Reference Figure 1 , the memory device 100 may include a memory cell array 110 and a peripheral circuit 180 .

[0032] The memory cell array 110 may include first to j-th memory blocks BLK1 to BLKj. Each of the first to j-th memory blocks BLK1 to BLKj may include a memory cell capable of storing data. A drain select line DSL, a word line WL, a source select line SSL, and a source line SL may be coupled to each of the first to j-th memory blocks BLK1 to BLKj, and a bit line BL may be commonly coupled to the first to j-th memory blocks BLK1 to BLKj.

[0033] Each of the first to j-th memory blocks BLK1 to BLKj may be formed to have a three-dimensional (3D) structure. Each memory block having the 3D structure may include memory cells stacked on a substrate in a vertical direction.

[0034] According to the programming scheme, each memory cell can store 1 bit of data or 2 or more bits of data. For example, the scheme for storing 1 bit of data in one memory cell is called a single-level cell (SLC) scheme, and the scheme for storing 2 bits of data in one memory cell is called a multi-level cell (MLC) scheme. The scheme for storing 3 bits of data in one memory cell is called a three-level cell (TLC) scheme, and the scheme for storing 4 bits of data in one memory cell is called a quad-level cell (QLC) scheme. In addition, 5 or more bits of data can be stored in one memory cell.

[0035] The peripheral circuit 180 may perform a program operation to store data in the memory cell array 110, a read operation to output data stored in the memory cell array 110, and an erase operation to erase data stored in the memory cell array 110. For example, the peripheral circuit 180 may include a voltage generator 120, a row decoder 130, a page buffer group 140, a column decoder 150, an input / output circuit 160, and a control circuit 170.

[0036] The voltage generator 120 may generate various operating voltages Vop for programming operations, reading operations, or erasing operations in response to the operation code OPCD. For example, the voltage generator 120 may generate a programming voltage, a turn-on voltage, a turn-off voltage, a negative voltage, a precharge voltage, a verification voltage, a read voltage, a pass voltage, an erase voltage, an auxiliary voltage, or a compensation voltage in response to the operation code OPCD. In addition, the voltage generator 120 may float the node of the voltage generated by its output. The operating voltage Vop generated by the voltage generator 120 may be applied to the drain selection line DSL, the word line WL, the source selection line SSL, and the source line SL of the memory block selected by the row decoder 130.

[0037] The programming voltage may be a voltage applied to a selected word line among word lines WL during a programming operation, and may be used to increase the threshold voltage of a memory cell connected to the selected word line. A turn-on voltage may be applied to a drain select line DSL or a source select line SSL, and may be used to turn on a drain select transistor or a source select transistor. A cut-off voltage may be applied to a drain select line DSL or a source select line SSL, and may be used to turn off a drain select transistor or a source select transistor. For example, the cut-off voltage may be set to 0V. A precharge voltage may be a voltage higher than 0V, and may be applied to a bit line during a read operation. A verification voltage may be used during a verification operation to determine whether the threshold voltage of a selected memory cell has increased to a target level. The verification voltage may be set to various levels according to the target level, and may be applied to a selected word line.

[0038] The read voltage may be applied to the selected word line during a read operation performed on the selected memory cell. For example, the read voltage may be set to various levels according to a programming scheme for the selected memory cell. The pass voltage may be a voltage applied to an unselected word line among the word lines WL during a programming operation or a read operation, and may be used to turn on the memory cell connected to the unselected word line.

[0039] The erase voltage may be used during an erase operation of erasing memory cells included in a selected memory block, and may be applied to the source line SL.

[0040] The auxiliary voltage may be a positive voltage applied to a transmission word line or a plurality of transmission word lines connected to the corresponding memory block during an erase operation. The auxiliary voltage may be output simultaneously with the erase voltage. The pumping speed of the auxiliary voltage may be the same as the pumping speed of the erase voltage, but may vary depending on the temperature of the memory device. The pumping speed represents the amount of change in the potential of a node applied with 0V or an initial voltage that increases within a specific time period. The voltage generator 120 may change the slope of the increase of the auxiliary voltage in response to the operation code OPCD.

[0041] The compensation voltage may be a positive voltage applied to the word line during an erase operation. For example, the compensation voltage may be a voltage applied to the word line before the word line is discharged and may be a positive voltage higher than a voltage applied to the word line when performing an erase operation.

[0042] The row decoder 130 may send an operation voltage Vop to a drain select line DSL, a word line WL, a source select line SSL, and a source line SL coupled to a memory block selected according to a row address RADD. For example, the row decoder 130 may be coupled to the voltage generator 120 through a global line GL, and may be coupled to the first memory block BLK1 to the j-th memory block BLKj through the drain select line DSL, the word line WL, the source select line SSL, and the source line SL.

[0043] The page buffer group 140 may include page buffers (not shown) respectively connected to the first to j-th memory blocks BLK1 to BLKj. The page buffers (not shown) may be respectively connected to the first to j-th memory blocks BLK1 to BLKj through the bit lines BL. During a read operation, the page buffers (not shown) may sense a current or voltage of a bit line that varies with a threshold voltage of a selected memory cell in response to a page buffer control signal PBSIG, and may temporarily store the sensed data.

[0044] The column decoder 150 may be configured so that data is transmitted between the page buffer group 140 and the input / output circuit 160 in response to the column address CADD. For example, the column decoder 150 may be coupled to the page buffer group 140 through the column line CL, and may send an enable signal through the column line CL. A page buffer (not shown) included in the page buffer group 140 may receive or output data through the data line DL in response to the enable signal.

[0045] The input / output circuit 160 may receive or output a command CMD, an address ADD, or data through an input / output line I / O. For example, the input / output circuit 160 may send a command CMD and an address ADD received from an external controller through the input / output line I / O to the control circuit 170, and may send data received from the external controller through the input / output line I / O to the page buffer group 140. Alternatively, the input / output circuit 160 may output data received from the page buffer group 140 to the external controller through the input / output line I / O.

[0046] The control circuit 170 may output an operation code OPCD, a row address RADD, a page buffer control signal PBSIG, and a column address CADD in response to a command CMD and an address ADD. For example, when the command CMD input to the control circuit 170 is a command corresponding to a programming operation, the control circuit 170 may control a device included in the peripheral circuit 180 so that a programming operation is performed on a storage block selected by the address ADD. When the command CMD input to the control circuit 170 is a command corresponding to a read operation, the control circuit 170 may control a device included in the peripheral circuit 180 so that a read operation is performed on a storage block selected by the address and read data is output. When the command CMD input to the control circuit 170 is a command corresponding to an erase operation, the control circuit 170 may control a device included in the peripheral circuit 180 so that an erase operation is performed on a selected storage block. The control circuit 170 may include a sensor 170a configured to sense the temperature of the memory device 100. The sensor 170a may sense the temperature of the memory cell array 110 or the peripheral circuit 180, and may store the sensed value.

[0047] Figure 2A and Figure 2B is a diagram illustrating a memory cell array.

[0048] Reference Figure 2A , the memory cell array 110 may be disposed on the peripheral circuit 180. The memory cell array 110 may include first to j-th memory blocks BLK1 to BLKj. For example, assuming that the peripheral circuit 180 is horizontally formed on a substrate having an XY plane, the memory cell array 110 may be disposed on the peripheral circuit 180 along a Z direction perpendicular to the XY plane. The first to j-th memory blocks BLK1 to BLKj may be arranged to be spaced apart from each other along the Y direction.

[0049] The first storage block BLK1 to the jth storage block BLKj may be arranged between the bit line BL and the source line SL. When the bit line BL is arranged on the first storage block BLK1 to the jth storage block BLKj, the source line SL may be arranged below the first storage block BLK1 to the jth storage block BLKj. For example, the source line SL may be arranged between the peripheral circuit 180 and the first storage block BLK1 to the jth storage block BLKj. The drain selection line DSL, the source selection line SSL, the word line WL, and the transmission word line PWL may be connected to the first storage block BLK1 to the jth storage block BLKj. The drain selection line DSL may be arranged in a region close to the source line SL, the source selection line SSL may be arranged in a region close to the bit line BL, and the word line WL and the transmission word line PWL may be arranged between the drain selection line DSL and the source selection line SSL. The transmission word line PWL may be arranged between the word lines WL.

[0050] Reference Figure 2B , the memory cell array 110 may be disposed on the peripheral circuit 180. The memory cell array 110 may include first to j-th memory blocks BLK1 to BLKj. For example, assuming that the peripheral circuit 180 is horizontally formed on a substrate having an XY plane, the memory cell array 110 may be disposed on the peripheral circuit 180 along a Z direction perpendicular to the XY plane. The first to j-th memory blocks BLK1 to BLKj may be arranged to be spaced apart from each other along the Y direction.

[0051] The first storage block BLK1 to the jth storage block BLKj may be arranged between the bit line BL and the source line SL. When the source line SL is arranged on the first storage block BLK1 to the jth storage block BLKj, the bit line BL may be arranged below the first storage block BLK1 to the jth storage block BLKj. For example, the bit line BL may be arranged between the peripheral circuit 180 and the first storage block BLK1 to the jth storage block BLKj. The drain selection line DSL, the source selection line SSL, the word line WL, and the transmission word line PWL may be connected to the first storage block BLK1 to the jth storage block BLKj. The drain selection line DSL may be arranged in a region close to the bit line BL, the source selection line SSL may be arranged in a region close to the source line SL, and the word line WL and the transmission word line PWL may be arranged between the drain selection line DSL and the source selection line SSL. The transmission word line PWL may be arranged between the word lines WL.

[0052] Figure 3 is a diagram illustrating a storage block.

[0053] Reference Figure 3 , which is illustrated by way of example Figure 2A The first memory block BLK1 shown in FIG. The second to j-th memory blocks BLK2 to BLKj as the remaining memory blocks may be configured similarly to the first memory block BLK1.

[0054] The first memory block BLK1 may include a first sub-block 1S_BLK and a second sub-block 2S_BLK disposed between a source line SL and the first to i-th bit lines BL1 to BLi, and may include a transmission unit PC disposed between the first and second sub-blocks 1S_BLK and 2S_BLK. In the first and second sub-blocks 1S_BLK and 2S_BLK, the first sub-block 1S_BLK may be positioned closer to the source line SL, and the second sub-block 2S_BLK may be positioned closer to the first to i-th bit lines BL1 to BLi.

[0055] The first sub-block 1S_BLK may include a source selection transistor SST and first to eighth memory cells MC1 to MC8. The second sub-block 2S_BLK may include ninth to sixteenth memory cells MC9 to MC16 and a drain selection transistor DST. The transmission unit PC may be connected between the eighth memory cell MC8 of the first sub-block 1S_BLK and the ninth memory cell MC9 of the second sub-block 2S_BLK. The source selection transistor SST, the first to sixteenth memory cells MC16, the transmission unit PC, and the drain selection transistor DST connected between a bit line and a source line may form a cell string ST. For example, the cell string ST may be connected to the first to i-th bit lines BL1 to BLi, respectively. Because Figure 31 is a diagram illustrating an embodiment of the first storage block BLK1, so the number of source selection transistors SST, first memory cells MC1 to sixteenth memory cells MC16, and drain selection transistors DST included in the cell string ST may vary depending on the memory device. The gates of the source selection transistors SST included in different cell strings ST may be connected to the source selection line SSL, the gates of the first memory cells MC1 to sixteenth memory cells MC16 may be connected to the first word lines WL1 to sixteenth word lines WL16, the gates of the transmission cells PC may be connected to the transmission word lines PWL, and the gates of the drain selection transistors DST may be connected to the drain selection lines DSL. A group of memory cells connected to the same word line may be a page (PG). A programming operation or a read operation may be performed based on a page (PG). Because the number of source selection transistors SST, first memory cells MC1 to sixteenth memory cells MC16, transmission cells PC and drain selection transistors DST included in the cell string ST can vary depending on the memory device, the number of source selection lines SSL, first word lines WL1 to sixteenth word lines WL16, transmission word lines PWL and drain selection lines DSL can also vary depending on the memory device.

[0056] Figures 4A to 4G The diagrams illustrate various structures of storage blocks.

[0057] Reference Figure 4A The memory block may include a source selection line SSL, a first word line group 1WLG, a pass word line PWL, a second word line group 2WLG, a drain selection line DSL, a cell plug CP, a bit line contact BLc, and a bit line BL stacked on a source line SL and spaced apart from each other.

[0058] Each of the source line SL, the bit line contact BLc, and the bit line BL may be formed of a conductive material such as polysilicon, tungsten, or nickel. Each of the source selection line SSL, the first word line group 1WLG, the transfer word line PWL, the second word line group 2WLG, and the drain selection line DSL may be formed of a conductive material such as tungsten (W), molybdenum (Mo), cobalt (Co), or nickel (Ni), or a semiconductor material such as silicon (Si) or polysilicon (Poly-Si). Since the conductive material or the semiconductor material is an example for explaining the memory block according to the present disclosure, various materials having conductivity may be used in addition to the above-mentioned materials.

[0059] The cell plug CP may contact the source line SL after penetrating the source selection line SSL, the first word line group 1WLG, the transfer word line PWL, the second word line group 2WLG, and the drain selection line DSL. The cell plug CP may include a core column CR, a channel layer CH, a tunnel isolation layer TX, a charge trapping layer CTL, and a barrier layer BX. Each of the core column CR, the channel layer CH, the tunnel isolation layer TX, the charge trapping layer CTL, and the barrier layer BX may be used as a source selection transistor, a memory cell, or a drain selection transistor depending on its position. The core column CR may have a column shape and may be formed of an insulating material or a conductive material. The channel layer CH may surround the side surface of the core column CR and may be formed of polysilicon. The tunnel isolation layer TX may surround the side surface of the channel layer CH and may be formed of an oxide layer. The charge trapping layer CTL may surround the side surface of the tunnel isolation layer TX and may be formed of a nitride layer. The barrier layer BX may surround the side surface of the charge trapping layer CTL and may be formed of an oxide layer. A capping layer CA for improving current flow may also be formed on the stem CR in the drain selection transistor DST. When the capping layer CA is disposed on the stem CR, the position of the upper surface of the stem CR may be lower than the position of the upper surface of the channel layer CH. Therefore, the side surface of the capping layer CA may be surrounded by the channel layer CH. The capping layer CAP may be formed of a conductive material.

[0060] The bit line contact BLc may be disposed on the cell plug CP, and the bit line BL may be disposed on the bit line contact BLc. Each of the bit line contact BLc and the bit line BL may be formed of a conductive material. Therefore, the bit line BL, the bit line contact BLc, and the cell plug CP may be electrically connected to each other.

[0061] Due to the characteristics of the manufacturing process of the memory block, the width of the cell plug CP may be narrowed from top to bottom. This phenomenon may occur in the etching process and may further increase with the increase of the aspect ratio. When the cell plug CP is formed in a stacked manner, a bend may be formed in the connection area CNR where the cell plugs contact each other. For example, in order to increase the number of memory cells, a lower cell plug is formed, and then an upper cell plug may be formed on the lower cell plug. The upper width of the lower cell plug may be greater than the lower width of the upper cell plug, and the upper width of the upper cell plug may also be greater than the lower width of the upper cell plug. Therefore, the lower width of the upper cell plug may be less than the upper width of the lower cell plug, whereby the width difference in the cell plug CP is the largest in the connection area CNR where the lower cell plug and the upper cell plug contact each other. For example, where the lower cell plug and the upper cell plug contact each other, the cell plug suddenly changes its width.

[0062] Because the layers BX, CTL, TX, CH, CR, and CA forming the memory cell extend in the Z direction of the cell plug CP, a difference between the electrical characteristics of the memory cell may occur in the connection region CNR where a large size difference occurs. In this way, since the memory cell disposed in the connection region CNR where the difference between the electrical characteristics occurs may have low reliability, the cell disposed in the connection region CNR may be used as a transmission cell. The transmission cell does not store data and may be used as a switching transistor that electrically connects or disconnects the lower and upper portions of the cell plug to each other. The gate line connected to the transmission cell may be a transmission word line PWL.

[0063] The memory block may be divided into a first sub-block 1S_BLK and a second sub-block 2S_BLK with respect to a transmission word line PWL. The first sub-block 1S_BLK may be disposed between the transmission word line PWL and the source line SL, and the second sub-block 2S_BLK may be disposed between the transmission word line PWL and the bit line BL. Among the word lines, the word lines of the first sub-block 1S_BLK may be included in the first word line group 1WLG, and the word lines of the second sub-block 2S_BLK may be included in the second word line group 2WLG. Therefore, the first sub-block 1S_BLK may include a source selection line SSL and a first word line group 1WLG, and the second sub-block 2S_BLK may include a drain selection line DSL and a second word line group 2WLG.

[0064] The connection region CNR may be designated as various regions depending on the memory device, and the number and positions of the transmission word lines disposed in the connection region CNR may also be varied in various ways depending on the memory device.

[0065] FIG. 4B to FIG. 4G Implementations of various memory blocks each including a pass word line PWL are illustrated. FIG. 4B to FIG. 4G The components except the transmission word line PWL are Figure 4A The components shown are similar, so repeated descriptions thereof will be omitted.

[0066] Reference Figure 4B, the gate line in the connection region CNR and the gate line adjacent to the connection region CNR may be designated as a transmission word line. For example, among the word lines included in the first sub-block 1S_BLK, the gate line adjacent to the connection region CNR may be designated as a first transmission word line 1PWL. The gate line set in the connection region CNR may be designated as a second transmission word line 2PWL, and the gate line adjacent to the connection region CNR among the word lines included in the second sub-block 2S_BLK may be designated as a third transmission word line 3PWL. The same voltage or different voltages may be applied to the first transmission word line 1PWL to the third transmission word line 3PWL at the same time. Alternatively, the same voltage or different voltages may be applied to the first transmission word line 1PWL to the third transmission word line 3PWL at different times.

[0067] Reference Figure 4C , no gate line may be formed in the connection region CNR, and a gate line located in an uppermost portion among the gate lines included in the first sub-block 1S_BLK may be designated as a transfer word line PWL.

[0068] Reference Figure 4D , no gate line may be formed in the connection region CNR, and two gate lines adjacent to the connection region CNR among the gate lines included in the first sub-block 1S_BLK may be designated as the first transmission word line 1PWL and the second transmission word line 2PWL. For example, the second transmission word line 2PWL may be a gate line adjacent to the first word line group 1WLG, and the first transmission word line 1PWL may be disposed on the second transmission word line 2PWL. Alternatively, at least three gate lines adjacent to the connection region CNR among the gate lines included in the first sub-block 1S_BLK may also be designated as transmission word lines.

[0069] Reference Figure 4E , no gate line may be formed in the connection region CNR, and a gate line located in a lowermost portion among the gate lines included in the second sub-block 2S_BLK may be designated as a transfer word line PWL.

[0070] Reference Figure 4F , no gate line may be formed in the connection region CNR, and two gate lines adjacent to the connection region CNR among the gate lines included in the second sub-block 2S_BLK may be designated as the first transmission word line 1PWL and the second transmission word line 2PWL. For example, the first transmission word line 1PWL may be a gate line located in the lowermost portion among the gate lines included in the second sub-block 2S_BLK, and the second transmission word line 2PWL may be disposed on the first transmission word line 1PWL. Alternatively, at least three gate lines adjacent to the connection region CNR among the gate lines included in the second sub-block 2S_BLK may also be designated as transmission word lines.

[0071] Reference Figure 4G , no gate line may be formed in the connection region CNR, and some gate lines respectively adjacent to the connection region CNR among the gate lines included in the first sub-block 1S_BLK and the second sub-block 2S_BLK may be designated as transmission word lines. For example, a gate line located in an uppermost portion among the gate lines included in the first sub-block 1S_BLK may be designated as a first transmission word line 1PWL, and a gate line located in a lowermost portion among the gate lines included in the second sub-block 2S_BLK may be designated as a second transmission word line 2PWL.

[0072] Figure 5 is a diagram illustrating gate induced drain leakage (GIDL).

[0073] Reference Figure 5 , gate induced drain leakage (GIDL) may be leakage that occurs due to the difference between the drain voltage and the gate voltage. When describing a transistor TR composed of a substrate 51, a gate 52, and an insulating layer 53 as an example, a drain voltage Vd may be applied to a drain 54 of the substrate 51, and a cut-off voltage Voff lower than the drain voltage Vd may be applied to the gate 52. For example, the drain voltage Vd may be a positive voltage higher than 0V, and the cut-off voltage Voff may be a voltage lower than the drain voltage Vd. For example, the cut-off voltage Voff may be 0V.

[0074] When the voltage difference between the drain voltage Vd and the cut-off voltage Voff increases to exceed a specific value, the energy band of the drain 54 can be changed. Due to this, electrons (-) can move from the substrate 51 toward the gate 52, and holes (+) can move from the region adjacent to the gate 52 toward the substrate 51. That is, relative to the transistor TR, the hole (+) can move in the opposite direction to the region to which the drain voltage Vd is applied. When GIDL occurs, the voltage of the substrate 51 can increase more slowly than when the transistor TR is turned on. The reason is that the movement speed of the hole (+) generated by GIDL is lower than the transmission speed of the voltage in the substrate 51.

[0075] The holes (+) generated by GIDL have a low moving speed but may be generated in a uniform amount and may move at a constant speed, thus helping the memory device to improve the reliability of its erase operation.

[0076] Figure 6 is a diagram illustrating a principle of an erase operation according to an embodiment of the present disclosure.

[0077] Reference Figure 6, the erase voltage Vers may be applied to the cell plug CP through the lower region or the upper region of the cell plug CP. GIDL may occur in the region 61 to which the erase voltage Vers is applied. The erase voltage Vers may be applied through the source line or the bit line, and Figure 6 An embodiment of applying the erase voltage Vers through the source line is illustrated. When the erase voltage Vers is applied to the source line, a positive voltage, 0V, or a negative voltage may be applied to the bit line. Alternatively, the bit line may be floated. The voltage applied to the bit line may vary in various ways depending on the erase method of the memory device.

[0078] Since a source line or a bit line is coupled through a lower end or an upper end of the cell plug CP, GIDL may occur in a region adjacent to an end of the cell plug CP.

[0079] In the first structure 1STK where GIDL occurs only at the end 61 of the cell plug CP, it is assumed that the time required for the hole (+) to move to the opposite end of the cell plug CP is the first time. Unlike the first structure 1STK, in the second structure 2STK where GIDL occurs at both the end 61 and the midpoint 62 of the cell plug CP, the second time required for the hole (+) to move to the opposite end of the cell plug CP can be shorter than the first time. That is, as in the case of the second structure 2STK, when GIDL occurs at the end 61 and the midpoint 62 of the cell plug CP, the hole (+) generated at the midpoint 62 can reach the portion of the cell plug CP to which the erase voltage Vers is not applied, and thus the time required for the hole (+) to reach the entire cell plug CP can be shortened.

[0080] The erase operation described in this embodiment is based on the second structure 2STK.

[0081] Figure 7 is a timing chart illustrating an erase operation according to the first embodiment of the present disclosure.

[0082] Reference Figure 7 The described source lines SL, bit lines BL, drain selection lines DSL, source selection lines SSL, word lines WL, transfer word lines PWL, first sub-blocks 1S_BLK and second sub-blocks 2S_BLK may correspond to FIG. 4A to FIG. 4G The erase operation according to the embodiment of the present disclosure may be performed by a peripheral circuit (e.g., Figure 1 The peripheral circuit can be implemented in the control circuit (for example, Figure 1 170) under the control of operation.

[0083] Reference Figure 7, at the first time T1, an erase voltage Vers may be applied to the source line SL or the bit line BL, and an auxiliary voltage Vat may be applied to the transmission word line PWL. The erase voltage Vers may be a positive voltage higher than 0V, and the auxiliary voltage Vat may be a voltage equal to the erase voltage Vers. At the first time T1, a cut-off voltage Voff may be applied to the drain selection line DSL and the source selection line SSL, and the word lines WL of the first sub-block 1S_BLK and the second sub-block 2S_BLK may float (FLT). The cut-off voltage Voff may be 0V. Therefore, the drain selection transistor and the source selection transistor may be cut off. When the word line WL floats in a state where the drain selection transistor and the source selection transistor are cut off, coupling or boosting may occur in the word line WL due to the voltage applied to the adjacent line of the word line WL, and as a result, the voltage of the word line WL may increase. Even if the voltage of the word line WL increases, since the voltage is increased by coupling or boosting, the voltage does not become high enough to affect the electrons captured in the memory cell.

[0084] During the period from the first time T1 to the second time T2, the levels of the erase voltage Vers applied to the source line SL or the bit line BL and the auxiliary voltage Vat applied to the transfer word line PWL increase, whereby GIDL may occur in the drain selection transistor or the source selection transistor that is turned off. For example, when the erase voltage Vers is applied to the source line SL, GIDL may occur in the source selection transistor. When the erase voltage Vers is applied to the bit line BL instead of the source line SL, GIDL may occur in the drain selection transistor.

[0085] Because the auxiliary voltage Vat is equal to the erase voltage Vers, the slope (DG) at which the erase voltage Vers increases may be the same as the slope (GD) at which the auxiliary voltage Vat increases.

[0086] When the second time T2 when the erase voltage Vers increases to the target level Lt is reached, the turn-on voltage Von may be applied to the drain selection line DSL and the source selection line SSL. The turn-on voltage Von may be set to a positive voltage that enables the drain selection transistor or the source selection transistor to be turned on.

[0087] Even if the turn-on voltage Von is applied at the second time T2, the pumping operation for the auxiliary voltage Vat applied to the transmission word line PWL may continue to be performed. For example, although the auxiliary voltage Vat is also increased to the same target level Lt as the erase voltage Vers at the second time T2, the auxiliary voltage Vat may be further increased during the period from the second time T2 to the third time T3 to maintain the GIDL for a longer duration in the middle portion of the cell plug. That is, the main erase operation of erasing the memory cell starts from the second time T2 when the erase voltage Vers reaches the target level Lt, but even during the period from the first time T1 to the second time T2 as the GIDL occurrence period, a weak erase operation may be performed on the memory cell due to holes. The weak erase operation refers to an operation in which the memory cell is erased more slowly than the main erase operation.

[0088] When the third time T3 is reached, the voltage generator (eg, Figure 1 120) can reduce the voltage of the transmission word line PWL, and can make the transmission word line PWL float (FLT).

[0089] When a fourth time T4 to terminate the erase operation is reached, the potentials of the source line SL, the bit line BL, the drain select line DSL, the source select line SSL, the word line WL, and the pass word line PWL may be discharged to 0V.

[0090] Figure 8 is a timing chart illustrating an erase operation according to the second embodiment of the present disclosure.

[0091] Reference Figure 8 The described source lines SL, bit lines BL, drain selection lines DSL, source selection lines SSL, word lines WL, transfer word lines PWL, first sub-blocks 1S_BLK and second sub-blocks 2S_BLK may correspond to FIG. 4A to FIG. 4G Any line or block shown in FIG.

[0092] Reference Figure 8 , the operation performed during the period from the first time T1 to the third time T3 in the erasing operation according to the second embodiment can be performed in the same manner as the operation performed during the period from the first time T1 to the third time T3 in the erasing operation according to the first embodiment, and thus a repeated description thereof will be omitted.

[0093] In the second embodiment, before the fourth time T4 when the word line WL is discharged, an equalization operation may be further performed. The equalization operation is an operation to prevent the voltage of the word line WL from being excessively reduced when the word line WL is discharged. The equalization operation may be performed at the 3'th time T3' between the third time T3 and the fourth time T4. For example, during the period from the 3'th time T3' to the fourth time T4, a compensation voltage Vco may be applied to the word line WL. The compensation voltage Vco may be set to a positive voltage whose level is lower than or equal to that of the on-voltage Von.

[0094] When the fourth time T4 is reached, the potentials of the source line SL, the bit line BL, the drain select line DSL, the source select line SSL, the word line WL, and the pass word line PWL may be discharged to 0V.

[0095] Fig. 9 is a flowchart illustrating an erase operation according to the third embodiment of the present disclosure.

[0096] Reference Fig. 9 The described source lines SL, bit lines BL, drain selection lines DSL, source selection lines SSL, word lines WL, transfer word lines PWL, first sub-blocks 1S_BLK and second sub-blocks 2S_BLK may correspond to FIG. 4A to FIG. 4G Any line or block shown in FIG.

[0097] Reference Fig. 9 In the erase operation according to the third embodiment, the slope of the auxiliary voltage may be adjusted according to the temperature of the memory device. The erase operation according to the third embodiment may be performed as follows.

[0098] When an erase command is input to the memory device, a channel initialization operation S91 may be performed on the selected memory block. The channel initialization operation S91 may be an operation of uniformly reducing the channel voltage of the selected memory block. For example, the channel initialization operation may be an operation of reducing the channel layer (e.g., Figure 4A For example, during the channel initialization operation S91, the channel layer CH may be discharged.

[0099] When the channel initialization operation S91 is completed, a temperature sensing operation S92 may be performed. The temperature sensing operation S92 may be performed using a temperature sensor of the memory device. The temperature sensor of the memory device may sense the temperature of a memory cell array or a peripheral circuit.

[0100] When the temperature sensed at step S92 is equal to the reference temperature (ie, the temperature is maintained), the memory device may maintain the slope of the auxiliary voltage set by default at step S93.

[0101] When the temperature sensed at step S92 is higher than the reference temperature (ie, the temperature increases), the memory device may increase the slope of the auxiliary voltage set by default at step S94.

[0102] When the temperature sensed at step S92 is lower than the reference temperature (ie, the temperature drops), the memory device may reduce the slope of the auxiliary voltage set by default at step S95.

[0103] When any one of steps S93, S94 and S95 is completed, an erase operation may be performed on the selected storage block in step S96. Fig.10 Describe the erase operation in detail.

[0104] Fig.10 is a timing chart illustrating an erase operation according to the third embodiment of the present disclosure.

[0105] Reference Fig.10 The described source lines SL, bit lines BL, drain selection lines DSL, source selection lines SSL, word lines WL, transfer word lines PWL, first sub-blocks 1S_BLK and second sub-blocks 2S_BLK may correspond to FIG. 4A to FIG. 4G Any line or block shown in FIG.

[0106] Reference Fig.10 At the first time T1, the erase voltage Vers may be applied to the source line SL or the bit line BL, and an auxiliary voltage selected from the first auxiliary voltage 1Vat to the third auxiliary voltage 3Vat may be applied to the pass word line PWL. The erase voltage Vers may be a positive voltage higher than 0V.

[0107] The first auxiliary voltage 1Vat may be an auxiliary voltage set by default, and may be a voltage equal to the erase voltage Vers. The second auxiliary voltage 2Vat may be a voltage higher than the erase voltage Vers, and the third auxiliary voltage 3Vat may be a positive voltage lower than the erase voltage Vers. The target levels of the first auxiliary voltage 1Vat to the third auxiliary voltage 3Vat may be different from each other, and their slopes DG may also be different from each other. For example, assuming that the slope DG of the first auxiliary voltage 1Vat is the default slope, the second auxiliary voltage 2Vat may have a slope greater than the default slope, and the third auxiliary voltage 3Vat may have a slope less than the default slope.

[0108] At the first time T1, the cut-off voltage Voff may be applied to the drain selection line DSL and the source selection line SSL, and the word line WL of the first sub-block 1S_BLK and the second sub-block 2S_BLK may float (FLT). The cut-off voltage Voff may be 0V. Therefore, the drain selection transistor and the source selection transistor may be cut off. When the word line WL floats in a state where the drain selection transistor and the source selection transistor are cut off, coupling or boosting may occur in the word line WL due to the voltage applied to the adjacent line of the word line WL, and as a result, the voltage of the word line WL may increase. Even if the voltage of the word line WL increases, since the voltage is increased by coupling or boosting, the voltage does not become high enough to affect the electrons captured in the memory cell.

[0109] During the period from the first time T1 to the second time T2, the level of the erase voltage Vers applied to the source line SL or the bit line BL and the auxiliary voltage selected from the first auxiliary voltage 1Vat to the third auxiliary voltage 3Vat applied to the transmission word line PWL increases, so GIDL may occur in the drain selection transistor or the source selection transistor that is turned off. For example, when the erase voltage Vers is applied to the source line SL, GIDL may occur in the source selection transistor. When the erase voltage Vers is applied to the bit line BL instead of the source line SL, GIDL may occur in the drain selection transistor.

[0110] When the second time T2 when the erase voltage Vers increases to the target level Lt is reached, the turn-on voltage Von may be applied to the drain selection line DSL and the source selection line SSL. The turn-on voltage Von may be set to a positive voltage that enables the drain selection transistor or the source selection transistor to be turned on.

[0111] Even if the turn-on voltage Von is applied at the second time T2, the pumping operation for the auxiliary voltage selected from the first auxiliary voltage 1Vat to the third auxiliary voltage 3Vat applied to the transmission word line PWL may continue to be performed. For example, although the selected auxiliary voltage increases at the second time T2, the selected auxiliary voltage may be further increased during the period from the second time T2 to the third time T3 to maintain the GIDL for a longer duration in the middle portion of the cell plug. That is, the main erase operation of erasing the memory cell starts from the second time T2 when the erase voltage Vers reaches the target level Lt, but even during the period from the first time T1 to the second time T2 as the GIDL occurrence period, a weak erase operation may be performed on the memory cell due to holes. The weak erase operation refers to an operation in which the memory cell is erased more slowly than the main erase operation.

[0112] When the third time T3 is reached, the voltage generator (eg, Figure 1120) can reduce the voltage of the transmission word line PWL, and can make the transmission word line PWL float (FLT).

[0113] When a fourth time T4 to terminate the erase operation is reached, the potentials of the source line SL, the bit line BL, the drain select line DSL, the source select line SSL, the word line WL, and the pass word line PWL may be discharged to 0V.

[0114] Even in the third embodiment, the equalization operation may be performed at the 3 ′ time T3 ′ before the fourth time T4 at which the word line WL is discharged.

[0115] Fig.11 is a diagram illustrating a structure of a unit plug according to an embodiment of the present disclosure.

[0116] Reference Fig.11 , a storage block may include at least three sub-blocks. Fig.11 , a memory block including first to third sub-blocks 1S_BLK to 3S_BLK is illustrated by way of example.

[0117] The third sub-block 3S_BLK may be disposed on the second sub-block 2S_BLK. The first connection region 1CNR may be disposed between the first sub-block 1S_BLK and the second sub-block 2S_BLK, and the second connection region 2CNR may be disposed between the second sub-block 2S_BLK and the third sub-block 3S_BLK.

[0118] A gate line adjacent to the first connection region 1CNR among the gate lines included in the first sub-block 1S_BLK may be designated as a first transmission word line 1PWL. A gate line adjacent to the first connection region 1CNR among the gate lines included in the second sub-block 2S_BLK may be designated as a second transmission word line 2PWL. A gate line adjacent to the second connection region 2CNR among the gate lines included in the second sub-block 2S_BLK may be designated as a third transmission word line 3PWL. A gate line adjacent to the second connection region 2CNR among the gate lines included in the third sub-block 3S_BLK may be designated as a fourth transmission word line 4PWL. The number of the first to fourth transmission word lines 1PWL to 4PWL is not limited to Fig.11 Quantity shown.

[0119] The first sub-block 1S_BLK may include a source selection line SSL, a first word line group 1WLG, and a first transmission word line 1PWL. The second sub-block 2S_BLK may include a second word line group 2WLG, a second transmission word line 2PWL, and a third transmission word line 3PWL. The third sub-block 3S_BLK may include a fourth transmission word line 4PWL, a third word line group 3WLG, and a drain selection line DSL.

[0120] Fig.12 is a diagram illustrating the principle of an erase operation according to a fourth embodiment of the present disclosure.

[0121] Reference Fig.11 and Fig.12 , when the erase voltage Vers is applied to the source line SL, GIDL may occur in a region 121 adjacent to the source line SL among the regions of the cell plug CP, and GIDL may occur in each of the first connection region 1CNR and the second connection region 2CNR. In the first connection region 1CNR, GIDL may occur due to the auxiliary voltage applied to the first and second transfer word lines 1PWL and 2PWL. In the second connection region 2CNR, GIDL may occur due to the auxiliary voltage applied to the third and fourth transfer word lines 3PWL and 4PWL.

[0122] When GIDL occurs in both the end 121 of the cell plug CP and the first and second connection regions 1CNR and 2CNR, time required for holes (+) to move to opposite ends of the cell plug CP may be shortened. The erase operation according to the fourth embodiment may be performed as follows.

[0123] Fig.13 is a timing chart illustrating an erase operation according to the fourth embodiment of the present disclosure.

[0124] Reference Fig.13 , at the first time T1, the erase voltage Vers may be applied to the source line SL, and the auxiliary voltage Vat may be applied to the first to fourth transfer word lines 1PWL to 4PWL. The erase voltage Vers may be a positive voltage higher than 0V. The auxiliary voltage Vat may be equal to the erase voltage Vers. A positive voltage or a ground voltage may be applied to the bit line BL.

[0125] At the first time T1, a cut-off voltage Voff may be applied to the drain selection line DSL and the source selection line SSL, and the word lines WL of the first sub-block 1S_BLK to the third sub-block 3S_BLK may float (FLT). The cut-off voltage Voff may be 0V. Therefore, the drain selection transistor and the source selection transistor may be cut off. When the word line WL floats in a state where the drain selection transistor and the source selection transistor are cut off, coupling or boosting may occur in the word line WL due to the voltage applied to the adjacent line of the word line WL, and as a result, the voltage of the word line WL may increase. Even if the voltage of the word line WL increases, since the voltage is increased by coupling or boosting, the voltage does not become high enough to affect the electrons captured in the memory cell.

[0126] During the period from the first time T1 to the second time T2, the levels of the erase voltage Vers applied to the source line SL and the auxiliary voltage Vat applied to the first to fourth transfer word lines 1PWL to 4PWL increase, so GIDL may occur in the drain selection transistor or the source selection transistor that is turned off. For example, when the erase voltage Vers is applied to the source line SL, GIDL may occur in the source selection transistor.

[0127] When the second time T2 when the erase voltage Vers increases to the target level Lt is reached, the turn-on voltage Von may be applied to the drain selection line DSL and the source selection line SSL. The turn-on voltage Von may be set to a positive voltage that enables the drain selection transistor or the source selection transistor to be turned on.

[0128] Even if the turn-on voltage Von is applied at the second time T2, the pumping operation for the auxiliary voltage Vat applied to the first to fourth transfer word lines 1PWL to 4PWL may continue to be performed. For example, at the second time T2, the auxiliary voltage Vat may be further increased during the period from the second time T2 to the third time T3 to maintain the GIDL in the middle portion of the cell plug for a longer duration. That is, the main erase operation of erasing the memory cell starts from the second time T2 when the erase voltage Vers reaches the target level Lt, but even during the period from the first time T1 to the second time T2 as the GIDL occurrence period, a weak erase operation may be performed on the memory cell due to holes. The weak erase operation refers to an operation in which the memory cell is erased more slowly than the main erase operation.

[0129] When the third time T3 is reached, the voltage generator (eg, Figure 1 120) may reduce the voltage of the first to fourth transfer word lines 1PWL to 4PWL, and may float (FLT) the first to fourth transfer word lines 1PWL to 4PWL.

[0130] When a fourth time T4 to terminate the erase operation is reached, the potentials of the source line SL, the bit line BL, the drain select line DSL, the source select line SSL, the word line WL, and the first to fourth transfer word lines 1PWL to 4PWL may be discharged to 0V.

[0131] Even in the fourth embodiment, the equalization operation may be performed at the 3' time T3' before the fourth time T4 at which the word line WL is discharged.

[0132] Fig.14 is a diagram illustrating the principle of an erase operation according to a fifth embodiment of the present disclosure.

[0133] Reference Fig.11 and Fig.14, additional GIDL may occur in a connection region relatively far from a portion to which the erase voltage Vers is applied, and additional GIDL may not occur in a connection region relatively close to the portion. For example, when the erase voltage Vers is applied to the source line SL, main GIDL may occur in a region 141 adjacent to the source line SL among the regions of the cell plug CP. Among the first connection region 1CNR and the second connection region 2CNR, the second connection region 2CNR relatively far from the region 141 where the main GIDL occurs may cause additional GIDL, while the first connection region 1CNR relatively close thereto may not cause additional GIDL.

[0134] The erase operation according to the fifth embodiment may be performed as follows.

[0135] Fig.15 is a timing chart illustrating an erase operation according to the fifth embodiment of the present disclosure.

[0136] Reference Fig.15 , at the first time T1, the erase voltage Vers may be applied to the source line SL, and the auxiliary voltage Vat may be applied to the third transfer word line 3PWL and the fourth transfer word line 4PWL. The erase voltage Vers may be a positive voltage higher than 0V. The auxiliary voltage Vat may be equal to the erase voltage Vers. A positive voltage or a ground voltage may be applied to the bit line BL.

[0137] At the first time T1, the cut-off voltage Voff may be applied to the drain selection line DSL and the source selection line SSL, and the word lines WL of the first sub-block 1S_BLK to the third sub-block 3S_BLK and the first transfer word line 1PWL and the second transfer word line 2PWL may float (FLT). The cut-off voltage Voff may be 0V. Therefore, the drain selection transistor and the source selection transistor may be turned off. When the word line WL and the first transfer word line 1PWL and the second transfer word line 2PWL float in a state where the drain selection transistor and the source selection transistor are turned off, coupling or boosting may occur in the first transfer word line 1PWL and the second transfer word line 2PWL and the word line WL due to the voltage applied to the adjacent lines of the first transfer word line 1PWL and the second transfer word line 2PWL and the word line WL, and as a result, the voltage of the first transfer word line 1PWL and the second transfer word line 2PWL and the word line WL may increase. Even if the voltage of the word line WL increases, since the voltage is increased by coupling or boosting, the voltage does not become high enough to affect the electrons trapped in the memory cell.

[0138] During the period from the first time T1 to the second time T2, the levels of the erase voltage Vers applied to the source line SL and the auxiliary voltage Vat applied to the third transfer word line 3PWL and the fourth transfer word line 4PWL increase, whereby a main GIDL may occur in the drain selection transistor or the source selection transistor that is turned off. For example, when the erase voltage Vers is applied to the source line SL, a main GIDL may occur in the source selection transistor.

[0139] When the second time T2 when the erase voltage Vers increases to the target level Lt is reached, the turn-on voltage Von may be applied to the drain selection line DSL and the source selection line SSL. The turn-on voltage Von may be set to a positive voltage that enables the drain selection transistor or the source selection transistor to be turned on.

[0140] Even if the turn-on voltage Von is applied at the second time T2, the pumping operation for the auxiliary voltage Vat applied to the third transfer word line 3PWL and the fourth transfer word line 4PWL may continue to be performed. For example, at the second time T2, the auxiliary voltage Vat may be further increased during the period from the second time T2 to the third time T3 to maintain the GIDL for a longer duration in a portion of the cell plug. That is, the main erase operation of erasing the memory cell starts from the second time T2 when the erase voltage Vers reaches the target level Lt, but even during the period from the first time T1 to the second time T2 as the GIDL occurrence period, a weak erase operation may be performed on the memory cell due to holes. The weak erase operation refers to an operation in which the memory cell is erased more slowly than the main erase operation.

[0141] When the third time T3 is reached, the voltage generator (eg, Figure 1 120) can reduce the voltage of the third transfer word line 3PWL and the fourth transfer word line 4PWL, and can make the third transfer word line 3PWL and the fourth transfer word line 4PWL float (FLT).

[0142] When a fourth time T4 to terminate the erase operation is reached, the potentials of the source line SL, the bit line BL, the drain select line DSL, the source select line SSL, the word line WL, and the first to fourth transfer word lines 1PWL to 4PWL may be discharged to 0V.

[0143] Even in the fifth embodiment, the equalization operation may be performed at the 3' time T3' before the fourth time T4 at which the word line WL is discharged.

[0144] Fig.16 is a diagram illustrating the principle of an erase operation according to a sixth embodiment of the present disclosure.

[0145] Reference Fig.11 and Fig.16, the erase voltage Vers may be applied to the bit line BL. In this case, the main GIDL may occur in the region 161 adjacent to the bit line BL among the regions of the cell plug CP. Of the first connection region 1CNR and the second connection region 2CNR, the first connection region 1CNR relatively far from the region 161 where the main GIDL occurs may cause the additional GIDL, and the second connection region 2CNR relatively close thereto may not cause the additional GIDL.

[0146] The erase operation according to the sixth embodiment may be performed as follows.

[0147] Fig.17 is a timing chart illustrating an erase operation according to a sixth embodiment of the present disclosure.

[0148] Reference Fig.17 , at the first time T1, the erase voltage Vers may be applied to the bit line BL, and the auxiliary voltage Vat may be applied to the first transfer word line 1PWL and the second transfer word line 2PWL. The erase voltage Vers may be a positive voltage higher than 0V. The auxiliary voltage Vat may be equal to the erase voltage Vers. A positive voltage or a ground voltage may be applied to the source line SL.

[0149] At the first time T1, the cut-off voltage Voff may be applied to the drain selection line DSL and the source selection line SSL, and the word lines WL of the first sub-block 1S_BLK to the third sub-block 3S_BLK and the third transmission word line 3PWL and the fourth transmission word line 4PWL may float (FLT). The cut-off voltage Voff may be 0V. Therefore, the drain selection transistor may be turned off and the source selection transistor may be turned off. When the word line WL and the third transmission word line 3PWL and the fourth transmission word line 4PWL float in a state where the drain selection transistor and the source selection transistor are turned off, coupling or boosting may occur in the word line WL and the third transmission word line 3PWL and the fourth transmission word line 4PWL due to the voltage applied to the adjacent lines of the word line WL and the third transmission word line 3PWL and the fourth transmission word line 4PWL, and as a result, the voltage of the word line WL and the third transmission word line 3PWL and the fourth transmission word line 4PWL may increase. Even if the voltage of the word line WL increases, since the voltage is increased by coupling or boosting, the voltage does not become high enough to affect the electrons trapped in the memory cell.

[0150] During the period from the first time T1 to the second time T2, the levels of the erase voltage Vers applied to the source line SL and the auxiliary voltage Vat applied to the first and second transfer word lines 1PWL and 2PWL increase, so a main GIDL may occur in the drain selection transistor or the source selection transistor that is turned off. For example, when the erase voltage Vers is applied to the bit line BL, a main GIDL may occur in the drain selection transistor.

[0151] When the second time T2 when the erase voltage Vers increases to the target level Lt is reached, the turn-on voltage Von may be applied to the drain selection line DSL and the source selection line SSL. The turn-on voltage Von may be set to a positive voltage that enables the drain selection transistor or the source selection transistor to be turned on.

[0152] Even if the turn-on voltage Von is applied at the second time T2, the pumping operation for the auxiliary voltage Vat applied to the first transfer word line 1PWL and the second transfer word line 2PWL may continue to be performed. For example, at the second time T2, the auxiliary voltage Vat may be further increased during the period from the second time T2 to the third time T3 to maintain the GIDL for a longer duration in a portion of the cell plug. That is, the main erase operation of erasing the memory cell starts from the second time T2 when the erase voltage Vers reaches the target level Lt, but even during the period from the first time T1 to the second time T2 as the GIDL occurrence period, a weak erase operation may be performed on the memory cell due to holes. The weak erase operation refers to an operation in which the memory cell is erased more slowly than the main erase operation.

[0153] When the third time T3 is reached, the voltage generator (eg, Figure 1 120) can reduce the voltage of the first transfer word line 1PWL and the second transfer word line 2PWL, and can float the first transfer word line 1PWL and the second transfer word line 2PWL (FLT).

[0154] When a fourth time T4 to terminate the erase operation is reached, potentials of the source line SL, the bit line BL, the drain select line DSL, the source select line SSL, the word line WL, and the first to fourth transfer word lines 1PWL to 4PWL may be discharged to 0V.

[0155] Even in the sixth embodiment, the equalization operation may be performed at the 3' time T3' before the fourth time T4 at which the word line WL is discharged.

[0156] Fig.18 is a diagram illustrating a memory card system to which a memory device according to the present disclosure is applied.

[0157] Reference Fig.18 , the memory card system 3000 includes a controller 3100 , a memory device 3200 , and a connector 3300 .

[0158] The controller 3100 is coupled to the memory device 3200. The controller 3100 may access the memory device 3200. For example, the controller 3100 may control a program operation, a read operation, or an erase operation of the memory device 3200 or control a background operation of the memory device 3200. The controller 3100 may provide an interface between the memory device 3200 and a host. The controller 3100 may run firmware for controlling the memory device 3200. In an embodiment, the controller 3100 may include components such as a RAM, a processor, a host interface, a memory interface, and an error correction circuit.

[0159] The controller 3100 can communicate with an external device through the connector 3300. The controller 3100 can communicate with an external device (e.g., a host) based on a specific communication standard. In an embodiment, the controller 3100 can communicate with an external device through at least one of various communication standards such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), a PCI-Express (PCI-E), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), Firewire, a universal flash memory (UFS), WiFi, Bluetooth (Bluetooth), and a fast non-volatile memory (NVMe). In an embodiment, the connector 3300 can be defined according to at least one of the various communication standards mentioned above.

[0160] The memory device 3200 may include a plurality of memory cells and may be configured in a manner similar to that of FIG. Figure 1 The memory device 100 shown is configured in the same manner.

[0161] The controller 3100 and the memory device 3200 may be integrated into a single semiconductor device to form a memory card. For example, the controller 3100 and the memory device 3200 may be integrated into a single semiconductor device, and then a memory card such as a PC card (Personal Computer Memory Card International Association: PCMCIA), a Compact Flash card (CF), a Smart Media Card (SM or SMC), a Memory Stick, a Multimedia Card (MMC, RS-MMC, Micro MMC or eMMC), an SD card (SD, Mini SD, Micro SD or SDHC), a Universal Flash Storage (UFS), etc. may be formed.

[0162] Fig.19 is a diagram illustrating a solid state drive (SSD) system to which a memory device according to the present disclosure is applied.

[0163] Reference Fig.19, the SSD system 4000 includes a host 4100 and an SSD 4200. The SSD 4200 may exchange signals with the host 4100 through a signal connector 4001, and may receive power through a power connector 4002. The SSD 4200 may include a controller 4210, a plurality of memory devices 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0164] The controller 4210 may control the plurality of memory devices 4221 to 422n in response to a signal received from the host 4100. In an embodiment, the signal may include a signal based on an interface of the host 4100 and the SSD 4200. For example, the signal may be a signal defined in accordance with at least one of interfaces such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI-Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, Universal Flash Storage (UFS), WiFi, Bluetooth (Bluetooh), and Non-Volatile Memory Express (NVMe).

[0165] Each of the plurality of memory devices 4221 to 422n may include a plurality of memory cells storing data. Figure 1 The illustrated memory device 100 is configured in the same manner. A plurality of memory devices 4221 to 422n may communicate with a controller 4210 through channels CH1 to CHn.

[0166] The auxiliary power supply 4230 may be coupled to the host 4100 through the power connector 4002. The auxiliary power supply 4230 may be supplied with a power supply voltage from the host 4100 and may be charged. When power supply from the host 4100 cannot be smoothly performed, the auxiliary power supply 4230 may provide a power supply voltage for the SSD 4200. In an embodiment, the auxiliary power supply 4230 may be located inside the SSD 4200 or outside the SSD 4200. For example, the auxiliary power supply 4230 may be located on a mainboard and may also provide auxiliary power to the SSD 4200.

[0167] The buffer memory 4240 is used as a buffer memory of the SSD 4200. For example, the buffer memory 4240 may temporarily store data received from the host 4100 or data received from the plurality of memory devices 4221 to 422n or may temporarily store metadata (e.g., a mapping table) of the memory devices 4221 to 422n. The buffer memory 4240 may include a volatile memory such as DRAM, SDRAM, DDR SDRAM, and LPDDR SDRAM, or a nonvolatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0168] In some implementations, the teachings of the present disclosure can shorten the time required for an erase operation of a memory device.

[0169] CROSS-REFERENCE TO RELATED APPLICATIONS

[0170] This application claims priority to Korean Patent Application No. 10-2023-0143057, filed on October 24, 2023, the entire contents of which are incorporated herein by reference.

Claims

1. A memory device, comprising: a memory block including a cell plug extending between a first line and a second line, wherein a first selection line, a first word line group, a first transfer word line, a second word line group, and a second selection line are arranged between the first line and the second line along the cell plug; and A peripheral circuit applies an erase voltage to the first line or the second line, applies an auxiliary voltage to the first transfer word line when applying the erase voltage, and lowers a potential of the first transfer word line when the erase voltage is maintained at a target level.

2. The memory device according to claim 1, wherein: The peripheral circuit further applies the auxiliary voltage to the first transmission word line for a time interval after the erase voltage applied to the first line or the second line has reached the target level.

3. The memory device according to claim 2, wherein: The auxiliary voltage increases during the time interval.

4. The memory device according to claim 1, wherein: The peripheral circuit comprises: A voltage generator generates the erase voltage and the auxiliary voltage.

5. The memory device according to claim 4, wherein: The voltage generator generates the auxiliary voltage equal to the erase voltage.

6. The memory device according to claim 1, wherein: Each of the erase voltage and the auxiliary voltage is a positive voltage higher than 0V.

7. The memory device according to claim 1, wherein: The peripheral circuit applies a cutoff voltage to the first selection line and the second selection line while the erase voltage and the auxiliary voltage are increasing.

8. The memory device according to claim 7, wherein: The peripheral circuit applies an on voltage higher than the off voltage to the first selection line and the second selection line when the erase voltage reaches the target level.

9. The memory device according to claim 1, wherein: The peripheral circuit floats word lines included in the first and second word line groups.

10. The memory device according to claim 1, wherein: The storage block also includes: A second transmission word line and a third word line group are provided between the second word line group and the second selection line.

11. The memory device according to claim 10, wherein: The peripheral circuit applies the auxiliary voltage to the first and second transfer word lines while applying the erase voltage to the first line.

12. The memory device according to claim 10, wherein: When the peripheral circuit applies the erase voltage to the second line, applying an auxiliary voltage to the first transmission word line, and The second transmission word line is floated.

13. The memory device according to claim 1, wherein: The first transfer word line is located within a word line of a connection region in which the cell plug abruptly changes a width of the cell plug.

14. The memory device according to claim 1, wherein: The unit plug comprises: a first selection transistor coupled to the first selection line; a first memory cell coupled to a word line included in the first word line group; a first transmission unit, the first transmission unit being coupled to the first transmission word line; a second memory cell coupled to a word line included in the second word line group; and A second selection transistor is coupled to the second selection line.

15. The memory device according to claim 1, wherein: The peripheral circuit also includes: A sensor senses a temperature of the memory device.

16. The memory device of claim 15, wherein: The peripheral circuit adjusts the level of the auxiliary voltage according to the temperature sensed by the sensor.

17. The memory device of claim 15, wherein: The peripheral circuit adjusts a level of the auxiliary voltage in proportion to the temperature sensed by the sensor.

18. A memory device, the memory device comprising: A first sub-block, a second sub-block and a third sub-block, wherein the first to third sub-blocks are arranged between a first line and a second line; a first connection region, the first connection region being arranged between the first sub-block and the second sub-block; a second connection region, the second connection region being arranged between the second sub-block and the third sub-block; a first transmission word line, the first transmission word line being adjacent to the first connection region; a second transmission word line, the second transmission word line being adjacent to the second connection region; as well as A peripheral circuit that applies an auxiliary voltage to the first transfer word line or the second transfer word line when an erase voltage is applied to the first line or the second line, and lowers a potential of the first transfer word line or the second transfer word line to which the auxiliary voltage is applied while the erase voltage is maintained at a target level.

19. The memory device of claim 18, wherein: The peripheral circuit applies the auxiliary voltage to the first transfer word line or the second transfer word line while applying the erase voltage to the first line or the second line.

20. The memory device of claim 18, wherein: The peripheral circuit applies the auxiliary voltage to a transfer word line, among the first transfer word line and the second transfer word line, which is located away from a region to which the erase voltage is applied.

21. The memory device of claim 18, wherein: The peripheral circuit applies the auxiliary voltage to the first and second transfer word lines while applying the erase voltage to the first line or the second line.

22. The memory device of claim 18, wherein: The peripheral circuit floats the first transfer word line and the second transfer word line whose potentials are lowered while the erase voltage is maintained at a target level.

23. A method of operating a memory device, the method comprising the steps of: During an erase operation performed on a memory block including a cell plug extending between a first line and a second line, wherein a first selection line, a first word line group, a first transfer word line, a second word line group, and a second selection line are arranged along the cell plug between the first line and the second line, applying an erase voltage to the first line or the second line; applying an auxiliary voltage to the first transmission word line when the erase voltage is applied to the first line or the second line; and While the erase voltage is maintained at a target level, the potential of the first transmission word line is lowered.

24. The method according to claim 23, further comprising the steps of: The auxiliary voltage is applied to the first transmission word line for a time interval after the erase voltage applied to the first line or the second line reaches the target level.

25. The method according to claim 23, wherein: The auxiliary voltage increases with the same slope as that of the erase voltage.

26. The method of claim 23, wherein: The auxiliary voltage varies depending on the temperature of the memory device.

27. The method according to claim 23, wherein: The auxiliary voltage changes in proportion to the temperature of the memory device.

28. The method according to claim 23, further comprising the steps of: When the erase voltage is applied to the first line or the second line, a cutoff voltage is applied to the first selection line and the second selection line.

29. The method according to claim 23, further comprising the steps of: While the erase voltage is maintained at the target level, a turn-on voltage is applied to the first selection line and the second selection line.

30. The method according to claim 23, further comprising the steps of: After the potential of the first transfer word line is lowered, the first transfer word line is floated.

31. The method according to claim 23, further comprising the steps of: When the memory block further includes a third word line group and a second transmission word line between the second word line group and the second selection line and the erase voltage is applied to the second line, The auxiliary voltage is applied to the first and second transfer word lines.

32. The method according to claim 23, further comprising the steps of: When the memory block further includes a third word line group and a second transmission word line between the second word line group and the second selection line and the erase voltage is applied to the second line, applying the auxiliary voltage to the first transmission word line; and The second transmission word line is floated.

Images