Information storage method and device of memory, memory and storage medium

Abstract

The invention discloses an information storage method and device of a memory, the memory and a storage medium. The information storage method of the memory comprises the following steps: writing target parameter data in a target word line; keeping two groups of adjacent word lines adjacent to the target word line in an erasing state; and writing the target parameter data in other word lines, wherein the other word lines are the word lines except the target word line and the two groups of adjacent word lines. According to the invention, the target parameter data which is the same as the target word line is written on the other word lines, the target parameter data on the target word line is reinforced, two groups of adjacent word lines which are adjacent to the target word line are kept in an erasing state, the interference caused by the voltage change of the adjacent word lines is reduced, the data interference and misreading can be effectively avoided, and the data processing efficiency is improved. Therefore, the reliability and accuracy of the stored data are improved.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a memory information storage method, device, memory and storage medium. Background Art

[0002] When NAND FLash is used in the client, it has an ECC error correction function. With the help of the ECC error correction function, the correctness of the data stored by the user can be judged when the data has just been written and has been stored for a certain period of time.

[0003] NAND FLash itself has a lot of important data information written to a fixed location. After the chip is powered on, when doing Power on read (power on read), these important data information will be read into the latch of the chip. When the user uses the chip, the parameters in the latch (the above important data information) will be used. However, during Power on read, these parameters have not been read into the latch, so when doing Power on read, the default parameters are used. For example, the voltage added to select WL (select word line) during Read. When the chip is designed, the voltage range allowed is 0-2V, 0.1V per step, and the voltage is 0.1V under default conditions. But the result obtained from the experiment is that the voltage is set to 0.5V for the best chip performance. Then the 0.5V information will be written in the special Block area of ​​the chip. There are many voltage information like this and these information are critical. Once an error occurs, the Power on read of the chip will fail, and the chip will not work properly.

[0004] When NAND FLash is powered on, it will read its own parameter information into the corresponding cache (cache memory). However, when powered on, the cache contains a set of fixed parameters designed by the design, without ECC error correction algorithm, and it is not the optimal parameter setting for NAND FLash. And after the chip is applied to the client, this information is only read out when powered on, without erasing and reprogramming. It needs to be able to persist in the placement of the entire NNAD FLash life without error. Once an error occurs, the chip cannot be read and written normally, and the reliability is poor. Summary of the invention

[0005] The present invention provides an information storage method for a memory device, aiming to improve the storage quality of important data information of NAND FLash itself, thereby ensuring the correctness of these important data information. The present invention reinforces the target parameter data on the target word line by writing the same target parameter data as the target word line on the remaining word lines, and reduces the interference caused by the change of the voltage of the adjacent word lines by keeping the two groups of adjacent word lines adjacent to the target word line in an erased state, thereby effectively avoiding data interference and misreading, thereby improving the reliability and accuracy of the stored data.

[0006] To achieve the above object, the present invention proposes an information storage method for a memory.

[0007] The memory is a Nand flash memory, and the Nand flash memory includes a plurality of storage cells connected in series, each storage cell corresponds to a word line, and the method includes:

[0008] Writing target parameter data in a target word line;

[0009] keeping two groups of adjacent word lines adjacent to the target word line in an erased state;

[0010] The target parameter data is written into the remaining word lines, which are the target word line and word lines other than the two groups of adjacent word lines.

[0011] Optionally, after writing the target parameter data in the remaining word lines, the method further includes:

[0012] When powering on and reading data, applying a conduction voltage to the two groups of adjacent word lines and the remaining word lines;

[0013] And, applying a read voltage to the target word line to obtain read data on the target word line.

[0014] Optionally, after applying a read voltage to the target word line to obtain read data on the target word line, the method further includes:

[0015] Verifying the read data on the target word line by means of positive and negative code verification;

[0016] If the verification passes, the target parameter data is read into the latch.

[0017] Optionally, after verifying the read data, the method further includes:

[0018] If the verification fails, applying a read voltage to the remaining word lines to obtain read data on the remaining word lines;

[0019] The read data on the remaining word lines are verified by a positive and negative code verification method until the verification succeeds or all the verifications fail.

[0020] Optionally, after reading the target parameter data into the latch, the method further includes:

[0021] reading the target parameter data in the latch into a cache memory;

[0022] The Nand flash memory is configured by the target parameter data in the cache memory.

[0023] Optionally, the read voltage is configured to be between a first voltage threshold and a second voltage threshold, the first voltage threshold being a threshold voltage when there are electrons on the floating gate of the memory cell, and the second voltage threshold being a threshold voltage when there are no electrons on the floating gate of the memory cell.

[0024] Optionally, the target parameter data includes non-default operating parameter data required by the Nand flash memory when reading data.

[0025] The present invention also proposes a memory information storage device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and the computer program implements the steps of the above-mentioned memory information storage method when executed by the processor.

[0026] The present invention also provides a memory, which includes a Nand flash memory and an information storage device of the memory, and a plurality of storage units connected in series, each storage unit corresponds to a word line, and the information storage device of the memory is the information storage device of the above-mentioned memory.

[0027] The present invention further provides a storage medium having a computer program stored thereon, and the computer program, when executed by a processor, implements the steps of the above-mentioned memory information storage method.

[0028] The technical solution of the information storage method of the memory of the present invention is to write target parameter data in the target word line; keep two groups of adjacent word lines adjacent to the target word line in an erased state; write target parameter data in the remaining word lines, and the remaining word lines are the target word line and the word lines other than the two groups of adjacent word lines. The present invention reinforces the target parameter data on the target word line by writing the same target parameter data as the target word line on the remaining word lines, and reduces the interference caused by the change of the voltage of the adjacent word lines by keeping the two groups of adjacent word lines adjacent to the target word line in an erased state, so as to effectively avoid data interference and misreading, thereby improving the reliability and accuracy of the stored data. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A schematic diagram of a flow chart of an information storage method of a memory provided by an embodiment of the present invention;

[0030] Figure 2 It is a schematic diagram of word line arrangement of a NAND FLash provided by an embodiment of the present invention;

[0031] Figure 3 It is a schematic diagram of the internal structure of a NAND FLash provided by an embodiment of the present invention;

[0032] Figure 4 Schematic diagram of a positive and negative code verification method provided by an embodiment of the present invention;

[0033] Figure 5 is a schematic diagram of the influence between storage units provided by an embodiment of the present invention;

[0034] Figure 6 A schematic diagram of the structure of an information storage device of a memory provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0036] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0037] It should also be noted that when an element is referred to as being "fixed on" or "disposed on" another element, it may be directly on the other element or there may be an intermediate element at the same time. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or there may be an intermediate element at the same time.

[0038] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0039] See also Figure 1 , Figure 1 1 is a flow chart of a method for storing information in a memory provided by an embodiment of the present invention. The method for storing information in a memory comprises the following steps:

[0040] S10, writing target parameter data into the target word line.

[0041] In this embodiment, the memory is a Nand flash memory, which includes a plurality of storage cells connected in series. Nand flash memory can also be called NAND flash memory or Nand flash memory. Nand flash memory is a type of flash memory, which adopts a nonlinear macro cell mode internally, and provides a cheap and effective solution for the implementation of solid-state large-capacity memory. In the Nand flash memory, the storage cell cell is a double-layer floating gate MOS tube similar to NMOS, also known as a floating gate transistor. The storage cell cell consists of a source, a drain, a control electrode (usually a word line) and a floating gate. The floating gate is surrounded by an insulating layer above and below, and is used to store charge.

[0042] Writing operation (programming) of a memory cell: by applying a high voltage to the control electrode, a quantum tunneling effect is induced, causing electrons to be injected from the source through the insulating layer into the floating gate. This changes the charge state on the floating gate, which in turn affects the conduction state of the transistor, indicating the stored information (usually "0" or "1").

[0043] Memory cell erase operation: Erasing is usually performed in blocks. By applying a strong voltage to the substrate, a quantum tunneling effect is induced, so that the electrons on the floating gate are removed and the original state of the transistor is restored.

[0044] Memory cell read operation: The cell state is read by applying a low read voltage to the control electrode and detecting the conduction state between the source and drain. If there are electrons in the floating gate, the read voltage will be offset, making the transistor non-conductive, indicating that the stored information is "0"; if there are no electrons in the floating gate, the transistor is conductive, indicating that the stored information is "1".

[0045] The word line distribution of NAND FLash is as follows Figure 2 As shown, Figure 2 FIG. 1 is a schematic diagram of a word line arrangement of a NAND FLash provided by an embodiment of the present invention. The internal structure of the NAND FLash is as follows: Figure 3 As shown, Figure 3 is a schematic diagram of the internal structure of a NANDFLash provided by an embodiment of the present invention, Figure 3 It is a schematic diagram of the internal structure of a NAND FLash provided by an embodiment of the present invention.

[0046] exist Figure 2 In the embodiment of the present invention, a method of writing many WLs is adopted to strengthen the storage of target parameter data. n The writing method remains unchanged. n-2 , W.L. n-3 , W.L. n-4 , W.L. n+2 , W.L. n+3 , W.L. n+4 Write the target word line WL n Same data as WL n Two adjacent word lines WL n+1 and WL n-1 Still keep the Erase status.

[0047] Power on read (power on read) still reads and verifies the target word line WL n , the remaining word lines WL n-2 , W.L. n-3 , W.L. n-4 , W.L. n+2 , W.L. n+3 , W.L. n+4 The data above can reinforce the data of WLn.

[0048] The target word line may be a middle word line. A group of word lines may include at least one word line, that is, the target word line may be one word line or multiple word lines. In the embodiment of the present invention, considering that the target parameter data in NAND Flash is relatively small, the target word line may be a middle word line.

[0049] exist Figure 2In, WL n The target word line, the target parameter data may be non-default parameter data of the NAND Flash. The default parameter data of the NAND Flash is fixed parameter data stored in the cache. When the non-default parameter data of the NAND Flash is not read, the NAND Flash will be configured using the default parameter data in the cache.

[0050] After the target parameter data is written in the target word line, the Floating Gate has electrons in the cell corresponding to the target word line, and the corresponding flag data is "0". If the target parameter data is not written in the target word line, the Floating Gate has no electrons in the cell corresponding to the target word line, and the corresponding flag data is "1".

[0051] exist Figure 3 In the example, cells are connected in series to form a cell string (…, WL n-4 , W.L. n-3 , W.L. n-2 , W.L. n-1 , W.L. n , W.L. n+1 , W.L. n+2 , W.L. n+3 , W.L. n+4 , …), the source end of the current cell is connected to the drain end of the next cell, and the drain end of the first cell is connected to the bit line.

[0052] S20, keeping two groups of adjacent word lines adjacent to the target word line in an erased state.

[0053] In the embodiment of the present invention, the adjacent word lines are adjacent to the target word line, and may be a group of word lines before the target word line and a group of word lines after the target word line, and the two groups of adjacent word lines are respectively before and after the target word line. The erased state indicates that no data is written, that is, in the cell corresponding to the adjacent word line, the floating gate has no electrons, and the corresponding flag data is "1".

[0054] Each group of adjacent word lines includes at least one word line, which can be determined according to the interference degree between adjacent word lines. The greater the interference degree between two adjacent word lines, the more word lines there are in each group of adjacent word lines. In this way, the interference when adjacent word lines change can be reduced.

[0055] exist Figure 2 In the example, the adjacent word line may be a WL adjacent to the target word line. n , namely WL n+1 and WL n-1. WL n+1 and WL n-1 Remains in the erased state and does not write any data.

[0056] S30 , writing target parameter data into the remaining word lines.

[0057] In an embodiment of the present invention, the above-mentioned remaining word lines are word lines other than the target word line and the adjacent word lines, and the above-mentioned remaining word lines are written with the same target parameter data as the target word line, so that the target parameter data of the target word line can be reinforced. When the target parameter data is written into the target word line and the target parameter data is written into the remaining word lines, when the data is read at startup, the probability of the target word line reading the flag data 0 is increased.

[0058] The information storage method of the memory of the present embodiment is implemented, and the target parameter data is written in the target word line; the two groups of adjacent word lines adjacent to the target word line are kept in an erased state; the target parameter data is written in the remaining word lines, and the remaining word lines are the target word line and the word lines other than the two groups of adjacent word lines. The present invention reinforces the target parameter data on the target word line by writing the same target parameter data as the target word line on the remaining word lines, and reduces the interference caused by the change of the voltage of the adjacent word lines by keeping the two groups of adjacent word lines adjacent to the target word line in an erased state, so as to effectively avoid data interference and misreading, thereby improving the reliability and accuracy of the stored data.

[0059] It can be understood that in the specific implementation of this application, memory data, control data, parameter data and other related data are involved. When the embodiments in this application are applied to specific products or technologies, user permission or consent is required, and the collection, use and processing of relevant data, as well as the training and use of various models need to comply with relevant laws, regulations and standards of relevant countries and regions.

[0060] Optionally, after writing the target parameter data in the remaining word lines, when powering on to read data, a conduction voltage may be applied to two groups of adjacent word lines and the remaining word lines; and a read voltage may be applied to the target word line to obtain the read data on the target word line.

[0061] In the embodiment of the present invention, at the initial stage of powering on and reading data, it is first necessary to apply a conduction voltage to two groups of adjacent word lines and the remaining word lines, so that the adjacent word lines and the remaining word lines are in a conduction state, thereby creating necessary conditions for subsequent data reading operations. The application of the conduction voltage is usually achieved by a voltage control circuit inside the memory.

[0062] The on-voltage is a relatively high voltage, which can be determined according to the default parameters of the NAND Flash. If the voltage is too low, the word line may not be fully turned on, resulting in data reading failure. Therefore, in practical applications, it is necessary to select a suitable on-voltage value according to the specific characteristics and usage requirements of the memory.

[0063] After applying the conduction voltage to the two groups of adjacent word lines and the remaining word lines, it is necessary to apply the read voltage to the target word line. The read voltage is a voltage specifically used to read the data in the memory cell, and its magnitude is usually configured between the first voltage threshold and the second voltage threshold. The first voltage threshold corresponds to the threshold voltage when there are no electrons on the floating gate of the memory cell, and the second voltage threshold corresponds to the threshold voltage when there are electrons on the floating gate. By applying the read voltage, the data state in the memory cell can be determined, thereby reading the stored information.

[0064] When a read voltage is applied to the target word line, the current or voltage signal in the memory cell will change accordingly. Figure 3 , Bit Line is charged during Read, except for the target word line WL n The other word lines WL are added with a higher voltage to turn on the cell, and the target word line WL n A read voltage is applied. If there are electrons on the floating gate of the cell, the voltage threshold VT is higher (VT1, the first voltage threshold). If there are no electrons on the floating gate, VT is very low (VT2, the second voltage threshold), and the read voltage is between VT1 and VT2.

[0065] Furthermore, a cell can be considered as a resistor. When voltage is applied to WL, the cell is turned on, which can be considered as a small resistance. When the voltage on WL is not enough to turn on the cell, it can be considered as a large resistance. If there are electrons in the floating gate, the cell is not turned on, the electricity in BL (Block) cannot be discharged, and the flag data read is 0; if there are no electrons in the floating gate, the cell can be turned on, the electricity in BL can be discharged, and the flag data read is 1.

[0066] By applying a turn-on voltage to two groups of adjacent word lines and the remaining word lines, and applying a read voltage to a target word line, data in a memory cell can be effectively read, and the accuracy and reliability of the data can be ensured.

[0067] Optionally, after applying a read voltage to the target word line to obtain the read data on the target word line, the read data on the target word line can also be verified by a positive and negative code verification method; if the verification passes, the target parameter data is read into the latch.

[0068] In the embodiment of the present invention, in order to ensure the correctness of the target parameter data, the positive and negative codes may be written to the target parameter data, and multiple copies of the positive and negative codes may be written.

[0069] The positive and negative code check detects whether errors occur during data transmission or storage by comparing the original value of the data with its negative code value. In Nand flash memory, the positive and negative code check is used to ensure that the data read from the target word line is accurate.

[0070] Specifically, when a read voltage is applied to the target word line, the memory will output the read data on the word line. In order to verify the correctness of this data, the inverse code of this data will be generated. The inverse code is usually generated by inverting each bit of the data, that is, 0 becomes 1, and 1 becomes 0. Then, the system will compare the original data with the generated inverse code. If the two are exactly the same, it means that there is no error in the data reading process and the verification passes; if there is a difference, it means that the data may be interfered with or damaged, and the verification fails.

[0071] Specifically, Figure 4 As shown, Figure 4 is a schematic diagram of a positive and negative code verification method provided by an embodiment of the present invention, Figure 4 It includes multiple copies, namely copy1, copy2, copy3, copy4, ..., each copy includes byte1 positive code, byte1 reverse code, byte2 positive code, byte2 reverse code, ...

[0072] After the chip is powered on, when doing Power on read, if the verification passes, this information will be read into the latch of the chip. When the user uses the chip, the parameters in the latch will be used.

[0073] like Figure 4 When doing power on read, the positive and negative codes are checked based on the byte. If the positive and negative code check fails, the next copy is read from the failed byte until all information is correctly read into the latch. Otherwise, the status inside the chip will be set to 1. In the embodiment of the present invention, the target word line and the other word lines are set according to Figure 3 In this way, information is written, and the adjacent word lines adjacent to the target word line in the block are all in the FF state (erased state).

[0074] Optionally, after the step of verifying the read data, if the verification fails, a read voltage can be applied to the remaining word lines to obtain the read data on the remaining word lines; the read data on the word lines can be verified by a positive and negative code verification method until the verification succeeds or all verifications fail.

[0075] In the embodiment of the present invention, considering that the target parameter data is also written into the remaining word lines, after the read data verification of the target word line fails, a read voltage can be applied to the remaining word lines to obtain the read data on the remaining word lines, and the read data on the remaining word lines is verified. The verification method is the same as the verification method for the target word line, which will not be repeated here.

[0076] Optionally, after the step of reading the target parameter data into the latch, the target parameter data in the latch may also be read into a cache memory; and the Nand flash memory is configured using the target parameter data in the cache memory.

[0077] In the embodiment of the present invention, the latch is a temporary storage element with the characteristic of fast data access, but is usually not suitable as a storage medium for long-term or large amounts of data due to its limited storage capacity and access speed. Therefore, the target parameter data in the latch can be read into a cache memory.

[0078] Cache memory is a component in a computer system that temporarily stores data for quick access. It is located between the main memory and the processor and improves the overall performance of the system by reducing the number of times the processor accesses the main memory. In the context of Nand flash memory, cache memory can be used to store frequently accessed or critical data, such as configuration parameters, index information, etc., so that it can be quickly read when needed.

[0079] The process of reading data from the latch to the cache memory usually involves data movement and cache management strategies. That is, when the NAND FLash is powered on, if the read data verification of the target word line passes, its own target parameter data will be read into the read latch, and then read from the latch into the corresponding cache. When the NAND Flash is used, the target parameter data is read from the cache to configure the NAND Flash.

[0080] When the target parameter data is successfully read into the cache memory, it can be used to configure the Nand flash memory. During the configuration process, the advantage of the cache memory is its fast access speed. Since the configuration parameters usually need to be read and applied before the memory is initialized or a specific operation is performed, storing them in the cache memory can significantly reduce the configuration time and improve the response speed of the memory.

[0081] Optionally, the read voltage is configured to be between a first voltage threshold and a second voltage threshold, the first voltage threshold being a threshold voltage when there are electrons on the floating gate of the memory cell, and the second voltage threshold being a threshold voltage when there are no electrons on the floating gate of the memory cell.

[0082] In the embodiment of the present invention, the above-mentioned read voltage is a voltage specifically used to read data in the storage cell, and its magnitude is usually configured between a first voltage threshold and a second voltage threshold. The first voltage threshold corresponds to a threshold voltage when there are no electrons on the floating gate of the storage cell, and the second voltage threshold corresponds to a threshold voltage when there are electrons on the floating gate. By applying the read voltage, the data state in the storage cell can be determined, thereby reading the stored information.

[0083] When a read voltage is applied to the target word line, the current or voltage signal in the memory cell will change accordingly. Figure 3 , Bit Line is charged during Read, except for the target word line WL n The other word lines WL are added with a higher voltage to turn on the cell, and the target word line WL n A read voltage is applied. If there are electrons on the floating gate of the cell, the voltage threshold VT is higher (VT1, the first voltage threshold). If there are no electrons on the floating gate, VT is very low (VT2, the second voltage threshold), and the read voltage is between VT1 and VT2.

[0084] Optionally, the target parameter data includes non-default working parameter data required by the Nand flash memory when reading data.

[0085] In an embodiment of the present invention, the above-mentioned target parameter data may be non-default operating parameter data of NAND Flash. The default operating parameter data of NAND Flash is fixed parameter data stored in the cache. When the non-default operating parameter data of NAND Flash is not read, the NAND Flash will be configured using the default operating parameter data in the cache.

[0086] The above target parameter data is, for example, the read voltage added to select WL (select word line) during Read. When the chip is designed, the voltage range allowed is 0-2V, with a step of 0.1V. Under default conditions, the read voltage is 0.1V. However, the experimental results show that setting the read voltage to 0.5V is the best for chip performance. Then the information of read voltage = 0.5V will be written in the corresponding Block area of ​​the chip. There are many similar voltage information, such as erase voltage, programming voltage, etc. Generally, it does not exceed one eighth of a page (storage page) of the chip.

[0087] In the embodiments of the present invention, please refer to Figure 3 , the same value is written in the Bit Line direction, there are electrons in the floating gate or there are no electrons in the floating gate. For 0, except for the floating gates of WLn+1 and WLn-1 cells, there are electrons in the floating gates of the other cells, and the resistance of the entire cell string will increase, increasing the probability that the read data is 0. For 1, there are no electrons in the floating gates of the entire cell string, which does not affect the reading of 1.

[0088] Because the spacing between NAND FLash cells is relatively small, when the floating gate of a cell changes from having electrons to having electrons, it will affect the VT of the adjacent cells, so WLn-1 and WLn+1 are not programmed.

[0089] Please refer to Figure 5 , Figure 5 is a schematic diagram of the influence between storage units provided by an embodiment of the present invention. Figure 5 In the figure, programming the floating gates of cells ②④⑥⑧ from 1 to 0 will have a very obvious impact on the VT of cell ⑤. Programming the floating gates of cells ①③⑦⑨ from 1 to 0 will have some impact on cell ⑤. It can be seen that the voltage impact between cells is strongly related to the distance between cells.

[0090] The present invention also provides an information storage device of a memory, referring to Figure 6 , Figure 6 It is a schematic diagram of the structure of an information storage device of a memory in a hardware operating environment involved in an embodiment of the present invention.

[0091] The information storage device of the memory of the embodiment of the present invention can be a computing device such as a desktop computer, a notebook, a palm computer, and a server. Figure 6As shown, the information storage device of the memory may include: a processor 1001 (e.g., a CPU), a network interface 1004, a user interface 1003, a memory 1005, and a communication bus 1002. Among them, the communication bus 1002 is used to realize the connection and communication between these components. The user interface 1003 may include a display screen (Display), an input unit, such as a keyboard (Keyboard), and the optional user interface 1003 may also include a standard wired interface and a wireless interface. The network interface 1004 may optionally include a standard wired interface and a wireless interface (such as a WI-FI interface). The memory 1005 may be a high-speed RAM memory, or it may be a stable memory (non-volatile memory), such as a disk memory. The memory 1005 may optionally be a storage device independent of the aforementioned processor 1001.

[0092] Those skilled in the art will understand that Figure 6 The information storage device structure of the memory shown in the figure does not constitute a limitation on the information storage device of the memory, and may include more or less components than shown in the figure, or combine certain components, or arrange the components differently.

[0093] The present invention also provides a memory, the memory comprising a Nand flash memory and an information storage device of the memory, and a plurality of storage units connected in series, each storage unit corresponding to a word line, the information storage device of the memory being Figure 6 The memory shown is an information storage device.

[0094] like Figure 6 As shown, the memory 1005 as a computer storage medium may include an operating system, a network communication module, a user interface module and a computer program.

[0095] exist Figure 6 In the information storage device of the memory shown, the network interface 1004 is mainly used to connect to the background server and communicate data with the background server; the user interface 1003 is mainly used to connect to the client (user end) and communicate data with the client; and the processor 1001 can be used to call the computer program stored in the memory 1005. When the computer program is called and executed by the processor 1001, the steps of the above-mentioned memory information storage method are implemented.

[0096] Based on the computer program proposed in the aforementioned embodiment, the present invention further proposes a storage medium, which stores the computer program. When the computer program is executed by a controller, the information storage method of the memory described in the aforementioned embodiment is implemented.

[0097] The information storage device, memory and storage medium of the memory of the present invention can implement the steps of the information storage method of the above-mentioned memory, and therefore have at least all the beneficial effects brought by the technical solution of the embodiment of the information storage method of the above-mentioned memory, which will not be described one by one here.

[0098] In the several embodiments provided in the present application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules, which can be electrical, mechanical or other forms.

[0099] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0100] In addition, each functional module in each embodiment of the present invention may be integrated into one processing module, or each module may exist physically separately, or two or more modules may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of software functional modules.

[0101] If the integrated module is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0102] The above description is only a partial or preferred embodiment of the present invention. Neither the text nor the drawings can limit the scope of protection of the present invention. All equivalent structural changes made by using the contents of the present invention specification and drawings under the overall concept of the present invention, or direct / indirect application in other related technical fields are included in the scope of protection of the present invention.

Claims

1. A method for storing information in a memory, characterized in that: The memory is a Nand flash memory, and the Nand flash memory includes a plurality of storage cells connected in series, each storage cell corresponds to a word line, and the method includes: Writing target parameter data in a target word line; keeping two groups of adjacent word lines adjacent to the target word line in an erased state; The target parameter data is written into the remaining word lines, which are the target word line and word lines other than the two groups of adjacent word lines.

2. The information storage method of the memory according to claim 1, characterized in that: After writing the target parameter data in the remaining word lines, the method further includes: When powering on and reading data, applying a conduction voltage to the two groups of adjacent word lines and the remaining word lines; And, applying a read voltage to the target word line to obtain read data on the target word line.

3. The information storage method of the memory according to claim 2, characterized in that: After applying a read voltage to the target word line to obtain read data on the target word line, the method further includes: Verifying the read data on the target word line by means of positive and negative code verification; If the verification passes, the target parameter data is read into the latch.

4. The information storage method of the memory according to claim 3, characterized in that: After verifying the read data, the method further includes: If the verification fails, applying a read voltage to the remaining word lines to obtain read data on the remaining word lines; The read data on the remaining word lines are verified by a positive and negative code verification method until the verification succeeds or all the verifications fail.

5. The information storage method of the memory according to claim 3, characterized in that: After reading the target parameter data into the latch, the method further includes: reading the target parameter data in the latch into a cache memory; The Nand flash memory is configured by the target parameter data in the cache memory.

6. The information storage method of the memory according to claim 2, characterized in that: The read voltage is configured to be between a first voltage threshold and a second voltage threshold, wherein the first voltage threshold is a threshold voltage when there are electrons on the floating gate of the memory cell, and the second voltage threshold is a threshold voltage when there are no electrons on the floating gate of the memory cell.

7. The information storage method of the memory according to any one of claims 1 to 6, characterized in that: The target parameter data includes non-default operating parameter data required by the Nand flash memory when reading data.

8. An information storage device of a memory, characterized in that: The information storage device of the memory includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the computer program is executed by the processor, the steps of the information storage method of the memory as described in any one of claims 1 to 7 are implemented.

9. A memory, characterized in that: The memory comprises a Nand flash memory and an information storage device of the memory, and a plurality of storage units connected in series, each storage unit corresponding to a word line, and the information storage device of the memory is the information storage device of the memory as claimed in claim 8.

10. A storage medium, characterized in that: The storage medium stores a computer program, which, when executed by a processor, implements the steps of the information storage method of the memory according to any one of claims 1 to 8.

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