An Optimization Method, Device, and Storage Medium for Flash Memory Reading Performance in a Controller

Abstract

The present invention discloses an optimization method, device and storage medium for the flash memory reading performance in a controller, belonging to the technical field of flash memory. The method includes: inputting preset feature quantities, erase / write / read times and data retention time into the current prediction model to obtain a reading voltage offset range; predicting the threshold voltage distribution of the flash memory according to the usage of the flash memory, which is more real-time; based on the reading voltage offset range, performing a read retry operation; when performing the read retry operation, only one offset value of the reading voltage is adjusted for each page, and the other voltage offset values under the same page change following the change of the offset value of the reading voltage; the correlation of different reading voltage offset values for the same page greatly reduces the number of read retry times, reduces the read retry time, and improves the reading performance. Further, the threshold voltage distribution data determined by the read retry operation is used to update the current prediction model and save it, and the updated prediction model is used for the next reading operation, which increases the accuracy of the prediction.

Description

Technical Field

[0001] The present invention belongs to the technical field of flash memory, and more specifically, relates to a method, device, and storage medium for optimizing the flash memory reading performance within a controller. Background Art

[0002] As a non-volatile storage medium, flash memory has been widely used in today's electronic devices, from smartphones, tablets to solid-state drives, etc. With the continuous development of technology, the requirements for flash memory reading performance are also getting higher and higher. Mobile devices such as smartphones and tablets require fast flash memory reading performance to quickly start applications, load multimedia content such as photos and videos. Solid-state drives are increasingly widely used in computer systems, and the flash memory reading performance directly affects the system startup speed, file transfer speed, and application response time.

[0003] The manufacturing process of flash memory chips has been continuously improved, resulting in continuous improvement of storage density and also improvement of reading performance. The design of flash memory controllers is also being continuously optimized, improving the efficiency and reliability of data transmission. The controller can adopt more advanced algorithms to manage flash memory chips, improving the reading speed and lifespan. When reading flash memory, a method combining read retry and error correction code is often used. In actual operation, with repeated erasing and long-term data retention, the optimal reading voltage will shift, resulting in reading errors. At this time, the controller will adjust the read reference voltage and repeat the reading until the error rate is restored within the error correction ability range of the error correction code. This method effectively guarantees the reliability of flash memory reading results.

[0004] However, the default initial reading voltage offset of flash memory is often 0, and the number of repeated readings is relatively large, which greatly increases the reading duration of flash memory and reduces the reading performance of flash memory. In summary, a new reading optimization method is needed to improve the reading rate while ensuring reading reliability. Summary of the Invention

[0005] In view of the above-mentioned defects or improvement requirements of the prior art, the present invention provides a method, device, and storage medium for optimizing the flash memory reading performance within a controller, aiming to solve the technical problem that the flash memory reading voltage offset in the prior art leads to overly complicated read retry steps, resulting in a decrease in read and write performance.

[0006] To achieve the above object, according to one aspect of the present invention, a method for optimizing the flash memory reading performance within a controller is provided, including:

[0007] S1: When receiving a current reading operation, extract the preset feature quantity, the number of erase-write-read cycles, and the data retention time of the flash memory chip;

[0008] S2: Input the preset feature quantity, the number of erase / write / read cycles, and the data retention time into the current prediction model to predict the threshold voltage distribution; determine the read voltage offset range from the threshold voltage distribution;

[0009] S3: Based on the read voltage offset range, perform read retry operations until the target range is found, and perform a read within the target range to obtain the error count and its corresponding page number;

[0010] Among them, during the read retry operation, only the offset value of one read voltage is adjusted for each page, and the other voltage offset values under the same page change following the change of the offset value of the read voltage.

[0011] S4: Calculate the threshold voltage distribution data using the error count and its corresponding page number;

[0012] S5: Update the current prediction model using the threshold voltage distribution data and save it for predicting the corresponding threshold voltage distribution during the next read operation.

[0013] Further, the preset feature quantity includes: the storage unit number and the storage page number of the flash memory chip.

[0014] Further, the preset feature quantity further includes: one or more of the programming time, read time, erase time, and current of the flash memory chip.

[0015] Further, before the S2, it further includes: using the preset feature quantity, the number of erase / write / read cycles, and the data retention time in the sample set corresponding to the preset flash memory chip as inputs, and using the threshold voltage distribution corresponding to the preset flash memory chip as the output to train the initial prediction model to obtain the current prediction model in the first execution of the read operation.

[0016] Further, the process of obtaining the sample set includes:

[0017] Step 1. Perform an erase operation on the flash memory chip to be tested;

[0018] Step 2. Write test data to the flash memory chip to be tested;

[0019] Step 3. Wait for time T0, perform a read operation on the flash memory chip to be tested, compare the read data with the data written in Step 3, count the generated error count, and store it in the sample set;

[0020] Step 4. Determine whether the number of erase / write / read cycles experienced by the flash memory chip to be tested is less than the first threshold C1. If it is less, repeat Step 1 to Step 3; otherwise, go to Step 5;

[0021] Step 5. Power off and wait for time T1;

[0022] Step 6. Perform a read operation, save the read data, collect chip parameters and store them in the sample set;

[0023] Step 7. Waiting time T2;

[0024] Step 8. Perform a data reading operation on the flash memory chip under test, compare the read data with the data saved in step 6, count the number of errors generated during the statistical data retention period, and collect chip parameters and store them in the sample set;

[0025] Step 9. Determine whether the total data retention time exceeds time T3, if it is less, repeat steps 7 and 8, otherwise proceed to step 10 and clear the total data retention time count;

[0026] Step 10: Determine whether the cumulative number of erase / write / read times executed exceeds the second threshold value C2. If so, repeat steps 1 to 9. Otherwise, complete the test.

[0027] Furthermore, the read retry step length L of the i-th read reference voltage of the same page i and the jth read reference voltage read retry step length L j The relationship conforms to the formula: L i =a×L j ; where a is the proportionality coefficient, which can be expressed by the formula a=△R i / △R j Calculation shows that △R i =(R i -R i ' ), △R j = (R j -R j ' ), R i is the center value of the i-th read reference voltage on the same page, R j is the jth read reference voltage center value, R i ' and R j ' It is the initial read reference voltage center value set when the flash memory chip leaves the factory. Therefore, the read retry interval can be determined according to the read reference voltage center value and the read retry step size.

[0028] According to another aspect of the present invention, there is provided a device for optimizing flash memory read performance, comprising:

[0029] An extraction module, used for extracting preset characteristic quantities, erase and write read times and data retention time of the flash memory chip when receiving a current read operation;

[0030] A prediction module, configured to input the preset feature quantity, the number of erase / write / read operations, and the data retention time into a current prediction model to predict a threshold voltage distribution; and determine a read voltage offset interval from the threshold voltage distribution;

[0031] A read retry module, configured to perform a read retry operation on the basis of the read voltage offset interval until a target interval is found, and perform a read operation in the target interval to obtain an error count and its corresponding page number; wherein, during the read retry operation, only the offset value of one read voltage is adjusted for each page, and the other voltage offset values of the same page change following the change of the offset value of the read voltage;

[0032] A calculation module, configured to calculate threshold voltage distribution data by using the error count and its corresponding page number;

[0033] An update module, configured to update and save the current prediction model by using the threshold voltage distribution data for predicting a corresponding threshold voltage distribution during the next read operation.

[0034] According to another aspect of the present invention, a flash memory system is provided, including: a flash memory chip and a controller;

[0035] The controller stores a computer program, and is configured to implement the steps of the method for optimizing the flash memory reading performance in the controller when executing the computer program.

[0036] According to another aspect of the present invention, a computer-readable storage medium is provided, on which a computer program is stored, and the computer program, when executed by a processor, implements the steps of the method for optimizing the flash memory reading performance in the controller.

[0037] Generally speaking, compared with the prior art by the above technical solution conceived by the present invention, the following beneficial effects can be achieved:

[0038] (1) The present invention inputs the preset feature quantity, the number of erase / write / read cycles, and the data retention time into the current prediction model to obtain a read voltage offset range; predicting the threshold voltage distribution of the flash memory according to the usage of the flash memory is more real-time than using the initial threshold voltage during general read retry operations as a reference; based on the read voltage offset range, perform read retry operations until the target range is found and the error count and its corresponding page number are obtained; when performing the read retry operation, only one read voltage offset value is adjusted for each page, and the other voltage offset values on the same page change following the change of the read voltage offset value; the correlation of different read voltage offset values on the same page greatly reduces the number of read-retry times, reduces the reread time, and improves the read performance. Further, use the threshold voltage distribution data to update the current prediction model and save it for predicting the corresponding threshold voltage distribution during the next read operation. Using the updated prediction model for the next read operation is more in line with the actual situation of each flash memory chip in the actual situation compared to a fixed prediction model, increasing the accuracy of the prediction.

[0039] (2) In this solution, the preset feature quantity includes: the storage unit number and the storage page number of the flash memory chip. This design takes into account the influence of the differences in specific storage units and storage pages of the flash memory chip on the prediction model, maintaining the performance stability of the model.

[0040] (3) In this solution, the preset feature quantity further includes: one or more of the programming time, read time, erase time, and current of the flash memory chip. This design takes into account the manifestations of flash memory chip aging in multiple feature quantities during the actual use process, enhancing the robustness of the prediction model.

[0041] (4) In this solution, the preset feature quantity, the number of erase / write / read cycles, and the data retention time in the sample set corresponding to the preset flash memory chip are used as inputs, and the threshold voltage distribution corresponding to the preset flash memory chip is used as the output to train the initial prediction model; the training of the initial prediction model takes into account the wear and aging characteristics of the flash memory, realizing the prediction of the relationship between threshold voltage changes and flash memory wear and aging.

[0042] (5) In this solution, the process of obtaining the sample set simulates the flash memory usage situation in actual applications, collecting the parameters during the usage process as the sample set, making the model more in line with the application situation and realizing the improvement of the prediction accuracy.

[0043] (6) In this solution, the read retry step size \(L\) of the \(i\)th read reference voltage and the read retry step size \(L\) of the \(j\)th read reference voltage on the same page i and the relationship conforms to the formula: \(L\) j = \(a\times L\) i = \(a\times L\) j; This design takes into account the correlation of different read reference voltage changes on the same page, reduces the number of read retries, and realizes the improvement of reading efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 is a flowchart of a method for optimizing the flash memory reading performance in a controller provided by an embodiment of the present invention.

[0045] Figure 2 is a schematic flowchart of establishing a prediction model provided by an embodiment of the present invention.

[0046] Figure 3 is a schematic flowchart of obtaining a sample set provided by an embodiment of the present invention.

[0047] Figure 4 is a schematic diagram of determining a read reference voltage scanning range according to a threshold voltage provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0048] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0049] As Figure 1 shown, this embodiment provides a method for optimizing the flash memory reading performance in a controller, including: S1 - S5. Among them, S1: When receiving a current reading operation, extract the preset feature quantity, the number of erase / write / read times, and the data retention time of the flash memory chip. S2: Input the preset feature quantity, the number of erase / write / read times, and the data retention time into the current prediction model, and predict the threshold voltage distribution; determine the read voltage offset range from the threshold voltage distribution. S3: Based on the read voltage offset range, perform read retry operations until the target range is found, and perform reading in the target range to obtain the error number and its corresponding page number; among them, when performing read retry operations, only the offset value of one read voltage is adjusted for each page, and the other voltage offset values under the same page change following the change of the offset value of the read voltage. S4: Calculate the threshold voltage distribution data using the error number and its corresponding page number. S5: Update the current prediction model using the threshold voltage distribution data and save it for predicting the corresponding threshold voltage distribution during the next reading operation.

[0050] It should be noted that most of the technologies on the market are designed for flash memory chips themselves. After the flash memory is processed and packaged in a device, many parameters cannot be extracted due to the existence of the firmware layer. This solution is based on the controller, enabling the flash memory in packaged devices (such as SSDs, etc.) to be predicted, thereby optimizing the reading. All algorithm models are fixed in the controller.

[0051] Further, the preset feature quantities include: the storage unit number and the storage page number of the flash memory chip. Further, the preset feature quantities also include: one or more of the programming time, reading time, erasing time, and current of the flash memory chip.

[0052] Further, before S2, it also includes: using the initial preset feature quantities, the initial number of erase / write / read cycles, and their corresponding data retention times in the sample set corresponding to the preset flash memory chip as inputs, and using the threshold voltage distribution corresponding to the preset flash memory chip as the output, training the initial prediction model to obtain the current prediction model in the first execution of the reading operation.

[0053] Figure 2 It is a schematic flowchart of establishing a prediction model for an embodiment of the present invention. The model type adopted in this embodiment is a multi-layer artificial neural network. The artificial neural network includes: an input layer, a hidden layer, a softmax layer, and an output layer. Among them, the number of hidden layers is 10, the number of units in each layer is 50, and the activation function is sigmoid. The model can be the same as that in the input and application stages. Randomly select 70% of the obtained parameter data set as the training set, and the remaining 30% as the test set. The specific steps of building the prediction model are as follows:

[0054] 1. Initialize the training algorithm;

[0055] 2. Input the training set data into the artificial neural network, and the training algorithm calculates the error between the output of the artificial neural network and the actual value;

[0056] 3. The training algorithm adjusts the weights of the artificial neural network;

[0057] 4. Determine whether the number of epochs reaches 100. If it reaches 100, stop training; otherwise, return to step 2;

[0058] 5. The program outputs the prediction model.

[0059] Further, the process of obtaining the sample set is as follows: Select samples from the storage units in the flash memory chip, randomly select the same number of storage units with odd block numbers and even block numbers, and ensure that the selected storage units are evenly distributed throughout the address range of the chip. For each selected storage unit, the flash memory chip randomly selects word line storage units for testing to obtain the sample set. The process is as Figure 3 shown.

[0060] At room temperature, the selected flash memory chip is placed in the test equipment, and the test equipment is powered on. In this embodiment, the test data used for flash memory testing is pseudo-random test data, the number of erase / program cycles is C1, the total number of erase / program cycles is C2, the waiting time is T0, the power-off placement time of the flash memory chip is T1, the holding time is T2, and the total data holding time is T3. The amount of data written to each storage unit is determined according to the test requirements, and the data volume should be not less than the minimum write unit size of the storage unit and not higher than the data volume that can be stored in the storage unit specified in the data sheet. The value of the total data holding time T3 is determined according to the test requirements and should be less than the upper limit of the data holding time specified in the data sheet of the flash memory chip under test. The specific test steps are as follows:

[0061] Step 1. The test equipment performs an erase operation on the flash memory chip under test;

[0062] Step 2. The test equipment writes test data to the flash memory chip under test;

[0063] Step 3. Wait for time T0, and the test equipment performs a read operation on the flash memory chip under test and collects chip parameters;

[0064] Step 4. Determine whether the number of erase / program cycles experienced by the flash memory chip under test is less than C1. If the erase / write cycle is less than C1, repeat Steps 1 to 3; otherwise, proceed to Step 5;

[0065] Step 5. The test equipment powers off and waits for time T1;

[0066] Step 6. The test equipment performs one erase / program / read operation, saves the read data, and collects chip parameters;

[0067] Step 7. The test equipment waits for time T2;

[0068] Step 8. The test equipment performs a read data operation on the flash memory chip under test, compares the read data with the data saved in Step 6, counts the number of errors generated during the data holding period, and collects chip parameters;

[0069] Step 9. Determine whether the total data holding time exceeds time T3. If it is less, repeat Steps 7 and 8. Otherwise, proceed to Step 10 and clear the total data holding time count;

[0070] Step 10. Determine whether the cumulative number of erase / write operations performed exceeds the threshold C2. If it is less, repeat Steps 1 to 9. Otherwise, complete the test.

[0071] Further, the relationship between the read retry step length L of the i-th read reference voltage and the read retry step length L of the j-th read reference voltage on the same page i and the read retry step length L of the j-th read reference voltage j complies with the formula: L i =a×Lj ; where a is a proportionality coefficient, which can be calculated by the formula a = △R i / △R j . △R i =(R i -R i ' ), △R j = (R j -R j ' ), R i is the center value of the i-th read reference voltage on the same page, and R j is the center value of the j-th read reference voltage, and R i ' and R j ' are the initial read reference voltage center values set when the flash memory chip leaves the factory. Thus, the read retry interval can be determined based on the read reference voltage center value and the read retry step size.

[0072] For example, during the read retry operation, the offset values of R5, R6, and R7 are controlled to change. Since R1 and R5 are used to control the same page, R2, R4, and R6 are used to control the same page, and R3 and R7 are used to control the same page; the offset value of R1 changes following the offset value of R5; the offset values of R2 and R4 change following the offset value of R6, and the offset value of R3 changes following the offset value of R7. The relationship between the reread interval and the threshold voltage distribution interval is as Figure 4 shown. Figure 4 As marked in, R1 to R7 are the center values of the read reference intervals, and the scanning interval amplitude and step size of R5 to R7 are the same as the default values. The relationship between the read reference voltage center values of the same page conforms to the formula: R i = a × R j + f (C pe ).

[0073] Where R i and R j are the center values of two read reference voltages controlled by the same page, f (C pe ) is a linear function related to the number of erase and write cycles C pe . C pe is a determined value during a single read, f (C pe ) is also determined accordingly and can be regarded as a constant. The specific value is the value of R j when R i is 0. a is the proportionality coefficient.

[0074] Further, a can be obtained from the ratio of the difference between the offset values of the two read voltage centers, a = (R i -Ri ’ ) / (R j -R j ’ ), where R i ’ and R j ’ are the initial read reference voltage center values set when the chip leaves the factory. Thus, after confirming the reread scan step sizes of R5 to R7, the scan amplitudes and step sizes of R1 to R4 can be calculated accordingly. That is, the reread step size L i of the i-th read voltage on the same page and the reread step size L j of the j-th read voltage have the following relationship: L i =a×L j .

[0075] According to another aspect of the present invention, there is provided an apparatus for optimizing the flash memory reading performance, including: an extraction module, a prediction module, a read retry module, a calculation module, and an update module. The extraction module is configured to extract the preset feature quantity, the number of erase / write / read operations, and the data retention time of the flash memory chip when receiving a current read operation; the prediction module is configured to input the preset feature quantity, the number of erase / write / read operations, and the data retention time into a current prediction model to predict a threshold voltage distribution; determine a read voltage offset interval from the threshold voltage distribution; the read retry module is configured to perform a read retry operation on the basis of the read voltage offset interval until a target interval is found, and perform a read in the target interval to obtain the number of errors and their corresponding page numbers; wherein, when performing the read retry operation, only the offset value of one read voltage is adjusted for each page, and the offset values of other voltages on the same page change following the change of the offset value of the read voltage; the calculation module is configured to calculate threshold voltage distribution data by using the number of errors and their corresponding page numbers; the update module is configured to update the current prediction model by using the threshold voltage distribution data and save it for predicting the corresponding threshold voltage distribution during the next read operation.

[0076] According to another aspect of the present invention, there is provided a flash memory system, including: a flash memory chip and a controller; the controller stores a computer program, and is configured to implement the steps of the method for optimizing the flash memory reading performance in the controller when executing the computer program.

[0077] According to another aspect of the present invention, there is provided a computer-readable storage medium, on which a computer program is stored, and the steps of the method for optimizing the flash memory reading performance in the controller are implemented when the computer program is executed by a processor.

[0078] It is easy for those skilled in the art to understand that the above are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An optimization method for the flash memory reading performance in a controller, characterized in that Including: S1: When receiving a current read operation, extract the preset feature quantity, the number of erase / write / read cycles, and the data retention time of the flash memory chip; S2: Input the preset feature quantity, the number of erase / write / read cycles, and the data retention time into the current prediction model, and predict to obtain the threshold voltage distribution; Determine the read voltage offset interval from the threshold voltage distribution; S3: Based on the read voltage offset interval, perform read retry operations until the target interval is found, and perform a read in the target interval to obtain the error number and its corresponding page number; Wherein, during the read retry operation, only the offset value of one read voltage is adjusted for each page, and the offset values of other read voltages on the same page change following the change of the offset value of the read voltage; S4: Calculate the threshold voltage distribution data using the error number and its corresponding page number; S5: Update the current prediction model using the threshold voltage distribution data and save it for predicting the corresponding threshold voltage distribution during the next read operation.

2. The optimization method for the flash memory reading performance in the controller according to claim 1, characterized in that, The preset feature quantity includes: the storage unit number and the storage page number of the flash memory chip.

3. The method for optimizing the flash memory reading performance in the controller according to claim 2, characterized in that, The preset feature quantity further includes: one or more of the programming time, the read time, the erase time, and the current of the flash memory chip.

4. The optimization method for the flash memory reading performance in the controller according to claim 1, characterized in that Before S2, it further includes: Using the preset feature quantity, the number of erase / write / read cycles, and the data retention time in the sample set corresponding to the preset flash memory chip as inputs, and using the threshold voltage distribution corresponding to the preset flash memory chip as the output, training the initial prediction model to obtain the current prediction model in the first execution of the read operation.

5. The optimization method for the flash memory reading performance in the controller according to claim 4, wherein The process of obtaining the sample set includes: Step 1. Perform an erase operation on the flash memory chip to be tested; Step 2. Write test data to the flash memory chip to be tested; Step 3. Wait for time T0, perform a read operation on the flash memory chip to be tested, compare the read data with the data written in Step 2, count the generated error number, and collect the chip parameters and store them in the sample set; Step 4. Determine whether the number of erase / write / read cycles experienced by the flash memory chip to be tested is less than the first threshold C1. If it is less, repeat Steps 1 to 3, otherwise enter Step 5; Step 5. Power off and wait for time T1; Step 6. Perform a read operation once, save the read data and collect the chip parameters and store them in the sample set; Step 7. Wait for time T2; Step 8. Perform a read data operation on the flash memory chip to be tested, compare the read data with the data saved in Step 6, count the error number generated during the data retention period, and collect the chip parameters and store them in the sample set; Step 9. Determine whether the total data retention time exceeds time T3. If it is less, repeat Steps 7 and 8, otherwise perform Step 10 and clear the total data retention time count; Step 10. Determine whether the cumulative number of erase / write / read cycles performed exceeds the second threshold C2. If it is less, repeat Steps 1 to 9, otherwise complete the test.

6. The optimization method for the flash memory reading performance in the controller according to claim 1, characterized in that, The read retry step size L of the i-th read reference voltage on the same page i and the read retry step size L of the j-th read reference voltage j satisfy the formula: L i = a × L j ; where a is a proportionality coefficient, which can be calculated by the formula a = △R i / △R j △R i = (R i -R i ' ), △R j = (R j -R j ' ), R i is the central value of the i-th read reference voltage on the same page, R j is the central value of the j-th read reference voltage, and R i ' and R j ' are the initial central values of the read reference voltages set when the flash memory chip leaves the factory; Determine the read retry interval according to the read reference voltage center value and the read retry step size.

7. An optimization device for flash memory reading performance, characterized in that, Including: An extraction module, configured to extract the preset feature quantity, the number of erase / write / read cycles, and the data retention time of the flash memory chip when receiving a current read operation; A prediction module, configured to input the preset feature quantity, the number of erase / write / read cycles, and the data retention time into a current prediction model to predict a threshold voltage distribution; and determine a read voltage offset interval from the threshold voltage distribution; A read retry module, configured to perform a read retry operation based on the read voltage offset interval until a target interval is found, and perform a read operation in the target interval to obtain an error count and its corresponding page number; wherein, during the read retry operation, only the offset value of one read voltage is adjusted for each page, and the offset values of other read voltages on the same page change following the change of the offset value of the read voltage; A calculation module, configured to calculate threshold voltage distribution data by using the error count and its corresponding page number; An update module, configured to update and save the current prediction model by using the threshold voltage distribution data for predicting a corresponding threshold voltage distribution during the next read operation.

8. A flash memory system, characterized in that, Comprising: A flash memory chip and a controller; The controller stores a computer program, and is configured to implement the steps of the method for optimizing the flash memory reading performance according to any one of claims 1 to 6 when executing the computer program.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, The computer program, when executed by a processor, implements the steps of the method according to any one of claims 1 to 6.

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