Erasing control method and device of memory and storage medium

Abstract

The invention discloses an erasure control method and device of a memory and a storage medium, and the erasure control method of the memory comprises the following steps: determining the current frequency stage of the current Nand flash memory according to the P / E cycle frequency of the Nand flash memory; on the basis of the current frequency stage, corresponding grid bias voltages are configured for the storage unit, the grid bias voltages correspond to the frequency stages of the Nand flash memory, and one frequency stage corresponds to one set of grid bias voltages; and based on the gate bias voltage corresponding to the current frequency stage, performing erasure verification on the P / E cycle of the current frequency stage. According to the invention, the grid bias voltage is dynamically adjusted through the P / E cycle times, the voltage condition in the erasing process can be more accurately controlled, and the stress on the memory unit can be reduced by dynamically adjusting the grid bias voltage, so that the deformation and damage of the gate oxide layer are delayed, and the stability of a data memory mechanism is improved.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a memory erasure control method, device and storage medium. Background Art

[0002] In general, Nand Flash repeatedly writes and deletes information on the storage cell according to the user's usage. If the characteristics of Nand Flash Cell are repeatedly used for programming and erasing, the electrons will be dragged by the oxide layer during the movement, causing the threshold voltage (VT) to rise. The increase in threshold voltage leads to faster programming speed and slower erasing speed, thereby increasing the well bias during erasing to help the erasing proceed smoothly. However, during the erasing process, when the well bias increases, the movement of the hole changes greatly, resulting in a larger dispersion of the threshold voltage (Erase Cell VT) of the erased cell. When the Erase Cell VT distribution increases, the distribution of the program threshold voltage (Program VT) will also increase. As these actions are repeated, the stress (Stress) applied to the gate oxide layer (Gate Oxide) of the cell increases, and the deformation and damage of the oxide proceed rapidly. Due to this behavior, if the number of P / E cycles (Program and Erase cycle) increases, the data retention characteristics of the Cell will drop sharply, resulting in a decrease in the performance of the Nand Flash and shortening the functional life of the Nand Flash. Summary of the invention

[0003] The present invention provides an erase control method for a memory, aiming to solve the problem that the data memory mechanism characteristics of a cell will drop sharply due to the increase in the number of P / E cycles. By dynamically adjusting the gate bias voltage according to the number of P / E cycles of the Nand Flash memory, the voltage conditions during the erase process can be more accurately controlled. Dynamically adjusting the gate bias voltage can reduce the stress on the memory cell, thereby delaying the deformation and damage of the gate oxide layer and improving the stability of the data memory mechanism.

[0004] To achieve the above object, the present invention provides a memory erase control method, wherein the memory is a Nand flash memory, and the Nand flash memory includes a plurality of storage units. The method includes:

[0005] Determine the current number stage of the Nand flash memory according to the number of P / E cycles of the Nand flash memory;

[0006] Based on the current number stage, a corresponding gate bias voltage is configured for the storage unit, wherein the gate bias voltage has a corresponding relationship with the number stage of the Nand flash memory, and one number stage corresponds to a group of the gate bias voltages;

[0007] Based on the gate bias voltage corresponding to the current number stage, the P / E cycle of the current number stage is erased and verified.

[0008] Optionally, before configuring a corresponding gate bias voltage for the storage unit based on the current number stage, the method further includes:

[0009] Determining variable gate bias voltages corresponding to the storage unit in different states, each state corresponding to a set of the variable gate bias voltages;

[0010] The memory cells are configured with corresponding variable gate bias voltages, and each memory cell is configured with a corresponding set of variable gate bias voltages.

[0011] Optionally, determining the variable gate bias voltage corresponding to the storage unit in different states includes:

[0012] determining a first variable gate bias voltage corresponding to the memory cell in a non-selected state, the non-selected state being used to indicate that the memory cell is not selected to perform a P / E cycle;

[0013] And, determining a second variable gate bias voltage corresponding to the memory cell in a selected state, wherein the selected state is used to indicate that the memory cell is selected to perform a P / E cycle.

[0014] Optionally, configuring the corresponding variable gate bias voltage for the storage unit includes:

[0015] When the memory cell is in a non-selected state, configuring a pass bias voltage of each erase pulse based on the first variable gate bias voltage;

[0016] When the memory cell is in a selected state, a selection bias voltage of each erase pulse is configured based on the second variable gate bias voltage.

[0017] Optionally, when the memory cell is in a non-selected state, configuring the pass bias voltage of each of the erase pulses based on the first variable gate bias voltage comprises:

[0018] When the memory cell is in a non-selected state, configuring the selection bias voltage to be 0;

[0019] Within the variable range of the first variable gate bias voltage, the pass bias voltage of each of the erase pulses is configured in an incremental manner as the number of the erase pulses increases based on an initial pass bias voltage.

[0020] Optionally, when the memory cell is in a selected state, configuring a selection bias voltage of each of the erase pulses based on the second variable gate bias voltage comprises:

[0021] When the memory cell is in a selected state, configuring the pass bias voltage to be a fixed value;

[0022] Within the variable range of the second variable gate bias voltage, as the number of the erase pulses increases, the selection bias voltage of each of the erase pulses is configured in an incremental manner.

[0023] Optionally, configuring the variable gate bias voltage corresponding to the odd-numbered gates or the even-numbered gates of the storage unit includes:

[0024] Configuring the odd-numbered gates of the memory cell to be a fixed gate bias voltage, and configuring the even-numbered gates of the memory cell to be a first variable gate bias voltage or a second variable gate bias voltage;

[0025] Alternatively, the even-numbered gates of the memory cell are configured as a fixed gate bias voltage, and the odd-numbered gates of the memory cell are configured as a first variable gate bias voltage or a second variable gate bias voltage.

[0026] Optionally, performing erasure verification on the P / E cycle of the current number stage based on the gate bias voltage corresponding to the current number stage includes:

[0027] Performing voltage verification on the current voltage of the storage unit and the bias voltage of the current erase pulse to determine whether the storage unit has completed the erase verification;

[0028] If the storage unit completes the erasure verification, the erasure verification of the storage unit passes, and the erasure verification of the storage unit is stopped;

[0029] If the storage unit has not completed the erasure verification, the storage unit has failed the erasure verification, and the current voltage of the storage unit is subjected to voltage verification with the pass bias voltage of the next erasure pulse until the erasure verification is completed, or the voltage verification of all the erasure pulses is completed;

[0030] After completing the voltage verification of all erase pulses, if the memory cell still has not completed the erase verification, it is determined that the erase verification has failed, and the erase verification of the memory cell is stopped.

[0031] The present invention also proposes a memory erasure control device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program implements the steps of the above-mentioned memory erasure control method when executed by the processor.

[0032] The present invention further provides a storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above-mentioned memory erasure control method are implemented.

[0033] The technical scheme of the erase control method of the memory of the present invention determines the current number stage of the current Nand flash memory according to the number of P / E cycles of the Nand flash memory; based on the current number stage, a corresponding gate bias voltage is configured for the storage unit, the gate bias voltage has a corresponding relationship with the number stage of the Nand flash memory, and one number stage corresponds to a group of gate bias voltages; based on the gate bias voltage corresponding to the current number stage, the P / E cycle of the current number stage is erased and verified, and the gate bias voltage is dynamically adjusted according to the number of P / E cycles of the Nand Flash memory, so that the voltage condition in the erase process can be more accurately controlled, and the dynamic adjustment of the gate bias voltage can reduce the stress on the storage unit, thereby delaying the deformation and damage of the gate oxide layer and improving the stability of the data memory mechanism. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 A schematic diagram of a flow chart of a memory erase control method provided by an embodiment of the present invention;

[0035] Figure 2 A schematic diagram of the relationship between the number of erase pulses and the number of P / E cycles provided in an embodiment of the present invention;

[0036] Figure 3 A schematic diagram of an erasing process provided by an embodiment of the present invention;

[0037] Figure 4 A schematic diagram of another erasing process provided by an embodiment of the present invention;

[0038] Figure 5 A schematic diagram of another erasing process provided by an embodiment of the present invention;

[0039] Fig. 6A A schematic diagram of a fixed gate bias voltage of a conventional Nand flash memory;

[0040] Figure 6B A schematic diagram of a fixed gate bias voltage of another conventional Nand flash memory;

[0041] Fig. 7A A schematic diagram of a fixed gate bias voltage of another conventional Nand flash memory;

[0042] Figure 7B A schematic diagram of a fixed gate bias voltage of another conventional Nand flash memory;

[0043] Figure 8 A schematic diagram of a variable gate bias voltage provided by an embodiment of the present invention;

[0044] Fig.9A A schematic diagram of another variable gate bias voltage provided by an embodiment of the present invention;

[0045] Fig. 9B A schematic diagram of another variable gate bias voltage provided by an embodiment of the present invention;

[0046] Fig. 10A A schematic diagram of another variable gate bias voltage provided by an embodiment of the present invention;

[0047] Fig. 10B A schematic diagram of another variable gate bias voltage provided by an embodiment of the present invention;

[0048] Fig.11A A schematic diagram of the threshold voltage distribution of the erased cell by biasing and adjusting the erased cell in the prior art;

[0049] Fig. 11B A schematic diagram of the threshold voltage distribution of the existing P / E cycle and erase unit;

[0050] Fig. 12A A schematic diagram of the threshold voltage distribution of the erase unit through bias and adjustment during the erase verification provided by the embodiment of the present invention;

[0051] Fig. 12B A schematic diagram of the threshold voltage distribution of the P / E cycle and the erase unit provided in an embodiment of the present invention;

[0052] Fig.13 A schematic diagram of the structure of an erase control device for a memory provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0053] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0054] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0055] It should also be noted that when an element is referred to as being "fixed on" or "disposed on" another element, it may be directly on the other element or there may be an intermediate element at the same time. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or there may be an intermediate element at the same time.

[0056] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0057] See also Figure 1 , Figure 1 It is a flowchart of a memory erase control method provided by an embodiment of the present invention.

[0058] In this embodiment, the memory is a Nand flash memory, which includes multiple storage units. Nand flash memory can also be called NAND flash memory or Nand flash memory. Nand flash memory is a type of flash memory, which uses a nonlinear macro unit mode internally, providing a cheap and effective solution for the implementation of solid-state large-capacity memory. Nand flash memory is written in a programming manner, and needs to be erased before each programming. After erasing, an erase verification is performed to ensure that the erasure is complete. A programming and erasing action is called a P / E cycle. The erase control method of the memory includes the following steps:

[0059] Step S10, determining the current number stage of the current Nand flash memory according to the number of P / E cycles of the Nand flash memory.

[0060] In this embodiment, the number of P / E cycles of the Nand Flash memory can be monitored and recorded. It is understandable that as the number of P / E cycles increases, the physical properties of the memory will change, so it is necessary to adjust the operating parameters according to these changes. Specifically, as the number of P / E cycles increases, the threshold voltage of the memory cell will also increase, the stress applied to the gate oxide layer of the memory cell will increase, the deformation and damage of the gate oxide layer will proceed rapidly, and the data memory mechanism characteristics of the memory cell will drop sharply.

[0061] If the number of P / E cycles increases, the threshold voltage of the memory cell rises, and the number of erase pulses required for erase verification will also increase. Figure 2 As shown, Figure 2 1 is a schematic diagram of the relationship between the number of erase pulses and the number of P / E cycles provided by an embodiment of the present invention. Figure 2 The relationship between the number of erase pulses and the number of P / E (program / erase) cycles is shown in Figure 1. Figure 2 In the graph, the horizontal axis represents the number of P / E cycles, which ranges from 10K to 80K, while the vertical axis represents the number of erase pulses, which gradually increases from 1 to 8 times, reflecting the number of pulses required for the erase operation.

[0062] It can be seen that as the number of P / E cycles increases, the number of erase pulses also shows a step-by-step upward trend. At the initial number of cycles, only one pulse is needed to complete the erase operation. However, as the number of cycles continues to increase, the number of pulses required for the erase operation also gradually increases, eventually reaching 8 times.

[0063] based on Figure 2 The number stage of the memory can be determined according to different P / E cycle numbers. One number stage corresponds to a group of gate bias voltages, and a group of gate bias voltages can include gate bias voltages corresponding to the number of pulses.

[0064] Step S20, configuring a corresponding gate bias voltage for the storage unit based on the current number stage.

[0065] In the embodiment of the present invention, the gate bias voltage has a corresponding relationship with the number of stages of the Nand flash memory. As the number of P / E cycles of the Nand flash memory increases, the gate bias voltage increases, that is, as the number of stages of the Nand flash memory increases, the gate bias voltage increases.

[0066] When the number of P / E cycles increases, if the threshold voltage Vt of the memory cell Cell rises, in order to quickly perform the Erase action, the gate bias (gate bias voltage) of the memory cell Cell will be increased during Erase Verify to reduce the Erase stress, thereby minimizing the threshold voltage Vt distribution of the memory cell Cell for the erase operation.

[0067] Step S30, performing erase verification on the P / E cycle of the current number stage based on the gate bias voltage corresponding to the current number stage.

[0068] In this embodiment, the gate bias voltage may include a pass bias voltage Pass Bias and a select bias voltage Select Bias, and the pass bias voltage is used for. Pass Bias refers to the bias voltage applied to the gate of a non-target memory cell (a memory cell in a non-selected state, i.e., a memory cell that is not currently undergoing a read, program, or erase operation) in a Nand flash operation. Select Bias refers to the bias voltage applied to the gate of a target memory cell (a memory cell in a selected state, i.e., a memory cell that is currently undergoing a read, program, or erase operation) in a NAND Flash operation.

[0069] Pass Bias is used to ensure that non-target memory cells remain in a stable state during operation to avoid interference with target memory cells. In a read operation, Pass Bias helps ensure that non-target memory cells do not turn on, thereby avoiding interference with the read current. In a P / E cycle, Pass Bias helps prevent non-target memory cells from being accidentally programmed or erased.

[0070] Select Bias is used to control the state of the target memory cell to implement read, program or erase operations. In a read operation, Select Bias is used to activate the target memory cell so that it is turned on and outputs the stored data. In a programming operation, Select Bias is used to control the application of programming voltage to program the target memory cell to the desired storage state. In an erase operation, Select Bias is used to control the application of erase voltage to erase the target memory cell to the initial state.

[0071] In the read and write operations of NAND Flash, Pass Bias and Select Bias exist at the same time. Pass Bias is used to ensure that the memory cells on the non-selected gates are not disturbed, while Select Bias is used to perform P / E cycle operations on the memory cells on the selected gates.

[0072] like Figure 3As shown, Figure 3 FIG. 1 is a schematic diagram of an erasure process provided by an embodiment of the present invention. First, it should be noted that: Figure 3 Applicable storage cells can be storage cells with fewer erase times, that is, storage cells with a smaller current erase time stage. There is no need to increase the gate bias voltage. The erase process of the storage cell includes 8 erase pulses, corresponding to 8 loop erases. After starting to erase, according to the current erase time stage, the corresponding gate bias voltage is configured to 6V for the storage cell, that is, the erase pass bias of each loop erase is set to 6V (loop erase pass bias=6), and a judgment condition is set for each loop erase: whether the erase verification is successful (Erase Verify Pass=?), if so, end the erase, if not, proceed to the next loop erase. When the erase verification of the last loop erase fails, it means that the erase of the storage cell fails, and the storage cell will no longer be erased.

[0073] exist Figure 3 In the process, the non-selected storage cells are erased, including multiple (8) erase pulses. As the number of P / E cycles increases, the number of erase pulses required for the erase operation also increases. For example, at the beginning, only the 1st loop erase (1st loop erase) is needed to complete the erase and pass the erase verification. As the number of P / E cycles increases, the 2nd loop erase (2nd loop erase), 3rd loop erase (3rd loop erase) and so on may be needed later, until the maximum number of erase pulses (8th loop erase (8th loop erase)) is reached. When the maximum erase pulse cannot completely erase, the erase of the storage cell fails, and the storage cell is no longer erased.

[0074] like Figure 4 As shown, Figure 4 It is a schematic diagram of another erasing process provided by an embodiment of the present invention. As the number of P / E cycles increases, the passing bias voltage of the above-mentioned erasing pulse will also increase. Figure 4Applicable storage cells may be storage cells with a large number of erase times, that is, storage cells with a large number of times in the current stage, which need to increase the gate bias voltage. The erase process of the storage cell includes 8 erase pulses, corresponding to 8-ring erase. After starting to erase, according to the current number of stages, the corresponding gate bias voltages configured for the storage cells are 6V, 6V, 6.5V, 6.5V, 7V, 7V, 7.5V, and 7.5V in order of increasing the number of loops, that is, the erase pass bias of each loop is set to 6V (loop erase pass bias = 6), 6V (loop erase pass bias = 6), 6.5V (loop erase pass bias = 6.5), 6.5V (loop erase pass bias = 6.5), 7V (loop erase pass bias = 7), 7V (loop erase pass bias = 7), 7.5V (loop erase pass bias = 7.5), and 7.5V (loop erase pass bias = 7.5). Each loop erase is set with a judgment condition: whether the erase verification is successful (Erase Verify Pass =?). If so, the erase is terminated, and if not, the next loop erase is performed. When the erase verification of the last loop erase is not successful, it means that the erase of the storage cell fails, and the storage cell is no longer erased.

[0075] As the number of P / E cycles increases, the number of erase pulses required for the erase operation also increases. For example, at the beginning, only the 1st loop erase is needed to complete the erase and pass the erase verification. As the number of P / E cycles increases, the 2nd loop erase, 3rd loop erase, etc. may be required later until the maximum number of erase pulses (8th loop erase). When the maximum erase pulse cannot completely erase, the memory cell fails to be erased and will no longer be erased. In the process of increasing the number of erase loops, the erase pass bias is also increasing, making it easier to succeed in judging the pass of the erase verification.

[0076] like Figure 5 As shown, Figure 5 is a schematic diagram of another erasing process provided by an embodiment of the present invention, Figure 5For erasing of non-selected memory cells, applicable memory cells may be memory cells with a large number of erase times, that is, memory cells with a large number of current times. It is necessary to increase the gate bias voltage. The erasing process of the memory cell includes 8 erase pulses, corresponding to 8-ring erasure. After erasing starts, according to the current stage, the corresponding gate bias voltage configured for the storage cell is 0V, 0.1V, 0.2V, 0.3V, 0.4V, 0.5V, 0.6V, and 0.7V in increasing order according to the number of loops, that is, the erase select bias of each loop erasing is set to 0V (loop erase Select bias=0), 0.1V (loop erase Select bias=0.1), 0.2V (loop erase Select bias=0.2), 0.3V (loop erase Select bias=0.3), 0.4V (looperase Select bias=0.4), 0.5V (loop erase Select bias=0.5), 0.6V (loop erase Select bias=0.6), and 0.7V (loop erase Select bias=0.7). A judgment condition is set for each loop erasing: whether the erase verification passes successfully (Erase Verify Pass=?). If so, erase is ended; if not, proceed to the next loop erasing. When the erasure verification of the last erasure cycle fails, it indicates that the erasure of the storage unit has failed, and the storage unit will not be erased any more.

[0077] As the number of P / E cycles increases, the number of erase pulses required for the erase operation also increases. For example, at the beginning, only the 1st loop erase is needed to complete the erase and pass the erase verification. As the number of P / E cycles increases, the 2nd loop erase, 3rd loop erase, etc. may be required later until the maximum number of erase pulses (8th loop erase). When the maximum erase pulse cannot completely erase, the memory cell fails to be erased and will no longer be erased. In the process of increasing the number of erase loops, the erase pass bias is also increasing, making it easier to succeed in judging the pass of the erase verification.

[0078] Considering that the number of erase pulses increases with the number of P / E cycles, Figure 2As the number of stages increases, the bias voltage is controlled to increase at different increasing amplitudes and speeds, thereby completing the configuration of the gate bias voltage of the current number stage, and using the configuration of the gate bias voltage of the current number stage to perform erase verification on the P / E cycle of the current number stage.

[0079] The erase control method of the memory of the present embodiment is implemented. According to the number of P / E cycles of the Nand flash memory, the current number stage of the current Nand flash memory is determined; based on the current number stage, a corresponding gate bias voltage is configured for the storage unit, and the gate bias voltage has a corresponding relationship with the number stage of the Nand flash memory; based on the gate bias voltage corresponding to the current number stage, the P / E cycle of the current number stage is erased and verified, and the gate bias voltage is dynamically adjusted according to the number of P / E cycles of the Nand Flash memory, so that the voltage condition in the erase process can be more accurately controlled, and the dynamic adjustment of the gate bias voltage can reduce the stress on the storage unit, thereby delaying the deformation and damage of the gate oxide layer and improving the stability of the data memory mechanism.

[0080] It is understandable that in the specific implementation of this application, memory data, control data, operation data and other related data are involved. When the embodiments in this application are applied to specific products or technologies, user permission or consent is required, and the collection, use and processing of relevant data, as well as the training and use of various models need to comply with relevant laws, regulations and standards of relevant countries and regions.

[0081] Optionally, before configuring the corresponding gate bias voltage for the storage unit based on the current number stage, a variable gate bias voltage corresponding to the storage unit in different states may be determined; and the corresponding variable gate bias voltage may be configured for the storage unit.

[0082] In the embodiment of the present invention, it should be noted that the conventional Nand flash memory mainly uses a fixed gate bias voltage, such as Fig. 6A , Figure 6B , 7A and Figure 7B As shown, Fig. 6A This is a schematic diagram of a fixed gate bias voltage of a traditional Nand flash memory. Figure 6B This is another conventional Nand flash memory fixed gate bias voltage diagram. Fig. 7A This is another conventional Nand flash memory fixed gate bias voltage diagram. Figure 7B This is another conventional Nand flash memory fixed gate bias voltage schematic.

[0083] exist Fig. 6Aand Figure 6B In the conventional method, fixed gate bias technology is demonstrated. Fig. 6A and Figure 6B In the figure, it can be seen that there are two circuit structure layouts. Fig. 6A In the circuit, the odd gate (Odd WL) and the even gate (Even WL) are configured to different bias states through the control of the GDL (gate dielectric leakage) signal. Among them, "Odd WL (0v)" and "EvenWL (0v)" mean that the gate is grounded, that is, the gate bias voltage is 0v; Figure 6B In the circuit, different bias states of odd and even gates are realized through the control of GDL signal, and "Odd WL (1v)" and "Even WL (1v)" indicate that the gate is not grounded, that is, the gate bias voltage is 1v. Fig. 6A and Figure 6B , using fixed gate bias technology, the gate bias voltage is a fixed value.

[0084] exist Fig. 7A and Figure 7B In the , another traditional method of fixed gate bias technology is shown. "Odd WL (0v)" and "Even WL (0v)" mean that the gate is grounded, that is, the gate bias voltage is 0v; "Odd WL (7v)" and "Even WL (7v)" mean that the gate is not grounded, that is, the gate bias voltage is 7v. Fig. 7A In the example, the fixed gate bias is set to Odd WL (7 V). Figure 7B In the example, the fixed gate bias is set to Even WL (7 V).

[0085] It can be seen that Fig. 6A , Figure 6B , 7A and Figure 7B The gate bias voltage is fixed.

[0086] Please refer to Figure 8 , Fig.9A and Fig. 9B , Figure 8 is a schematic diagram of a variable gate bias voltage provided by an embodiment of the present invention, Fig.9A is another diagram of variable gate bias voltage. Fig. 9B is another diagram of a variable gate bias voltage.

[0087] exist Figure 8 In the embodiment of the present invention, a variable gate bias technology is shown, which can be adjusted according to the number of erase pulses in the erase verification process. Figure 8It can be seen that there is a circuit structure layout in which the odd gate (Odd WL) is configured to different bias states through the control of the GDL (gate dielectric leakage) signal. Among them, "Odd WL (0~1.5v)" means that the gate bias voltage is a variable gate bias voltage, that is, the gate bias voltage is adjusted from 0 to 1.5v.

[0088] exist Figure 8 In the figure, "Odd WL (0 ~ 1.5v)" and "Even WL (0 ~ 1.5v)" indicate that the gate bias voltage is a variable gate bias voltage, that is, the gate bias voltage is adjusted from 0 to 1.5v; specifically, the gate bias voltage can be set to OddWL (0 ~ 1.5v) and Even WL (0 ~ 1.5v), that is, the erase selection bias can be set to Odd WL (0 ~ 1.5v) and EvenWL (0 ~ 1.5v).

[0089] exist Fig.9A In the example, "Odd WL (7v)" indicates that the gate bias voltage is a fixed gate bias voltage, that is, the gate bias voltage is 7v, which is used to set the erase pass bias. The gate bias voltage can be set to Even WL (0~1.5v) to set the erase select bias.

[0090] exist Fig. 9B In the example, "Even WL (7v)" indicates that the gate bias voltage is a fixed gate bias voltage, that is, the gate bias voltage is 7v, which is used to set the erase pass bias. The gate bias voltage can be set to Odd WL (0~1.5v) to set the erase select bias.

[0091] Before configuring the gate bias voltage corresponding to the current P / E cycle number stage for the memory cell, it is necessary to first determine the variable gate bias voltage corresponding to the memory cell in different states and configure these voltages for these memory cells. This can ensure the accuracy and efficiency of the erase operation while reducing the potential damage to the memory cell caused by improper voltage.

[0092] The state of a storage cell mainly refers to whether the storage cell is selected for P / E cycling. A storage cell in a non-selected state does not participate in the current P / E cycling operation, while a storage cell in a selected state is the target of the P / E cycling operation.

[0093] The process of determining the variable gate bias voltage is based on a deep understanding of the physical characteristics of the memory cell. As the number of P / E cycles increases, the gate oxide of the memory cell will be subjected to more and more stress, causing its electrical characteristics to change. In order to compensate for this change, the gate bias voltage needs to be adjusted accordingly. This adjustment is not static, but dynamic, that is, it is adjusted in real time according to the actual condition of the memory cell.

[0094] In the unselected state, the memory cell does not need to be programmed, but needs to be erased, so its gate bias voltage can be set to a relatively low value to reduce unnecessary voltage stress.

[0095] In the selected state, the memory cell needs to withstand the voltage stress caused by the erase or program operation. In order to ensure the smooth operation, the variable gate bias voltage needs to be set higher. This voltage is high enough to overcome the threshold voltage increase caused by the P / E cycle, and also consider the effect of the increase in the well bias (Well Bias) during the erase process on the amount of hole movement.

[0096] Optionally, in the step of determining the variable gate bias voltages corresponding to different types of memory cells, a first variable gate bias voltage corresponding to the memory cell in a non-selected state can be determined, the non-selected state being used to indicate that the memory cell is not selected to perform a P / E cycle; and a second variable gate bias voltage corresponding to the memory cell in a selected state can be determined, the selected state being used to indicate that the memory cell is selected to perform a P / E cycle.

[0097] In this embodiment, the state of the memory cell mainly refers to whether the memory cell is selected for P / E cycling. A memory cell in a non-selected state does not participate in the current P / E cycling operation, while a memory cell in a selected state is the target of the P / E cycling operation.

[0098] For a memory cell in a non-selected state, the corresponding variable gate bias voltage is called a first variable gate bias voltage. The first variable gate bias voltage is targeted at a pass bias voltage, which can be set to 5V to 8V and dynamically adjusted within a voltage range of 5V to 8V to adapt to changes in memory cell characteristics under different P / E cycle times.

[0099] For the memory cell in the selected state, the corresponding variable gate bias voltage is called the second variable gate bias voltage. The first variable gate bias voltage is the selected bias voltage, which can be set to 0v~1.5v. As the number of erase pulses increases, the second variable gate bias voltage will also be adjusted in an incremental manner to compensate for the increase in threshold voltage and the change in well bias during the erase process.

[0100] Optionally, in the step of configuring a corresponding variable gate bias voltage for the memory cell, when the memory cell is in a non-selected state, the pass bias voltage of each erase pulse can be configured based on the first variable gate bias voltage; when the memory cell is in a selected state, the selection bias voltage of each erase pulse can be configured based on the second variable gate bias voltage.

[0101] In this embodiment, the gate bias voltage may include a pass bias voltage Pass Bias and a select bias voltage Select Bias, and the pass bias voltage is used for. Pass Bias refers to the bias voltage applied to the gate of a non-target memory cell (a memory cell in a non-selected state, i.e., a memory cell that is not currently undergoing a read, program, or erase operation) in a Nand flash operation. Select Bias refers to the bias voltage applied to the gate of a target memory cell (a memory cell in a selected state, i.e., a memory cell that is currently undergoing a read, program, or erase operation) in a NAND Flash operation.

[0102] Erasing the non-selected storage cells includes multiple (8) erase pulses. As the number of P / E cycles increases, the number of erase pulses required for the erase operation also increases. As the number of erase pulses increases, the pass bias voltage of the erase pulses also increases.

[0103] Erasing the selected storage cell includes multiple (8) erase pulses. As the number of P / E cycles increases, the number of erase pulses required for the erase operation also increases. As the number of erase pulses increases, the selection bias voltage of the erase pulses increases.

[0104] Optionally, in the step of configuring the pass bias voltage of each erase pulse based on the first variable gate bias voltage when the memory cell is in a non-selected state, the selection bias voltage can be configured to 0 when the memory cell is in a non-selected state; within the variable range of the first variable gate bias voltage, on the basis of the initial pass bias voltage, the pass bias voltage of each erase pulse can be configured in an incremental manner as the number of erase pulses increases.

[0105] In this embodiment, the memory cells in the non-selected state are erased, and the selection bias voltage is configured to be zero.

[0106] Erasing the non-selected storage cells includes multiple erase pulses. At the beginning, only one erase pulse is needed to complete the erasure and pass the erase verification. As the number of P / E cycles increases, 2, 3, ... may be needed until the maximum number of erase pulses is reached. When the maximum erase pulse cannot completely erase, the erasure of this storage cell fails and the storage cell will no longer be erased.

[0107] The initial pass bias can be set to 6 V. As the number of erase pulses increases, the pass bias voltage of the erase pulse will also increase. For example, for erasing a non-selected memory cell, the pass bias voltage of the erase pulse can be configured to be 6 V, 6.5 V, 7 V, 7.5 V, etc. in 5 V to 8 V, and increases with the number of erase pulses.

[0108] Optionally, in the step of configuring the selection bias voltage of each erase pulse based on the second variable gate bias voltage when the memory cell is in the selected state, the bias voltage can be configured as a fixed value when the memory cell is in the selected state; and within the variable range of the second variable gate bias voltage, as the number of erase pulses increases, the selection bias voltage of each erase pulse is configured in an incremental manner.

[0109] In this embodiment, the memory cells in the non-selected state are erased, and the bias voltage is configured to a fixed value, such as 6V.

[0110] Erasing the non-selected storage cells includes multiple erase pulses. At the beginning, only one erase pulse is needed to complete the erasure and pass the erase verification. As the number of P / E cycles increases, 2, 3, etc. may be needed later until the maximum number of erase pulses is reached. When the maximum erase pulse cannot completely erase, the erase of the storage cell fails and the storage cell is no longer erased. As the number of erase pulses increases, the selection bias voltage of the erase pulse will increase. For example, 0v~1.5v is configured as 0v, 0.1v, 0.2v, 0.3v, 0.4v, 0.5v, 0.6v, 0.7v, etc., and increases with the number of erase pulses. The specific increase can be selected according to specific needs.

[0111] Optionally, in the step of configuring a corresponding variable gate bias voltage for the odd-numbered gates or the even-numbered gates of the memory cell, the odd-numbered gates of the memory cell may be configured as a fixed gate bias voltage, and the even-numbered gates of the memory cell may be configured as a first variable gate bias voltage or a second variable gate bias voltage; or, the even-numbered gates of the memory cell may be configured as a fixed gate bias voltage, and the odd-numbered gates of the memory cell may be configured as a first variable gate bias voltage or a second variable gate bias voltage.

[0112] In this embodiment, for the storage unit in the selected state, please refer to Fig.9A and Fig. 9B ,like Fig.9A In the embodiment, the odd-numbered gates of the memory cells are configured as a fixed gate bias voltage, namely Odd WL (7v), and the even-numbered gates of the memory cells are configured as a second variable gate bias voltage (0v~1.5v), namely Even WL (0~1.5v). Or, Fig. 9B In the embodiment, the even-numbered gates of the memory cells are configured as a fixed gate bias voltage, namely Even WL (7v), and the odd-numbered gates of the memory cells are configured as a second variable gate bias voltage (0v~1.5v), namely Odd WL (0~1.5v).

[0113] For non-selected memory cells, refer to Fig. 10A and Fig. 10B ,like Fig. 10A In the example, the even-numbered gates of the memory cells are configured as a fixed gate bias voltage, namely Even WL (7v), and the odd-numbered gates of the memory cells are configured as a first variable gate bias voltage (8v~5v), namely Odd WL (8v~5v). Fig. 10B In the embodiment, the odd-numbered gates of the memory cells are configured as a fixed gate bias voltage, namely Odd WL (7v), and the even-numbered gates of the memory cells are configured as a first variable gate bias voltage (8v~5v), namely Even WL (8v~5v).

[0114] In a possible embodiment, for a storage unit in a selected state, please refer to Figure 8 ,like Figure 8 In the circuit diagram in , the odd-numbered gates of the memory cells are configured to be a second variable gate bias voltage (0v~1.5v), namely Odd WL (0~1.5v).

[0115] Optionally, in an erase verification step for the P / E cycle of the current stage based on the gate bias voltage corresponding to the current stage, the current voltage of the storage cell and the pass bias voltage of the current erase pulse may be voltage-verified to determine whether the storage cell has completed the erase verification; if the storage cell has completed the erase verification, the erase verification of the storage cell passes, and the erase verification of the storage cell is stopped; if the storage cell has not completed the erase verification, the erase verification of the storage cell fails, and the current voltage of the storage cell and the pass bias voltage of the next erase pulse are voltage-verified until the erase verification is completed, or the voltage verification of all erase pulses is completed; after completing the voltage verification of all erase pulses, if the storage cell still has not completed the erase verification, it is determined that the erase verification has failed, and the erase verification of the storage cell is stopped.

[0116] Specifically, erasing the non-selected storage cells includes multiple erase pulses, each erase pulse corresponds to one cycle of erasure. As the number of P / E cycles increases, the number of erase pulses required for the erase operation also increases. For example, only one erase pulse is needed to complete the erasure and pass the erase verification at the beginning. As the number of P / E cycles increases, 2, 3, etc. may be needed later until the maximum number of erase pulses is reached. When the maximum erase pulse cannot completely erase, the erasure of the storage cell fails and the storage cell will no longer be erased. Figure 3 In the example, the pass bias voltage corresponding to the erase pulse is Pass Bias, and the pass bias voltage of the first erase pulse is 6v, that is, 1st Loop Erase Pass Bias = 6v. After the first erase pulse completes the erasure, determine whether the erase verification is passed (Erase verify =?). When Eraseverify = Yes, the erase verification is passed, and when Erase verify = No, the erase verification is not passed. When Eraseverify = Yes, jump to Erase Pass and stop the erase operation. When Erase verify = No, enter the next erase pulse until Erase verify = Yes, then jump to Erase Pass and stop the erase operation, or the last erase pulse, when Erase verify = No, jump to Erase Fail and stop the erase operation.

[0117] A possible embodiment, in Figure 4 In the embodiment, for erasing the memory cells in the non-selected state, the passing bias voltage of the erase pulse is 6V, 6.5V, 7V, and 7.5V, which increases with the number of erase pulses.

[0118] Erasing the selected storage cell includes multiple erase pulses, each erase pulse corresponds to one cycle of erasure. As the number of P / E cycles increases, the number of erase pulses required for the erase operation also increases. For example, only one erase pulse is needed to complete the erasure and pass the erase verification at the beginning. As the number of P / E cycles increases, 2, 3, etc. may be needed later until the maximum number of erase pulses is reached. When the maximum erase pulse cannot completely erase, the erasure of the storage cell fails and the storage cell will no longer be erased. Figure 5In the process, the bias voltage is a fixed value, such as 6v, the select bias voltage corresponding to the erase pulse is Select Bias, and the select bias voltage of the first erase pulse is 0v, that is, 1st Loop Erase Select Bias=0v. After the first erase pulse completes the erasure, determine whether the erase verification is passed (Erase verify=?). When Erase verify=Yes, the erase verification is passed, and when Erase verify=No, the erase verification is not passed. When Erase verify=Yes, jump to Erase Pass and stop the erase operation. When Erase verify=No, enter the next erase pulse until Erase verify=Yes, then jump to Erase Pass and stop the erase operation, or the last erase pulse, when Erase verify=No, jump to Erase Fail and stop the erase operation. The selective bias voltage of the erase pulse will increase gradually, such as 0v, 0.1v, 0.2v, 0.3v, 0.4v, 0.5v, 0.6v, 0.7v, etc., and will increase with the increase of the number of erase pulses. The specific increase amount can be selected according to specific needs.

[0119] When implementing the embodiment of the present invention, when the number of P / E cycles increases, if the threshold voltage Vt of the memory cell Cell rises, in order to quickly perform the Erase action, the gate bias (gate bias voltage) of the memory cell Cell will be increased during Erase Verify to reduce the Erase stress, thereby minimizing the threshold voltage Vt distribution of the memory cell Cell for the erase operation.

[0120] If the number of P / E cycles increases, the threshold voltage Vt of the memory cell rises, and the number of erase pulses ErasePulse increases (e.g. Fig.11A and Fig. 11B As shown), in order to prevent this from happening, after the number of erase pulses is increased, as shown in Figure 2 As shown, and Figure 3 As shown in the flowchart in , the number of erase pulses can be monitored to control the gate bias voltage gatebias in the storage cell Cell during the erase verification, so that the erase verification Erase Verify can be passed more easily. Through the erase control method of the memory provided by this embodiment, if erasing and programming are repeatedly performed, the pressure applied to the storage cell Cell can be reduced, thereby reducing the threshold voltage distribution divergence of the storage cell Cell after erasure, such as Fig. 12A and Fig. 12BAs shown in the figure. Using this Erase method, the threshold voltage Vt distribution of the memory cell can be stabilized even if the number of P / E cycles increases. The data retention characteristics of the memory cell can also be maintained in a large number of P / E cycles.

[0121] The present invention also provides a memory erase control device, see Fig.13 , Fig.13 It is a structural schematic diagram of a memory erase control device in a hardware operating environment involved in an embodiment of the present invention.

[0122] The memory erase control device of the embodiment of the present invention can be a computing device such as a desktop computer, a notebook, a palm computer, and a server. Fig.13 As shown, the erase control device of the memory may include: a processor 1001 (e.g., a CPU), a network interface 1004, a user interface 1003, a memory 1005, and a communication bus 1002. Among them, the communication bus 1002 is used to realize the connection and communication between these components. The user interface 1003 may include a display screen (Display), an input unit, such as a keyboard (Keyboard), and the optional user interface 1003 may also include a standard wired interface and a wireless interface. The network interface 1004 may optionally include a standard wired interface and a wireless interface (such as a WI-FI interface). The memory 1005 may be a high-speed RAM memory, or a stable memory (non-volatile memory), such as a disk memory. The memory 1005 may optionally be a storage device independent of the aforementioned processor 1001.

[0123] Those skilled in the art will understand that Fig.13 The structure of the erase control device of the memory shown in the figure does not constitute a limitation on the erase control device of the memory, and may include more or less components than shown in the figure, or combine certain components, or arrange the components differently.

[0124] like Fig.13 As shown, the memory 1005 as a computer storage medium may include an operating system, a network communication module, a user interface module and a computer program.

[0125] exist Fig.13 In the memory erasure control device shown, the network interface 1004 is mainly used to connect to the background server and communicate data with the background server; the user interface 1003 is mainly used to connect to the client (user end) and communicate data with the client; and the processor 1001 can be used to call the computer program stored in the memory 1005. When the computer program is called and executed by the processor 1001, the steps of the above-mentioned memory erasure control method are implemented.

[0126] Based on the computer program proposed in the aforementioned embodiment, the present invention further proposes a storage medium, which stores the computer program. When the computer program is executed by a controller, the memory erasure control method described in the aforementioned embodiment is implemented.

[0127] Since the memory erasure control device and storage medium of the present invention can implement the steps of the memory erasure control method described above, they at least have all the beneficial effects brought by the technical solution of the memory erasure control method embodiment described above, which will not be described one by one here.

[0128] In the several embodiments provided in the present application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules, which can be electrical, mechanical or other forms.

[0129] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0130] In addition, each functional module in each embodiment of the present invention may be integrated into one processing module, or each module may exist physically separately, or two or more modules may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of software functional modules.

[0131] If the integrated module is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0132] The above description is only a partial or preferred embodiment of the present invention. Neither the text nor the drawings can limit the scope of protection of the present invention. All equivalent structural changes made by using the contents of the present invention specification and drawings under the overall concept of the present invention, or direct / indirect application in other related technical fields are included in the scope of protection of the present invention.

Claims

1. A memory erase control method, characterized in that: The memory is a Nand flash memory, the Nand flash memory includes a plurality of storage units, and the method includes: Determine the current number stage of the Nand flash memory according to the number of P / E cycles of the Nand flash memory; Based on the current number stage, a corresponding gate bias voltage is configured for the storage unit, wherein the gate bias voltage has a corresponding relationship with the number stage of the Nand flash memory, and one number stage corresponds to a group of the gate bias voltages; Based on the gate bias voltage corresponding to the current number stage, the P / E cycle of the current number stage is erased and verified.

2. The memory erasure control method according to claim 1, characterized in that: Before configuring a corresponding gate bias voltage for the storage unit based on the current number stage, the method further includes: Determining variable gate bias voltages corresponding to the storage unit in different states, each state corresponding to a set of the variable gate bias voltages; The memory cells are configured with corresponding variable gate bias voltages, and each memory cell is configured with a corresponding set of variable gate bias voltages.

3. The memory erasure control method according to claim 2, characterized in that: The determining of the variable gate bias voltage corresponding to the storage unit in different states includes: determining a first variable gate bias voltage corresponding to the memory cell in a non-selected state, the non-selected state being used to indicate that the memory cell is not selected to perform a P / E cycle; And, determining a second variable gate bias voltage corresponding to the memory cell in a selected state, wherein the selected state is used to indicate that the memory cell is selected to perform a P / E cycle.

4. The memory erasure control method according to claim 3, characterized in that: The configuring the corresponding variable gate bias voltage for the storage unit includes: When the memory cell is in a non-selected state, configuring a pass bias voltage of each erase pulse based on the first variable gate bias voltage; When the memory cell is in a selected state, a selection bias voltage of each erase pulse is configured based on the second variable gate bias voltage.

5. The memory erasure control method according to claim 4, characterized in that: The method of configuring the pass bias voltage of each of the erase pulses based on the first variable gate bias voltage when the memory cell is in a non-selected state comprises: When the memory cell is in a non-selected state, configuring the selection bias voltage to be 0; Within the variable range of the first variable gate bias voltage, the pass bias voltage of each of the erase pulses is configured in an incremental manner as the number of the erase pulses increases based on an initial pass bias voltage.

6. The memory erasure control method according to claim 4, characterized in that: The method of configuring the selection bias voltage of each of the erase pulses based on the second variable gate bias voltage when the memory cell is in a selected state comprises: When the memory cell is in a selected state, configuring the pass bias voltage to be a fixed value; Within the variable range of the second variable gate bias voltage, as the number of the erase pulses increases, the selection bias voltage of each of the erase pulses is configured in an incremental manner.

7. The memory erasure control method according to claim 3, characterized in that: The configuring the variable gate bias voltage corresponding to the odd-numbered gate or the even-numbered gate of the memory cell comprises: Configuring the odd-numbered gates of the memory cell to be a fixed gate bias voltage, and configuring the even-numbered gates of the memory cell to be a first variable gate bias voltage or a second variable gate bias voltage; Alternatively, the even-numbered gates of the memory cell are configured as a fixed gate bias voltage, and the odd-numbered gates of the memory cell are configured as a first variable gate bias voltage or a second variable gate bias voltage.

8. The memory erasure control method according to any one of claims 3 to 7, characterized in that: The erasing verification of the P / E cycle of the current number stage is performed based on the gate bias voltage corresponding to the current number stage, including: Performing voltage verification on the current voltage of the storage unit and the bias voltage of the current erase pulse to determine whether the storage unit has completed the erase verification; If the storage unit completes the erasure verification, the erasure verification of the storage unit passes, and the erasure verification of the storage unit is stopped; If the storage unit has not completed the erasure verification, the storage unit has failed the erasure verification, and the current voltage of the storage unit is subjected to voltage verification with the pass bias voltage of the next erasure pulse until the erasure verification is completed, or the voltage verification of all the erasure pulses is completed; After completing the voltage verification of all erase pulses, if the memory cell still has not completed the erase verification, it is determined that the erase verification has failed, and the erase verification of the memory cell is stopped.

9. A memory erase control device, characterized in that: The memory erasure control device comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the computer program implements the steps of the memory erasure control method as claimed in any one of claims 1 to 8 when executed by the processor.

10. A storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the memory erasure control method according to any one of claims 1 to 8 are implemented.

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