Method for detecting programming interference of flash memory chip, flash memory chip and storage equipment

Abstract

The invention discloses a method for detecting programming interference of a flash memory chip, the flash memory chip and storage equipment. The method for detecting the programming interference of the flash memory chip comprises the following steps: selecting a target cell unit in a storage block of the flash memory chip; random data are written into the target cell unit; reading threshold voltage data of the target cell unit, and recording the threshold voltage data as target detection data; writing random data in a preset cell unit of the storage block according to a preset rule; reading threshold voltage data of the preset cell unit, and recording the threshold voltage data as reference detection data; and calculating the offset of the reference detection data relative to the target detection data, and when the offset exceeds a preset value, judging that the flash memory chip has serious programming interference. Through the method, the programming interference degree of the flash memory chip can be accurately evaluated, and the reliability of the flash memory chip is guaranteed.

Description

Technical Field

[0001] The present application relates to the field of memory technology, and in particular to a method for detecting programming disturbance of a flash memory chip, a flash memory chip and a storage device. Background Art

[0002] In recent years, NAND flash memory has been widely used in various types of systems from embedded systems to high-end enterprise servers due to its low power consumption, high shock resistance, and non-volatility. Due to the rapid development of computers and electronic mobile devices, the market demand for large-capacity non-volatile memory is increasing. In order to meet this rapidly growing capacity demand, suppliers are constantly improving the manufacturing process of NAND flash memory. On the one hand, the structure of NAND flash memory has been improved to increase the amount of data stored in each unit; on the other hand, by improving the manufacturing process of flash memory chips, their size has been continuously reduced.

[0003] Although the cost of flash memory chips has been reduced due to the increase in storage density, it has also caused some problems, seriously affecting the reliability of NAND flash memory. For example, as the charge stored in each cell increases, the interval between two adjacent threshold voltages becomes smaller and smaller, making the charge of NAND flash memory very unstable. It is easy to interfere with adjacent cells during programming. After interference, the charge of nearby cells will deviate from the actual logical value, causing bit errors. Therefore, it is necessary to detect the programming interference problem of flash memory chips to ensure the reliability of flash memory chips. Summary of the invention

[0004] The purpose of the present application is to provide a method for detecting programming disturbance of a flash memory chip, a flash memory chip and a storage device, so as to accurately evaluate the degree of programming disturbance of the flash memory chip and ensure the reliability of the flash memory chip.

[0005] The present application discloses a method for detecting programming disturbance of a flash memory chip, comprising the steps of:

[0006] Selecting a target cell in a storage block of a flash memory chip;

[0007] Writing random data into the target cell;

[0008] Reading the threshold voltage data of the target cell unit and recording it as target detection data;

[0009] Writing random data into a preset cell unit of the storage block according to a preset rule;

[0010] Reading the threshold voltage data of the preset cell unit and recording it as reference detection data; and

[0011] An offset of the reference detection data relative to the target detection data is calculated, and when the offset exceeds a preset value, it is determined that severe program disturbance exists in the flash memory chip.

[0012] Optionally, in the step of writing random data into a preset cell unit of the storage block according to a preset rule, the cell units in the storage block are programmed in the same programming order, and the preset cell unit is adjacent to the target cell unit.

[0013] Optionally, the storage block includes a plurality of storage layers, the preset cell unit includes a first adjacent cell unit and a second adjacent cell unit, the first adjacent cell unit and the target cell unit are arranged in the same storage layer, and the first adjacent cell unit is a next cell unit of the target cell unit; the second adjacent cell unit and the target cell unit are arranged in different storage layers, the second adjacent cell unit is a cell unit of the next storage layer of the target cell unit, and the position of the second adjacent cell unit in the corresponding storage layer is the same as the position of the target cell unit in the corresponding storage layer; in the step of reading the threshold voltage data of the preset cell unit and recording it as reference detection data, the threshold voltage data of the first adjacent cell unit and the threshold voltage data of the second adjacent cell unit are read respectively and recorded as first reference detection data and second reference detection data;

[0014] In the step of calculating the offset of the reference detection data relative to the target detection data and determining that the flash memory chip has severe programming interference when the offset exceeds a preset value, the offset of the first reference detection data relative to the target detection data and the offset of the second reference detection data relative to the target detection data are calculated respectively; when one of the offset of the first reference detection data relative to the target detection data and the offset of the second reference detection data relative to the target detection data exceeds a preset value, it is determined that the flash memory chip has severe programming interference.

[0015] Optionally, the storage block includes a plurality of storage layers, the preset cell unit includes a first adjacent cell unit, a second adjacent cell unit and a third adjacent cell unit, the first adjacent cell unit and the target cell unit are arranged in the same storage layer, and the first adjacent cell unit is a cell unit next to the target cell unit; the second adjacent cell unit and the target cell unit are arranged in different storage layers, the second adjacent cell unit is a cell unit of a storage layer next to the target cell unit, and a position of the second adjacent cell unit in the corresponding storage layer is the same as a position of the target cell unit in the corresponding storage layer; the third adjacent cell unit and the second adjacent cell unit are arranged in the same storage layer, and the third adjacent cell unit is adjacent to the second adjacent cell unit;

[0016] In the step of reading the threshold voltage data of the preset cell unit and recording it as reference detection data, the threshold voltage data of the first adjacent cell unit, the threshold voltage data of the second adjacent cell unit and the threshold voltage data of the third adjacent cell unit are read respectively and recorded as first reference detection data, second reference detection data and third reference detection data; in the step of calculating the offset of the reference detection data relative to the target detection data and determining that the flash memory chip has severe programming disturbance when the offset exceeds a preset value, the offset of the first reference detection data relative to the target detection data, the offset of the second reference detection data relative to the target detection data and the offset of the third reference detection data relative to the target detection data are calculated respectively; when one of the offset of the first reference detection data relative to the target detection data, the offset of the second reference detection data relative to the target detection data and the offset of the third reference detection data relative to the target detection data exceeds a preset value, it is determined that the flash memory chip has severe programming disturbance.

[0017] Optionally, the first cell unit in the storage block is taken as the target cell unit, and in the step of writing random data in the preset cell unit of the storage block according to a preset rule, the cell units in the storage block are programmed in at least two different programming orders, and the preset cell unit is the same as the target cell unit.

[0018] Optionally, programming is performed in a first programming sequence until the storage block is filled with random data, and the threshold voltage data of the preset cell unit is read and recorded as first-sequence reference detection data; programming is performed in a second programming sequence until the storage block is filled with random data, and the threshold voltage data of the preset cell unit is read and recorded as second-sequence reference detection data; in calculating the offset of the reference detection data relative to the target detection data, when the offset exceeds a preset value, determining that the flash memory chip has severe program interference, this step includes:

[0019] Calculating an offset of the first sequence reference detection data relative to the target detection data, recorded as a first offset;

[0020] Calculating an offset of the second sequential reference detection data relative to the target detection data, recorded as a second offset; and

[0021] When the first offset or the second offset exceeds a preset value, it is determined that severe program disturbance exists in the flash memory chip.

[0022] Optionally, the first programming order is an arrangement order of cell units in the storage block, and the second programming order is an arrangement order of character strings in the storage block.

[0023] Optionally, the method for detecting flash memory chip programming disturbance further includes the steps of:

[0024] Writing specific data into a preset cell unit of the storage block according to a preset rule;

[0025] Reading the threshold voltage data of the preset cell unit and recording it as specific detection data; and

[0026] Calculating an offset of the specific detection data relative to the target detection data, and when the offset exceeds a preset value, determining that the flash memory chip has severe program disturbance;

[0027] The specific data includes data consisting entirely of bit0 or data consisting entirely of bit1.

[0028] The present application also discloses a flash memory chip, and the flash memory chip is detected by using the method for detecting programming disturbance of the flash memory chip as described above.

[0029] The present application also discloses a storage device, which includes the flash memory chip as described above.

[0030] The beneficial effects of the present application are as follows: the present application writes random data to the target cell unit and the preset cell unit in the storage block respectively, then records the target detection data and reference detection data corresponding to the two, and calculates the offset of the target detection data and the reference detection data, and determines whether the flash memory chip has a serious programming disturbance problem according to the size of the offset. The present application can not only accurately detect whether the flash memory chip has a serious programming disturbance problem, but also judge the severity of the programming disturbance according to the difference between the offset and the preset value, thereby greatly ensuring the reliability of the flash memory chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation methods of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0032] Figure 1 This is a flow chart of a method for detecting programming interference of a flash memory chip provided by the present application;

[0033] Figure 2 is an exemplary schematic diagram of a storage block;

[0034] Figure 3 It is a waveform curve corresponding to target detection data;

[0035] Figure 4 It is a waveform curve corresponding to target detection data and reference detection data;

[0036] Figure 5 It is a schematic diagram of a storage block;

[0037] Figure 6 This is a partial flow chart of a method for detecting programming disturbance of a flash memory chip provided in the second embodiment of the present application;

[0038] Figure 7 This is a partial flow chart of a method for detecting programming disturbance of a flash memory chip provided in the third embodiment of the present application;

[0039] Figure 8 is a schematic diagram of a first programming sequence provided in the third embodiment of the present application;

[0040] Fig. 9 It is a schematic diagram of a second programming sequence provided in the third embodiment of the present application. DETAILED DESCRIPTION

[0041] It should be understood that the terms used herein, the specific structures and functional details disclosed are only for describing specific embodiments and are representative, but the present application can be implemented in many alternative forms and should not be construed as being limited to only the embodiments described herein.

[0042] Program disturb is mainly caused by the voltage applied during programming of NAND flash memory cells, which causes the charge state of adjacent cells to change, thus affecting the data stored in them. In order to ensure the integrity of written data, it is particularly important to study how to reduce data errors caused by program disturb.

[0043] Based on this, the present application provides a method for detecting programming disturbance of a flash memory chip to accurately evaluate the degree of programming disturbance of the flash memory chip and ensure the reliability of the flash memory chip.

[0044] like Figure 1 As shown, the method for detecting flash memory chip programming disturbance includes the steps of:

[0045] S1: Select a target cell in a storage block of a flash memory chip;

[0046] S2: writing random data into the target cell;

[0047] S3: reading the threshold voltage data of the target cell unit and recording it as target detection data;

[0048] S4: writing random data into a preset cell unit of the storage block according to a preset rule;

[0049] S5: reading the threshold voltage data of the preset cell unit and recording it as reference detection data;

[0050] S6: Calculate the offset of the reference detection data relative to the target detection data, and when the offset exceeds a preset value, determine that the flash memory chip has severe program disturbance.

[0051] The present application writes random data to the target cell unit and the preset cell unit in the storage block respectively, then records the target detection data and reference detection data corresponding to the two, and calculates the offset of the target detection data and the reference detection data, and determines whether the flash memory chip has a serious programming disturbance problem according to the size of the offset. The present application can not only accurately detect whether the flash memory chip has a serious programming disturbance problem, but also judge the severity of the programming disturbance according to the difference between the offset and the preset value, thereby greatly ensuring the reliability of the flash memory chip.

[0052] The present application provides multiple embodiments for detecting the program disturbance problem of a flash memory chip, as shown below:

[0053] Embodiment 1

[0054] The embodiment of the present application is to test the degree of program disturbance when programming different positions in a flash memory chip. In the flash memory chip, a NAND storage block (Block) is composed of many cell units (Wordline, WL), and the physical structure of the cell units arranged inside the storage block is mainly based on the number of strings (String). Figure 2 is an exemplary schematic diagram of a storage block, such as Figure 2 As shown, the storage block has 6 strings, and the physical arrangement of the cell units is 6 cell units as a layer, which are continuously arranged layer by layer until the maximum capacity of the NAND storage block is reached.

[0055] In the embodiment of the present application, the target cell unit in step S1 can be any cell unit in the flash memory chip, and the random data in step S2 refers to randomly written data, and the number of bit0 and bit1 in the written data is approximately equal. In step S4, the cell units in the storage block are programmed in the same programming order, and the preset cell unit is adjacent to the target cell unit.

[0056] In steps S2 and S5, the target detection data and the reference detection data are presented in the form of waveforms in the coordinate axis, which is specifically composed of two parameters: threshold voltage and charge quantity. The horizontal axis of the coordinate axis represents the threshold voltage, and the vertical axis of the coordinate axis represents the charge quantity. The target detection data and the reference detection data are respectively processed into smoother and continuous curves using Gaussian smoothing in the coordinate axis, and then the deviation between the target detection data and the reference detection data is calculated by analyzing the curve represented by the target detection data and the curve represented by the reference detection data, so as to determine whether there is serious programming interference in the flash memory chip.

[0057] Combination Figure 3 and Figure 4 As shown in the figure, after the target detection data and the reference detection data are processed into smoother continuous curves using Gaussian smoothing in the coordinate axis, the deviation degree of the curve is analyzed. The greater the deviation degree, the more serious the interference. Specifically, the width of a waveform is the distance from the lowest point on the left to the lowest point on the right. If the deviation is greater than 10% of the waveform width, it can be defined as a serious deviation. For example Figure 3 The first waveform is the horizontal coordinate 118-the horizontal coordinate 22=96. If its left or right deviation is greater than 96 / 10=9.6≈10 (rounded off), the preset value is 10% of the deviation of the waveform curve corresponding to the target detection data, that is, the horizontal coordinate deviation in the figure is 10 points; then when the deviation is greater than 10, it can be defined as a serious deviation. Figure 4 As shown, the embodiment of the present application records the waveform curves represented by the target detection data and all the reference detection data in the coordinate axis, and then calculates the deviation of the waveform curves represented by all the reference detection data relative to the waveform curve represented by the target detection data. If there is a deviation that exceeds 10% of the width of the waveform curve represented by the target detection data, it means that the deviation is serious, thereby determining that the flash memory chip has serious programming interference.

[0058] Figure 5 is a schematic diagram of a storage block, such as Figure 5 As shown, as a specific example, the storage block includes multiple storage layers (Layer), the preset cell unit includes a first adjacent cell unit and a second adjacent cell unit, the first adjacent cell unit and the target cell unit are set in the same storage layer, and the first adjacent cell unit is the next cell unit of the target cell unit; the second adjacent cell unit and the target cell unit are set in different storage layers, the second adjacent cell unit is the cell unit of the next storage layer of the target cell unit, and the position of the second adjacent cell unit in the corresponding storage layer is the same as the position of the target cell unit in the corresponding storage layer. As a specific example, Figure 5 As shown, the target cell unit is the cell unit numbered 3, the first adjacent cell unit is the cell unit numbered 4, and the second adjacent cell unit is the cell unit numbered 11.

[0059] Correspondingly, in step S5, the threshold voltage data of the first adjacent cell unit and the threshold voltage data of the second adjacent cell unit are read respectively and recorded as the first reference detection data and the second reference detection data. In step S6, the offset of the first reference detection data relative to the target detection data and the offset of the second reference detection data relative to the target detection data are calculated respectively; when one of the offset of the first reference detection data relative to the target detection data and the offset of the second reference detection data relative to the target detection data exceeds a preset value, it is determined that the flash memory chip has severe program disturbance.

[0060] This embodiment can detect the problem of program disturbance of the flash memory chip by comparing the target cell unit with the adjacent cell unit without changing the programming order, and test the degree of program disturbance influence from different programming positions. The detection method is simple and the detection efficiency is high.

[0061] As another specific example, the storage block also includes multiple storage layers (Layer), and the preset cell unit includes a first adjacent cell unit, a second adjacent cell unit and a third adjacent cell unit, the first adjacent cell unit and the target cell unit are set in the same storage layer, and the first adjacent cell unit is the next cell unit of the target cell unit; the second adjacent cell unit and the target cell unit are set in different storage layers, the second adjacent cell unit is the cell unit of the next storage layer of the target cell unit, and the position of the second adjacent cell unit in the corresponding storage layer is the same as the position of the target cell unit in the corresponding storage layer; the third adjacent cell unit and the second adjacent cell unit are set in the same storage layer, and the third adjacent cell unit is adjacent to the second adjacent cell unit. As a specific example, Figure 5 As shown, the target cell is the cell numbered 3, the first adjacent cell is the cell numbered 4, the second adjacent cell is the cell numbered 11, and the third adjacent cell is the cell numbered 10. Of course, the third adjacent cell may also be the cell numbered 12.

[0062] Correspondingly, in step S5, the threshold voltage data of the first adjacent cell unit, the threshold voltage data of the second adjacent cell unit, and the threshold voltage data of the third adjacent cell unit are read respectively and recorded as the first reference detection data, the second reference detection data, and the third reference detection data. In step S6, the offset of the first reference detection data relative to the target detection data, the offset of the second reference detection data relative to the target detection data, and the offset of the third reference detection data relative to the target detection data are calculated respectively; when one of the offset of the first reference detection data relative to the target detection data, the offset of the second reference detection data relative to the target detection data, and the offset of the third reference detection data relative to the target detection data exceeds a preset value, it is determined that the flash memory chip has severe programming interference.

[0063] In this embodiment, more adjacent cell units are further added to detect the problem of program disturbance of the flash memory chip without changing the programming order, thereby further improving the accuracy of the detection.

[0064] Embodiment 2

[0065] The embodiment of the present application provides a second method for detecting program disturbance of a flash memory chip. The difference from the first embodiment is that the embodiment of the present application further tests the influence degree of program disturbance of programming different data on the basis of the first embodiment. Specifically, Figure 6 As shown, the method for detecting flash memory chip programming disturbance also includes the steps of:

[0066] S7: writing specific data into a preset cell unit of the storage block according to a preset rule;

[0067] S8: reading the threshold voltage data of the preset cell unit and recording it as specific detection data;

[0068] S9: calculating the offset of the specific detection data relative to the target detection data, and when the offset exceeds a preset value, determining that the flash memory chip has severe program disturbance;

[0069] The specific data includes data consisting entirely of bit0 or data consisting entirely of bit1.

[0070] Specifically, in step S7, after recording the target detection data and the reference detection data, the random data written in the preset cell unit is erased, and the specific data is written in the preset cell unit; specifically, the random data can be written only in the target cell unit in the storage block, and the specific data can be written in other cell units in the storage block. In steps S8 and S9, the specific detection data is also recorded in the form of a waveform curve, and then the offset of the specific detection data relative to the target detection data is calculated by the waveform curve offset to determine whether the flash memory chip has serious programming interference when testing programming different data. The specific calculation process refers to the first embodiment and is not repeated here.

[0071] In the embodiment of the present application, step S7 is located after step S6, that is, after testing the degree of programming interference influence of programming different positions, the embodiment of the present application tests the degree of programming interference influence of programming different data. The embodiment of the present application detects whether the flash memory chip is programmed disturbed from two dimensions, so that the detection reliability is higher.

[0072] Embodiment 3

[0073] The embodiment of the present application provides a third method for detecting programming interference of a flash memory chip. Different from the first embodiment, the embodiment of the present application only tests the degree of programming interference influence of different programming orders. The embodiment of the present application takes the first cell unit in the storage block as the target cell unit, and in step S4, the cell units in the storage block are programmed in at least two different programming orders, and the preset cell unit is the same as the target cell unit.

[0074] Specifically, programming is performed in a first programming order until the storage block is filled with random data, and the threshold voltage data of the preset cell unit is read and recorded as first-order reference detection data; programming is performed in a second programming order until the storage block is filled with random data, and the threshold voltage data of the preset cell unit is read and recorded as second-order reference detection data.

[0075] like Figure 7 As shown, in step S6, it includes:

[0076] S61: Calculate an offset of the first sequence reference detection data relative to the target detection data, recorded as a first offset;

[0077] S62: Calculate an offset of the second-order reference detection data relative to the target detection data, recorded as a second offset;

[0078] S63: When the first offset or the second offset exceeds a preset value, it is determined that severe program disturbance exists in the flash memory chip.

[0079] The detection and calculation methods of the offset in the embodiments of the present application are specifically referred to the first embodiment and will not be elaborated here.

[0080] As a specific example, the first programming order is the arrangement order of the cell units in the storage block, such as Figure 8 As shown in the figure, according to the order of the arrows in the figure, programming starts from WL0 (cell numbered 0) inside the storage block, then to WL1, WL2, WL3... until the last WL in the programming WL. Fig. 9 As shown, the second programming order is the arrangement order of the strings in the storage block. According to the order of the arrows in the figure, WL0 / 6 / 12 / 18 is programmed first until the last WL of String0, then WL1 / 7 / 13 / 19 of String1 is programmed until the last WL of String1, and finally the last WL of String5 is programmed.

[0081] The embodiment of the present application can test the degree of program disturbance influence of different programming sequences. Compared with the first embodiment and the second embodiment, the program disturbance problem of the flash memory chip is detected from another dimension, so that the test method has more selectivity.

[0082] Embodiment 4

[0083] The embodiment of the present application provides a fourth method for detecting program disturbance of a flash memory chip. Based on the third embodiment, in addition to testing the degree of program disturbance impact of different programming sequences, the embodiment of the present application also tests the degree of program disturbance impact of programming different data.

[0084] Specifically, after completing the test of the third embodiment, the random data written in the preset cell unit is erased, and the specific data is written in the preset cell unit; specifically, the random data can be written only in the target cell unit in the storage block, and the specific data can be written in other cell units in the storage block. At the same time, according to the method of the third embodiment, two programming orders are used to program the cell units in the storage block, and then the offset is calculated, which will not be described in detail here.

[0085] The embodiment of the present application combines the two dimensions of testing different programming sequences and testing different programming data to test the degree of program disturbance influence of the flash memory chip, thereby further improving the accuracy of the detection.

[0086] Embodiment 5

[0087] The embodiment of the present application provides a fifth method for detecting programming interference of a flash memory chip. The embodiment of the present application combines three dimensions, namely, testing different programming positions, testing different programming orders, and testing different programming data, to test the degree of programming interference impact on the flash memory chip, thereby comprehensively testing the programming interference problem of the flash memory chip, greatly ensuring the accuracy of the programming interference test on the flash memory chip and guaranteeing the integrity of the written data.

[0088] Specifically, the test of Example 4 may be performed after the detection steps of Example 2 are completed; or the test of Example 2 may be performed after the detection steps of Example 4 are completed. The specific order may be selected according to actual conditions and is not limited here.

[0089] The present application also provides a flash memory chip (NAND Flash), and the flash memory chip is detected by using the method for detecting flash memory chip programming disturbance as described above.

[0090] The present application also discloses a storage device, which includes the flash memory chip as described above. The storage device may be a memory card, a solid-state hard disk, etc.

[0091] It should be noted that the limitations on the various steps involved in this solution, without affecting the implementation of the specific solution, are not deemed to limit the order of the steps. The steps written in front can be executed first, or later, or even simultaneously. As long as this solution can be implemented, it should be deemed to fall within the scope of protection of this application.

[0092] The above content is a further detailed description of the present application in combination with specific optional implementation methods, and it cannot be determined that the specific implementation of the present application is limited to these descriptions. For ordinary technicians in the technical field to which the present application belongs, several simple deductions or substitutions can be made without departing from the concept of the present application, which should be deemed to fall within the scope of protection of the present application.

Claims

1. A method for detecting programming disturbance of a flash memory chip, characterized in that: Includes steps: Selecting a target cell in a storage block of a flash memory chip; Writing random data into the target cell; Reading the threshold voltage data of the target cell unit and recording it as target detection data; Writing random data into a preset cell unit of the storage block according to a preset rule; Reading the threshold voltage data of the preset cell unit and recording it as reference detection data; as well as An offset of the reference detection data relative to the target detection data is calculated, and when the offset exceeds a preset value, it is determined that severe program disturbance exists in the flash memory chip.

2. The method for detecting flash memory chip programming disturbance as claimed in claim 1, characterized in that: In the step of writing random data into a preset cell unit of the storage block according to a preset rule, the cell units in the storage block are programmed in the same programming order, and the preset cell unit is adjacent to the target cell unit.

3. The method for detecting flash memory chip programming disturbance as claimed in claim 2, characterized in that: The storage block includes a plurality of storage layers, the preset cell unit includes a first adjacent cell unit and a second adjacent cell unit, the first adjacent cell unit and the target cell unit are arranged in the same storage layer, and the first adjacent cell unit is a next cell unit of the target cell unit; The second adjacent cell unit and the target cell unit are arranged in different storage layers, the second adjacent cell unit is a cell unit of the next storage layer of the target cell unit, and the position of the second adjacent cell unit in the corresponding storage layer is the same as the position of the target cell unit in the corresponding storage layer; In the step of reading the threshold voltage data of the preset cell unit and recording it as reference detection data, the threshold voltage data of the first adjacent cell unit and the threshold voltage data of the second adjacent cell unit are read respectively and recorded as first reference detection data and second reference detection data; In the step of calculating the offset of the reference detection data relative to the target detection data and determining that the flash memory chip has serious programming disturbance when the offset exceeds a preset value, respectively calculating the offset of the first reference detection data relative to the target detection data and the offset of the second reference detection data relative to the target detection data; When one of an offset of the first reference detection data relative to the target detection data and an offset of the second reference detection data relative to the target detection data exceeds a preset value, it is determined that severe program disturbance exists in the flash memory chip.

4. The method for detecting flash memory chip programming disturbance as claimed in claim 2, characterized in that: The storage block includes a plurality of storage layers, the preset cell unit includes a first adjacent cell unit, a second adjacent cell unit and a third adjacent cell unit, the first adjacent cell unit and the target cell unit are arranged in the same storage layer, and the first adjacent cell unit is a next cell unit of the target cell unit; The second adjacent cell unit and the target cell unit are arranged in different storage layers, the second adjacent cell unit is a cell unit of the next storage layer of the target cell unit, and the position of the second adjacent cell unit in the corresponding storage layer is the same as the position of the target cell unit in the corresponding storage layer; The third adjacent cell unit and the second adjacent cell unit are arranged in the same storage layer, and the third adjacent cell unit is adjacent to the second adjacent cell unit; In the step of reading the threshold voltage data of the preset cell unit and recording it as reference detection data, the threshold voltage data of the first adjacent cell unit, the threshold voltage data of the second adjacent cell unit and the threshold voltage data of the third adjacent cell unit are read respectively and recorded as first reference detection data, second reference detection data and third reference detection data; In the step of calculating the offset of the reference detection data relative to the target detection data and determining that the flash memory chip has serious programming interference when the offset exceeds a preset value, respectively calculating the offset of the first reference detection data relative to the target detection data, the offset of the second reference detection data relative to the target detection data, and the offset of the third reference detection data relative to the target detection data; When one of the offset of the first reference detection data relative to the target detection data, the offset of the second reference detection data relative to the target detection data, and the offset of the third reference detection data relative to the target detection data exceeds a preset value, it is determined that the flash memory chip has severe programming interference.

5. The method for detecting program disturbance of a flash memory chip according to claim 1, characterized in that: Taking the first cell unit in the storage block as the target cell unit, in the step of writing random data in the preset cell unit of the storage block according to a preset rule, the cell units in the storage block are programmed in at least two different programming orders, and the preset cell unit is the same as the target cell unit.

6. The method for detecting program disturbance of a flash memory chip according to claim 5, characterized in that: Programming in a first programming order until the storage block is filled with random data, and reading the threshold voltage data of the preset cell unit, and recording it as first-order reference detection data; programming in a second programming order until the storage block is filled with random data, and reading the threshold voltage data of the preset cell unit, and recording it as second-order reference detection data; In the step of calculating the offset of the reference detection data relative to the target detection data and determining that the flash memory chip has severe program disturbance when the offset exceeds a preset value, the method includes: Calculating an offset of the first sequence reference detection data relative to the target detection data, recorded as a first offset; Calculating an offset of the second sequential reference detection data relative to the target detection data, recorded as a second offset; and When the first offset or the second offset exceeds a preset value, it is determined that severe program disturbance exists in the flash memory chip.

7. The method for detecting program disturbance of a flash memory chip according to claim 6, characterized in that: The first programming order is an arrangement order of cell units in the storage block, and the second programming order is an arrangement order of character strings in the storage block.

8. The method for detecting program disturbance of a flash memory chip according to claim 2 or 5, characterized in that: The method for detecting flash memory chip programming disturbance also includes the steps of: Writing specific data into a preset cell unit of the storage block according to a preset rule; Reading the threshold voltage data of the preset cell unit and recording it as specific detection data; and Calculating an offset of the specific detection data relative to the target detection data, and when the offset exceeds a preset value, determining that the flash memory chip has severe program disturbance; The specific data includes data consisting entirely of bit0 or data consisting entirely of bit1.

9. A flash memory chip, characterized in that: The detection is performed using the method for detecting programming disturbance of a flash memory chip as described in any one of claims 1 to 8.

10. A storage device, characterized in that: Comprising the flash memory chip as claimed in claim 9.

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