Methods for detecting programming interference in flash memory chips, flash memory chips and storage devices

Abstract

This application discloses a method for detecting programming interference in a flash memory chip, a flash memory chip, and a storage device. The method for detecting programming interference in a flash memory chip includes the following steps: selecting a target cell in a storage block of the flash memory chip; writing random data into the target cell; reading the threshold voltage data of the target cell and recording it as target detection data; writing random data into a preset cell in the storage block according to a preset rule; reading the threshold voltage data of the preset cell and recording it as reference detection data; calculating the offset of the reference detection data relative to the target detection data; and determining that the flash memory chip has severe programming interference when the offset exceeds a preset value. This method can accurately assess the degree of programming interference in a flash memory chip, ensuring the reliability of the flash memory chip.

Description

Technical Field

[0001] This application relates to the field of memory technology, and in particular to a method for detecting programming interference in a flash memory chip, a flash memory chip, and a storage device. Background Technology

[0002] In recent years, NAND flash memory has been widely used in various types of systems, from embedded systems to high-end enterprise servers, due to its low power consumption, high shock resistance, and non-volatility. Driven by the rapid development of computers and electronic mobile devices, the market demand for high-capacity non-volatile memory is increasing. To meet this rapidly growing capacity demand, suppliers are continuously improving the manufacturing process of NAND flash memory. On the one hand, they are improving the structure of NAND flash memory to increase the amount of data stored in each cell; on the other hand, they are continuously shrinking its size by improving the manufacturing process of flash memory chips.

[0003] While increased storage density has reduced the cost of flash memory chips, it has also created several problems that severely impact the reliability of NAND flash memory. For example, as the charge stored in each cell increases and the interval between two adjacent threshold voltages decreases, the charge in NAND flash memory becomes highly unstable. During programming, this can easily interfere with neighboring cells, causing the charge in nearby cells to deviate from its actual logical value and resulting in bit errors. Therefore, it is necessary to detect programming interference issues in flash memory chips to ensure their reliability. Summary of the Invention

[0004] The purpose of this application is to provide a method, a flash memory chip, and a storage device for detecting programming interference in flash memory chips, so as to accurately assess the degree of programming interference in flash memory chips and ensure the reliability of flash memory chips.

[0005] This application discloses a method for detecting programming interference in flash memory chips, including the following steps:

[0006] Select the target cell within a storage block of the flash memory chip;

[0007] Random data is written into the target cell.

[0008] The threshold voltage data of the target cell is read and recorded as target detection data;

[0009] Random data is written into the preset cell unit of the storage block according to preset rules;

[0010] Read the threshold voltage data of the preset cell unit and record it as reference detection data; and

[0011] The offset of the reference detection data relative to the target detection data is calculated. When the offset exceeds a preset value, it is determined that the flash memory chip has serious programming interference.

[0012] Optionally, in the step of writing random data into the preset cell of the storage block according to preset rules, the cell cells in the storage block are programmed in the same programming order, and the preset cell cells are adjacent to the target cell cells.

[0013] Optionally, the storage block includes multiple storage layers, and the preset cell unit includes a first adjacent cell unit and a second adjacent cell unit. The first adjacent cell unit and the target cell unit are disposed in the same storage layer, and the first adjacent cell unit is the next cell unit of the target cell unit. The second adjacent cell unit and the target cell unit are disposed in different storage layers, and the second adjacent cell unit is the cell unit of the next storage layer of the target cell unit. The position of the second adjacent cell unit in the corresponding storage layer is the same as the position of the target cell unit in the corresponding storage layer. In the step of reading the threshold voltage data of the preset cell unit and recording it as reference detection data, the threshold voltage data of the first adjacent cell unit and the threshold voltage data of the second adjacent cell unit are read respectively and recorded as the first reference detection data and the second reference detection data.

[0014] In the step of calculating the offset of the reference detection data relative to the target detection data, and determining that the flash memory chip has serious programming interference when the offset exceeds a preset value, the offset of the first reference detection data relative to the target detection data and the offset of the second reference detection data relative to the target detection data are calculated respectively; when either the offset of the first reference detection data relative to the target detection data or the offset of the second reference detection data relative to the target detection data exceeds a preset value, it is determined that the flash memory chip has serious programming interference.

[0015] Optionally, the storage block includes multiple storage layers, and the preset cell unit includes a first adjacent cell unit, a second adjacent cell unit, and a third adjacent cell unit. The first adjacent cell unit is disposed in the same storage layer as the target cell unit, and the first adjacent cell unit is the next cell unit after the target cell unit. The second adjacent cell unit is disposed in a different storage layer from the target cell unit, and the second adjacent cell unit is a cell unit in the next storage layer of the target cell unit. The position of the second adjacent cell unit in the corresponding storage layer is the same as the position of the target cell unit in the corresponding storage layer. The third adjacent cell unit is disposed in the same storage layer as the second adjacent cell unit, and the third adjacent cell unit is adjacent to the second adjacent cell unit.

[0016] In the step of reading the threshold voltage data of the preset cell unit and recording it as reference detection data, the threshold voltage data of the first adjacent cell unit, the threshold voltage data of the second adjacent cell unit, and the threshold voltage data of the third adjacent cell unit are read and recorded as first reference detection data, second reference detection data, and third reference detection data, respectively. In the step of calculating the offset of the reference detection data relative to the target detection data, and determining that the flash memory chip has serious programming interference when the offset exceeds a preset value, the offset of the first reference detection data relative to the target detection data, the offset of the second reference detection data relative to the target detection data, and the offset of the third reference detection data relative to the target detection data are calculated, respectively. When any one of the offsets of the first reference detection data relative to the target detection data, the second reference detection data relative to the target detection data, and the third reference detection data relative to the target detection data exceeds a preset value, it is determined that the flash memory chip has serious programming interference.

[0017] Optionally, the first cell in the storage block is taken as the target cell. In the step of writing random data into the preset cell of the storage block according to preset rules, the cell in the storage block is programmed in at least two different programming orders, and the preset cell is the same as the target cell.

[0018] Optionally, programming is performed in a first programming order until the storage block is filled with random data, and the threshold voltage data of the preset cell is read and recorded as the first sequence reference detection data; programming is performed in a second programming order until the storage block is filled with random data, and the threshold voltage data of the preset cell is read and recorded as the second sequence reference detection data; in the step of calculating the offset of the reference detection data relative to the target detection data, and determining that the flash memory chip has serious programming interference when the offset exceeds a preset value, the following steps are included:

[0019] Calculate the offset of the first sequential reference detection data relative to the target detection data, and denot it as the first offset;

[0020] Calculate the offset of the second sequential reference detection data relative to the target detection data, and denote it as the second offset; and

[0021] When the first offset or the second offset exceeds a preset value, it is determined that the flash memory chip has serious programming interference.

[0022] Optionally, the first programming order is the arrangement order of cell units in the storage block, and the second programming order is the arrangement order of strings in the storage block.

[0023] Optionally, the method for detecting programming interference in a flash memory chip further includes the step of:

[0024] Specific data is written into the preset cell unit of the storage block according to preset rules;

[0025] Read the threshold voltage data of the preset cell unit and record it as specific detection data; and

[0026] Calculate the offset of the specific detection data relative to the target detection data. When the offset exceeds a preset value, it is determined that the flash memory chip has serious programming interference.

[0027] The specific data includes data consisting entirely of bit 0 or data consisting entirely of bit 1.

[0028] This application also discloses a flash memory chip, which is detected using the method for detecting flash memory chip programming interference as described above.

[0029] This application also discloses a storage device comprising the flash memory chip described above.

[0030] The beneficial effects of this application are as follows: This application writes random data to the target cell and the preset cell in the storage block, then records the corresponding target detection data and reference detection data, and calculates the offset between the target detection data and the reference detection data. Based on the magnitude of the offset, it determines whether the flash memory chip has a serious programming interference problem. This application can not only accurately detect whether the flash memory chip has a serious programming interference problem, but also determine the severity of the programming interference based on the difference between the offset and the preset value, thereby greatly ensuring the reliability of the flash memory chip. Attached Figure Description

[0031] The accompanying drawings, which form part of the specification, are used to provide a further understanding of the embodiments of this application and illustrate the implementation methods of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any creative effort. In the drawings:

[0032] Figure 1 This is a flowchart of a method for detecting programming interference in a flash memory chip provided in this application;

[0033] Figure 2 This is an exemplary schematic diagram of a storage block;

[0034] Figure 3 It is a waveform curve corresponding to target detection data;

[0035] Figure 4 It is a waveform curve corresponding to target detection data and reference detection data;

[0036] Figure 5 This is a schematic diagram of a storage block;

[0037] Figure 6 This is a partial flowchart of a method for detecting programming interference in a flash memory chip according to the second embodiment of this application;

[0038] Figure 7 This is a partial flowchart of a method for detecting programming interference in a flash memory chip according to the third embodiment of this application;

[0039] Figure 8 This is a schematic diagram of a first programming order provided in the third embodiment of this application;

[0040] Figure 9 This is a schematic diagram of a second programming order provided in the third embodiment of this application. Detailed Implementation

[0041] It should be understood that the terminology, specific structural and functional details used herein are merely for describing particular embodiments and are representative. However, this application may be implemented in many alternative forms and should not be construed as being limited to the embodiments set forth herein.

[0042] Programming interference is primarily caused by changes in the charge state of adjacent cells due to the applied voltage during NAND flash memory cell programming, thus affecting the stored data. To ensure the integrity of written data, researching ways to reduce data errors caused by programming interference is crucial.

[0043] Based on this, this application provides a method for detecting programming interference in flash memory chips, so as to accurately assess the degree of programming interference in flash memory chips and ensure the reliability of flash memory chips.

[0044] like Figure 1 As shown, the method for detecting programming interference in a flash memory chip includes the following steps:

[0045] S1: Select the target cell in a storage block of the flash memory chip;

[0046] S2: Write random data into the target cell unit;

[0047] S3: Read the threshold voltage data of the target cell unit and record it as target detection data;

[0048] S4: Write random data into the preset cell unit of the storage block according to preset rules;

[0049] S5: Read the threshold voltage data of the preset cell unit and record it as reference detection data;

[0050] S6: Calculate the offset of the reference detection data relative to the target detection data. When the offset exceeds a preset value, it is determined that the flash memory chip has serious programming interference.

[0051] This application writes random data to the target cell and a preset cell in the storage block, then records the corresponding target detection data and reference detection data, and calculates the offset between the target detection data and the reference detection data. Based on the magnitude of the offset, it determines whether the flash memory chip has a serious programming interference problem. This application can not only accurately detect whether the flash memory chip has a serious programming interference problem, but also determine the severity of the programming interference based on the difference between the offset and the preset value, thereby greatly ensuring the reliability of the flash memory chip.

[0052] This application provides several embodiments for detecting programming interference problems in flash memory chips, as detailed below:

[0053] Example 1

[0054] This application embodiment tests the degree of programming interference when programming different locations in a flash memory chip. In the flash memory chip, a NAND storage block is composed of many cell units (Wordline, WL), and the physical structure of the cell units arranged inside the storage block is mainly based on the number of strings. Figure 2 This is an exemplary diagram of a storage block, such as... Figure 2 As shown, the storage block has 6 strings, so the physical arrangement of the cell units is 6 cells per layer, and they are arranged layer by layer until the maximum capacity of the NAND storage block is reached.

[0055] In this embodiment, the target cell in step S1 can be any cell in the flash memory chip, and the random data in step S2 refers to randomly written data, in which the number of bits 0 and bits 1 are approximately equal. In step S4, the cell cells in the storage block are programmed in the same programming order, and the preset cell cell is adjacent to the target cell cell.

[0056] In steps S2 and S5, the target detection data and reference detection data are presented as waveforms on a coordinate axis. Specifically, the coordinate axis is composed of two parameters: threshold voltage and charge quantity. The horizontal axis represents the threshold voltage, and the vertical axis represents the charge quantity. The target detection data and reference detection data are smoothed into relatively smooth and continuous curves using Gaussian smoothing. Then, by analyzing the curves represented by the target detection data and the curves represented by the reference detection data, the deviation between the target detection data and the reference detection data is calculated, thereby determining whether there is serious programming interference in the flash memory chip.

[0057] Combination Figure 3 and Figure 4 As shown, after smoothing the target detection data and reference detection data into relatively smooth and continuous curves on the coordinate axes using Gaussian smoothing, the degree of curve offset is analyzed. The greater the offset, the more severe the interference. Specifically, the width of a waveform is defined as the distance from the lowest point on the left to the lowest point on the right. If the offset is greater than 10% of the waveform width, it can be defined as a severe offset. For example... Figure 3 The first waveform is represented by the horizontal coordinate 118 - 22 = 96. If its left or right offset is greater than 96 / 10 = 9.6 ≈ 10 (rounded to the nearest integer), the preset value is 10% of the deviation of the waveform curve corresponding to the target detection data, which is equivalent to a deviation of 10 points on the horizontal coordinate in the graph. Therefore, when the offset is greater than 10, it can be defined as a severe offset. Figure 4 As shown, in this embodiment of the application, the waveform curves represented by the target detection data and all reference detection data are recorded on the coordinate axis. Then, the deviation of the waveform curves represented by all reference detection data relative to the waveform curves represented by the target detection data is calculated. If there is a deviation that exceeds 10% of the width of the waveform curve represented by the target detection data, it indicates that the deviation is serious, thereby determining that the flash memory chip has serious programming interference.

[0058] Figure 5 This is a schematic diagram of a storage block, such as... Figure 5 As shown, as a specific example, the storage block includes multiple storage layers. The preset cell unit includes a first adjacent cell unit and a second adjacent cell unit. The first adjacent cell unit and the target cell unit are located in the same storage layer, and the first adjacent cell unit is the next cell unit after the target cell unit. The second adjacent cell unit and the target cell unit are located in different storage layers. The second adjacent cell unit is a cell unit in the next storage layer of the target cell unit, and the position of the second adjacent cell unit in the corresponding storage layer is the same as the position of the target cell unit in the corresponding storage layer. As a specific example, such as... Figure 5 As shown, the target cell is cell number 3, the first adjacent cell is cell number 4, and the second adjacent cell is cell number 11.

[0059] Correspondingly, in step S5, the threshold voltage data of the first adjacent cell and the threshold voltage data of the second adjacent cell are read and recorded as the first reference detection data and the second reference detection data. In step S6, the offset of the first reference detection data relative to the target detection data and the offset of the second reference detection data relative to the target detection data are calculated respectively; when either the offset of the first reference detection data relative to the target detection data or the offset of the second reference detection data relative to the target detection data exceeds a preset value, it is determined that the flash memory chip has serious programming interference.

[0060] This implementation method can detect flash memory chip programming interference problems by comparing the target cell and adjacent cell without changing the programming order. It tests the degree of programming interference from different programming positions, and the detection method is simple and efficient.

[0061] As another specific example, the storage block also includes multiple storage layers. The preset cell unit includes a first adjacent cell unit, a second adjacent cell unit, and a third adjacent cell unit. The first adjacent cell unit is located in the same storage layer as the target cell unit, and the first adjacent cell unit is the next cell unit after the target cell unit. The second adjacent cell unit is located in a different storage layer from the target cell unit, and the second adjacent cell unit is a cell unit in the next storage layer of the target cell unit. The position of the second adjacent cell unit in the corresponding storage layer is the same as the position of the target cell unit in the corresponding storage layer. The third adjacent cell unit is located in the same storage layer as the second adjacent cell unit, and the third adjacent cell unit is adjacent to the second adjacent cell unit. As a specific example, such as... Figure 5 As shown, the target cell is cell number 3, the first adjacent cell is cell number 4, the second adjacent cell is cell number 11, and the third adjacent cell is cell number 10. Of course, the third adjacent cell could also be cell number 12.

[0062] Correspondingly, in step S5, the threshold voltage data of the first adjacent cell, the second adjacent cell, and the third adjacent cell are read and recorded as first reference detection data, second reference detection data, and third reference detection data, respectively. In step S6, the offsets of the first reference detection data relative to the target detection data, the second reference detection data relative to the target detection data, and the third reference detection data relative to the target detection data are calculated. When any one of these offsets exceeds a preset value, it is determined that the flash memory chip has severe programming interference.

[0063] This implementation adds more adjacent cell units to detect flash memory chip programming interference without changing the programming order, thus further improving the detection accuracy.

[0064] Example 2

[0065] This application provides a second method for detecting programming interference in flash memory chips. Unlike the first method, this application, in addition to the first method, further tests the degree of programming interference affecting different types of programming data. Specifically, for example... Figure 6 As shown, the method for detecting programming interference in a flash memory chip further includes the following steps:

[0066] S7: Write specific data into the preset cell unit of the storage block according to preset rules;

[0067] S8: Read the threshold voltage data of the preset cell unit and record it as specific detection data;

[0068] S9: Calculate the offset of the specific detection data relative to the target detection data. When the offset exceeds a preset value, it is determined that the flash memory chip has serious programming interference.

[0069] The specific data includes data consisting entirely of bit 0 or data consisting entirely of bit 1.

[0070] Specifically, in step S7, after recording the target detection data and reference detection data, the random data written in the preset cell is erased, and specific data is written to the preset cell. Specifically, random data can be written only in the target cell of the storage block, while specific data is written in other cells of the storage block. In steps S8 and S9, the specific detection data is also recorded using a waveform curve. Then, the offset of the specific detection data relative to the target detection data is calculated using the waveform curve offset method to determine whether there is serious programming interference in the flash memory chip when different data is programmed during testing. The specific calculation process is described in the first embodiment and will not be repeated here.

[0071] In this embodiment, step S7 is placed after step S6. That is, after testing the degree of programming interference at different programming locations, this embodiment tests the degree of programming interference for different data. This embodiment detects whether the flash memory chip is experiencing programming interference from two dimensions, making the detection more reliable.

[0072] Example 3

[0073] This application provides a third method for detecting programming interference in flash memory chips. Unlike the first embodiment, this application only tests the degree of programming interference caused by different programming orders. This application uses the first cell in the storage block as the target cell. In step S4, the cell in the storage block is programmed with at least two different programming orders, and the preset cell is the same as the target cell.

[0074] Specifically, programming is performed in a first programming order until the storage block is filled with random data, and the threshold voltage data of the preset cell unit is read and recorded as the first sequence reference detection data; programming is performed in a second programming order until the storage block is filled with random data, and the threshold voltage data of the preset cell unit is read and recorded as the second sequence reference detection data.

[0075] like Figure 7 As shown, step S6 includes:

[0076] S61: Calculate the offset of the first sequential reference detection data relative to the target detection data, and record it as the first offset;

[0077] S62: Calculate the offset of the second sequential reference detection data relative to the target detection data, and record it as the second offset;

[0078] S63: When the first offset or the second offset exceeds a preset value, it is determined that the flash memory chip has serious programming interference.

[0079] The specific methods for detecting and calculating offsets in this application are the same as those in the first embodiment, and will not be repeated here.

[0080] As a specific example, the first programming order is the arrangement order of the cell units in the storage block, such as... Figure 8 As shown in the diagram, programming begins with WL0 (cell number 0) within the memory block, following the order of the arrows, then proceeds to WL1, WL2, WL3... until the last WL within that block is programmed. Figure 9 As shown, the second programming order is the arrangement order of the strings in the storage block. According to the order of the arrows in the figure, WL0 / 6 / 12 / 18 are programmed first until the last WL of String0, then WL1 / 7 / 13 / 19 of String1 until the last WL of String1, and finally the last WL of String5 is programmed.

[0081] The embodiments of this application can test the degree of programming interference caused by different programming sequences. Compared with the first and second embodiments, it detects the programming interference problem of flash memory chips from another dimension, thereby making the testing method more selective.

[0082] Example 4

[0083] This application provides a fourth method for detecting programming interference in flash memory chips. Based on the third embodiment, this application provides an additional method for testing the degree of programming interference caused by different programming sequences, as well as the degree of programming interference caused by programming different data.

[0084] Specifically, after completing the test in Embodiment 3, the random data written in the preset cell is erased, and specific data is written into the preset cell. Specifically, random data can be written only in the target cell of the storage block, while specific data is written in other cell cells of the storage block. Simultaneously, following the method in Embodiment 3, two programming sequences are used to program the cell cells in the storage block, and then offset calculations are performed; these details are not elaborated here.

[0085] This application embodiment combines testing different programming sequences and testing different programming data to test the degree of influence of programming interference on flash memory chips, further improving the accuracy of detection.

[0086] Example 5

[0087] This application provides a fifth method for detecting programming interference in flash memory chips. This application combines three dimensions—testing different programming locations, testing different programming sequences, and testing different programming data—to test the degree of impact of programming interference on flash memory chips. This comprehensive testing of programming interference issues in flash memory chips greatly ensures the accuracy of the testing and guarantees the integrity of the written data.

[0088] Specifically, the test of Example 4 can be performed after the test steps of Example 2 are completed; or the test of Example 2 can be performed after the test steps of Example 4 are completed. The specific order can be selected according to the actual situation and is not limited here.

[0089] This application also provides a flash memory chip (NAND Flash), which is detected using the method for detecting flash memory chip programming interference as described above.

[0090] This application also discloses a storage device, which includes the flash memory chip described above, and the storage device may be a memory card, a solid-state drive, etc.

[0091] It should be noted that the limitations on each step involved in this solution are not considered as limiting the order of steps, provided that they do not affect the implementation of the specific solution. The steps listed first can be executed first, later, or even simultaneously. As long as this solution can be implemented, it should be considered to fall within the scope of protection of this application.

[0092] The above description, in conjunction with specific optional embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. A method for detecting programming interference in a flash memory chip, characterized in that, Including the following steps: Select the target cell within a storage block of the flash memory chip; Random data is written into the target cell. The threshold voltage data of the target cell is read and recorded as target detection data; Random data is written into the preset cell unit of the storage block according to preset rules; Read the threshold voltage data of the preset cell unit and record it as reference detection data; as well as Calculate the offset of the reference detection data relative to the target detection data. When the offset exceeds a preset value, it is determined that the flash memory chip has serious programming interference. Taking the first cell in the storage block as the target cell, in the step of writing random data into the preset cell in the storage block according to preset rules, the cell in the storage block is programmed in at least two different programming orders, and the preset cell is the same as the target cell. Programming is performed in a first programming order until the storage block is filled with random data, and the threshold voltage data of the preset cell is read and recorded as the first sequence reference detection data; programming is performed in a second programming order until the storage block is filled with random data, and the threshold voltage data of the preset cell is read and recorded as the second sequence reference detection data; The step of calculating the offset of the reference detection data relative to the target detection data, and determining that the flash memory chip has serious programming interference when the offset exceeds a preset value, includes: Calculate the offset of the first sequential reference detection data relative to the target detection data, and denot it as the first offset; Calculate the offset of the second sequential reference detection data relative to the target detection data, and denote it as the second offset; and When the first offset or the second offset exceeds a preset value, it is determined that the flash memory chip has serious programming interference.

2. The method for detecting programming interference in a flash memory chip as described in claim 1, characterized in that, The first programming order is the arrangement order of cell units in the storage block, and the second programming order is the arrangement order of strings in the storage block.

3. The method for detecting programming interference in a flash memory chip as described in claim 1, characterized in that, The method for detecting programming interference in flash memory chips further includes the following steps: Specific data is written into the preset cell unit of the storage block according to preset rules; Read the threshold voltage data of the preset cell unit and record it as specific detection data; and Calculate the offset of the specific detection data relative to the target detection data. When the offset exceeds a preset value, it is determined that the flash memory chip has serious programming interference. The specific data includes data consisting entirely of bit 0 or data consisting entirely of bit 1.

4. A flash memory chip, characterized in that, The detection is performed using the method for detecting programming interference in flash memory chips as described in any one of claims 1-3.

5. A storage device, characterized in that, Includes the flash memory chip as described in claim 4.

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