Method and apparatus for data retention in non-volatile two-end memory

Abstract

The invention discloses a method and device for data retention of a nonvolatile two-end memory, and the method comprises the steps: starting a data writing state machine, and writing data into a storage unit in the nonvolatile two-end memory through the data writing state machine; judging whether the storage unit meets an enhancement processing condition or not by adopting a data writing time judgment condition, wherein the data writing time judgment condition is used for judging whether the data writing time of the storage unit exceeds a data writing time threshold value or not; the condition that the storage unit meets the enhancement processing condition includes that the data writing time of the storage unit does not exceed a data writing time threshold value; and in response to the enhancement processing condition being satisfied, performing enhancement processing on the storage unit. By utilizing the scheme provided by the invention, the storage unit meeting the condition that the data writing time does not exceed the data writing time threshold value is subjected to the reinforcement processing, so that the problem of degradation of the data of the memories at the two ends of the nonvolatile memory in the storage process can be improved under the condition of not occupying the data writing time, and the reinforcement processing is performed only when the data writing time is sufficient.

Description

Technical Field

[0001] The present disclosure generally relates to the field of non-volatile two-terminal memory data processing technology. More specifically, the present disclosure relates to a method and apparatus for non-volatile two-terminal memory data retention. Background Art

[0002] Non-volatile two-terminal memories represent a recent innovation in the field of integrated circuit technology. Although many non-volatile two-terminal memory technologies are in the development stage, a number of technical concepts proposed for non-volatile two-terminal memory devices have been demonstrated by the inventors and are in one or more verification stages to disprove related theories or technologies. The inventors believe that a variety of two-terminal memory technologies (e.g., resistive switch memory, magnetoresistive memory, ferroelectric memory, phase change memory, conductive bridge memory) have convincing evidence to show a number of advantages over competing technologies in the semiconductor electronics industry.

[0003] Non-volatile two-terminal memories generally include resistive memory and polarization state memory, both of which are likely to degrade.

[0004] Taking resistive random access memory as an example, in the prior art, data can be written, read and stored through resistive random access memory (RRAM). Resistive random access memory has the advantages of high density, low power consumption and fast read and write speed, so it has broad application prospects in the field of data storage.

[0005] However, the data in the resistive memory may experience degradation during the retention process. Specifically, the data is initially stored in a specific data storage unit (data cell) in the resistive memory in a highly reliable and accurate form. With the passage of time and the influence of external environmental factors (such as temperature fluctuations, electromagnetic interference, material aging, etc.), some data storage units (data cells) begin to experience a degradation process, and the data storage units (data cells) degenerate into resistive memory marginal cells (marginal cells). Resistive memory marginal cells (marginal cells) refer to those storage cells at the edge of the normal working range. Their data retention capabilities begin to weaken and their sensitivity to external interference and internal physical changes increases. Over time, this degradation trend tends to accelerate. When this degradation reaches a certain level, especially when the stability of the data is reduced to below the limit threshold of the sense amplifier (Sense Amplifier), the sense amplifier (Sense Amplifier) ​​may not be able to accurately distinguish between signals and noise, resulting in read errors.

[0006] Similarly, polarization state memory also has this type of degradation phenomenon, which will not be introduced in detail here.

[0007] In view of this, there is an urgent need to provide a solution for maintaining data in a non-volatile two-terminal memory, so as to strengthen the processing of edge units of the non-volatile two-terminal memory and improve the degradation problem of data in the non-volatile two-terminal memory during the storage process. Summary of the invention

[0008] In order to at least solve one or more of the technical problems mentioned above, the present disclosure proposes a solution for data retention in a non-volatile two-terminal memory in multiple aspects.

[0009] According to a first aspect of the present application, a method for maintaining data in a non-volatile two-terminal memory is provided, characterized in that the method comprises: starting a write data state machine, and writing data to a storage unit in the non-volatile two-terminal memory through the write data state machine; using a write data time judgment condition to judge whether the storage unit satisfies an enhanced processing condition, and the write data time judgment condition is used to judge whether the write data time of the storage unit exceeds a write data time threshold; the storage unit satisfies the enhanced processing condition including: the write data time of the storage unit does not exceed the write data time threshold; in response to satisfying the enhanced processing condition, performing enhanced processing on the storage unit.

[0010] According to one embodiment of the present application, a state verification condition is used to determine whether the storage unit satisfies the enhanced processing condition, and the state verification condition is used to determine whether the state of the storage unit is a weak state or a strong state; the storage unit satisfies the enhanced processing condition including: the state of the storage unit is a weak state.

[0011] According to one embodiment of the present application, in the process of determining whether a storage unit satisfies the enhanced processing condition, the write data time determination condition is first executed, and then the status verification condition is executed.

[0012] According to one embodiment of the present application, in the process of determining whether a storage unit satisfies the enhanced processing condition, the state verification condition is first executed, and then the data writing time determination condition is executed.

[0013] According to one embodiment of the present application, after the storage unit is enhanced, the following steps are performed: determining again whether the storage unit after the enhancement processing meets the enhancement processing conditions; in response to meeting the enhancement processing conditions, returning to the step of enhancing the storage unit until the storage unit does not meet the enhancement processing conditions.

[0014] According to one embodiment of the present application, a reinforcement area address is stored in the non-volatile two-terminal memory; a state verification condition is used to determine whether the storage unit meets the reinforcement processing condition, and the state verification condition is used to determine whether the state of the storage unit is a weak state or a strong state; before the state verification condition is used to determine whether the storage unit meets the reinforcement processing condition, the reinforcement area address is loaded in the non-volatile two-terminal memory, and 1 is added to the reinforcement area address stored in the non-volatile two-terminal memory to obtain the address of the storage unit.

[0015] According to one embodiment of the present application, when the state of the storage unit is a strong state, the address of the storage unit is recorded.

[0016] According to one embodiment of the present application, the method further includes: in response to not satisfying the enhanced processing condition, exiting the write data state machine.

[0017] According to one embodiment of the present application, the state verification condition includes: a first storage state verification condition and a second storage state verification condition, the first storage state verification condition is used to verify that the storage unit is a first high state or a second high state, and the second storage state verification condition is used to verify that the storage unit is a first low state or a second low state.

[0018] According to one embodiment of the present application, the non-volatile two-terminal memory is a resistive memory, and the state verification condition includes: a first resistance state verification condition and a second resistance state verification condition, the first resistance state verification condition is used to verify that the storage unit is a first high resistance state or a second high resistance state, and the second resistance state verification condition is used to verify that the storage unit is a first low resistance state or a second low resistance state.

[0019] According to one embodiment of the present application, the first resistance state verification condition includes a first erasure verification condition and a first edge erasure verification condition, and the current of the storage unit in the first high resistance state is greater than the first erasure verification current and less than the first edge erasure verification current.

[0020] According to one embodiment of the present application, the second resistance state verification condition includes a first programming verification condition and a first edge programming verification condition, and the current of the memory cell in the first low resistance state is less than the first programming verification current and greater than the first edge programming verification current.

[0021] According to one embodiment of the present application, performing enhanced processing on the storage cell includes: when the state of the storage cell is a first high-resistance state, performing enhanced erasing operation processing on the storage cell; when the state of the storage cell is a first low-resistance state, performing enhanced programming operation processing on the storage cell.

[0022] According to one embodiment of the present application, the resistive memory includes one or more of an electric resistance switch memory, a phase change memory, a magnetoresistive memory and a conductive bridge memory.

[0023] According to one embodiment of the present application, the non-volatile two-terminal memory is a polarization state memory, and the state verification condition includes: a first polarization state verification condition and a second polarization state verification condition, the first polarization state verification condition is used to verify that the storage unit is a first negative polarization state or a second negative polarization state, and the second polarization state verification condition is used to verify that the storage unit is a first positive polarization state or a second positive polarization state.

[0024] According to one embodiment of the present application, the first polarization state verification condition includes a second erase verification condition and a second edge erase verification condition, and the polarization amount of the storage unit in the first negative polarization state is between the second erase verification polarization amount and the second edge erase verification polarization amount.

[0025] According to one embodiment of the present application, the second polarization state verification condition includes a second programming verification condition and a second edge programming verification condition, and the polarization amount of the storage cell in the first positive polarization state is between the second programming verification polarization amount and the second edge programming verification polarization amount.

[0026] According to one embodiment of the present application, performing enhanced processing on the storage cell includes: when the state of the storage cell is a first negative polarization state, performing enhanced erasing operation processing on the storage cell; when the state of the storage cell is a first positive polarization state, performing enhanced programming operation processing on the storage cell.

[0027] According to one embodiment of the present application, the polarization state memory includes a ferroelectric random access memory (FeRAM).

[0028] According to a second aspect of the present application, there is provided a device for maintaining data in a non-volatile two-terminal memory, characterized in that it comprises: a processor; a memory for storing a computer program; wherein the processor is configured to execute the computer program to implement the method as described above.

[0029] According to a third aspect of the present application, a computer-readable storage medium is provided, on which a computer program is stored, characterized in that when the computer program is executed by one or more processors, the method as described above is implemented.

[0030] According to a fourth aspect of the present application, a data writing system is provided, characterized in that the data writing system comprises: a data writing module, the data writing module is used to start a data writing state machine, and write data to a storage unit in a non-volatile two-terminal memory through the data writing state machine; a judgment module, the judgment module is used to use a write data time judgment condition to judge whether the storage unit meets an enhanced processing condition, the write data time judgment condition is used to judge whether the write data time of the storage unit exceeds a write data time threshold, and the storage unit meets the enhanced processing condition including: the write data time of the storage unit does not exceed the write data time threshold; an enhanced processing module, in response to meeting the enhanced processing condition, the enhanced processing module is used to perform enhanced processing on the storage unit.

[0031] By means of the scheme for maintaining data in a non-volatile two-end memory as provided above, the disclosed embodiment can improve the degradation problem of data in the non-volatile two-end memory during storage without occupying the write data time by performing enhanced processing on the storage unit that satisfies the write data time not exceeding the write data time threshold, so that the enhanced processing is performed only when the write data time is sufficient, thereby avoiding the problem of excessive occupation of system resources or processing delay caused by too long write data time due to enhanced processing, and can make full use of the write data time to improve the efficiency of processing the storage unit. Further, in some embodiments, before using the state verification condition to determine whether the storage unit meets the enhanced processing condition, the enhanced area address is loaded in the non-volatile two-end memory, and the enhanced area address is added by 1, so that the address of the storage unit that currently needs to be judged as strong or weak can be located, so that the storage unit that meets the enhanced processing condition can be enhanced in sequence. Furthermore, in some embodiments, when the state of the storage unit is determined to be a strong state, the address of the storage unit is recorded, and a starting address can be provided for the next enhanced processing operation, so that the storage units that meet the enhanced processing conditions can be enhanced in sequence, ensuring that the strength judgment and enhanced processing operations can traverse the addresses of all storage units in the non-volatile two-end memory, avoiding the need to re-acquire the enhanced area address, thereby significantly improving the efficiency of the enhanced processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] By reading the detailed description below with reference to the accompanying drawings, the above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood. In the accompanying drawings, several embodiments of the present disclosure are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0033] Figure 1a An exemplary flow chart of a resistive memory in the prior art during a data writing process is shown;

[0034] Figure 1b A schematic diagram showing the degradation of a resistive memory is shown;

[0035] Figure 1c A schematic diagram showing degradation of polarization state memory is shown;

[0036] Figure 2 An exemplary flowchart of a method for maintaining data in a resistive memory according to some embodiments of the present application is shown;

[0037] Figure 3 An exemplary flowchart of a process of writing data to a storage unit in a resistive random access memory according to an embodiment of the present application is shown;

[0038] Figure 4 An exemplary flowchart of determining whether a storage unit meets enhanced processing conditions in one embodiment of the present application is shown;

[0039] Figure 5 An exemplary flowchart of determining whether a storage unit meets enhanced processing conditions in another embodiment of the present application is shown;

[0040] Figure 6 An exemplary structural block diagram of a device for maintaining data in a resistive memory according to an embodiment of the present application is shown;

[0041] Figure 7 An exemplary structural block diagram of a data writing system according to an embodiment of the present application is shown;

[0042] Figure 8 An exemplary structural block diagram of the resistive memory electronic operating environment of an embodiment of the present application is shown. DETAILED DESCRIPTION

[0043] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0044] It should be understood that the terms "include" and "comprising" used in the specification and claims of the present disclosure indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections thereof.

[0045] It should also be understood that the terms used in this disclosure are only for the purpose of describing specific embodiments and are not intended to limit the disclosure. As used in this disclosure and claims, the singular forms of "a", "an", and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It should also be further understood that the term "and / or" used in this disclosure and claims refers to any combination of one or more of the associated listed items and all possible combinations, including these combinations.

[0046] As used in this specification and claims, the term "if" may be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" may be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0047] The present invention relates to a nonvolatile two-terminal memory for digital information storage. In some embodiments, the nonvolatile two-terminal memory cell may include a memory based on resistance technology and a memory based on polarity technology, the former may be, for example, a nonvolatile resistance switch two-terminal memory cell, or may be, for example, a polarization state memory. The nonvolatile resistance two-terminal memory cell (also referred to as a resistance switch memory cell or a resistive memory) used herein includes a circuit element having two conductive contacts (also referred to as electrodes or terminals in this article), and having a storage functional area (also referred to as a switching layer) between the two conductive contacts. In the context of resistive memory, the storage functional area of ​​the two-terminal memory device exhibits multiple stable or semi-stable resistance states, each resistance state having a different resistance. Examples of resistance switch two-terminal memory devices may include, but are not limited to, a resistance random access memory currently being developed by the assignee of the present patent application.

[0048] In addition to the resistance characteristic, the corresponding state of the plurality of states can also be formed or activated in response to a suitable electrical signal applied to the two conductive contacts. The suitable electrical signal can be a voltage value, a current value, a pulse width, a pulse height or a current polarity, etc. or a suitable combination thereof.

[0049] Therefore, the non-volatile two-terminal memory of the present application mainly includes resistive random access memory and polarization state memory, wherein the resistive random access memory includes resistive random access memory (RRAM), phase change random access memory (PCRAM), magnetoresistive random access memory (MRAM) and conductive bridging random access memory (CBRAM) or their combination. Polarization state memory includes ferroelectric random access memory (FeRAM).

[0050] The specific implementation of the present disclosure is described in detail below with reference to the accompanying drawings.

[0051] Figure 1a An exemplary flow chart of a resistive memory in the prior art during a data writing process 100 is shown.

[0052] like Figure 1a As shown, in the prior art, during the data writing process of the resistive memory, first, in step S110, the data writing state machine is started. Then, in step S120, the PGM stage or ERS stage is entered, that is, data programming or data erasure is performed. Specifically, data programming is the process of writing "1" to the storage cell of the resistive memory, at which time the storage cell of the resistive memory changes from a high resistance state to a low resistance state. The PGM stage covers the entire process of data programming, including writing data to the designated cell of the resistive memory and performing a verification process to ensure that the data is stored accurately. Data erasure is the process of writing "0" to the storage cell of the resistive memory, at which time the storage cell of the resistive memory changes from a low resistance state to a high resistance state. In the ERS stage, the target data is erased from the storage cell, and the thoroughness of the erasure operation is also verified through a verification process. After completing the above operations, in step S130, the data writing state machine will execute the end process, marking the successful completion of the entire data writing process.

[0053] However, in the process of writing data in the resistive memory shown above, as time goes by and due to the influence of external environmental factors (such as temperature fluctuations, electromagnetic interference, material aging, etc.), some data storage units (data cells) begin to experience a degradation process, and the data storage units (data cells) degenerate into marginal cells of the resistive memory, which gradually reduces the storage performance of the resistive memory. And this degradation phenomenon is continuous and aggravated. When the degree of degradation reaches below the limit threshold of the sense amplifier (Sense Amplifier), it will cause data reading errors, seriously affecting the integrity and reliability of the data.

[0054] Figure 1b A schematic diagram showing degradation of a resistive memory is shown.

[0055] like Figure 1b As shown, the horizontal axis represents the schematic diagram of the current intensity in the storage unit. When "0" is stored in the storage unit of the resistive memory, it is in a high resistance state and the current is low; when "1" is stored in the storage unit of the resistive memory, it is in a low resistance state and the current is high.

[0056] Assume that the lower threshold of the current in the storage unit of the resistive memory is EV, and the upper threshold is PV. Then, when the storage unit of the resistive memory stores "0", ideally its low current value should not be higher than the EV value (in Figure 1b When the RRAM cell stores “1”, the high current value should ideally be no less than the PV value (in Figure 1b is referred to as “strong 1”).

[0057] However, if the RRAM degrades, the following situation may occur: when "0" is stored in the storage cell of the RRAM, the low current value may gradually increase and exceed the lower threshold EV; and when "1" is stored in the storage cell of the RRAM, its high current value may gradually decrease and fall below the upper threshold PV. Therefore, if the RRAM degrades more and more seriously, the low current value and the high current value will gradually move closer to the middle, and when this convergence reaches a certain degree, it will be impossible to distinguish whether "0" or "1" is stored in the storage cell.

[0058] Assume that the lower critical threshold of the current in the storage cell of the resistive memory is MEV, and the upper critical threshold is MPV. Then, when the storage cell of the resistive memory stores "0", if its low current value exceeds the lower critical threshold MEV, the data stored in the storage cell may not be recognized and cannot be recovered; and when the storage cell of the resistive memory stores "1", if its high current value is lower than the upper critical threshold MPV, the data stored in the storage cell may not be recognized and cannot be recovered.

[0059] In order to prevent the memory cells of the resistive memory from further degradation to the point where they cannot be recognized or restored, a low current value between EV and MEV (at Figure 1b It is strengthened when the current value is between MPV and PV (referred to as "weak 0"), so that the low current value is restored to no higher than EV; further, the high current value can be between MPV and PV (in Figure 1b It is strengthened when the high current value is restored to not less than PV.

[0060] It can be seen that the degradation of the resistive memory will cause the low current value and the high current value to be close to each other and become indistinguishable; while strengthening the resistive memory will push the low current value and the high current value away from each other to make the distinction between the two greater.

[0061] Figure 1c A schematic diagram showing degradation of polarization state memory is shown.

[0062] like Figure 1c As shown, the vertical axis represents the schematic diagram of the electric field strength or electrode voltage in the storage unit, and the horizontal axis represents the polarization amount of the storage unit. When "0" is stored in the storage unit, it is negatively (this application Figure 1c When "1" is stored in the memory cell, it is polarized in the forward direction.

[0063] Assume that the negative threshold of negative polarization in the storage unit of the polarization state memory is P0, and the positive threshold is P1. Then, when the storage unit of the polarization state memory stores "0", ideally, its polarization should be on the left side of the P0 point (at Figure 1c In the example, it is called "strong 0", at which point the absolute value of the polarization of the storage unit is greater than the absolute value of the polarization at P0), and when the storage unit of the polarization state memory stores "1", ideally its polarization should be on the right side of point P1 (at Figure 1c It is called "strong 1" in the figure. At this time, the absolute value of the polarization of the storage unit is greater than the absolute value of the polarization at P1).

[0064] However, if the polarization memory degrades, the following situation may occur: when "0" is stored in the storage cell of the polarization memory, its negative polarization may gradually weaken and exceed the P0 point; and when "1" is stored in the storage cell of the polarization memory, its positive polarization may gradually weaken and exceed the P1 point. Therefore, if the degradation of the polarization memory becomes more and more serious, the negative polarization and the positive polarization will gradually move closer to the middle, and when this convergence reaches a certain degree, it will be impossible to distinguish whether the storage cell is "0" or "1".

[0065] Assume that the negative critical threshold of the current in the storage cell of the polarization state memory is MP0, and the positive critical threshold is MP1. Then, when the storage cell of the polarization state memory stores "0", if its negative polarization exceeds the negative critical threshold MP0, the data stored in the storage cell may not be recognized and cannot be recovered; and when the storage cell of the polarization state memory stores "1", if its positive polarization exceeds the positive critical threshold MP1, the data stored in the storage cell may not be recognized and cannot be recovered.

[0066] In order to prevent the storage unit of the polarization state memory from further degrading to the point where it cannot be recognized or restored, the negative polarization amount can be between P0 and MP0 (in Figure 1c It can be strengthened when the positive polarization is between MP1 and P1 (referred to as "weak 0"), so that the negative polarization does not exceed P0; further, it can be strengthened when the positive polarization is between MP1 and P1 (referred to as "weak 0" in Figure 1c It is strengthened when the forward polarization is at a value not exceeding P1 (referred to as "weak 1" in the text).

[0067] It can be seen that the degradation of the polarization state memory will cause the negative polarization amount and the positive polarization amount to be so close to each other that they cannot be distinguished; while strengthening the polarization state memory will push the negative polarization amount and the positive polarization amount away from each other to make the distinction between the two greater.

[0068] In view of this, the disclosed embodiments provide a solution for maintaining data in a non-volatile two-terminal memory, which can improve the problem of data degradation in the non-volatile two-terminal memory during the storage process without occupying the data writing time.

[0069] According to one aspect of the present disclosure, a method for maintaining data in a non-volatile two-terminal memory is provided, comprising: starting a write data state machine, and writing data to a storage unit in the non-volatile two-terminal memory through the write data state machine; using a write data time judgment condition to judge whether the storage unit satisfies an enhanced processing condition, the write data time judgment condition being used to judge whether the write data time of the storage unit exceeds a write data time threshold; the storage unit satisfying the enhanced processing condition comprises: the write data time of the storage unit not exceeding the write data time threshold; in response to satisfying the enhanced processing condition, performing enhanced processing on the storage unit.

[0070] The following will first take the resistive random access memory as an example for introduction.

[0071] According to an embodiment of the present disclosure, the disclosed embodiment provides a solution for maintaining data in a resistive random access memory, which can improve the degradation problem of data in the resistive random access memory during the storage process without occupying the data writing time.

[0072] Figure 2An exemplary flowchart of a method 200 for maintaining data in a resistive memory according to an embodiment of the present application is shown.

[0073] like Figure 2 As shown, in step S210, a data write state machine is started, and data is written to a storage unit in the resistive random access memory through the data write state machine.

[0074] In one embodiment of the present application, in the process of writing data to a storage unit in a resistive random access memory through a data write state machine, steps S310 to S330 are performed in sequence.

[0075] Figure 3 An exemplary flowchart of a process of writing data to a storage unit in a resistive random access memory according to an embodiment of the present application is shown.

[0076] like Figure 3 As shown, in step S310, a write data operation is performed. In step S320, it is determined whether the storage unit meets the write data completion condition through the status verification condition. In response to meeting the write data completion condition, in step S330, the write data operation is terminated. In response to not meeting the write data completion condition, the process returns to step S310 and continues to perform the write data operation until the write data completion condition is met.

[0077] In an embodiment of the present application, the state of the memory cell includes a high resistance state (0) and a low resistance state (1). Specifically, the high resistance state (0) includes a first high resistance state (weak 0) and a second high resistance state (strong 0), and the low resistance state (1) includes a first low resistance state (weak 1) and a second low resistance state (strong 1). The current of the memory cell in the first high resistance state is greater than the erase verification current and less than the edge erase verification current, and the current of the memory cell in the second high resistance state is less than the erase verification current. The current of the memory cell in the first low resistance state is less than the programming verification current and greater than the edge programming verification current, and the current of the memory cell in the second low resistance state is greater than the programming verification current.

[0078] Specifically, the erase verification current is the current threshold that the memory cell should reach after performing a data erase operation on the memory cell. The edge erase verification current is the current threshold that the memory cell reaches when over-erasing data is performed on the memory cell. The programming verification current is the current threshold that the memory cell should reach after performing a data programming operation on the memory cell. The edge programming verification current is the current threshold that the memory cell reaches when over-programming data is performed on the memory cell. In the embodiments of the present application, the values ​​of the erase verification current, the edge erase verification current, the programming verification current, and the edge programming verification current can be set according to actual needs and application scenarios, and are not limited here.

[0079] Specifically, the state verification condition is used to determine whether the state of the storage unit is a strong state or a weak state. The state verification condition includes: a first storage state verification condition and a second storage state verification condition, wherein the first storage state verification condition is used to verify that the storage unit is a first high state or a second high state, and the second storage state verification condition is used to verify that the storage unit is a first low state or a second low state.

[0080] Specifically, taking a resistive random access memory as an example, the state of a storage unit that meets the data writing completion condition is a strong state, and the strong state includes a second high resistance state and a second low resistance state.

[0081] When the data write operation is data erasure, the charge of the storage cell is usually reduced. After performing a data erase operation on a storage cell, if the current of the storage cell is less than the erase verification current, it means that the charge state of the storage cell is close to the logic 0 level. At this time, the storage cell changes from the second low resistance state to the second high resistance state, so that the state of the storage cell is the second high resistance state.

[0082] When the write data operation is data programming, the charge of the storage cell is usually increased. After performing a data programming operation on a storage cell, if the current of the storage cell is greater than the programming verification current, it means that the charge state of the storage cell is high enough to be reliably identified as logic 1. At this time, the storage cell changes from the second high resistance state to the second low resistance state, so that the state of the storage cell is the second low resistance state.

[0083] Specifically, the state verification condition includes a programming verification condition and an erasure verification condition. The erasure verification condition may be whether the current of the storage cell is less than the erasure verification current, and the programming verification condition may be whether the current of the storage cell is greater than the programming verification current. When the write data operation is data erasure, the erase verification condition is used to verify whether the state of the storage cell is the second high impedance state. When the write data operation is data programming, the program verification condition is used to verify whether the state of the storage cell is the second low impedance state.

[0084] In an embodiment of the present application, instructions provided to a write data state machine can be implemented according to the control logic configuration, so that the write data state machine can manage the write data process of the resistive random access memory and other functions related to the resistive random access memory. Specifically, the write data process includes data programming, data erasure, data enhancement, and recording enhancement area addresses, and during data programming and data erasure, verification conditions can be used to verify the state of each storage unit, and storage units in a weak state can also be enhanced. Operation processing. Other functions related to resistive random access memory include data reading, data input, data output, etc. Further, the write data state machine can send and receive confirmation and negative confirmation of successful reception or execution of various commands, and can also decode and implement commands related to the write data process.

[0085] In an embodiment of the present application, the aforementioned resistive random access memory stores a reinforcement area address, and the reinforcement area address is stored as user data in a specific area of ​​the resistive random access memory. Specifically, the specific area may be an area for recording user information. The reinforcement area address is the address of the latest recorded storage unit in a strong state, and when the address of the storage unit in a strong state has not been recorded, the reinforcement area address is 0. Specifically, the storage unit in a strong state includes a storage unit that does not need to be reinforced after judgment and a storage unit in a weak state whose state is a strong state after reinforcement processing.

[0086] By storing the enhanced region address as user data in a specific region of the resistive random access memory, it is allowed to load the enhanced region address in the resistive random access memory and add 1 to the enhanced region address before using the state verification condition to determine whether the storage unit meets the enhanced processing condition during the data writing process, thereby directly locating the address of the storage unit that currently needs to be judged as strong or weak. For example, when the enhanced region address stored in the resistive random access memory is 15, before using the state verification condition to determine whether the storage unit meets the enhanced processing condition, the enhanced region address 15 is loaded, and then the enhanced region address 15 is added by 1, and the obtained enhanced region address 16 is the address of the storage unit that currently needs to be judged as strong or weak.

[0087] By directly locating the address of the storage unit that currently needs to be judged for strength, re-acquisition of the address of the enhanced area is avoided, thereby significantly improving the efficiency of the enhanced processing.

[0088] Next, in step S220, it is determined whether the storage unit meets the enhanced processing condition.

[0089] In an embodiment of the present application, a write data time judgment condition and a state verification condition are used to judge whether a storage unit satisfies an enhanced processing condition. Specifically, the write data time judgment condition is used to judge whether the write data time of the storage unit exceeds the write data time threshold, and the state verification condition is used to judge whether the state of the storage unit is a weak state or a strong state. The storage unit satisfies the enhanced processing condition including: the write data time of the storage unit does not exceed the write data time threshold and the state of the storage unit is a weak state. Thus, even though the state of the storage unit is a weak state, the storage unit cannot be subjected to enhanced processing when the write data time exceeds the write data time threshold. This arrangement allows enhanced processing to be performed only when there is sufficient write data time, thereby avoiding the problem of excessive occupation of system resources or processing delays caused by excessive write data time due to enhanced processing, and being able to make full use of the write data time to improve the efficiency of processing the storage unit.

[0090] Specifically, the aforementioned data writing time threshold can be set according to actual needs and application scenarios and is not limited here.

[0091] In one embodiment of the present application, in the process of determining whether a storage unit meets the enhanced processing condition, the write data time determination condition is first executed, and then the state verification condition is executed. That is, the write data time determination condition is first used to determine whether the write data time exceeds the write data time threshold, and then the state verification condition is used to determine whether the state of the storage unit is a weak state or a strong state. Specifically, steps S410 to S460 are executed in sequence.

[0092] Figure 4 An exemplary flowchart for determining whether a storage unit meets enhanced processing conditions in one embodiment of the present application is shown.

[0093] like Figure 4 As shown, in step S410, the write data time judgment condition is used to judge whether the write data time exceeds the write data time threshold. In response to the write data time exceeding the write data time threshold, in step S420, it is judged that the storage unit does not meet the enhanced processing condition, and the write data state machine is exited. In response to the write data time not exceeding the write data time threshold, in step S430, the enhanced area address is loaded in the resistive memory, and the enhanced area address stored in the resistive memory is added by 1 to obtain the address of the storage unit that currently needs to be judged strong or weak. In step S440, the state verification condition is used to judge whether the state of the storage unit is weak or strong. In response to the state of the storage unit being strong, in step S450, it is judged that the storage unit does not meet the enhanced processing condition, and the address of the storage unit is recorded. That is, when it is judged that the storage unit does not meet the enhanced processing condition, the address after the enhanced area address stored in the resistive memory is added by 1 is recorded. In response to the state of the storage unit being weak, in step S460, it is judged that the storage unit meets the enhanced processing condition.

[0094] Therefore, in this embodiment, it is first determined whether the data write time exceeds the data write time threshold. When the data write time exceeds the data write time threshold, it is directly determined that the storage unit does not meet the enhanced processing conditions, thereby eliminating the need to locate the address of the storage unit that currently needs to be judged strong or weak and to judge the status of the storage unit, thereby saving judgment time.

[0095] In another embodiment of the present application, in the process of determining whether the storage unit meets the enhanced processing condition, the state verification condition is first executed, and then the write data time determination condition is executed. That is, the state verification condition is first used to determine whether the state of the storage unit is a weak state or a strong state, and then the write data time determination condition is used to determine whether the write data time exceeds the write data time threshold. Specifically, steps S510 to S560 are executed in sequence.

[0096] Figure 5 An exemplary flowchart for determining whether a storage unit meets enhanced processing conditions in another embodiment of the present application is shown.

[0097] like Figure 5 As shown, in step S510, the enhanced region address is loaded in the resistive memory, and the enhanced region address stored in the resistive memory is added by 1 to obtain the address of the storage unit that currently needs to be judged strong or weak. Next, in step S520, the state verification condition is used to determine whether the state of the storage unit is weak or strong. In response to the state of the storage unit being strong, in step S530, it is determined that the storage unit does not meet the enhanced processing condition, and the address of the storage unit is recorded. That is, when it is determined that the storage unit does not meet the enhanced processing condition, the address after the enhanced region address stored in the resistive memory is added by 1 is recorded. In response to the state of the storage unit being weak, in step S540, the write data time judgment condition is used to determine whether the write data time exceeds the write data time threshold. In response to the write data time exceeding the write data time threshold, it is determined that the storage unit does not meet the enhanced processing condition, and in step S550, the write data state machine is exited. In response to the write data time not exceeding the write data time threshold, in step S560, it is determined that the storage unit meets the enhanced processing condition.

[0098] Therefore, in this embodiment, the enhanced region address is loaded into the resistive random access memory, and the enhanced region address stored in the resistive random access memory is added by 1 to obtain the address of the storage unit that currently needs to be judged as strong or weak. First, it is judged whether the state of the storage unit is weak or strong. If the state of the storage unit is strong, it is directly judged that the storage unit does not meet the enhanced processing conditions. Therefore, it is no longer necessary to judge whether the data writing time exceeds the data writing time threshold, which saves judgment time.

[0099] In the above two embodiments, in the process of judging whether the storage unit meets the enhanced processing condition, whether the write data time judgment condition is executed first and then the state verification condition is executed, or the state verification condition is executed first and then the write data time judgment condition is executed. Before the state verification condition is used to judge whether the storage unit meets the enhanced processing condition, the enhanced area address is loaded in the resistive random access memory, and the enhanced area address stored in the resistive random access memory is added by 1, so that the address of the storage unit that currently needs to be judged as strong or weak can be directly located. Therefore, when it is subsequently determined that the state of the storage unit is a strong state, the address of the storage unit is recorded to provide a starting address for the next enhanced processing operation.

[0100] In the above two embodiments, in the process of judging whether the storage unit meets the enhanced processing condition, when the data writing time exceeds the data writing time threshold, it is determined that the enhanced processing condition is not met, and the data writing state machine is exited. As a result, enhanced processing is performed only when there is sufficient time for writing data, thereby avoiding the problem of excessive occupation of system resources or processing delay caused by excessive data writing time due to enhanced processing, and making full use of the data writing time to improve the efficiency of storage unit processing.

[0101] In the above two embodiments, in the process of judging whether the storage unit meets the enhanced processing conditions, when the state of the storage unit is in a strong state, it is judged that the enhanced processing conditions are not met, and the address of the storage unit is recorded. When it is judged that the state of the storage unit is in a strong state, the storage unit does not need to be enhanced, that is, the state of the storage unit is already in a strong state. By recording the address of the storage unit, a starting address can be provided for the next enhanced processing operation, ensuring that the strength judgment and processing operations can traverse the addresses of all storage units in the resistive random access memory, avoiding the need to re-acquire the enhanced area address, thereby significantly improving the efficiency of the enhanced processing.

[0102] Specifically, in the above two embodiments, in the process of recording the address of the storage unit, that is, recording the address after adding 1 to the enhanced area address stored in the resistive memory, the enhanced area address originally stored in the resistive memory is erased, and then the address after adding 1 to the enhanced area address stored in the resistive memory is recorded in the specific area of ​​the resistive memory where the enhanced area address originally stored is located. In other words, the enhanced area address stored in the specific area of ​​the resistive memory is updated according to the address of the storage unit whose state is the strong state as recently determined. For example, when the enhanced area address stored in the resistive memory is 15, 1 is added to the enhanced area address 15 to obtain address 16. When it is determined that the state of the storage unit is the strong state, the enhanced area address 15 stored in the specific area of ​​the resistive memory is erased, and the address 16 is stored in the specific area of ​​the resistive memory.

[0103] By updating the enhanced region address stored in the specific region of the resistive random access memory, there is only one enhanced region address stored in the specific region of the resistive random access memory, and the enhanced region address can be loaded at a faster speed during the subsequent enhancement process.

[0104] In an embodiment of the present application, the aforementioned weak state includes a first high resistance state and a first low resistance state.

[0105] When the data writing operation is data erasure, the charge of the storage cell is usually reduced. After performing a data erasure operation on a certain storage cell, if the current of the storage cell is greater than the erase verification current and less than the edge erase verification current, it means that the charge state of the storage cell is not low enough and the state of the storage cell is unstable. At this time, the storage cell cannot be completely transformed from the second low resistance state to the second high resistance state, so the state of the storage cell can only be identified as the first high resistance state.

[0106] When the data writing operation is data programming, the charge of the memory cell is usually increased. After performing the data programming operation on a certain memory cell, if the current of the memory cell is less than the programming verification current and greater than the marginal programming verification current, it means that the charge state of the memory cell is not high enough and the state of the memory cell is unstable. At this time, the memory cell cannot be completely transformed from the second high resistance state to the second low resistance state, so the state of the memory cell can only be identified as the first low resistance state.

[0107] In an embodiment of the present application, the state verification condition includes: a first resistance state verification condition and a second resistance state verification condition. The first resistance state verification condition is used to verify that the storage cell is in the first high resistance state or the second high resistance state. The first resistance state verification condition includes a first erase verification condition and a first edge erase verification condition. The first erase verification condition may be whether the current of the storage cell is less than the erase verification current. The first edge erase verification condition may be whether the current of the storage cell is less than the first edge erase verification current. The second resistance state verification condition is used to verify that the storage cell is in the first low resistance state or the second low resistance state. The second resistance state verification condition includes a first programming verification condition and a first edge programming verification condition. The programming verification condition may be whether the current of the storage cell is greater than the first programming verification current. The first edge programming verification condition may be whether the current of the storage cell is greater than the first edge programming verification current.

[0108] When the write data operation is data erasure, the state of the storage unit is verified to be the first high resistance state or the second high resistance state through the first resistance state verification condition. Specifically, the state of the storage unit is verified to be the first high resistance state or the second high resistance state through the first erasure verification condition and the first edge erasure verification condition. Since after the data erasure operation, when the state of the storage unit is unstable, the storage unit is read by the read operation, and the state of the unstable storage unit is determined to be normal. Therefore, by verifying that the state of each storage unit is the first high resistance state or the second high resistance state through the first erasure verification condition and the first edge erasure verification condition, the storage unit whose state is unstable after the data erasure operation can be accurately determined, thereby avoiding misjudgment when reading the storage unit whose state is unstable after the data erasure operation.

[0109] When the write data operation is data programming, the state of the storage cell is verified to be the first low resistance state or the second low resistance state through the second resistance state verification condition. Specifically, the state of the storage cell is verified to be the first low resistance state or the second low resistance state through the first programming verification condition and the edge programming verification condition. Since after the data programming operation, when the state of the storage cell is unstable, when the storage cell is read by the read operation, the state of the unstable storage cell is determined to be normal. Therefore, through the first programming verification condition and the first edge programming verification condition, the state of each storage cell is the first low resistance state or the second low resistance state, it is possible to accurately determine the storage cell whose state is unstable after the data programming operation, thereby avoiding misjudgment when reading the storage cell whose state is unstable after the data programming operation.

[0110] In response to not meeting the enhanced processing condition, step S230 is executed to not perform enhanced processing on the storage unit. Specifically, as described in the above two embodiments, when it is determined that the data writing time exceeds the data writing time threshold, the data writing state machine is exited. When it is determined that the state of the storage unit is a strong state, the address of the storage unit is recorded.

[0111] In response to the enhanced processing condition being met, in step S240, the storage unit is subjected to enhanced processing.

[0112] In the embodiment of the present application, during the process of strengthening the processing of the storage unit, when the state of the storage unit is the first high impedance state, the storage unit is subjected to the strengthened erasing operation processing. Specifically, the strengthened erasing operation processing refers to performing a data erasing operation again on the storage unit in the first high impedance state after the data erasing operation, so that the state of the storage unit in the first high impedance state changes to the second high impedance state.

[0113] Specifically, during the enhanced erase operation process, the voltage of the bit line (BL), the voltage of the word line (WL), the voltage of the source line (SL), and the pulse time can be set and adjusted according to actual needs.

[0114] In the embodiment of the present application, during the process of strengthening the memory cell, when the state of the memory cell is the first low resistance state, the memory cell is subjected to the strengthening programming operation. Specifically, the strengthening programming operation means that after the data programming operation, the memory cell in the state of the first low resistance state is subjected to the data programming operation again, so that the state of the memory cell in the state of the first low resistance state is changed to the second low resistance state.

[0115] Specifically, during the enhanced programming operation, the voltage of the bit line (BL), the voltage of the word line (WL), the voltage of the source line (SL), and the pulse time can be set and adjusted according to actual needs.

[0116] By changing the state of a memory cell in a first high resistance state to a second high resistance state, or changing the state of a memory cell in a first low resistance state to a second low resistance state, the problem of data degradation in the resistive memory during storage can be improved.

[0117] In an embodiment of the present application, after the aforementioned storage unit is enhanced, the write data time judgment condition and the status verification condition are used to again judge whether the storage unit after the enhanced processing meets the enhanced processing conditions.

[0118] Specifically, the process of determining again whether the storage unit after the enhanced processing meets the enhanced processing condition is the same as the determination process adopted in the aforementioned step S220, and will not be repeated here.

[0119] By judging again whether the storage unit after the enhancement processing meets the enhancement processing conditions, it is possible to judge whether the enhancement processing step is effective, thereby avoiding judging the storage unit in the weak state as the strong state when the enhancement processing step is invalid.

[0120] In an embodiment of the present application, in response to the storage unit satisfying the enhanced processing condition after the enhanced processing, the step of performing enhanced processing on the storage unit is returned, that is, it returns to step S240 until the enhanced processing condition is no longer satisfied.

[0121] Specifically, when it is determined that the conditions for enhanced processing are met, that is, when it is determined that the enhanced processing is invalid, return to the step of performing enhanced processing on the storage unit and continue to perform enhanced processing on the storage unit, thereby ensuring that the state of the storage unit after the enhanced processing is indeed a strong state or the data writing time exceeds the data writing time threshold, and then the enhanced processing is terminated.

[0122] In an embodiment of the present application, when it is determined that the storage unit after the enhanced processing still does not meet the enhanced processing conditions, the storage unit is not subjected to enhanced processing. Under the condition that the data writing time exceeds the data writing time threshold, the data writing state machine is exited. Under the condition that the state of the storage unit after the enhanced processing is determined to be a strong state, the address of the storage unit is recorded. Thus, under the condition that the data writing time exceeds the data writing time threshold, the data writing state machine is exited, and the address of the storage unit is not recorded. Only when the state of the storage unit after the enhanced processing is a strong state, the enhanced area address corresponding to the storage unit is recorded, providing a starting address for the next enhanced processing operation, thereby ensuring that the state of the storage unit corresponding to the recorded enhanced area address is a strong state.

[0123] In summary, with the help of the scheme for maintaining data in a resistive random access memory as provided above, the disclosed embodiment can improve the degradation problem of data in the resistive random access memory during storage without occupying the write data time by performing enhanced processing on the storage unit that satisfies the write data time not exceeding the write data time threshold, so that the enhanced processing is performed only when the write data time is sufficient, thereby avoiding the problem of excessive occupation of system resources or processing delays caused by too long write data time due to enhanced processing, and can make full use of the write data time to improve the efficiency of processing the storage unit. Further, in some embodiments, before using the state verification condition to determine whether the storage unit meets the enhanced processing condition, the enhanced area address is loaded in the resistive random access memory, and the enhanced area address is added by 1, so that the address of the storage unit that currently needs to be judged strong or weak can be located. Furthermore, in some embodiments, when the state of the storage unit is determined to be a strong state, the address of the storage unit is recorded, and a starting address can be provided for the next enhanced processing operation, so that the storage units that meet the enhanced processing conditions can be enhanced in sequence, ensuring that the strength judgment and enhanced processing operations can traverse the addresses of all storage units in the resistive random access memory, avoiding the need to re-acquire the enhanced area address, thereby significantly improving the efficiency of the enhanced processing.

[0124] Some embodiments of the present application are introduced above by taking resistive random access memory as an example. According to other embodiments of the present application, the non-volatile two-terminal memory is a polarization state memory, and the state verification condition includes: a first polarization state verification condition and a second polarization state verification condition, the first polarization state verification condition is used to verify that the storage unit is a first negative polarization state or a second negative polarization state, and the second polarization state verification condition is used to verify that the storage unit is a first positive polarization state or a second positive polarization state.

[0125] According to one embodiment of the present application, the first polarization state verification condition includes a second erasure verification condition (eg Figure 1c P0 shown in ) and the second edge erase verification condition (e.g. Figure 1c As shown in MP0), the polarization amount of the memory cell in the first negative polarization state is between the second erase verification polarization amount and the second edge erase verification polarization amount.

[0126] According to one embodiment of the present application, the second polarization state verification condition includes a second programming verification condition (for example, Figure 1c P1 shown in FIG. 1 and a second edge programming verification condition (eg Figure 1c As shown in MP1), the polarization amount of the memory cell in the first positive polarization state is between the second programming verification polarization amount and the second edge programming verification polarization amount.

[0127] According to one embodiment of the present application, performing enhanced processing on the storage cell includes: performing enhanced erasing operation processing on the storage cell when the state of the storage cell is a first negative polarization state; and performing enhanced programming operation processing on the storage cell when the state of the storage cell is a first positive polarization state.

[0128] According to one embodiment of the present application, the polarization state memory includes a ferroelectric random access memory (FeRAM).

[0129] It should be understood that in the present application, the negative polarization state is used to represent that the memory cell stores "0", and the positive polarization state is used to represent that the memory cell stores "1", but this is merely an example, and those skilled in the art may also use the negative polarization state to represent that the memory cell stores "1", and the positive polarization state to represent that the memory cell stores "0".

[0130] The resistive random access memory has been introduced in detail above, and the detailed description of the polarization state memory will be omitted here.

[0131] Figure 6 An exemplary structural block diagram of an apparatus 600 for maintaining data in a non-volatile two-terminal memory according to an embodiment of the present application is shown.

[0132] like Figure 6 As shown, the device 600 includes a processor 610 and a memory 620. The aforementioned memory 620 may include but is not limited to a resistive random access memory RRAM (Resistive Random Access Memory), a polarized state memory, a dynamic random access resistive memory DRAM (Dynamic Random Access Memory), a static random access resistive memory SRAM (Static Random Access Memory), and an enhanced dynamic random access resistive memory EDRAM (Enhanced Dynamic Random Access Memory). The aforementioned processor 610 may include, for example, a general-purpose processor ("CPU"), a dedicated graphics processor ("GPU") or a microcontroller ("MCU"), and the aforementioned memory 620 stores at least a computer program, which is executed by the aforementioned processor 610 to implement the method 200 for non-volatile two-terminal memory data retention as described above. As the method has been described in detail in the previous text, it will not be repeated here.

[0133] In another aspect of the present invention, a computer storage medium is provided, on which a computer program for non-volatile two-terminal memory data retention is stored, and the instruction is executed by one or more processors to implement the method 200 for non-volatile two-terminal memory data retention as described above. Specifically, the aforementioned readable storage medium can be any tangible medium containing or storing a program, and the computer program can be used by an instruction execution system, an apparatus or a device or used in combination with it. For example, the computer-readable storage medium can be any appropriate magnetic storage medium or magneto-optical storage medium, such as a resistive random access memory RRAM (Resistive Random Access Memory), a dynamic random access resistive memory DRAM (Dynamic Random Access Memory), a static random access resistive memory SRAM (Static Random-Access Memory), an enhanced dynamic random access resistive memory EDRAM (Enhanced Dynamic Random Access Memory), a high-bandwidth memory HBM (High-Bandwidth Memory), a hybrid memory cube HMC (Hybrid Memory Cube), etc., or any other medium that can be used to store the required information and can be accessed by an application, a module or both. Any such computer storage medium may be part of the device or accessible or connectable to the device.Any application or module described in the present invention may be implemented using computer readable / executable instructions that may be stored or otherwise maintained by such computer readable media.

[0134] Figure 7 An exemplary structural block diagram of a system 700 according to an embodiment of the present application is shown.

[0135] like Figure 7 As shown, the system 700 includes a data writing module 710 , a determination module 720 and an enhanced processing module 730 .

[0136] Specifically, the data writing system 700 may adopt an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a microcontroller unit (MCU) or a digital signal processor (DSP), etc.

[0137] In an embodiment of the present application, the data writing module 710 is used to start the data writing state machine, and write data to the storage unit in the non-volatile two-terminal memory through the data writing state machine, wherein the non-volatile two-terminal memory stores the enhanced area address.

[0138] In an embodiment of the present application, the judgment module 720 can be connected to the write data module 710, and the judgment module 720 is used to judge whether the storage unit meets the enhanced processing conditions, wherein the enhanced processing conditions include: the write data time does not exceed the write data time threshold.

[0139] In an embodiment of the present application, the enhanced processing module 730 may be connected to the judgment module 720, and in response to satisfying the enhanced processing condition, the enhanced processing module is used to perform enhanced processing on the storage unit.

[0140] Specifically, the data writing module 710, the determination module 720 and the enhanced processing module 730 may be integrated into one integrated circuit, or may be connected as independent units.

[0141] In one embodiment of the present application, the data writing system 700 can execute a method 200 for maintaining data in a non-volatile two-terminal memory in any embodiment of the present application. In other embodiments of the present application, the data writing system 700 can also execute other methods for maintaining data in a non-volatile two-terminal memory, which are not limited here.

[0142] Figure 8 An exemplary structural block diagram of a non-volatile two-terminal memory electronic operating environment 800 according to an embodiment of the present application is shown.

[0143] like Figure 8 As shown, electronic operating environment 800 may be formed within a single semiconductor die, although the present disclosure is not limited thereto and in other embodiments, some components of electronic operating environment 800 may be formed on separate semiconductor dies.

[0144] The electronic operating environment 800 may include the aforementioned memory 620, column controller 810, sense amplifier 820, reference and control signal generator 830, row controller 840, input / output buffer 850, clock source 860, address register 870, write data state machine 880 and command interface 890.

[0145] Specifically, the column controller 810 and the sense amplifier 820 may be adjacent to the memory 620. The column controller 810 may be configured to activate (or identify to activate) a subset of the bit lines of the memory 620. The column controller 810 may utilize control signals provided by the reference and control signal generator 830 to activate and operate corresponding bit lines in the bit line subset, applying appropriate program, erase, or read voltages to these bit lines. Inactive bit lines in the memory 620 may be maintained at an inhibit voltage (also applied by the reference and control signal generator 830) to mitigate or avoid bit disturbance effects on these inactive bit lines.

[0146] Specifically, the row controller 840 can be adjacent to and electrically connected to the word lines of the memory 620. Also using the control signals of the reference and control signal generator 830, the row controller 840 can select a particular row of memory cells with an appropriate selection voltage. In addition, the row controller 840 can facilitate programming, erasing, or reading operations by applying an appropriate voltage at the selected word line.

[0147] Specifically, the sense amplifier 820 may read data from or write data to an activated memory cell of the memory 620 selected by the column controller 810 and the row controller 840. The data read from the memory 620 may be provided to the input / output buffer 850. Likewise, the data to be written to the memory 620 may be received from the input / output buffer 850 and written to the activated memory cell of the memory 620.

[0148] Specifically, the clock source 860 can provide corresponding clock pulses to facilitate the timing of read, write and programming operations of the row controller 840 and the column controller 810. The clock source 860 can be responsive to external or internal commands received by the electronic operating environment 800 to further facilitate the selection of word lines or bit lines. The input / output buffer 850 can include command and address inputs, and bidirectional data inputs and outputs. Instructions are provided through command and address inputs, and data to be written to the memory 620 and data read from the memory 620 are transmitted on the bidirectional data inputs and outputs, thereby facilitating connection to an external host device such as the device 600, such as the device 600.

[0149] Specifically, the input / output buffer 850 may be configured to receive write data, receive erase instructions, receive status or maintenance instructions, output read data, output status information, receive address data and command data, and address data of corresponding instructions. The address data may be transmitted to the row controller 840 and the column controller 810 through the address register 870. In addition, the input data is transmitted to the memory 620 through the signal input line between the sense amplifier 820 and the input / output buffer 850, and the output data is received from the memory 620 through the signal output line from the sense amplifier 820 to the input / output buffer 850. The input data may be received from a host device such as the device 600, and the output data may be transmitted to a host device such as the device 600 through the I / O bus.

[0150] Specifically, a command received from a host device such as the apparatus 600 may be provided to the command interface 890. The command interface 890 may be configured to receive an external control signal from a host device such as the apparatus 600 and determine whether the data input to the input / output buffer 850 is write data, a command, or an address. The input command may be transmitted to the write data state machine 880.

[0151] Specifically, the write data state machine 880 can manage the data writing process of the non-volatile two-terminal memory and other functions related to the non-volatile two-terminal memory. Specifically, the write data process includes data programming, data erasure, data recovery and recording of enhanced area addresses, and in the data programming and data erasure processes, the verification conditions can be used to verify the state of each storage unit and the write data time, and the storage unit with a weak state can also be strengthened. Operation processing. Other functions related to the non-volatile two-terminal memory include data reading, data writing, data input, data output, etc. In some aspects, the write data state machine 880 can send and receive confirmation and denial of successful reception or execution of various commands. In a further embodiment, the write data state machine 880 can decode and implement commands related to the state, decode and implement configuration commands, etc.

[0152] Specifically, in order to implement functions such as read, write, erase, program, input, and output, the write data state machine 880 can control the clock source 860 or the reference and control signal generator 830. The control of the clock source 860 can generate output pulses configured to facilitate the row controller 840 and the column controller 810 to implement specific functions. For example, the output pulse can be transmitted to the selected bit line through the column controller 810. For another example, the output pulse can be transmitted to the selected word line through the row controller 840.

[0153] Although multiple embodiments of the present disclosure have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Those skilled in the art may think of many changes, modifications, and alternatives without departing from the thought and spirit of the present disclosure. It should be understood that in the process of practicing the present disclosure, various alternatives to the embodiments of the present disclosure described herein may be adopted. The attached claims are intended to define the scope of protection of the present disclosure, and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. A method for data retention in a non-volatile two-terminal memory, characterized in that: The method comprises: Start the data writing state machine, and write data to the storage unit in the non-volatile two-end memory through the data writing state machine; Adopting a data writing time judgment condition to judge whether the storage unit meets the enhanced processing condition, wherein the data writing time judgment condition is used to judge whether the data writing time of the storage unit exceeds the data writing time threshold; The storage unit meets the enhanced processing condition including: the data writing time of the storage unit does not exceed the data writing time threshold; In response to satisfying the strengthening processing condition, strengthening processing is performed on the storage unit.

2. The method according to claim 1, characterized in that Using a state verification condition to determine whether the storage unit meets the enhanced processing condition, the state verification condition is used to determine whether the state of the storage unit is a weak state or a strong state; The storage unit satisfies the enhanced processing condition, including: the state of the storage unit is a weak state.

3. The method according to claim 2, characterized in that In the process of determining whether the storage unit meets the enhanced processing condition, the write data time determination condition is first executed, and then the status verification condition is executed.

4. The method according to claim 2, characterized in that In the process of determining whether the storage unit meets the enhanced processing condition, the state verification condition is first executed, and then the data writing time determination condition is executed.

5. The method according to any one of claims 1 to 4, characterized in that After the storage unit is enhanced, the following steps are performed: Determine again whether the storage unit after the enhanced processing meets the enhanced processing condition; In response to satisfying the enhanced processing condition, returning to the step of performing enhanced processing on the storage unit until the storage unit no longer satisfies the enhanced processing condition.

6. The method according to claim 5, characterized in that The non-volatile two-terminal memory stores the enhanced area address; Adopting a state verification condition to determine whether the storage unit meets the enhanced processing condition, wherein the state verification condition is used to determine whether the state of the storage unit is a weak state or a strong state; Before using the state verification condition to determine whether the storage unit meets the enhanced processing condition, the enhanced area address is loaded in the non-volatile two-terminal memory, and 1 is added to the enhanced area address stored in the non-volatile two-terminal memory to obtain the address of the storage unit.

7. The method according to claim 6, characterized in that When the state of the memory cell is a strong state, the address of the memory cell is recorded.

8. The method according to claim 1, characterized in that The method further includes: in response to not satisfying the enhanced processing condition, exiting the write data state machine.

9. The method according to claim 2, characterized in that: The state verification condition includes: a first storage state verification condition and a second storage state verification condition, the first storage state verification condition is used to verify that the storage unit is a first high state or a second high state, and the second storage state verification condition is used to verify that the storage unit is a first low state or a second low state.

10. The method according to claim 9, characterized in that The non-volatile two-terminal memory is a resistive memory, and the state verification condition includes: a first resistance state verification condition and a second resistance state verification condition, the first resistance state verification condition is used to verify that the storage unit is a first high resistance state or a second high resistance state, and the second resistance state verification condition is used to verify that the storage unit is a first low resistance state or a second low resistance state.

11. The method according to claim 10, characterized in that The first resistance state verification condition includes a first erasure verification condition and a first edge erasure verification condition, and the current of the memory cell in the first high resistance state is greater than the first erasure verification current and less than the first edge erasure verification current.

12. The method according to claim 10, characterized in that The second resistance state verification condition includes a first program verification condition and a first edge program verification condition, and a current of the memory cell in the first low resistance state is smaller than the first program verification current and larger than the first edge program verification current.

13. The method according to claim 10, characterized in that The step of performing enhanced processing on the storage unit includes: When the state of the storage unit is a first high-impedance state, performing an enhanced erasing operation on the storage unit; When the state of the memory cell is the first low-resistance state, an enhanced programming operation is performed on the memory cell.

14. The method according to any one of claims 10 to 13, characterized in that: The resistive memory includes one or more of an electric resistance switch memory, a phase change memory, a magnetoresistive memory and a conductive bridge memory.

15. The method according to claim 9, characterized in that The non-volatile two-terminal memory is a polarization state memory, and the state verification condition includes: a first polarization state verification condition and a second polarization state verification condition, the first polarization state verification condition is used to verify that the storage unit is a first negative polarization state or a second negative polarization state, and the second polarization state verification condition is used to verify that the storage unit is a first positive polarization state or a second positive polarization state.

16. The method according to claim 15, characterized in that The first polarization state verification condition includes a second erasure verification condition and a second edge erasure verification condition, and the polarization amount of the memory cell in the first negative polarization state is between the second erasure verification polarization amount and the second edge erasure verification polarization amount.

17. The method according to claim 15, characterized in that The second polarization state verification condition includes a second programming verification condition and a second edge programming verification condition, and the polarization amount of the memory cell in the first positive polarization state is between the second programming verification polarization amount and the second edge programming verification polarization amount.

18. The method according to claim 15, characterized in that The step of performing enhanced processing on the storage unit includes: When the state of the memory cell is a first negative polarization state, performing an enhanced erasing operation on the memory cell; When the state of the memory cell is the first positive polarization state, an enhanced programming operation is performed on the memory cell.

19. The method according to any one of claims 15 to 18, characterized in that: The polarization state memory includes a ferroelectric random access memory (FeRAM).

20. A device for maintaining data in a non-volatile two-terminal memory, characterized in that: include: processor; Memory for storing computer programs; The processor is configured to execute the computer program to implement the method according to any one of claims 1 to 19.

21. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by one or more processors, the method according to any one of claims 1 to 19 is implemented.

22. A data writing system, characterized in that: The data writing system comprises: A data writing module, the data writing module is used to start a data writing state machine, and write data to a storage unit in a non-volatile two-terminal memory through the data writing state machine; A judgment module, the judgment module is used to judge whether the storage unit meets the enhanced processing condition by using a data writing time judgment condition, the data writing time judgment condition is used to judge whether the data writing time of the storage unit exceeds the data writing time threshold, and the storage unit meets the enhanced processing condition including: the data writing time of the storage unit does not exceed the data writing time threshold; The enhanced processing module is used to perform enhanced processing on the storage unit in response to satisfying the enhanced processing condition.

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