Anti-fuse memory array and anti-fuse memory

Abstract

The invention provides an anti-fuse memory array and an anti-fuse memory. There is provided an anti-fuse memory array including: a plurality of anti-fuse memory modules, each of the plurality of anti-fuse memory modules including: a bit line selection module, a plurality of anti-fuse cells connected to the read bit line module through one bit line, wherein a corresponding anti-fuse cell in each anti-fuse memory module is connected to one word line, and a protection unit having one end connected between the plurality of anti-fuse cells and the bit line selection module and the other end connected to a fixed voltage; and a third selection module, wherein the plurality of anti-fuse units are connected to the third selection module.

Description

Technical Field

[0001] The present invention relates to a memory, and in particular to an anti-fuse memory array and an anti-fuse memory with a protection unit. Background Art

[0002] Semiconductor memory devices are electronic devices used to store data and are widely used in computers, mobile phones, embedded systems and other devices. Semiconductor memory chips can be divided into many types according to the way and purpose of storing data. One-time programmable (OTP) memory is a non-volatile memory technology that allows data to be permanently stored and cannot be changed after programming. This feature makes OTP memory very suitable for applications that require high security and data integrity.

[0003] Antifuse memory is widely used in semiconductor memory to store the addresses of defective main memory cells. The working principle of antifuse memory is to apply a very high voltage (HV) to the gate oxide dielectric of the antifuse memory cell to break it down. After the breakdown, the impedance of the path decreases, and the storage logic 1 and logic 0 are determined by detecting the impedance of the antifuse cell. The capacity of the antifuse memory increases with the capacity of the semiconductor memory. In order to save area, more antifuse memory cells share the same node. When we apply a very high voltage to program some antifuse memory cells, it will inevitably affect some adjacent non-target antifuse cells, causing their impedance to also decrease. Summary of the invention

[0004] The present invention is intended to overcome the above and / or other problems in the prior art. Through the anti-fuse memory proposed by the present invention, a protection unit is provided to prevent misfire, eliminate the influence on non-target anti-fuse units, and set the voltage of non-target anti-fuse units to a safe voltage instead of a high voltage. Therefore, when programming other fuses, these non-target anti-fuse units will not be damaged by very high voltage.

[0005] According to a first aspect of the present invention, an anti-fuse memory array is provided, characterized in that the anti-fuse memory array comprises: a plurality of anti-fuse memory modules, each of the plurality of anti-fuse memory modules comprises: a bit line selection module, a plurality of anti-fuse units, the plurality of anti-fuse units are connected to the read bit line module via a bit line, wherein the corresponding anti-fuse unit in each anti-fuse memory module is connected to a word line, and a protection unit, one end of the protection unit is connected between the plurality of anti-fuse units and the bit line selection module and the other end is connected to a fixed voltage; and a third selection module, the plurality of anti-fuse units are connected to the third selection module.

[0006] Preferably, the protection unit includes one NMOS tube or a plurality of NMOS tubes connected in parallel.

[0007] Preferably, the protection unit includes two NMOS tubes.

[0008] Preferably, the NMOS tube is a long L weak NMOS tube.

[0009] Preferably, the source end of the NMOS tube of the protection unit is connected to the source ends of the multiple anti-fuse units of the anti-fuse memory module, and the drain end of the NMOS tube of the protection unit is connected to the fixed voltage inside the anti-fuse memory array.

[0010] According to a second aspect of the present invention, an anti-fuse memory is provided, wherein the anti-fuse memory comprises: a plurality of anti-fuse memory arrays as described in any one of the above items.

[0011] According to a third aspect of the present invention, an anti-fuse memory is provided, characterized in that the anti-fuse memory comprises: a plurality of anti-fuse memory arrays, each anti-fuse memory array comprises: a plurality of anti-fuse memory modules, each of the plurality of anti-fuse memory modules comprises: a bit line selection module, and a plurality of anti-fuse units, the plurality of anti-fuse units are connected to the bit line selection module via a bit line, wherein corresponding anti-fuse units in the plurality of anti-fuse memory modules of the plurality of anti-fuse memory arrays are connected to a word line, a third selection module, the plurality of anti-fuse units are connected to the third selection module; and a protection unit, one end of the protection unit is connected between each of the plurality of anti-fuse units and the bit line selection module and the other end is connected to a fixed voltage.

[0012] Preferably, the protection unit includes an NMOS tube.

[0013] Preferably, the NMOS tube is a long L weak NMOS tube.

[0014] Preferably, the source end of the NMOS tube of the protection unit is connected to the source ends of the plurality of anti-fuse units, and the drain end of the NMOS tube of the protection unit is connected to a fixed voltage inside the anti-fuse storage array. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art are briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work, among which:

[0016] Figure 1 A module diagram of an anti-fuse memory read / write circuit system according to an embodiment of the present invention is shown.

[0017] Figure 2 A schematic diagram of a write circuit of an anti-fuse memory is shown.

[0018] Figure 3 A schematic circuit diagram of an anti-fuse memory according to an embodiment of the present invention is shown.

[0019] Figure 4 FIG. 4 is a schematic circuit diagram of an anti-fuse memory according to another embodiment of the present invention.

[0020] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical components that are common to the figures. It is contemplated that components and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

[0021] It should be understood that the drawings are for illustrative purposes and are not to be considered to scale unless specifically stated to be to scale. Furthermore, as schematic diagrams, the drawings are provided to aid understanding and may not include all aspects or information compared to realistic representations.

[0022] In the accompanying drawings, similar components and / or features may have the same reference numerals. In addition, various components of the same type may be distinguished by letters following the reference numerals. If only the preceding reference numerals are used in the specification, the description applies to any similar components having the same preceding reference numerals. DETAILED DESCRIPTION

[0023] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0024] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0025] Unless otherwise defined, the technical or scientific terms used in the claims and the specification shall have the usual meaning understood by persons with ordinary skills in the technical field to which the invention belongs. The words "first", "second" and similar words used in the patent application specification and the claims of the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. "One" or "one" and other similar words do not indicate a quantitative limitation, but indicate the existence of at least one. "Include" or "comprises" and other similar words mean that the elements or objects appearing before "include" or "comprises" include the elements or objects listed after "include" or "comprises" and their equivalent elements, and do not exclude other elements or objects. "Connected" or "connected" and other similar words are not limited to physical or mechanical connections, nor are they limited to direct or indirect connections.

[0026] In this application, if there is no special description, all embodiments and preferred embodiments mentioned herein can be combined with each other to form a new technical solution. In this application, if there is no special description, all technical features and preferred features mentioned herein can be combined with each other to form a new technical solution.

[0027] In the description of the embodiments of the present application, the term "and / or" is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0028] Figure 1 A module diagram of an anti-fuse memory read-write circuit system according to an embodiment of the present invention is shown. The anti-fuse memory read-write circuit system includes a read circuit, multiple anti-fuse memory modules and a third selection module. Each anti-fuse memory module includes a read bit line module, multiple anti-fuse units, a bit line selection module and a protection unit. The read bit line module is connected to multiple anti-fuse memory modules through multiple bit lines. Multiple anti-fuse units of each anti-fuse memory module are connected to the same bit line, and are connected to the read bit line module, the bit line selection module and the protection unit through the bit line. Multiple anti-fuse units connected to the same bit line are respectively connected to different word lines, and each word line is connected to corresponding anti-fuse units of multiple anti-fuse memory modules. Figure 1In the figure, the solid line path on the left schematically shows the write path, i.e., the programming path. The selected anti-fuse unit is programmed by applying a very high voltage to the selected anti-fuse unit to make it burn out. When writing, the anti-fuse storage array to be written is selected by the third selection module, the multiple anti-fuse units corresponding to the bit lines are selected by the bit line selection module, and the anti-fuse unit is selected by the word line selection module. And the protection unit is used to eliminate the influence on the non-target anti-fuse unit in the process of the target anti-fuse unit to avoid being burned by mistake. Figure 1 The right side of the diagram schematically shows the read path with a dotted path. During readout, the read bit line module and the readout circuit are used to select which bit line to read and read out the corresponding data. The logic value written into the anti-fuse unit can be read out through the readout path. In addition, N bits of data can be read out at one time by enabling all FA signals (i.e., the third selection module).

[0029] Figure 2 FIG. 2 shows a schematic diagram of an anti-fuse memory 200. Figure 2 In the embodiment, the anti-fuse memory 200 includes an anti-fuse memory array 210 and an anti-fuse memory array 220, each of which includes a third selection module (for example, the anti-fuse memory array 210 includes a third selection module 210 with a control signal FA0). FA The anti-fuse memory array 220 includes a third selection module 220 whose control signal is FAn. FA ). The third selection module 210 FA ~220 FA Each of the third selection modules is connected to a plurality of anti-fuse memory modules. Figure 2 Schematically shows an anti-fuse memory module 211, an anti-fuse memory module 212, an anti-fuse memory module 221 and an anti-fuse memory module 222, each of which includes a bit line selection module (for example, the anti-fuse memory module 211 includes a bit line selection module 211 with a control signal BLSW0). BL The anti-fuse memory module 212 includes a bit line selection module 212 whose control signal is BLSWn. BL The anti-fuse memory module 221 includes a bit line selection module 221 whose control signal is BLSW0. BL The anti-fuse memory module 222 includes a bit line selection module 222 whose control signal is BLSWn. BL ).like Figure 2 As shown, the anti-fuse memory module 211 includes anti-fuse units A0-Ax, and the anti-fuse units A0-Ax are respectively connected to the word line selection module A0 with control signals PWLb0-PWLbx. WL ~Ax WLThe third selection module, the bit line selection module, and the word line selection module can form a three-dimensional address for the anti-fuse unit. The configurations of the anti-fuse memory module 212, the anti-fuse memory module 221, and the anti-fuse memory module 222 are similar to the anti-fuse memory module 211. Although Figure 2 Only anti-fuse memories 210 and 220 are shown, and only anti-fuse memory module 211, anti-fuse memory module 212, anti-fuse memory module 221 and anti-fuse memory module 222 are shown, but those skilled in the art should understand that fewer or more third selection modules may be included, and each third selection module may be connected to fewer or more anti-fuse memory modules.

[0030] As from Figure 2 As can be seen in FIG. 1 , the anti-fuse unit A0 of the anti-fuse memory module 211, the anti-fuse unit B0 of the anti-fuse memory module 212, the anti-fuse unit C0 of the anti-fuse memory module 221, and the anti-fuse unit D0 of the anti-fuse memory module 222 are connected to the same word line control signal PWLb0, and the anti-fuse unit Ax of the anti-fuse memory module 211, the anti-fuse unit Bx of the anti-fuse memory module 212, the anti-fuse unit Cx of the anti-fuse memory module 221, and the anti-fuse unit Dx of the anti-fuse memory module 222 are connected to the same word line control signal PWLbx. In this regard, the anti-fuse units connected to the same word line control signal in each anti-fuse memory module are referred to as corresponding anti-fuse units herein. For example, the anti-fuse unit A0 of the anti-fuse memory module 211, the anti-fuse unit B0 of the anti-fuse memory module 212, the anti-fuse unit C0 of the anti-fuse memory module 221 and the anti-fuse unit D0 of the anti-fuse memory module 222 connected to the same word line control signal PWLb0 are corresponding anti-fuse units.

[0031] exist Figure 2 In the example, in order to program the anti-fuse unit A0, a voltage VPP_HV much higher than the conventional voltage VPP can be applied to the gate oxide terminal vpi_sw of the anti-fuse unit A0, and a voltage VBB_HV much higher than the conventional voltage VBB can be applied to the source and drain terminal vbi_com of the anti-fuse unit A0, thereby blowing the anti-fuse unit A0. During the reading process, the gate oxide terminal vpi_sw and the source and drain terminal vbi_com of the anti-fuse unit A0 are their conventional voltages VPP and VBB, respectively. As an example, the voltage drop for blowing the anti-fuse unit can be about 6V, the conventional voltage VPP can be 2.8V, and the high voltage VPP_HV can be 4V to 4.5V. The conventional voltage VBB of the source and drain terminal vbi_com can be -0.7V, and the high voltage VBB_HV can be -2V.

[0032] As mentioned above, as the capacity of semiconductor memory increases, the capacity of anti-fuse memory also increases, resulting in a higher density of anti-fuse arrays, causing more anti-fuse units to share the same control circuit or node, and all anti-fuse units share the same high voltage source. Therefore, during the programming process, some non-target anti-fuse units will inevitably encounter very high voltages VPP_HV or VBB_HV. Figure 2 In the anti-fuse memory 200, the anti-fuse unit B0, the anti-fuse unit C0 and the anti-fuse unit D0 corresponding to the anti-fuse unit A0 are connected to the same word line control signal PWLb0. When programming the target programming anti-fuse unit A0, the word line control signal PWLb0, the bit line control signal BLSW0 and the third control signal FA0 are enabled. However, in this case, the gate oxide terminal vpi_sw of the anti-fuse unit (for example, the anti-fuse unit B0, the anti-fuse unit C0 and the anti-fuse unit D0) that shares the word line control signal PWLb0 with the anti-fuse unit A0 is also applied with the high voltage VPP_HV. Similarly, the source and drain terminals vbi_com of the anti-fuse unit (for example, the anti-fuse unit A1~AX) that shares the bit line control signal BLSW0 and / or the third control signal FA0 with the anti-fuse unit A0 are also applied with the high voltage VBB_HV. In this way, the parameters (for example, capacitance or resistance) of the non-target programming anti-fuse unit may also change. Since the anti-fuse cell is a special thin-gate cell, there is a risk that non-target anti-fuse cells are damaged or burned by mistake. In order to eliminate this risk, the present invention proposes an anti-fuse memory having a protection unit for preventing false burning.

[0033] Figure 3 FIG. 4 is a schematic circuit diagram of an anti-fuse memory 300 according to an embodiment of the present invention. Figure 3 The structure of the anti-fuse memory 300 is similar to that of the reference Figure 2 The structure of the described anti-fuse memory 200 is similar, and the same reference numerals are used here to represent similar parts and they are not described again and only the different parts are described.

[0034] In order to eliminate the risk of non-target anti-fuse cells being burned by mistake, the anti-fuse memory 300 further includes a protection unit having one end connected between the anti-fuse cell and the bit line selection module and the other end connected to a fixed voltage.

[0035] exist Figure 3In the illustrated embodiment, the anti-fuse memory module 211, the anti-fuse memory module 212, the anti-fuse memory module 221 and the anti-fuse memory module 222 of each anti-fuse memory array of the anti-fuse memory 300 include protection units 311, 312, 321 and 322, respectively, and each protection unit may include two NMOS. It should be understood by those skilled in the art that the anti-fuse memory 300 may include more or fewer anti-fuse memory modules, and may include more or fewer protection units depending on the number of anti-fuse memory modules. In addition, each protection unit may include other numbers of transistors. The source end of the NMOS tube of the protection unit is connected to the source ends of multiple anti-fuse units of the anti-fuse memory module where the protection unit is located (taking protection unit 311 as an example, the source end of the NMOS tube of the protection unit 311 is connected to the source end of the anti-fuse unit of the anti-fuse memory module 211 where the protection unit 311 is located), and the drain end of the NMOS tube of the protection unit is connected to a fixed voltage inside the anti-fuse storage array (for example, the normal voltage of the anti-fuse unit (2.8V)).

[0036] exist Figure 3 In the embodiment shown, the protection unit 311 of the anti-fuse memory module 211 includes an NMOS transistor N A0 And NMOS tube N A1 , where NMOS tube N A0 The control signal is FA0b and the NMOS tube N A1 The control signal of is BLSW0b. Similarly, the protection unit 312 of the anti-fuse memory module 212 includes an NMOS transistor N B0 And NMOS tube N B1 , where NMOS tube N B0 The control signal is FA0b and the NMOS tube N B1 The control signal is BLSWnb; the protection unit 321 of the anti-fuse memory module 221 includes an NMOS tube N C0 And NMOS tube N C1 , where NMOS tube N C0 The control signal is FAnb and the NMOS tube N C1 The control signal is BLSW0b; the protection unit 322 of the anti-fuse memory module 222 includes an NMOS tube N D0 And NMOS tube N D1 , where NMOS tube N D0 The control signal is FAnb and the NMOS tube N B1 The control signal is BLSWnb.

[0037] In the case where the anti-fuse cell A0 is the target programming anti-fuse cell, the NMOS transistor N of the protection unit 311 of the anti-fuse memory module 211 is switched to A0 The control signal of is set to FA0b, and the NMOS transistors N of the protection units 321 and 322 of the anti-fuse memory modules 221 and 222 are C0 and N D0 The control signal of is set to FAnb, which can protect the anti-fuse units (for example, anti-fuse units C0-CX, anti-fuse units D0-DX) connected to different third control signals, the same or different bit line control signals and word line control signals as the anti-fuse unit A0. A1 The control signal of is set to BLSW0b, and the NMOS transistor N of the protection unit 312 of the anti-fuse memory module 212 is B1 and the NMOS transistor N of the protection unit 322 of the anti-fuse memory module 222 D1 The control signal is set to BLSWnb, which can protect the anti-fuse units (for example, anti-fuse units B0~BX, anti-fuse units D0~DX) that are connected to different bit line control signals, the same or different third control signals and word line control signals as the anti-fuse unit A0.

[0038] In the absence of a protection unit, when programming the anti-fuse unit A0, the gate oxide terminals of the non-target anti-fuse units B0, C0, and D0 corresponding to the anti-fuse unit A0 will also be applied with a high voltage VPP_HV, and the NMOS tube (bit line selection module or third selection module) controlled by the BLSWn or FAn signal corresponding to the BLSW0 or FA0 signal is turned off and suspended, but with a long programming time, the potential vbi_com of the drain terminals of the two NMOS tubes controlled by the BLSWn or FAn signal will slowly drop close to VBB_HV, so the voltage drop across the non-target anti-fuse unit will be greater than the high voltage VPP_HV. After adding the protection unit, a voltage VPP is applied to the other end of the protection unit of the non-target programming anti-fuse unit, and by using the protection unit including the NMOS tube, the voltage of the source and drain terminals vbi_com of the non-target programming anti-fuse unit is set to VPP-VTH. By making these single-connected vbi_coms explicitly pulled up to VPP-VTH, the voltage drop on the non-target programming anti-fuse cells is reduced to VPP_HV-(VPP-VTH) below 2V, thereby reducing the voltage drop on the non-target programming anti-fuse cells to prevent them from receiving potential high-voltage shocks, making these non-target programming anti-fuse cells safer. For the target programming anti-fuse cells, the protection unit is completely turned off and will not affect the programming capability.

[0039] Optionally, since the NMOS tube in the protection unit only needs to maintain the VPP-VTH level on the source-drain terminal vbi_com of the non-target programming anti-fuse unit, a small and weak NMOS can be used to save area.

[0040] Figure 4 FIG. 4 is a schematic circuit diagram of an anti-fuse memory 400 according to another embodiment of the present invention. Figure 4 The anti-fuse memory 400 is conceptually and Figure 3 The concept of the anti-fuse memory 300 is similar to that of Figure 2 The protection unit is set on the basis of the anti-fuse memory 200. The difference is Figure 4 The configuration of the protection unit of the anti-fuse memory 400 is Figure 3 The anti-fuse memory 300 is different.

[0041] like Figure 4 As shown, the anti-fuse memory 400 provides a protection unit 410, which includes a long L weak NMOS tube, and the source of the NMOS tube is connected to the source and drain terminals vbi_com of all anti-fuse memory modules. Figure 4 It is shown that the protection unit 410 includes only one NMOS transistor, but it should be understood that the protection unit 410 may also include multiple NMOS transistors. Figure 4 The anti-fuse memory 400 is connected to Figure 3 Compared with the anti-fuse memory 300, the circuit efficiency is higher and the area can be saved. However, for the target programming anti-fuse unit (e.g., anti-fuse unit A0), a stronger or larger control signal (e.g., bit line control signal BLSW0 and third control signal FA0) is required to pull the potential of the source-drain terminal vbi_com to the level of VBB_HV.

[0042] So far, the anti-fuse memory array and the anti-fuse memory are described. By providing the anti-fuse memory array with a protection unit to prevent misfire, the voltage of the non-target programming anti-fuse unit is set to a safe voltage instead of a high voltage, so that when the target programming anti-fuse unit is programmed, the non-target programming anti-fuse unit will not be damaged by the high voltage.

[0043] It should be understood that the above description is illustrative and not restrictive. For example, the above embodiments (and / or their various aspects) can be used in combination with each other. In addition, without departing from the scope of the present invention, many modifications can be made to adapt specific conditions or materials to the teachings of the various embodiments of the present invention. Although the parameters of the various embodiments of the present invention are defined herein, the various embodiments are not meant to be restrictive, but exemplary embodiments. In the case of reading the above description, many other embodiments are obvious to those skilled in the art. Therefore, the scope of the various embodiments of the present invention should be determined with reference to the attached claims, and the full range of equivalent forms claimed by these claims.

Claims

1. An anti-fuse storage array, characterized in that: The anti-fuse storage array comprises: A plurality of anti-fuse memory modules, each of the plurality of anti-fuse memory modules comprising: Bit line selection module, a plurality of anti-fuse cells connected to the bit line selection module via a bit line, wherein a corresponding anti-fuse cell in each anti-fuse memory module is connected to a word line, and a protection unit having one end connected between the plurality of anti-fuse units and the bit line selection module and the other end connected to a fixed voltage; and A third selection module is provided to which the plurality of anti-fuse units of the plurality of anti-fuse memory modules are connected. 2 . The anti-fuse memory array as claimed in claim 1 , wherein the protection unit comprises one NMOS tube or a plurality of NMOS tubes connected in parallel. 3 . The anti-fuse memory array as claimed in claim 2 , wherein the protection unit comprises two NMOS transistors. 4 . The anti-fuse memory array as claimed in claim 2 , wherein the NMOS transistor is a long-L weak NMOS transistor.

5. The anti-fuse memory array of claim 2 , wherein the source end of the NMOS tube of the protection unit is connected to the source ends of the multiple anti-fuse units of the anti-fuse memory module, and the drain end of the NMOS tube of the protection unit is connected to a fixed voltage equal to the inside of the anti-fuse memory array.

6. An anti-fuse memory, characterized in that: The anti-fuse memory comprises: a plurality of anti-fuse memory arrays as claimed in claim 1 .

7. An anti-fuse memory, characterized in that: The anti-fuse memory comprises: A plurality of anti-fuse storage arrays, each anti-fuse storage array comprising: A plurality of anti-fuse memory modules, each of the plurality of anti-fuse memory modules comprising: bit line select module, and a plurality of anti-fuse cells connected to the bit line selection module via one bit line, wherein corresponding anti-fuse cells in the plurality of anti-fuse memory modules of the plurality of anti-fuse memory arrays are connected to one word line, a third selection module, the plurality of anti-fuse units being connected to the third selection module; and A protection unit has one end connected between each of the plurality of anti-fuse units and the bit line selection module and the other end connected to a fixed voltage.

8. The anti-fuse memory as claimed in claim 7, wherein the protection unit comprises an NMOS tube. 9 . The anti-fuse memory as claimed in claim 8 , wherein the NMOS transistor is a long-L weak NMOS transistor.

10. The anti-fuse memory as claimed in claim 7, wherein the source end of the NMOS tube of the protection unit is connected to the source ends of the plurality of anti-fuse units, and the drain end of the NMOS tube of the protection unit is connected to a fixed voltage inside the anti-fuse storage array.

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