High-bandwidth differential lead bonding structure

Abstract

The invention discloses a high-bandwidth differential lead bonding structure which comprises a carrier plate and a bare chip placed on the carrier plate, a first bare chip bonding pad and a fourth bare chip bonding pad on the bare chip are grounding of the chip, and a second bare chip bonding pad and a third bare chip bonding pad are differential signal positive / negative ends of the chip. The packaging structure is characterized in that the four bare chip and the four bonding pads of the bonding pad carrier plate adopt a lead bonding structure in which differential signal positive end and negative end bonding wires are overlapped, and the first bare chip bonding pad and the fourth bare chip bonding pad are respectively connected with the first carrier plate bonding pad and the fourth carrier plate bonding pad through two grounding bonding wires; the second bare chip bonding pad is connected with the third support plate bonding pad through a signal bonding wire; and the third bare chip bonding pad is connected with the second support plate bonding pad through another signal bonding wire. Compared with the prior art, the parasitic inductance is reduced, the parasitic capacitance is increased, the parasitic inductance is compensated at a high frequency band, the chip port bandwidth is improved, the problem that the bonding wire parasitic inductance reduces the chip port bandwidth is solved, and good application prospects and commercial development values are achieved.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuit packaging, in particular to a high-bandwidth differential wire bonding structure for a chip high-speed port. Background Art

[0002] Wire bonding is an important process in integrated circuit packaging. It connects the pads on the die to the pads on the substrate through metal bonding wires, so that the circuits in the die can be connected to the outside and powered. A differential signal is a signal transmitted through two wires, where the positive end transmits a positive polarity signal and the negative end transmits a negative polarity signal. The receiving end identifies the signal by comparing the difference between the two signals, and has a strong anti-interference ability.

[0003] See also Figure 1 , a traditional differential wire bonding structure: comprises a chip bare die (101), a substrate (102), a chip bare die pad (103), a bonding wire (104), and a substrate pad (105). The four chip bare die pads (103) are respectively recorded as the first, second, third, and fourth chip bare die pads from left to right, and the four substrate pads (105) are respectively recorded as the first, second, third, and fourth substrate pads from left to right. Among them, the first and fourth chip bare die pads are the ground of the chip (GND, marked as G in the figure), the second chip bare die pad is the differential signal positive terminal of the chip (marked as SP in the figure), and the third chip bare die pad is the differential signal negative terminal of the chip (marked as SN in the figure). The first, second, third, and fourth chip bare die pads are respectively connected to the first, second, third, and fourth substrate pads through bonding wires, and the four ports on the chip bare die can be led out to the outside. However, the bonding wire is not an ideal wire and has a certain parasitic inductance. As the frequency increases, the impedance mismatch caused by parasitic inductance becomes more serious, deteriorating signal integrity and becoming one of the bottlenecks limiting the improvement of chip port bandwidth. Therefore, reducing the parasitic inductance of the bonding wire is the key to improving the chip port bandwidth.

[0004] In summary, the wire bonding structure in the prior art has serious impedance mismatch, the parasitic inductance of the bonding wire reduces the chip port bandwidth, seriously deteriorates the signal integrity, and greatly limits the bandwidth improvement of the chip port. Summary of the invention

[0005] The purpose of the present invention is to provide a high-bandwidth wire bonding structure to address the deficiencies in the prior art. The wire bonding structure adopts a wire bonding structure in which the positive and negative bonding wires of the differential signal are overlapped to reduce parasitic inductance and increase parasitic capacitance, thereby improving the chip port bandwidth. The structure is simple and the problem of the parasitic inductance of the bonding wire reducing the chip port bandwidth is well solved. The structure has good application prospects and commercial development value.

[0006] The object of the present invention is achieved as follows: a high-bandwidth differential wire bonding structure, characterized in that the wire bonding structure comprises: a bonding wire, a carrier board and a chip bare die placed on the carrier board, the four bare die pads on the chip bare die are respectively recorded as the first, second, third and fourth chip bare die pads from left to right; the first and fourth bare die pads are grounded for the chip, the second bare die pad is the differential signal positive end of the chip, and the third bare die pad is the differential signal negative end of the chip; the four carrier board pads on the carrier board are respectively recorded as the first, second, third and fourth carrier board pads from left to right; the first, second, third and fourth bare die pads are placed in parallel and correspond one to one with the first, second, third and fourth carrier board pads; the bonding wires are four connections for connecting the bare die pads and the carrier board pads; the carrier board can be a printed circuit board (PCB) or a package substrate (Package The definition of the differential signal is exchangeable, that is, the second die pad can be defined as the negative terminal of the differential signal of the chip, and the third chip die pad can be defined as the positive terminal of the differential signal of the chip; in the high-bandwidth differential wire bonding structure, only the differential signal of the chip can be led out, and the grounding is not led out, that is, the two bonding wires connecting the first die pad, the fourth die pad, the first substrate pad, and the fourth substrate pad can be deleted.

[0007] Compared with the prior art, the present invention has the following beneficial technical effects and significant technical progress: 1) The bonding wires at the positive and negative ends of the differential signal overlap, which reduces the mutual inductance of the bonding wires and improves the chip port bandwidth; 2) The bonding wires at the positive and negative ends of the differential signal overlap, increasing the parasitic capacitance between the bonding wires, compensating for the parasitic inductance in the high frequency band, and improving the chip port bandwidth;.

[0008] 3) It can be applied to fields such as radio frequency and optical communication that require high-bandwidth chip ports. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a schematic diagram of the traditional differential wire bonding structure; Figure 2 It is a schematic diagram of the structure of the present invention; Figure 3 A schematic diagram showing a comparison of insertion loss curves of the present invention and a conventional wire bonding structure; Figure 4 It is a structural schematic diagram of Example 1; Figure 5 It is a structural schematic diagram of Example 2; Figure 6 This is a schematic diagram of the structure of Example 3. DETAILED DESCRIPTION

[0010] See also Figure 2 The present invention comprises: a chip die 201, a carrier board 202, two signal bonding wires 204S and two ground bonding wires 204G, wherein the first die pad 203G1 and the fourth die pad 203G2 on the chip die 201 are ground ports of the chip, the second die pad 203SP is a differential signal positive terminal of the chip, and the third die pad 203SN is a differential signal negative terminal of the chip; the four pads on the carrier board 202 are respectively the first carrier board pad 205a, the second carrier board pad 205b, the third carrier board pad 205c and the fourth carrier board pad 205d; the first die pad 203G1 and the fourth die pad 203G2 are respectively connected to the first carrier board pad 205a and the fourth carrier board pad 205d by two ground bonding wires 204G; the second die pad 203SP is connected to the third carrier board pad 205 by a signal bonding wire 204S. c connection; the third bare chip pad 203SN is connected to the second carrier pad 205b by another signal bonding wire 204S, forming a wire bonding structure in which the differential signal positive and negative bonding wires are overlapped.

[0011] The principle of improving the chip port bandwidth of the present invention is that the bonding wire of the differential signal positive end (SP) overlaps with the bonding wire of the differential signal negative end (SN), reducing the mutual inductance between the differential signal (SP, SN) bonding wires, thereby improving the chip port bandwidth. In addition, the overlap reduces the distance between the differential signal (SP, SN) bonding wires, increases the parasitic capacitance between the bonding wires, compensates for the parasitic inductance in the high frequency band, and further improves the bandwidth of the differential signal (SP, SN) port.

[0012] See also Figure 3 It can be seen that the insertion loss 402 of the present invention is lower than the insertion loss 401 of the traditional differential wire bonding structure. By comparing the insertion loss SDD21 curve, it is fully demonstrated that the present invention can achieve a higher signal bandwidth.

[0013] The present invention is described in detail below with reference to the accompanying drawings. Example

[0014] See also Figure 4 , the fourth die pad 203G2 is connected to the first carrier pad 205a by a ground bonding wire 204G; the second die pad 203SP is connected to the third carrier pad 205c by a signal bonding wire 204S; the third die pad 203SN is connected to the second carrier pad 205b by another signal bonding wire 204S, forming a set of wire bonding structures in which the differential signal positive and negative bonding wires of the chip grounding are overlapped. Example

[0015] See also Figure 5, the first bare die pad 203G1 is connected to the fourth carrier pad 205d by a ground bonding wire 204G; the second bare die pad 203SP is connected to the third carrier pad 205c by a signal bonding wire 204S; the third bare die pad 203SN is connected to the second carrier pad 205b by another signal bonding wire 204S, forming another group of pads leading out the chip grounding differential signal positive and negative bonding wires overlapped set of wire bonding structure. Example

[0016] See also Figure 6 The pad 203SP is connected to the pad 205b by a signal bonding wire 204S; the pad 203SN is connected to the pad 205a by another signal bonding wire 204S, forming a wire bonding structure in which a group of differential signal positive and negative bonding wires are overlapped.

[0017] The above is only an implementation mode of the present invention and is not intended to limit the present invention. Any modifications and improvements made without departing from the concept of the present invention shall fall within the protection scope of the claims of the present invention.

Claims

1. A high-bandwidth differential wire bonding structure, comprising a carrier and a chip die placed on the carrier, wherein the first die pad and the fourth die pad on the chip die are ground ports of the chip, the second die pad is a differential signal positive terminal of the chip, and the third die pad is a differential signal negative terminal of the chip; the four pads on the carrier are respectively the first, second, third and fourth carrier pads, characterized in that: The first bare die pad and the fourth bare die pad are respectively connected to the first carrier pad and the fourth carrier pad by two ground bonding wires; the second bare die pad is connected to the third carrier pad by a signal bonding wire; the third bare die pad is connected to the second carrier pad by another signal bonding wire, forming a wire bonding structure in which the differential signal positive and negative bonding wires are overlapped.

2. The high-bandwidth differential wire bonding structure according to claim 1, characterized in that: The four pads on the chip die and the four pads on the carrier are arranged in parallel and correspond one to one.

3. The high-bandwidth differential wire bonding structure according to claim 1, characterized in that: The carrier board is a printed circuit board, a packaging substrate or an intermediate layer of any material.

4. The high-bandwidth differential wire bonding structure according to claim 1, characterized in that: The positive end and the negative end of the differential signal are defined interchangeably, that is, the second bare die pad is defined as the negative end of the differential signal of the chip; and the third bare die pad is defined as the positive end of the differential signal of the chip.

5. The high-bandwidth differential wire bonding structure according to claim 1, characterized in that: The high-bandwidth differential wire bonding structure uses any group of pads connected between the first bare die pad and the first carrier pad or the fourth bare die pad and the fourth carrier pad to lead out the bonding structure of the chip grounding.

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