Efficient charging of capacitive loads based on automatic transitions between multiple overload protection thresholds

Abstract

The invention relates to efficient charging of capacitive loads based on automatic transitions between multiple overload protection thresholds. A power management system includes a power transistor coupled between a power source and a load, a driver circuit that drives the power transistor in response to an input signal, and an error amplifier that generates a control signal that modifies operation of the driver circuit based on a comparison between a selected reference voltage and a drain-source voltage of the power transistor. The multiplexer provides a selected reference voltage to the error amplifier and passes one of the plurality of different reference voltages as the selected reference voltage based on the first and second selection signals. The first selection circuit charges the first capacitor in response to an input signal and generates a first selection signal based on a first voltage across the first capacitor. The second selection circuit charges a second capacitor in response to the input signal and generates a second selection signal based on a second voltage across the second capacitor.

Description

Technical Field

[0001] The present disclosure relates to the technical field of power electronics, and is particularly focused on dynamically managing the charging of capacitive loads by automatically switching between various overload protection thresholds. Background Art

[0002] With the load resistor R L and load capacitance C L When the capacitive load 4 shown in FIG1 begins to charge, it simulates short-circuit behavior. Figure 1A In the figure, Figure 1A A power system 1 is depicted in which a voltage source 2 is connected between ground and a switch SW. The switch SW is positioned between the voltage source 2 and a capacitive load 4. As the charge within the capacitive load 4 rises, the voltage across the capacitive load 4 similarly rises, causing a corresponding decrease in the load current IOUT delivered to the capacitive load.

[0003] This inherent behavior introduces a challenge known as inrush current at the turn-on instant. Inrush current is the initial surge of current IOUT observed when power is first applied to the capacitive load 4. This surge can be many times higher than the steady-state current that the system 1 is designed to handle. Without proper overload (OVL) protection, this inrush current IOUT can lead to component damage, reduced system reliability, and other potential hazards.

[0004] Figure 1B Used to highlight this challenge. In this figure, the dashed line shows the uncontrolled output current IOUT at turn-on without any OVL protection. Such a current profile poses a risk to the power system.

[0005] To solve these problems and provide a safer charging mechanism, such as Figure 1C As shown in FIG. 1 , a power system 1 ′ has been designed. Here, an OVL protected power supply 3 is connected to a capacitive load 4. The system 1 ′ takes an active approach to the challenges posed by surge currents. Figure 1B The graph represented by the solid line in exemplifies the output current IOUT when the power supply 3 applies OVL protection thereby setting the current limit ILIM. This method provides a controlled rise of the current IOUT to the current limit ILIM during the initial charging phase and maintains the current IOUT at ILIM, thereby effectively mitigating the risks associated with the inrush current at turn-on. Summary of the invention

[0006] A power management system is disclosed herein, the power management system including a power transistor coupled between a power supply and a load, wherein a driver circuit is configured to drive the power transistor in response to an input signal. An error amplifier is configured to generate a control signal based on a comparison between a selected reference voltage and a drain-source voltage of the power transistor, the control signal controlling the driver circuit. A multiplexer is coupled to provide the selected reference voltage to the error amplifier, the multiplexer being configured to pass one of a plurality of different reference voltages as the selected reference voltage based on a first selection signal and a second selection signal. A first selection circuit is coupled to a first capacitor, the first selection circuit being configured to charge the first capacitor in response to the input signal, and to generate a first selection signal based on a first voltage across the first capacitor. A second selection circuit is coupled to a second capacitor, the second selection circuit being configured to charge the second capacitor in response to the input signal, and to generate a second selection signal based on a second voltage across the second capacitor.

[0007] The first selection circuit may include a first comparator configured to assert an output thereof when a first voltage across the first capacitor is greater than a reference voltage, thereby asserting the first selection signal.

[0008] The second selection circuit may include a second comparator configured to assert its output when a second voltage across the second capacitor is greater than a reference voltage, thereby activating the second selection signal.

[0009] A first current source may be associated with the first selection circuit, the first current source configured to provide a current to the first capacitor in response to the input signal being active.

[0010] The first selection circuit may include a first switch selectively coupled between an output of the first current source and the first capacitor, wherein the first switch is controlled based on an input signal.

[0011] A second current source may be associated with the second selection circuit, wherein the second current source is configured to provide a current to the second capacitor in response to the input signal being active.

[0012] The second selection circuit may further include a second switch selectively coupled between an output of the second current source and the second capacitor, wherein the second switch is controlled based on the input signal.

[0013] A method for managing power in a system is also disclosed herein. The method may include receiving an input signal at a driver circuit, and using the driver circuit and based on the validity of the received input signal to drive a power transistor coupled between a power supply and a load. The method may also include comparing a selected reference voltage with a drain-source voltage of the power transistor, generating a control signal based on the comparison to modify the operation of the driver circuit when the drain-source voltage is less than the selected reference voltage, and selecting a selected reference voltage from one of a plurality of different reference voltages based on a first selection signal and a second selection signal. The method also includes charging a first capacitor via a first selection circuit in response to the input signal, generating a first selection signal based on a first voltage across the first capacitor, charging a second capacitor via a second selection circuit in response to the input signal, and generating a second selection signal based on a second voltage across the second capacitor.

[0014] Generating the first selection signal may include comparing a first voltage across the first capacitor with a reference voltage and asserting the first selection signal when the first voltage is greater than the reference voltage.

[0015] Generating the second selection signal may include comparing a second voltage across the second capacitor with a reference voltage and asserting the second selection signal when the second voltage is greater than the reference voltage.

[0016] The method may include charging a first capacitor using a first current source associated with a first selection circuit when the input signal is valid.

[0017] The method may include controlling a first switch based on an input signal to facilitate charging of a first capacitor, the first switch being coupled between an output of a first current source and the first capacitor.

[0018] The method may include charging the second capacitor using a second current source associated with the second selection circuit when the input signal is valid.

[0019] The method may include controlling a second switch selectively coupled between an output of the second current source and the second capacitor based on the input signal to facilitate charging of the second capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1A is a schematic block diagram of a prior art power system without overload protection.

[0021] Figure 1B It is shown Figure 1A and Figure 1C Graph of the operation of a prior art power system.

[0022] Figure 1C is a schematic block diagram of a prior art power system with overload protection.

[0023] Figure 2 is a schematic block diagram of a power system disclosed herein.

[0024] Figure 3 It is shown Figure 2 Graphic of the operation of the power system. DETAILED DESCRIPTION

[0025] The following disclosure enables those skilled in the art to make and use the subject matter described herein. The general principles outlined in this disclosure may be applied to embodiments and applications other than those detailed above without departing from the spirit and scope of the disclosure. It is not intended that the disclosure be limited to the embodiments shown, but rather to be given the widest scope consistent with the principles and features disclosed or suggested herein.

[0026] Note that in the following description, unless otherwise stated, any resistor or resistance mentioned is a discrete device and is not merely an electrical lead between two points. Therefore, any resistor or resistance connected between two points has a higher resistance than the lead between those two points, and such a resistor or resistance cannot be interpreted as a lead. Similarly, unless otherwise stated, any capacitor or capacitance mentioned is a discrete device and is not a parasitic element unless otherwise stated. In addition, unless otherwise stated, any inductor or inductance mentioned is a discrete device and is not a parasitic element unless otherwise stated.

[0027] Reference now Figure 2A power system 5 is described, which includes a power transistor MN connected between a power supply VCC and a load 6 to supply power to the load 6. The transistor MN is driven by a driver circuit 8 in response to an input signal IN, and a Zener diode has its anode connected to the gate of the transistor MN and has its cathode connected to the power supply VCC. The driver circuit 8 has its gain controlled by a control signal CTRL, which is generated by an error amplifier 9 based on a comparison between a selected reference voltage Vds_ref and a drain-source voltage Vds of the power transistor MN. The selected reference voltage Vds_ref is provided at the output of a multiplexer 10. Specifically, the multiplexer 10 passes one of four different reference voltages Vds(ref1), Vds(ref2), Vds(ref3), Vds(ref4) as the output selected reference voltage Vds_ref based on a two-bit signal formed by single-bit selection signals Sel1, Sel2. The selection signal Sel1 is generated by the first selection circuit 13 , and the selection signal Sel2 is generated by the second selection circuit 23 .

[0028] The first selection circuit 13 includes a switch Sw1 connected between the output of the current source 15 and the node N1. The switch Sw1 is controlled by the output of the comparator 14, which asserts its output (to close the switch Sw1) when the input signal IN is greater than the reference voltage Vref. The switch Sw2 is connected between the node N1 and the ground, wherein the switch Sw2 is controlled by the output of the inverter 18, which inverts the input signal IN. Therefore, in general, when the input signal IN is greater than the reference voltage Vref, the switch Sw1 is closed (and the switch Sw2 is opened), and when the input signal IN is at a logic low, the switch Sw2 is closed (and the switch Sw1 is opened). The comparator 16 has its output connected to the latch 17, and its output is valid when the voltage at N1 is greater than the reference voltage Vref. The selection signal Sel1 is the output of the latch 17; therefore, when the output of the comparator 16 is asserted, the selection signal Sel1 is asserted, and when the output of the comparator 16 is deasserted, the selection signal Sel1 is deasserted.

[0029] Capacitor C1 is connected between node N1 and ground. Instead of C1, a first pull-up resistor Rpu1 (e.g., 220 kΩ) may be connected between the input signal IN and node N1, or a first pull-down resistor Rpd1 (e.g., 10 kΩ) may be connected between ground and node N1 to statically set the level of V1.

[0030] The second selection circuit 23 includes a switch Sw3 connected between the output of the current source 25 and the node N2. The switch Sw3 is controlled by the output of the comparator 24, and when the input signal IN is greater than the reference voltage Vref, the comparator 24 makes its output valid (to close the switch Sw3). The switch Sw4 is connected between the node N2 and the ground, wherein the switch Sw4 is controlled by the output of the inverter 28, and the inverter 28 inverts the input signal IN. Therefore, in general, when the input signal IN is greater than the reference voltage Vref, the switch Sw3 is closed (and the switch Sw4 is opened), and when the input signal IN is at a logic low, the switch Sw4 is closed (and the switch Sw3 is opened). The comparator 26 has its output connected to the latch 27, and makes its output valid when the voltage at N2 is greater than the reference voltage Vref. The selection signal Sel2 is the output of the latch 27; therefore, when the output of the comparator 26 is made valid, the selection signal Sel2 is made valid, and when the output of the comparator 26 is invalid, the selection signal Sel2 is invalid.

[0031] Capacitor C2 is connected between node N2 and ground. Instead of C2, a second pull-up resistor Rpu2 (e.g., 220 kΩ) may be connected between the input signal IN and node N2, or a second pull-down resistor Rpd2 (e.g., 10 kΩ) may be connected between ground and node N2 to statically set the level of V2.

[0032] The difference between the second selection circuit 23 and the first selection circuit 13 is the value of the capacitances C1 and C2, specifically, C1 is smaller than C2. The purpose for this will be described below.

[0033] Now, refer to Figure 3 Operation is described. Turn-on occurs at time T1, and the surge output current Iout flows into the load 6. At the same time, the input signal IN rises to a logic high. At this instant, both voltages V1 and V2 are less than Vref, causing the outputs of comparators 16 and 26 to remain at a logic low. This state is stored by latches 17 and 27. Therefore, both selection signals Sel1 and Sel2 are logic zero. This configures the multiplexer 10 to select its first input, thereby relaying the voltage Vds(ref1) as Vds_ref to the non-inverting input of the error amplifier 9.

[0034] At the instant that turn-on occurs, the drain-source voltage Vds of the transistor MN is less than Vds_ref. The error amplifier 9, which detects this difference, makes the control signal CTRL valid, becoming a logic high level, without limiting the operation of the driver 8. In response to the logic high input signal IN, the driver 8 activates the transistor MN, thereby allowing a high surge current to act as the output current Iout. However, shortly after T1, the surge causes the drain-source voltage Vds of the transistor MN to rise to a level greater than Vds_ref (at this time Vds(ref1)). As a result, the error amplifier 9 invalidates the control signal CTRL, thereby modifying the operation of the driver 8 by modifying the gate-source voltage of the transistor MN to limit the current through the transistor MN. This ensures that the output current Iout does not exceed a predefined first current limit (e.g., 8.0A). As the capacitive load 6 charges, its increased voltage causes a decrease in the Vds of the transistor MN, which can be seen shortly after the high surge current is limited and before T2. Figure 3 Clearly seen in.

[0035] In parallel, the logic high state of input signal IN causes comparators 14 and 24 to validate their outputs. This action closes switches Sw1 and Sw3. Inverters 18 and 28, which invert the state of input IN, invalidate their outputs, which opens switches Sw2 and Sw4. This allows current sources 15 and 25 to conduct current to nodes N1 and N2, thereby starting the charging of capacitors C1 and C2. As a result, the voltages V1 and V2 at these nodes rise. Due to the smaller size of capacitor C1 compared to C2, capacitor C1 charges faster than C2, and V1 increases faster than V2.

[0036] By time T2, V1 has risen to be greater than Vref. In response, comparator 16 asserts its output (later stored by latch 17), causing select signal Sel1 to switch to logic high. This action changes the selection of multiplexer 10 to its second input, thereby now forwarding Vds(ref2) to error amplifier 9 as Vds_ref. As a result, the current limit of Iout is set to a second lower value (e.g., 1.3A or 2.5A). It is observed that, due to the previous reduction in Vds, Iout remains less than this second current limit, thereby steadily decreasing as Vds continues to decrease. At the same time, V2 has not yet exceeded Vref, so Sel2 remains invalid.

[0037] The charging process of capacitors C1 and C2 continues due to the uninterrupted current from sources 15 and 25. By time T3, V2 eventually exceeds Vref. Comparator 26, sensing this change, makes its output valid. This state is stored by latch 27, causing Sel2 to switch to logic high. This transition causes multiplexer 10 to select its third input, thereby sending Vds (ref3) as Vds_ref to error amplifier 9. Therefore, the output current Iout is now limited to a third or even lower current limit (e.g., 0.7A). In addition, due to the previously described reduction in Vds, Iout remains less than the threshold, causing its amplitude to continue to decrease as Vds further decreases.

[0038] In many electronic systems, especially those using capacitive loads, managing inrush current is of concern for maintaining both performance and life of components. The power system 5 provides various advantages. First, it provides automatic conversion between different current limit levels, thereby eliminating the use of external control system intervention. This autonomous behavior not only simplifies the firmware running in the control system, but also permits the selection of a more cost-effective control system with lower computing power. Secondly, the power system 5 provides configurability of the startup time window for each current limit level, thereby allowing adaptability to different system conditions. Finally, it provides fast and safe charging for capacitive loads, thereby finding a balance between system responsiveness and protection. The initial high current limit helps this fast charging stage. However, continuing with such a high current may endanger components or cause unwelcome system behavior. As the system transitions to a lower current limit, potential risks such as overheating, electromagnetic interference or power supply stress are mitigated. Therefore, the power system 5 disclosed herein combines the benefits of fast response time with the protection of system components.

[0039] It will be apparent that modifications and variations may be made to what is described and illustrated herein without departing from the scope of the present disclosure.

[0040] The present disclosure is intended to cover configurations that include more than two selection circuits 13 and 23. Indeed, it is contemplated that additional selection circuits may be incorporated into the system to generate additional selection signals. By utilizing the addition of these signals, a multiplexer 10 may be used with a greater number of inputs, not just the current four. This provides the flexibility to customize the power management system for various applications where a greater number of current limit levels are desired. It is also understood that the timing between transitions to these different current limit levels may be precisely adjusted by varying the capacitance value of the respective capacitor linked to each individual selection circuit. This capacitive adjustment provides for fine-tuning of the system response to suit a particular application, thereby providing both fast and safe charging operation.

[0041] Although the present disclosure has been described with a limited number of embodiments, those skilled in the art having benefit of the present disclosure may conceive of other embodiments that do not depart from the scope of the disclosure. In addition, those skilled in the art may conceive of embodiments that represent various combinations of the embodiments disclosed herein made in various ways.

Claims

1. A power management system, comprising: a power transistor coupled between a power source and a load; a driver circuit configured to drive the power transistor in response to an input signal; an error amplifier configured to generate a control signal based on a comparison between a selected reference voltage and a drain-source voltage of the power transistor, the control signal controlling the driver circuit; a multiplexer coupled to provide the selected reference voltage to the error amplifier, the multiplexer configured to pass one of a plurality of different reference voltages as the selected reference voltage based on a first selection signal and a second selection signal; a first selection circuit coupled to a first capacitor, wherein the first selection circuit is configured to charge the first capacitor in response to the input signal and to generate the first selection signal based on a first voltage across the first capacitor; as well as A second selection circuit is coupled to the second capacitor, wherein the second selection circuit is configured to charge the second capacitor in response to the input signal and to generate the second selection signal based on a second voltage across the second capacitor.

2. The power management system of claim 1, wherein the first selection circuit comprises a first comparator, the first comparator being configured to enable an output of the first comparator when the first voltage across the first capacitor is greater than the reference voltage, thereby enabling the first selection signal.

3. The power management system of claim 1 , wherein the second selection circuit comprises a second comparator, the second comparator being configured to enable an output of the second comparator when the second voltage across the second capacitor is greater than the reference voltage, thereby enabling the second selection signal. 4 . The power management system of claim 1 , further comprising a first current source associated with the first selection circuit, the first current source configured to provide current to the first capacitor in response to the input signal being active. 5 . The power management system of claim 4 , wherein the first selection circuit further comprises a first switch selectively coupled between an output of the first current source and the first capacitor, wherein the first switch is controlled based on the input signal.

6. The power management system of claim 1, further comprising a second current source associated with the second selection circuit, the second current source configured to provide current to the second capacitor in response to the input signal being active.

7. The power management system of claim 6, wherein the second selection circuit further comprises a second switch selectively coupled between an output of the second current source and the second capacitor, wherein the second switch is controlled based on the input signal.

8. A method for managing power in a system, the method comprising: receiving an input signal at a driver circuit; driving a power transistor using the driver circuit and based on the received validity of the input signal, the power transistor being coupled between a power source and a load; comparing a selected reference voltage to a drain-source voltage of the power transistor; generating the control signal based on the comparison to modify operation of the driver circuit when the drain-source voltage is less than the selected reference voltage; selecting the selected reference voltage from one of a plurality of different reference voltages based on a first selection signal and a second selection signal; In response to the input signal, charging the first capacitor via the first selection circuit; generating the first selection signal based on a first voltage across the first capacitor; In response to the input signal, charging the second capacitor via a second selection circuit; as well as The second selection signal is generated based on a second voltage across the second capacitor.

9. The method of claim 8, wherein generating the first selection signal comprises: The first voltage across the first capacitor is compared to a reference voltage, and the first selection signal is asserted when the first voltage is greater than the reference voltage.

10. The method of claim 8, wherein generating the second selection signal comprises: The second voltage across the second capacitor is compared to a reference voltage, and the second selection signal is asserted when the second voltage is greater than the reference voltage.

11. The method of claim 8, further comprising charging the first capacitor using a first current source associated with the first selection circuit when the input signal is valid. 12 . The method of claim 11 , further comprising controlling a first switch based on the input signal to facilitate charging of the first capacitor, the first switch being coupled between an output of the first current source and the first capacitor.

13. The method of claim 8, further comprising charging the second capacitor using a second current source associated with the second selection circuit when the input signal is valid.

14. The method of claim 13, further comprising controlling a second switch based on the input signal to facilitate charging of the second capacitor, the second switch selectively coupled between an output of the second current source and the second capacitor.

15. A power management system, comprising: a power transistor coupled between a power source and a load; a driver circuit configured to drive the power transistor in response to an input signal; an error amplifier configured to generate a control signal based on a comparison between a selected reference voltage and a drain-source voltage of the power transistor, the control signal controlling the driver circuit; a multiplexer coupled to provide the selected reference voltage to the error amplifier, the multiplexer configured to pass one of a plurality of different reference voltages as the selected reference voltage based on a select input; A selection circuit is coupled to the capacitor and is configured to charge the capacitor in response to the input signal, and is further configured to generate the selection input based on a voltage across the capacitor.

16. The power management system of claim 15, wherein the selection circuit comprises a comparator configured to assert an output of the comparator, thereby asserting the selection input, when the voltage across the capacitor is greater than the reference voltage.

17. The power management system of claim 16, further comprising a current source associated with the selection circuit, the current source configured to provide current to the capacitor in response to the input signal being active.

18. The power management system of claim 4, wherein the selection circuit further comprises a first switch selectively coupled between an output of the current source and the capacitor, wherein the first switch is controlled based on the input signal.

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