Switching power supply and control circuit thereof

Abstract

The invention provides a switching power supply and a control circuit thereof. A first voltage generation circuit generates a first reference voltage according to an output voltage and an error amplification signal; the capacitor is charged by the second voltage generation circuit according to the input voltage, the charging time of the capacitor is controlled by using a clock signal, and a comparison signal is obtained at the first end of the capacitor; the comparison circuit compares the comparison signal with the first reference voltage to generate a pulse width modulation signal, and the second terminal voltage of the capacitor is equal to the second reference voltage when the load is larger than a load threshold value, is positively correlated with the error amplification signal when the load is smaller than the load threshold value, and is negatively correlated with the difference value between the third reference voltage and the first feedback signal; according to the scheme, self-adaptive adjustment of the duty ratio of the system can be achieved, it is ensured that the switching frequency of the system is always above the audio frequency, energy transmitted by the system to the rear stage can exactly meet the requirement of the rear stage in the light load / ultra-light load process, and power consumption is made to be the lowest.

Description

Technical Field

[0001] The present application relates to the technical field of switching power supplies, and in particular to a switching power supply and a control circuit thereof. Background Art

[0002] Switching power supplies are widely used in the power supply field because of their high efficiency. However, when the load becomes lighter, in order to continue to ensure the switching conversion efficiency, they generally choose to enter the spread spectrum mode. In the spread spectrum mode, the frequency of the switching action is reduced to reduce the loss of the switch itself. When the switching frequency of the switching power supply is further reduced, the switching frequency will enter the audio range. In some applications, the switching power supply noise in this audio range can be heard by the human ear (the human ear can hear vibrations in the frequency range of 20Hz~20KHz), generating unnecessary audio noise.

[0003] In order to prevent the chip from producing such audible sounds, the switching action is usually forced to maintain a frequency of more than 20kHz. However, how to ensure that the switching frequency is above 20kHz without causing the energy transmitted to the output end to be too high, and how to minimize the additional energy consumption for this purpose, is the main pursuit of solving this problem. Summary of the invention

[0004] In order to solve the above technical problems, the present application provides a switching power supply and a control circuit thereof, which aims to ensure that the system switching frequency is above the audio frequency, and at the same time achieve that the energy transmitted to the subsequent stage under light load / ultra-light load just meets the needs of the subsequent stage, so as to minimize power consumption.

[0005] According to a first aspect of the present application, a control circuit of a switching power supply is provided, comprising: An error amplification circuit generates an error amplification signal according to a first feedback signal representing an output voltage and a first reference voltage; A mode selection circuit generates an audio frequency cancellation enable signal according to a load state, wherein the audio frequency cancellation enable signal is in a valid state when the load is less than a preset load threshold, and is in an invalid state when the load is greater than the preset load threshold; a first voltage generating circuit, for generating a first reference voltage according to the first feedback signal and the error amplified signal, wherein the first reference voltage is equal to the sum of the voltage values ​​of the first feedback signal and the error amplified signal; a second voltage generating circuit, which charges the capacitor according to a second feedback signal representing the input voltage, and controls the charging time of the capacitor using a clock signal to obtain a comparison signal at a first end of the capacitor, wherein a second end of the capacitor is coupled to a charging reference node; A comparison circuit, which compares the comparison signal with the first reference voltage to generate a pulse width modulation signal, wherein the pulse width modulation signal is used to control the switching state of the main power tube in the switching power supply; Wherein, when the audio cancellation enable signal is invalid, the voltage value of the charging reference node is equal to the voltage value of the second reference voltage; When the audio cancellation enable signal is valid, the voltage value of the charging reference node is positively correlated with the error amplification signal and negatively correlated with the difference between a third reference voltage and the first feedback signal, and the third reference voltage is greater than the first reference voltage.

[0006] Optionally, the second voltage generating circuit converts the second feedback signal into a charging current based on a first resistor to charge the capacitor, and the product of the resistance of the first resistor and the capacitance of the capacitor is in direct proportion to the clock period of the clock signal; When the audio cancellation enable signal is invalid, the clock signal has a first clock frequency, and when the audio cancellation enable signal is valid, the clock signal has a second clock frequency, the first clock frequency is greater than the second clock frequency, and the second clock frequency is equal to the upper limit frequency of the audio range.

[0007] Optionally, the first voltage generating circuit further generates a second reference voltage according to the error amplified signal, and the second reference voltage is positively correlated with the error amplified signal; The second voltage generating circuit comprises: an audio frequency cancellation adjustment unit, for generating a first audio frequency cancellation adjustment voltage proportional to the difference between the third reference voltage and the first feedback signal according to the difference between the third reference voltage and the first feedback signal; a subtraction unit, performing subtraction processing on the second reference voltage and the first audio cancellation adjustment voltage to obtain a second audio cancellation adjustment signal; a selecting unit, receiving the audio frequency cancellation enable signal, the second audio frequency cancellation adjustment signal and the second reference voltage, and configured to output the second reference voltage to obtain a voltage value provided to the charging reference node when the audio frequency cancellation enable signal is invalid, or, when the audio frequency cancellation enable signal is valid, add the second audio frequency cancellation adjustment signal and the second reference voltage and output the resultant addition to obtain a voltage value provided to the charging reference node.

[0008] Optionally, the audio cancellation adjustment unit converts the difference between the third reference voltage and the first feedback signal into a first audio cancellation adjustment current based on a resistive element, and generates the first audio cancellation adjustment voltage based on the reference current and the first audio cancellation adjustment current; The third reference voltage is equal to the sum of the first reference voltage and a preset bias voltage.

[0009] Optionally, the control circuit further includes: The auxiliary pull-down circuit is used to provide an auxiliary pull-down current at the output end of the switching power supply to pull down the output voltage when the first audio cancellation adjustment current is greater than the reference current and the first feedback signal is greater than the third reference voltage.

[0010] Optionally, the first voltage generating circuit includes: a first voltage-current conversion unit, converting the error amplified signal into a first current signal based on a fifth resistor and a sixth resistor connected in series; a second voltage-current conversion unit, converting the first feedback signal into a second current signal based on a third resistor; a first current mirror and a second current mirror, wherein the first current mirror is used to copy the first current signal to a fourth resistor, and the second current mirror is used to copy the second current signal to the fourth resistor to obtain the first reference voltage on the fourth resistor; The first voltage generating circuit obtains the second reference voltage on the sixth resistor based on the first current signal; The resistance ratio of the fifth resistor to the sixth resistor is 1-n:n, where n is greater than 0 and less than 1.

[0011] Optionally, the audio frequency adjustment unit includes: A first current source and a first transistor coupled in series between a power supply terminal and a reference ground, wherein the first current source provides the reference current; a first operational amplifier, having a first input terminal receiving the first feedback signal, a second input terminal receiving the third reference voltage, and an output terminal coupled to the control terminal of the first transistor; The cancellation audio frequency adjustment unit outputs the first cancellation audio frequency adjustment voltage at a common connection node of the first current source and the first transistor.

[0012] Optionally, the subtraction unit comprises: a third voltage-current conversion unit, converting the first audio cancellation adjustment voltage into a third current signal based on a seventh resistor; a fourth voltage-current conversion unit, configured to convert the second reference voltage into a fourth current signal based on an eighth resistor; a third current mirror, used for copying the third current signal to an output end of the fourth voltage-current conversion unit; a fourth current mirror, wherein the current input branch is coupled to the output end of the fourth voltage-current conversion unit, The subtraction unit generates a difference current between the fourth current and the third current on a current input branch of the fourth current mirror, and generates the second audio cancellation adjustment signal on a current output branch of the fourth current mirror; And, the selection unit includes: The ninth resistor; A second transistor, coupled between the current output branch of the fourth current mirror and the first end of the ninth resistor, wherein a control end of the second transistor receives an inverted signal of the audio cancellation enable signal; a first voltage buffer, configured to provide the second reference voltage to the second end of the ninth resistor; The second voltage buffer has an input terminal coupled to the first terminal of the ninth resistor and an output terminal coupled to the charging reference node.

[0013] Optionally, the subtraction unit comprises: A subtractor, wherein a first input terminal receives the second reference voltage, a second input terminal receives the first audio cancellation adjustment voltage, and the subtractor performs a difference operation on the second reference voltage and the first audio cancellation adjustment voltage and then outputs the second audio cancellation adjustment signal; And, the selection unit includes: An adder, wherein the first input terminal receives the second audio cancellation adjustment signal through the third transistor, the second input terminal receives the second reference voltage, the output terminal is coupled to the charging reference node, and the control terminal of the third transistor receives the inverted signal of the audio cancellation enable signal.

[0014] Optionally, the auxiliary pull-down circuit includes: a second current source and a fourth transistor coupled in series between a power supply terminal and a reference ground, wherein the second current source provides the reference current; a fifth current mirror, a current input branch coupled to a common connection node of the second current source and the fourth transistor; a sixth current mirror, wherein a current input branch is coupled to a current output branch of the fifth current mirror, and a current output branch of the sixth current mirror is coupled to an output terminal of the switching power supply, The auxiliary pull-down circuit generates the auxiliary pull-down current on the current output branch of the sixth current mirror.

[0015] According to a second aspect of the present application, a switching power supply is provided, comprising: a control circuit as described in any embodiment of the present application.

[0016] The beneficial effects of this application include at least:

[0017] In the embodiment of the present application, a first voltage generating circuit is used to generate a first reference voltage according to an output voltage and an error amplification signal, a second voltage generating circuit is used to charge a capacitor according to an input voltage, and a clock signal is used to control the charging time of the capacitor to obtain a comparison signal at a first end of the capacitor, and then a pulse width modulation signal is generated by comparing the comparison signal with the first reference voltage. In this process, when the load is greater than a preset load threshold, the voltage at the second end of the capacitor is adjusted to be equal to the second reference voltage, and when the load is less than the preset load threshold, the voltage at the second end of the capacitor is adjusted to be positively correlated with the error amplification signal and negatively correlated with the difference between the third reference voltage (the third reference voltage is greater than the first reference voltage) and the first feedback signal. Compared with the prior art, the solution of the present application can realize adaptive adjustment of the system duty cycle, ensure that the system switching frequency is always above the audio frequency, and when the load is less than the preset load threshold (such as light load / ultra-light load) and enters the audio frequency elimination mode, since the voltage at the second end of the capacitor is negatively correlated with the difference between the third reference voltage and the first feedback signal, the duty cycle of the generated pulse width modulation signal can be positively correlated with the difference between the third reference voltage and the first feedback signal, and then the system duty cycle can be adaptively reduced when the output voltage increases, so as to meet the energy transmission to the subsequent stage with the minimum duty cycle in the audio frequency elimination mode, so that the energy transmitted by the system to the subsequent stage just meets the demand of the subsequent stage, the system power consumption is lowest, the output ripple is smallest, and the efficiency is highest.

[0018] In a further preferred embodiment, when the system is at the limit minimum duty cycle but still cannot meet the demand, the auxiliary pull-down circuit can adaptively turn on the auxiliary pull-down current on the chip to pull down the output voltage, thereby ensuring the highest efficiency of the system and achieving overvoltage protection for the output voltage.

[0019] It should be noted that the above general description and the following detailed description are merely exemplary and explanatory and do not limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of an embodiment of a switching power supply provided according to an embodiment of the present application is shown; Figure 2 Show Figure 1 A schematic diagram of an embodiment of a first voltage generating circuit; Figure 3 Show Figure 1 A schematic diagram of an embodiment of a voltage-current conversion unit; Figure 4 Show Figure 1 Schematic diagram of an embodiment of a mid-cancellation audio frequency adjustment unit and an auxiliary pull-down circuit; Figure 5 Show Figure 1 A schematic diagram of an embodiment of a subtraction unit and a selection unit; Figure 6 Show Figure 1 Schematic diagram of an embodiment of the overall structure of the control circuit. DETAILED DESCRIPTION

[0021] In order to facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive.

[0022] References to "one embodiment" or "some embodiments" etc. described in this specification mean that a particular feature, structure or characteristic described in conjunction with the embodiment is included in one or more embodiments of the present application. Thus, the phrases "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear at different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0023] In the description of the present application, the words "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment described as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments. "Coupled" in this article is a description of the connection relationship between associated objects. For example, A is coupled to B, which can indicate a direct connection between A and B, or an indirect connection between A and B through other devices / units / modules. In addition, in order to facilitate the clear description of the technical solutions of the embodiments of the present application, words such as "first" and "second" are used to distinguish between identical or similar items with substantially the same functions and effects. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not limit them to be necessarily different.

[0024] In addition, the same figure marks in the figures represent the same or similar structures, and thus their repeated description will be omitted. That is, the various parts in this specification are described in a combination of parallel and progressive manners, and each part focuses on the differences from other parts. The same or similar parts between the various parts can be referenced to each other.

[0025] Figure 1 FIG. 1 is a schematic diagram of an embodiment of a switching power supply provided in an embodiment of the present application. It should be noted that: Figure 1Only a buck-type switching power supply topology is shown as an example. The technical solution of the present application can also be applied to other switching power supply topologies such as boost, boost-buck, SWITCH CAP, forward, flyback, full-bridge or push-pull topologies.

[0026] exist Figure 1 In the example shown, the switching power supply includes: a main power tube Q1 , a rectifier tube Q2 , an inductor L, an output capacitor Co and a control circuit 100 .

[0027] The main power tube Q1 is coupled between the application terminal of the input voltage Vin and the switch node SW, and the rectifier tube Q2 is coupled between the switch node SW and the reference ground. Figure 1 Only the main power tube Q1 is an NMOS transistor and the rectifier tube Q2 is a diode as an example. The technical solution of the present application can also be applied to the scenario where the main power tube Q1 is a PMOS transistor and the rectifier tube Q2 is a synchronous rectifier tube.

[0028] A first terminal of the inductor L is coupled to the switch node SW, a second terminal of the inductor L is coupled to a first terminal of the output capacitor Co, and a second terminal of the output capacitor Co is coupled to the reference ground. The switching power supply generates an output voltage Vout at the first terminal of the output capacitor Co.

[0029] The control circuit 100 is coupled to the control terminal of the main power tube Q1 and is used to provide a pulse width modulation signal PWM to the main power tube Q1 , and control the switching state of the main power tube Q1 through the pulse width modulation signal PWM to achieve conversion from the input voltage Vin to the output voltage Vout.

[0030] In this embodiment, the control circuit 100 further includes: an error amplifier circuit 110 , a mode selection circuit 120 , a first voltage generation circuit 130 , a second voltage generation circuit 140 and a comparison circuit COMP.

[0031] The error amplifier circuit 110 is used to generate an error amplification signal Veao according to a first feedback signal k·Vout representing an output voltage Vout and a first reference voltage Vref, wherein k is greater than 0 and less than 1. The mode selection circuit 120 is used to generate an audio cancellation enable signal ENOOA according to a load state, wherein the audio cancellation enable signal ENOOA is in a valid state (such as a high level state) when the load is less than a preset load threshold, and is in an invalid state (such as a low level state) when the load is greater than the preset load threshold. The first voltage generation circuit 130 is used to generate a first reference voltage Vc according to the first feedback signal k·Vout and the error amplification signal Veao, wherein the first reference voltage Vc is equal to the sum of the voltage values ​​of the first feedback signal k·Vout and the error amplification signal Veao. The second voltage generation circuit 140 is used to charge the capacitor C1 according to the second feedback signal k·Vin representing the input voltage Vin, and to control the charging time of the capacitor C1 using the clock signal CLK, so as to obtain a comparison signal V at the first end of the capacitor C1. RAMP The second end of the capacitor C1 is coupled to the charging reference node to receive the charging reference voltage Vo. The comparison circuit COMP is used to compare the comparison signal V RAMP The voltage is compared with the first reference voltage Vc to generate a pulse width modulation signal PWM.

[0032] When the audio cancellation enable signal ENOOA is invalid, the voltage value of the charging reference node (ie, the charging reference voltage Vo) is equal to the second reference voltage V DC voltage value; when the audio elimination enable signal ENOOA is valid, the voltage value of the charging reference node (i.e., the charging reference voltage Vo) is positively correlated with the error amplification signal Veao, and is negatively correlated with the difference between the third reference voltage (denoted as Vref2) and the first feedback signal k·Vout. The third reference voltage Vref2 is greater than the first reference voltage Vref. For example, the third reference voltage Vref2 is equal to the sum of the first reference voltage Vref and a preset bias voltage (denoted as Vos).

[0033] In some embodiments, the output voltage Vout can be sampled by resistor voltage division sampling to obtain a first feedback signal k·Vout. Similarly, the input voltage Vin can be sampled by resistor voltage division sampling to obtain a second feedback signal k·Vin, where k is the resistor voltage division ratio.

[0034] refer to Figure 2The error amplifier circuit 110 includes, for example, an error amplifier EA, a first input terminal of the error amplifier EA receives a first reference voltage Vref, a second input terminal of the error amplifier EA receives a first feedback signal k·Vout, and the error amplifier EA performs error amplification processing on the first feedback signal k·Vout and the first reference voltage Vref and outputs an error amplified signal Veao. The specific working principles of the error amplifier circuit 110 and the mode selection circuit 120 can be understood by referring to the existing solutions.

[0035] In this embodiment, the first voltage generating circuit 130 further generates a second reference voltage V according to the error amplified signal Veao. B , the second reference voltage V B Positively correlated with the error amplified signal Veao.

[0036] In specific implementation, in some embodiments, the first voltage generating circuit 130 generates the first reference voltage Vc and the second reference voltage Vc using a plurality of voltage-current conversion units and a plurality of current mirrors. B In these embodiments, the first voltage generating circuit 130 includes, for example, a first voltage-current conversion unit, a second voltage-current conversion unit, a first current mirror and a second current mirror. Figure 2 As shown, the first voltage-current conversion unit includes a voltage buffer BUF6, a transistor M16, a resistor R1 and a resistor R2, the second voltage-current conversion unit includes a voltage buffer BUF7, a transistor M19 and a resistor R3, the transistor M17 and the transistor M18 constitute a first current mirror, the transistor M20 and the transistor M21 constitute a second current mirror, and the current output branches of the first current mirror and the second current mirror are both coupled to the reference ground through the resistor R4, wherein the first voltage-current conversion unit converts the error amplification signal Veao into a first current signal (i.e., the current flowing through the transistor M16) based on the resistance unit (including the resistor R1 and the resistor R2 connected in series), the second voltage-current conversion unit converts the first feedback signal k·Vout into a second current signal (i.e., the current flowing through the transistor M19) based on the resistor R3, the first current mirror is used to copy the first current signal to the resistor R4, and the second current mirror is used to copy the second current signal to the resistor R4, so as to obtain the first reference voltage Vc on the fourth resistor R4. Furthermore, the first voltage generating circuit 130 obtains a second reference voltage V on the resistor R2 based on the first current signal. B , wherein the resistance ratio of the resistor R1 to the resistor R2 is 1-n:n, where n is greater than 0 and less than 1.

[0037] Exemplarily, the size ratio of transistor M17 to transistor M18 is 1:1, the size ratio of transistor M20 to transistor M21 is 1:1, the resistance value of resistor R3 and resistor R4 is the same, for example, both are R, the resistance value of resistor R1 is (1-n)R, and the resistance value of resistor R2 is nR. Of course, in practical applications, the size ratio of each transistor in the first voltage generating circuit 130 and the resistance value of each resistor can also be optimized and modified according to requirements.

[0038] In addition, in other embodiments of the present application, the first voltage generating circuit 130 may also directly use an adder circuit and a multiplier circuit to generate the first reference voltage Vc and the second reference voltage V B .

[0039] In this embodiment, the second voltage generating circuit 140 specifically includes: a charging current generating unit 141, an audio frequency elimination adjusting unit 142, a subtraction unit 143, a selection unit 144, a capacitor C1, and a transistor M15. Among them, the input end of the charging current generating unit 141 receives the second feedback signal k·Vin, and the output end is coupled to the first end of the capacitor C1, the transistor M15 is connected in parallel with the capacitor C1, and the control end of the transistor M15 receives the clock signal CLK. The first input end of the audio frequency elimination adjusting unit 142 receives the first feedback signal k·Vout, the second input end of the audio frequency elimination adjusting unit 142 receives the first reference voltage Vref, the output end of the audio frequency elimination adjusting unit 142 is coupled to the first input end of the subtraction unit 143, and the second input end of the subtraction unit 143 receives the second reference voltage V B The output terminal of the subtraction unit 143 is coupled to the first input terminal of the selection unit 144, and the second input terminal of the selection unit 144 receives the second reference voltage V DC , the output end of the selection unit 144 is coupled to the second end of the capacitor C1.

[0040] In the second voltage generating circuit 140, the charging current generating unit 141 converts the second feedback signal k·Vin into a charging current and then charges the capacitor C1. The audio cancellation adjusting unit 142 generates a first audio cancellation adjusting voltage Vooat proportional to the difference between the third reference voltage Vref2 and the first feedback signal k·Vout. The subtracting unit 143 B The selection unit 144 is used to output the second reference voltage V when the audio cancellation enable signal ENOOA is invalid. DC To obtain the voltage value Vo provided to the charging reference node, or, when the audio cancellation enable signal ENOOA is valid, the second audio cancellation adjustment signal and the second reference voltage V DCAfter the addition process is performed, the voltage value Vo provided to the charging reference node is obtained.

[0041] In a specific implementation, the charging current generating unit 141 generates the charging current by, for example, using a voltage-current conversion unit and a current mirror. Figure 3 In the example shown, the voltage-current conversion unit in the charging current generating unit 141 includes: a voltage buffer BUF4, a transistor M12 and a resistor R5. The transistor M13 and the transistor M14 constitute a current mirror in the charging current generating unit 141. The current output branch of the current mirror is coupled to the first end of the capacitor C1. The charging current generating unit 141 converts the second feedback signal k·Vin into a current signal based on the resistor R5. The current mirror copies the current signal and outputs a charging current to the first end of the capacitor C1, thereby charging the capacitor C1.

[0042] Furthermore, transistor M15 is, for example, an NMOS transistor, which is turned on during the high level period of the clock signal CLK to quickly discharge the capacitor C1, and is turned off during the low level period of the clock signal CLK, so that the charging current can effectively charge the capacitor C1, that is, the voltage difference across the capacitor C1 can be raised.

[0043] In this embodiment, the clock period (denoted as Tsw) of the clock signal CLK is determined according to the actual application requirements. When setting the resistor R5 and the capacitor C1, the product of the resistance value (denoted as R) of the resistor R5 and the capacitance value (denoted as C) of the capacitor C1 can be set to be in direct proportion to the clock period Tsw of the clock signal CLK, preferably equal to the clock period Tsw of the clock signal CLK, that is, RC=Tsw. Furthermore, when the audio frequency elimination enable signal ENOOA is invalid, the clock signal CLK has a first clock frequency, and when the audio frequency elimination enable signal ENOOA is valid, the clock signal CLK has a second clock frequency, the first clock frequency is greater than the second clock frequency, and the second clock frequency is equal to the upper limit frequency of the audio range, for example, the second clock frequency is 20kHz.

[0044] The audio cancellation adjustment unit 142 converts the difference between the third reference voltage Vref2 and the first feedback signal k·Vout into a first audio cancellation adjustment current based on a resistive element, and generates a first audio cancellation adjustment voltage Vooa based on the reference current and the first audio cancellation adjustment current. Figure 4 In the example shown, the audio frequency adjustment unit 142 includes an operational amplifier OPA, a transistor M5, and a reference current source I B2, the first input terminal of the operational amplifier OPA receives the first feedback signal k·Vout, the second input terminal of the operational amplifier OPA receives the third reference voltage Vref2, the output terminal of the operational amplifier OPA outputs the difference signal between the third reference voltage Vref2 and the first feedback signal k·Vout, and at the same time, the output terminal of the operational amplifier OPA is coupled to the control terminal of the transistor M5, and the reference current source I B2 and transistor M5 are sequentially coupled in series between the power supply terminal VDD and the reference ground GND, and the reference current source I B2 Provides reference current (denoted as I B In this embodiment, the transistor M5 operates in the amplification region based on the output voltage of the operational amplifier OPA, and the audio cancellation adjustment unit 142 can convert the difference signal output by the operational amplifier OPA into a first audio cancellation adjustment current (i.e., a current flowing through the transistor M5) based on the transistor M5 operating in the amplification region, and then the audio cancellation adjustment unit 142 adjusts the reference current I B The difference between the first audio frequency cancellation adjustment current and the reference current source I B2 A first audio cancellation adjustment voltage Vooa is generated at the common connection node of the transistor M1 and the transistor M5.

[0045] exist Figure 4 In the example shown, the third reference voltage Vref2 received by the second input terminal of the operational amplifier OPA is obtained by adding the first reference voltage Vref to the bias voltage Vos. In other embodiments of the present application, the third reference voltage Vref2 received by the second input terminal of the operational amplifier OPA can also be directly provided by an independent reference voltage source.

[0046] In some embodiments, the subtraction unit 143 uses a plurality of voltage-current conversion units and a plurality of current mirrors to generate a first reference voltage Vc to form a second audio cancellation adjustment signal. In these embodiments, the subtraction unit 143 includes: a third voltage-current conversion unit, a fourth voltage-current conversion unit, a third current mirror, and a fourth current mirror, such as Figure 5 As shown, the third voltage-current conversion unit includes a voltage buffer BUF1, a transistor M6 and a resistor R6, the fourth voltage-current conversion unit includes a voltage buffer BUF2, a transistor M9 and a resistor R7, the transistor M7 and the transistor M8 constitute a third current mirror, the transistor M10 and the transistor M11 constitute a fourth current mirror, the current output branch of the third current mirror and the current input branch of the fourth current mirror are both coupled to the output end of the fourth voltage-current conversion unit, wherein the third voltage-current conversion unit converts the first audio cancellation adjustment voltage Vooa into a third current signal (i.e., a current flowing through the transistor M6) based on the resistor R6, and the fourth voltage-current conversion unit converts the second reference voltage V BThe fourth current signal is converted into a fourth current signal (i.e., the current flowing through the transistor M9), and the third current mirror copies the third current signal to the output end of the fourth voltage-current conversion unit. The current on the current output branch of the third current mirror and the current on the current input branch of the fourth current mirror are both branch currents. The fourth current signal output by the fourth voltage-current conversion unit is a main current. Then, the subtraction unit 143 generates a difference current signal between the fourth current and the third current on the current input branch of the fourth current mirror, and the fourth current mirror copies the difference current signal to its current output branch to generate a second audio cancellation adjustment signal. It can be understood that the second audio cancellation adjustment signal generated at this time is a current signal (which may be referred to as the second audio cancellation adjustment current in this article), and the voltage signal corresponding to the second audio cancellation adjustment signal (which may be referred to as the second audio cancellation adjustment voltage in this article) can be obtained after the current signal is subsequently processed into a voltage.

[0047] Exemplarily, the size ratio of transistor M7 to transistor M8 is 1:1, the size ratio of transistor M10 to transistor M11 is 1:1, and the resistance value of resistor R6 and resistor R7 is the same, for example, both are R. Of course, in practical applications, the size ratio of each transistor in the subtraction unit 143 and the resistance value of each resistor can also be optimized and modified according to requirements.

[0048] In some embodiments, the selection unit 144 uses a gate switch, a current-voltage conversion unit, and a plurality of voltage buffers to adjust the charging reference voltage Vo output to the charging reference node. Figure 5 As shown, the selection unit 144 includes: a transistor M22, a resistor R8, a voltage buffer BUF3 and a voltage buffer BUF5, wherein the voltage buffer BUF3 is used to adjust the second reference voltage V DC For cache output, the transistor M22 and the resistor R8 are coupled in sequence between the current output branch of the fourth current mirror in the subtraction unit 143 and the output end of the voltage buffer BUF3, the control end of the transistor M22 receives the inverted signal of the audio cancellation enable signal ENOOA, the input end of the voltage buffer BUF5 is coupled to the first end of the resistor R8 (i.e., the common connection node of the transistor M22 and the resistor R8), and the output end of the voltage buffer BUF5 is coupled to the charging reference node to provide a charging reference voltage Vo to the charging reference node.

[0049] Exemplarily, the resistance value of the resistor R8 is, for example, R. Of course, in practical applications, the resistance value of the resistor R8 can also be optimized and modified according to requirements.

[0050] In addition, in other embodiments of the present application, the subtraction unit 143 can also directly use the subtractor circuit to subtract the first audio frequency adjustment voltage Vooa from the second reference voltage V BThe difference operation is performed to obtain the second audio cancellation adjustment voltage. At this time, the first input terminal of the subtractor receives the second reference voltage V B The second input terminal of the subtractor receives the first audio frequency adjustment voltage Vooa, and the subtractor adjusts the second reference voltage V B After performing a difference operation with the first audio frequency elimination adjustment voltage Vooa, a second audio frequency elimination adjustment signal is output, and the second audio frequency elimination adjustment signal is a voltage signal.

[0051] On this basis, the selection unit 144 can also directly use the adder circuit to adjust the second audio frequency elimination voltage and the second reference voltage V CD The second audio cancellation adjustment voltage charging reference voltage Vo is obtained by performing a summation operation. At this time, the selection unit 144 includes a third transistor and an adder, the first input end of the adder receives the second audio cancellation adjustment voltage through the third transistor, and the second input end of the adder receives the second reference voltage V CD The output end of the adder is coupled to the charging reference node, and the control end of the third transistor receives the inverted signal of the audio elimination enable signal ENOOA.

[0052] In some preferred embodiments, the control circuit 100 further includes an auxiliary pull-down circuit 145, which is used to adjust the current to be greater than the reference current I B , and when the first feedback signal K·Vout is greater than the third reference voltage Vref2, an auxiliary pull-down current is provided at the output end of the switching power supply to pull down the output voltage Vout.

[0053] In specific implementation, the auxiliary pull-down circuit 145 uses a reference current source and a plurality of current mirrors to adaptively provide an auxiliary pull-down current. In these embodiments, Figure 4 As shown, the auxiliary pull-down circuit 145 includes: a reference current source I B1 , transistor M4, a fifth current mirror and a sixth current mirror, wherein the current source I B1 and transistor M4 are coupled in series between the power supply terminal VDD and the reference ground GND, and the reference current source I B1 Provides reference current I B The control end of transistor M4 is coupled to the output end of operational amplifier OPA, transistor M2 and transistor M3 form a fifth current mirror, transistor M0 and transistor M1 form a sixth current mirror, and the current input branch of the fifth current mirror is connected to the reference current source I B1 The auxiliary pull-down circuit 145 is coupled to the common connection node of the transistor M4, the current input branch of the sixth current mirror is coupled to the current output branch of the fifth current mirror, and the current output branch of the sixth current mirror is coupled to the output end of the switching power supply. The auxiliary pull-down circuit 145 generates an auxiliary pull-down current (i.e., the current flowing through the transistor M0) on the current output branch of the sixth current mirror.

[0054] In this embodiment, the reference current source I B1 and the reference current source I B2 have the same specifications, and the transistors M4 and M5 have the same specifications.

[0055] Exemplarily, the size ratio of the transistors M2 and M3 is 1:1, and the size ratio of the transistors M0 and M1 is M:1, where M is greater than 1. In some preferred embodiments, the value range of M can be 300 to 500. Of course, in actual applications, the proportional sizes of the transistors in the auxiliary pull-down circuit 145 can also be optimized and modified according to requirements so that the auxiliary pull-down circuit 145 can provide an appropriate auxiliary pull-down current.

[0056] For ease of understanding, Figure 6 a schematic diagram of an embodiment showing the overall structure of the Figure 1 control circuit is shown below. Referring to Figure 6 the working principle of the control circuit 100 disclosed in the embodiments of the present application will be described.

[0057] Combined with Figure 6 , when the clock signal CLK is at a high level, the transistor M15 is turned on, and the voltage drop across the capacitor C1 quickly drops to 0V. At this time, the comparison signal V RAMP is equal to the charging reference voltage Vo, that is, V RAMP =Vo. Since the charging reference voltage Vo is less than the first reference voltage Vc, that is, V RAMP <Vc, the comparison circuit COMP outputs a pulse-width modulation signal PWM with a low level, controlling the main power transistor Q1 in the switching power supply to turn off.

[0058] When the clock signal CLK is at a low level, the transistor M15 is turned off, and the charging current output via the transistor M14 starts to effectively charge the capacitor C1. At this time, there is: V RAMP =Vo + I14×t, where I14 represents the charging current output via the transistor M14, and t represents the charging time. As the voltage drop across the capacitor C1 increases, when it reaches V RAMP >Vc, the comparison circuit COMP outputs a pulse-width modulation signal PWM with a high level, controlling the main power transistor Q1 in the switching power supply to turn on. It can be seen that in this embodiment, the switching period of the pulse-width modulation signal PWM is equal to the clock period of the clock signal CLK, that is, the system switching frequency of the switching power supply is equal to the clock frequency of the clock signal CLK.

[0059] According to Figure 6 it can be obtained that the comparison signal V RAMP and the first reference voltage Vc respectively conform to the following formulas: (1), (2).

[0060] When the switching power supply operates in normal mode (i.e., the system load is greater than the preset load threshold), the audio cancellation enable signal ENOOA is in an invalid state (such as a low level state), at which time the transistor M22 is turned off, and the transistor M11 has no current output to the resistor R8. At this time, according to Figure 6 It can be obtained that the charging reference voltage Vo is equal to the second reference voltage V DC , that is, Vo = V A =V DC , further, assuming that the clock period of the clock signal CLK is T SW , then: t=D×T SW , D represents the switch duty cycle, and formula (2) can be transformed into: (3).

[0061] Assume that during the high level period of the clock signal CLK, the capacitor C1 is charged for a period of time t, so that the comparison signal V RAMP is equal to the charging reference voltage Vo, which causes the level state of the pulse width modulation signal PWM to flip. The charging time t at this time represents the low level time of the pulse width modulation signal PWM, that is, the conduction time of the main power tube Q1, and the duty cycle D represents the duty cycle of the pulse width modulation signal PWM. On this basis, based on the comparison signal V RAMP The principle that the level state of the pulse width modulation signal PWM is reversed when it is equal to the charging reference voltage Vo shows that when the audio cancellation enable signal ENOOA is in an invalid state, the duty cycle D of the pulse width modulation signal PWM conforms to the following formula: (4).

[0062] It can be seen that the duty cycle D can be modulated by adjusting the error amplification signal Veao in the system loop, thereby achieving the purpose of adjusting the output Vout. In other words, when the switching power supply operates in the normal mode, the control circuit 100 can realize adaptive adjustment of the duty cycle D of the pulse width modulation signal PWM.

[0063] Furthermore, when the system reaches a stable state, D = Vout / VIin. For ease of design, RC can be set to T SW , at this time, formula (2) can be transformed into: (5).

[0064] From formula (5), it can be seen that when the switching power supply system reaches a stable state, the error amplification signal Veao is equal to the second reference voltage V DC , namely Veao-VDC =0. This is equivalent to using the second reference voltage V DC The error amplified signal Veao is maintained at a stable voltage value, so that the control circuit 100 can provide an excellent response regulation space and achieve a fast response when facing a transient response.

[0065] When the switching power supply operates in the audio cancellation mode of light load / ultra-light load (i.e., when the system load is less than the preset load threshold), the audio cancellation enable signal ENOOA is in an effective state (e.g., a high level state), at which time the transistor M22 switches to an on state, and the transistor M11 outputs a second audio cancellation adjustment current to the resistor R8. At the same time, in order to ensure that the operating frequency of the system is higher than the audio audible to the human ear, the audio cancellation enable signal ENOOA is used to reduce the clock frequency of the clock signal CLK, and the clock frequency of the clock signal CLK can be adjusted to, for example, 20kHz at the lowest, and then when the audio cancellation enable signal ENOOA switches to an effective state, the clock signal CLK is triggered to send a clock pulse for resetting to start the switching cycle of the system.

[0066] In addition, it can be seen from the above description that when the system is in a stable state, the error amplified signal Veao will be stabilized or clamped at a suitable fixed voltage value, that is, the same as the second reference voltage V DC The same voltage value is used to ensure that the system can achieve fast transient response when jumping from ultra-light load to heavy load, that is, V DC =Veao.

[0067] On this basis, when the audio enable signal ENOOA is in a valid state, the comparison signal V RAMP Will conform to the following formula: (6)

[0068] Among them, I 11 represents the second audio cancellation adjustment current output by transistor M11, and according to Figure 6 So, the current I 11 It complies with the following formula: (7)

[0069] Wherein, n represents the voltage division ratio coefficient of the resistor R1 and the resistor R2, for example, n=75%, of course, n can also be other values. At the same time, the first audio frequency adjustment voltage Vooa meets the following expression: (8)

[0070] Among them, G Mrepresents the total transconductance of the operational amplifier OPA and the transistor M5, and Rooa represents the equivalent impedance of the output node of the first cancellation audio frequency adjustment voltage Vooa. Combining formula (7) and formula (8), we can get: (9).

[0071] Furthermore, by combining formula (6) and formula (9), we can obtain: (10).

[0072] On this basis, based on the comparison signal V RAMP It can be obtained from the principle that the level state of the pulse width modulation signal PWM is reversed when it is equal to the charging reference voltage Vo. When the audio cancellation enable signal ENOOA is in the effective state, by combining formula (1) and formula (10), it can be obtained that the duty cycle D of the pulse width modulation signal PWM meets the following formula: (11)

[0073] After deformation, we can get: (12)

[0074] Wherein, D0 represents the duty cycle of the input voltage Vin and the output voltage Vout in normal mode. It can be seen from formula (12) that after the system enters the audio cancellation mode, as the output voltage Vout increases, after the first feedback signal k*Vout is higher than the third reference voltage, namely, Vref+Vos, the duty cycle D of the pulse width modulation signal PWM will decrease accordingly, that is, the energy transmitted to the output end by the system in each clock cycle of the clock signal CLK will decrease accordingly. It can be understood that after the first audio cancellation adjustment voltage Vooa is adaptively adjusted to a suitable value, the energy transmitted to the output end by the system through each switching action will be exactly equal to the average consumption of the load, and the system loop enters a stable state. At this time, the output voltage Vout of the system meets the following formula: (13).

[0075] It should be noted that in the embodiment of the present application, the third reference voltage Vref2 is set to be equal to the sum of the first reference voltage Vref and the bias voltage Vos, which can appropriately raise the trigger condition for the system to enter the audio elimination adjustment strategy after the effective state of the audio elimination enable signal ENOOA is flipped, thereby avoiding the control strategy conflict between the audio elimination mode and the normal mode.

[0076] Furthermore, in the process of adjusting the audio frequency cancellation, by setting the second reference voltage V B , and the second reference voltage V BThe final audio cancellation adjustment signal is obtained by performing difference processing with the first audio cancellation adjustment voltage Vooa, which is equivalent to using the second reference voltage VB to set an upper limit threshold for the audio cancellation adjustment, thereby avoiding excessive increase of the audio cancellation adjustment voltage acting on the second end of the capacitor C1.

[0077] Furthermore, if the first audio frequency adjustment voltage Vooa is raised to the power supply voltage VDD, the current on the transistor M5 is greater than the reference current source I B2 The reference current I B , that is (Vref+Vos-kVout)·G M >I B , and the first feedback signal k*Vout is still higher than the third reference voltage Vref+Vos, indicating that under the minimum duty cycle state of the safety design, the average load consumption is still less than the minimum transmission energy. At this time, the operational amplifier OPA and transistors M0~M4 will be responsible for automatically turning on the adaptive auxiliary pull-down current to pull down the output voltage Vout, thereby reducing the output voltage Vout to prevent triggering the output overvoltage protection. Among them, since the currents on transistors M4 and M5 are the same, the current on transistor M4 will also be greater than the reference current source I B1 The reference current I B , which will generate a current flowing through transistor M3. After the current mirror, a corresponding auxiliary pull-down current (denoted as I0) will be generated on transistor M0, and the current I0 conforms to the following formula: (14).

[0078] It can be understood that by additionally pulling down the output voltage Vout through the auxiliary pull-down current I0, the output voltage Vout can be stabilized as shown in formula (13) after the system loop is stabilized.

[0079] In summary, the switching power supply control scheme provided in the embodiment of the present application can realize adaptive adjustment of the system duty cycle, ensure that the system switching frequency is always above the audio frequency, and after the load is less than the preset load threshold (such as light load / ultra-light load) and enters the audio frequency elimination mode, the system duty cycle can be adaptively reduced when the output voltage increases, so as to meet the energy transmission to the subsequent stage with the minimum duty cycle in the audio frequency elimination mode, so that the energy transmitted by the system to the subsequent stage just meets the needs of the subsequent stage, the system power consumption is lowest, the output ripple is smallest, and the efficiency is highest.

[0080] Furthermore, when the system is at the minimum duty cycle but still cannot meet the demand, the auxiliary pull-down circuit can adaptively turn on the auxiliary pull-down current on the chip to pull down the output voltage, thereby ensuring the highest efficiency of the system and achieving overvoltage protection for the output voltage.

[0081] Finally, it should be noted that: Obviously, the above embodiments are only examples for clearly explaining the present application, and are not intended to limit the implementation methods. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from this are still within the scope of protection of the present application.

Claims

1. A control circuit of a switching power supply, comprising: An error amplification circuit generates an error amplification signal according to a first feedback signal representing an output voltage and a first reference voltage; A mode selection circuit generates an audio frequency cancellation enable signal according to a load state, wherein the audio frequency cancellation enable signal is in a valid state when the load is less than a preset load threshold, and is in an invalid state when the load is greater than the preset load threshold; a first voltage generating circuit, for generating a first reference voltage according to the first feedback signal and the error amplified signal, wherein the first reference voltage is equal to the sum of the voltage values ​​of the first feedback signal and the error amplified signal; a second voltage generating circuit, which charges the capacitor according to a second feedback signal representing the input voltage, and controls the charging time of the capacitor using a clock signal to obtain a comparison signal at a first end of the capacitor, wherein a second end of the capacitor is coupled to a charging reference node; A comparison circuit, which compares the comparison signal with the first reference voltage to generate a pulse width modulation signal, wherein the pulse width modulation signal is used to control the switching state of the main power tube in the switching power supply; Wherein, when the audio cancellation enable signal is invalid, the voltage value of the charging reference node is equal to the voltage value of the second reference voltage; When the audio cancellation enable signal is valid, the voltage value of the charging reference node is positively correlated with the error amplification signal and negatively correlated with the difference between a third reference voltage and the first feedback signal, and the third reference voltage is greater than the first reference voltage.

2. The control circuit according to claim 1, wherein: The second voltage generating circuit converts the second feedback signal into a charging current based on a first resistor to charge the capacitor, and the product of the resistance of the first resistor and the capacitance of the capacitor is in direct proportion to the clock period of the clock signal; When the audio cancellation enable signal is invalid, the clock signal has a first clock frequency, and when the audio cancellation enable signal is valid, the clock signal has a second clock frequency, the first clock frequency is greater than the second clock frequency, and the second clock frequency is equal to the upper limit frequency of the audio range.

3. The control circuit according to claim 1, wherein: The first voltage generating circuit further generates a second reference voltage according to the error amplified signal, and the second reference voltage is positively correlated with the error amplified signal; The second voltage generating circuit comprises: an audio frequency cancellation adjustment unit, for generating a first audio frequency cancellation adjustment voltage proportional to the difference between the third reference voltage and the first feedback signal according to the difference between the third reference voltage and the first feedback signal; a subtraction unit, performing subtraction processing on the second reference voltage and the first audio cancellation adjustment voltage to obtain a second audio cancellation adjustment signal; a selecting unit, receiving the audio frequency cancellation enable signal, the second audio frequency cancellation adjustment signal and the second reference voltage, and configured to output the second reference voltage to obtain a voltage value provided to the charging reference node when the audio frequency cancellation enable signal is invalid, or, when the audio frequency cancellation enable signal is valid, add the second audio frequency cancellation adjustment signal and the second reference voltage and output the resultant addition to obtain a voltage value provided to the charging reference node.

4. The control circuit according to claim 3, wherein: The audio cancellation adjustment unit converts the difference between the third reference voltage and the first feedback signal into a first audio cancellation adjustment current based on a resistive element, and generates the first audio cancellation adjustment voltage based on the reference current and the first audio cancellation adjustment current; The third reference voltage is equal to the sum of the first reference voltage and a preset bias voltage.

5. The control circuit according to claim 4, wherein: The control circuit further comprises: The auxiliary pull-down circuit is used to provide an auxiliary pull-down current at the output end of the switching power supply to pull down the output voltage when the first audio cancellation adjustment current is greater than the reference current and the first feedback signal is greater than the third reference voltage.

6. The control circuit according to claim 3, wherein: The first voltage generating circuit comprises: a first voltage-current conversion unit, converting the error amplified signal into a first current signal based on a fifth resistor and a sixth resistor connected in series; a second voltage-current conversion unit, converting the first feedback signal into a second current signal based on a third resistor; a first current mirror and a second current mirror, wherein the first current mirror is used to copy the first current signal to a fourth resistor, and the second current mirror is used to copy the second current signal to the fourth resistor to obtain the first reference voltage on the fourth resistor; The first voltage generating circuit obtains the second reference voltage on the sixth resistor based on the first current signal; The resistance ratio of the fifth resistor to the sixth resistor is 1-n:n, where n is greater than 0 and less than 1.

7. The control circuit according to claim 4, wherein: The audio frequency adjustment unit comprises: A first current source and a first transistor coupled in series between a power supply terminal and a reference ground, wherein the first current source provides the reference current; a first operational amplifier, having a first input terminal receiving the first feedback signal, a second input terminal receiving the third reference voltage, and an output terminal coupled to the control terminal of the first transistor; The cancellation audio frequency adjustment unit outputs the first cancellation audio frequency adjustment voltage at a common connection node of the first current source and the first transistor.

8. The control circuit according to claim 3, wherein: The subtraction unit comprises: a third voltage-current conversion unit, converting the first audio cancellation adjustment voltage into a third current signal based on a seventh resistor; a fourth voltage-current conversion unit, configured to convert the second reference voltage into a fourth current signal based on an eighth resistor; a third current mirror, used for copying the third current signal to an output end of the fourth voltage-current conversion unit; a fourth current mirror, wherein the current input branch is coupled to the output end of the fourth voltage-current conversion unit, The subtraction unit generates a difference current between the fourth current and the third current on a current input branch of the fourth current mirror, and generates the second audio cancellation adjustment signal on a current output branch of the fourth current mirror; The selection unit comprises: The ninth resistor; A second transistor is coupled between the current output branch of the fourth current mirror and the first end of the ninth resistor, wherein the control end of the second transistor receives an inverted signal of the audio cancellation enable signal; a first voltage buffer, configured to provide the second reference voltage to the second end of the ninth resistor; The second voltage buffer has an input terminal coupled to the first terminal of the ninth resistor and an output terminal coupled to the charging reference node.

9. The control circuit according to claim 3, wherein: The subtraction unit comprises: A subtractor, wherein a first input terminal receives the second reference voltage, a second input terminal receives the first audio cancellation adjustment voltage, and the subtractor performs a difference operation on the second reference voltage and the first audio cancellation adjustment voltage and then outputs the second audio cancellation adjustment signal; The selection unit comprises: An adder, wherein the first input terminal receives the second audio cancellation adjustment signal through the third transistor, the second input terminal receives the second reference voltage, the output terminal is coupled to the charging reference node, and the control terminal of the third transistor receives the inverted signal of the audio cancellation enable signal.

10. The control circuit according to claim 5, wherein: The auxiliary pull-down circuit comprises: a second current source and a fourth transistor coupled in series between a power supply terminal and a reference ground, wherein the second current source provides the reference current; a fifth current mirror, a current input branch coupled to a common connection node of the second current source and the fourth transistor; a sixth current mirror, wherein a current input branch is coupled to a current output branch of the fifth current mirror, and a current output branch of the sixth current mirror is coupled to an output terminal of the switching power supply, The auxiliary pull-down circuit generates the auxiliary pull-down current on the current output branch of the sixth current mirror.

11. A switching power supply comprising: A control circuit as claimed in any one of claims 1 to 10.

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