High conversion ratio dual-path dc-dc converter

Abstract

The disclosure provides a double-path DC-DC converter, comprising an input stage and an output stage; the input stage adopts a multi-stage Fibonacci switch capacitor topology circuit structure; the output stage is connected with the input stage and adopts a double-path topology circuit structure in which an inductor and a switch capacitor are connected in parallel; wherein, by controlling the linkage on-off of switches in the input stage and the output stage, the flying capacitor in the output stage is charged and discharged, and the inductor is magnetized and demagnetized, so that the capacitor and the inductor in the output stage are connected in parallel and shunted in a full cycle, and the voltage conversion ratio is improved.

Description

Technical Field

[0001] This disclosure relates to the field of circuit design technology, and in particular to a high conversion ratio dual-path DC-DC converter. Background Technology

[0002] High-conversion-ratio DC-DC converters have wide applications in data centers, 5G communication base stations, and automotive electronics. However, in these converters, the power inductor often becomes a key bottleneck limiting system efficiency and power density. To improve system efficiency, larger and higher-performance inductors are typically required, but this also poses challenges to system miniaturization and power density. Therefore, achieving high efficiency and high power density in high-conversion-ratio DC-DC converters has become a core design challenge for optimizing the energy efficiency ratio of power supply units.

[0003] In high-conversion-ratio applications, traditional Buck DC-DC converters typically suffer from short on-time, low efficiency, and insufficient power density. In recent years, dual-path DC-DC converters have been proposed by academia. These converters utilize flying capacitors to step down the voltage and reduce the average current of the inductor, thereby improving the voltage conversion ratio and reducing reliance on large, high-performance inductors. However, current architectures suffer from insufficient utilization of flying capacitors, resulting in redundant flying capacitors at the step-down level. Furthermore, capacitors occupy a significant amount of motherboard space, limiting further improvements in power density. Summary of the Invention

[0004] In view of this, in order to at least partially solve at least one of the aforementioned technical problems, this disclosure provides a dual-path DC-DC converter.

[0005] To achieve the above objectives, the technical solution disclosed herein is as follows:

[0006] According to embodiments of this disclosure, a dual-path DC-DC converter is provided, including an input stage and an output stage. The input stage adopts a multi-stage Fibonacci switched capacitor topology. The output stage is connected to the input stage and adopts a dual-path topology with inductors and switched capacitors connected in parallel. By controlling the simultaneous on / off switching of the switches in the input and output stages, the switched capacitors in the output stage are charged and discharged, and the inductors are magnetized and demagnetized, thereby achieving full-cycle parallel current sharing between the capacitors and inductors in the output stage and improving the voltage conversion ratio.

[0007] According to embodiments of this disclosure, the output stage includes an inductor L, a capacitor C4, a switch S9, and a switch S1. 10 Switch S 11One end of inductor L is connected to one output terminal of the input stage, and the other end is connected to the load through the output node; one end of capacitor C4 is connected to the other output terminal of the input stage through node SW7, and the other end of capacitor C4 is connected to switch S. 11 After grounding, flying capacitor C4 and switch S 11 Node SW8 is set between them, and nodes SW7 and SW8 are connected by switches S9 and S1 respectively. 10 Connect to the output node.

[0008] According to embodiments of this disclosure, the input stage employs a modified Fibonacci switched capacitor topology with 3-stage connection point shifting.

[0009] The input stage includes switches S0, S1, S2, S3, S4, S5, S6, S7, S8, and flying capacitors C1, C2, and C3. Switches S0, S1, S4, and S7 are connected in series. A node SW1 is located between switches S0 and S1, a node SW3 is located between switches S1 and S4, and a node SW5 is located between switches S4 and S7. Switch S7 is connected to switch S9 via node SW7. Node SW1 is connected to flying capacitor C1 and switch S3 and then grounded. A node SW2 is located between flying capacitor C1 and switch S3, and node SW2 is connected to node SW5 via switch S2. Node SW3 is connected to flying capacitor C2 and switch S6 and then grounded. A node SW4 is located between flying capacitor C2 and switch S6, and node SW4 is connected to node SW7 via switch S5. Node SW5 is connected to flying capacitor C3 and switch S8 and then grounded. A node SW6 is located between flying capacitor C3 and switch S8. Switch S0 is connected to the input terminal before it, and switch S7 is connected to the output stage after it.

[0010] According to an embodiment of this disclosure, the dual-path DC-DC converter includes a first operating phase state and a second operating phase state. In the first operating phase state, capacitor C4 in the output stage discharges, inductor L is magnetized, and the load simultaneously receives discharge charge from capacitor C4 and inductor charge. In the second operating phase state, capacitor C4 in the output stage is charged, inductor L is demagnetized, and the load simultaneously receives charging charge from capacitor C4 and inductor charge.

[0011] According to an embodiment of this disclosure, in the first working phase state, switches S0, S2, S4, S6, S9, and S1 are... 11 On, switches S1, S3, S5, S7, S8, and S1 are connected. 10 When the circuit is turned off, flying capacitors C1 and C3 are charged, flying capacitors C2 and C4 are discharged, inductor L is magnetized, and the inductor current increases; flying capacitor C1 is powered by power supply V. INIn direct charging, the sum of the charging charge of flying capacitor C1 and the discharging charge of flying capacitor C2 constitutes the charging charge of flying capacitor C3, and the inductor L is the amount of charge transferred to the output node. At the same time, flying capacitor C4 directly supplies power to the load through the output node.

[0012] According to an embodiment of this disclosure, in the second operating phase state, switches S0, S2, S4, S6, S9, and S1 are... 11 Off, switches S1, S3, S5, S7, S8, and S... 10 When the circuit is turned on, flying capacitors C1 and C3 discharge, flying capacitors C2 and C4 charge, inductor L is demagnetized, and inductor current decreases. The series charge path of flying capacitors C1 and C2 is connected in parallel with the discharge path of flying capacitor C3 to charge flying capacitor C4. At this time, the load simultaneously receives charging charge from flying capacitor C4 and charge from the inductor.

[0013] According to an embodiment of this disclosure, when the dual-path DC-DC converter is operating, the steady-state voltage of the flying capacitor C1 is... for: The steady-state voltage of the flying capacitor C2 for: The steady-state voltage of the flying capacitor C3 for: The steady-state voltage of the flying capacitor C4 for: Based on the volt-second balance between the magnetized and demagnetized states of an inductor, we can obtain:

[0014] ;

[0015] but:

[0016] ;

[0017] The voltage conversion ratio M of the DC-DC converter is:

[0018] ;

[0019] Where D represents the duty cycle of the switch control signal, 0 <D<1, The input voltage is the power supply voltage. This is the output voltage.

[0020] According to embodiments of this disclosure, the ratio of the average inductor current to the load current can be obtained based on the charge conservation principle of the capacitor:

[0021] ;

[0022] in, The average current of the inductor. This is the load current. Attached Figure Description

[0023] The above and other objects, features and advantages of this disclosure will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0024] Figure 1 This is a schematic diagram of a dual-path hybrid Dickson DC-DC converter in the prior art.

[0025] Figure 2 This is a schematic diagram of the high conversion ratio dual-path DC-DC converter according to an embodiment of the present disclosure.

[0026] Figure 3 This is a schematic diagram of a high-conversion-ratio dual-path DC-DC converter with three flying capacitors included in the input stage of an embodiment of the present disclosure.

[0027] Figure 4 This is a schematic diagram of the high conversion ratio dual-path DC-DC converter in different operating phase states according to an embodiment of the present disclosure.

[0028] Figure 5 This is a schematic diagram of key waveforms in the first and second working phase states of an embodiment of this disclosure.

[0029] Figure 6 For converters with traditional structures and such Figure 3 The diagram shows a comparison of the inductor current ratio of the converter.

[0030] Figure 7 This is a schematic diagram of a high-conversion-ratio dual-path DC-DC converter that uses a MOSFET to implement the switching function, according to an embodiment of this disclosure. Detailed Implementation

[0031] This disclosure provides a high-conversion-ratio dual-path DC-DC converter that maximizes the utilization of flying capacitors based on a Fibonacci switched-capacitor topology, achieving the highest achievable conversion ratio for a given number of flying capacitors. It also extends the equivalent on-time and allows for the evaluation of the minimum number of flying capacitors required to achieve a specific conversion ratio, thus improving power density. The dual-path structure reduces the average inductor current by shunting the current through the full-cycle parallel connection of the switched capacitor and inductor, thereby reducing the inductor's direct current resistance (DCR) conduction loss and improving system efficiency. It also relaxes the requirements for large-size, small-DCR, high-saturation-current inductors, allowing for system miniaturization using small-size, large-DCR, low-saturation-current inductors while maintaining high system efficiency, thus increasing power density and reducing cost.

[0032] High-conversion-ratio DC-DC converters are widely used in data centers, 5G communication base stations, automotive electronics, and other fields. To achieve high system efficiency, large-size, high-performance inductors are the optimal choice, but this limits system miniaturization and power density. System miniaturization is a primary requirement for power management units today. Due to limitations in magnetic materials and manufacturing processes, power inductors in inductive DC-DC converters have relatively low energy density; inductors in the μH range often occupy a large motherboard area, becoming a major factor restricting miniaturization and also limiting the improvement of power density.

[0033] For traditional Buck DC-DC converters, the following two main problems exist in high conversion ratio applications: 1. The on-time of the upper transistor is only 1 / M of the switching cycle, where M represents the voltage conversion ratio of the converter (the ratio of input voltage to output voltage: V). IN / V O 1. The extremely short conduction time presents design challenges for control and drive circuits; 2. As the main passive component in the power stage, the inductor's average current is the load current. However, inductors have significant conduction losses (DCR), so large, high-performance inductors are often needed to reduce these losses, which in turn affects the system's power density. Generally, large inductors have better performance: low DCR and high saturation current. For DC-DC converters with rated load current, the selected inductor should first ensure sufficient saturation current to ensure the system's reliability at maximum load. Secondly, a low DCR ensures high system efficiency. To further improve power density, reducing inductor size is a relatively direct approach. To maintain high system efficiency, dual-path DC-DC converters with reduced average inductor current alleviate the reliance on large inductors with low DCR and high saturation current, achieving both high efficiency and high power density simultaneously.

[0034] To address the aforementioned issues of traditional Buck DC-DC converters, dual-path DC-DC converters, a hybrid DC-DC converter combining capacitors and inductors, have been widely adopted in recent years for high-conversion-ratio power supply applications, gaining popularity in both industry and academia. These DC-DC converters are based on traditional Buck DC-DC converters, introducing an additional flying capacitor in the power stage. They utilize a series voltage divider approach to reduce the inductor charging / demagnetizing voltage, thereby extending the conduction time, and a parallel current shunt approach to supply power to the output, reducing the average inductor current.

[0035] A research team has proposed a dual-path hybrid Dickson DC-DC converter for high conversion ratio applications such as 48V to 1V [Reference paper: C. Chen, J. Liu, and H. Lee, “A 92.7%-Efficiency 30A 48V-to-1V Dual-Path Hybrid Dickson Converter for PoL Applications,” in 2021 IEEE Energy Conversion Congress and Exposition (ECCE), Oct. 2021, pp. 1989–1994.]. Figure 1 As shown. This architecture, excluding the output capacitor, contains one inductor and six flying capacitors as passive components. The voltage conversion ratio M and the ratio of inductor current to load current are given by equations (1) and (2), respectively:

[0036] (1);

[0037] (2);

[0038] Where D represents the duty cycle (0 rpm) of the power switch control signal. <D<1),I L It is the average inductor current, I O This is the load current. According to formula (1), the voltage conversion ratio M of this converter can be as low as 7, and the equivalent conduction time is approximately 7 times higher than that of a traditional Buck converter. Meanwhile, the ratio of the average inductor current to the load current of this converter ranges from (…). ~1), compared to the traditional Buck, it can achieve a maximum reduction of 57% inductor current, reducing inductor conduction losses and improving system efficiency.

[0039] However, this converter requires a significant number of passive components, employing a total of six flying capacitors to achieve a sevenfold increase in conversion ratio. This results in low capacitor utilization, occupies a large motherboard area, and limits the improvement in power density. Furthermore, the reduction in inductor current is limited.

[0040] Traditional Buck DC-DC converters suffer from low system efficiency, low power density, and short turn-on time when applied to high conversion ratio scenarios. Existing dual-path DC-DC converters, by introducing flying capacitors to improve conversion ratio and reduce average inductor current, effectively improve efficiency or power density. However, their flying capacitor utilization is low, often requiring a large number of flying capacitors to achieve a significant increase in conversion ratio and reduction in inductor current. This translates to more passive components on the motherboard, which ultimately limits the improvement in power density.

[0041] To address the aforementioned shortcomings, this invention provides a dual-path DC-DC converter that simultaneously achieves high conversion ratio, high efficiency, and high power density. It utilizes a Fibonacci switched-capacitor topology to maximize the use of flying capacitors, achieving a high conversion ratio (8 times) voltage output and improving the equivalent on-time. This avoids the design challenges posed by extremely short on-time to the control and drive circuits. Furthermore, this architecture allows for the assessment of the minimum number of flying capacitors required to achieve a specific conversion ratio, which is beneficial for increasing power density. Simultaneously, the dual-path structure effectively reduces the average inductor current through parallel current sharing between the switched capacitor and the inductor, thereby reducing the inductor's DCR conduction loss and improving system efficiency. It also relaxes the requirement for large-size inductors, allowing for system miniaturization using small-size inductors with large DCR and low saturation current while maintaining high system efficiency, thus improving power density and reducing cost.

[0042] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0043] In this embodiment of the disclosure, a dual-path DC-DC converter suitable for 48V to 2-5V is provided, such as... Figure 2 As shown, the converter includes:

[0044] The input stage adopts a multi-stage Fibonacci switched capacitor topology circuit structure.

[0045] The output stage, connected to the input stage, adopts a dual-path topology circuit structure with inductor L and switched capacitor C connected in parallel.

[0046] Specifically, by controlling the simultaneous on / off switching of the switches in the input and output stages, the flying capacitor C in the output stage is charged and discharged, and the inductor L is magnetized and demagnetized, thereby realizing the full-cycle parallel current shunting of the capacitor and inductor in the output stage and improving the voltage conversion ratio.

[0047] According to embodiments of this disclosure, such as Figure 3 As shown, the input stage of the dual-path DC-DC converter adopts a modified Fibonacci switched capacitor topology with 3-stage connection point shift.

[0048] like Figure 3As shown, the input stage includes switches S0, S1, S2, S3, S4, S5, S6, S7, S8, flying capacitors C1, C2, and C3. Switches S0, S1, S4, and S7 are connected in series. A node SW1 is located between switches S0 and S1, a node SW3 is located between switches S1 and S4, and a node SW5 is located between switches S4 and S7. Switch S7 is connected to switch S9 via node SW7. Node SW1 is connected to flying capacitor C1 and switch S3 and then grounded. A node SW2 is located between flying capacitor C1 and switch S3, and node SW2 is connected to node SW5 via switch S2. Node SW3 is connected to flying capacitor C2 and switch S6 and then grounded. A node SW4 is located between flying capacitor C2 and switch S6, and node SW4 is connected to node SW7 via switch S5. Node SW5 is connected to flying capacitor C3 and switch S8 and then grounded. A node SW6 is located between flying capacitor C3 and switch S8. Switch S0 is connected to the input terminal before it, and switch S7 is connected to the output stage after it.

[0049] According to embodiments of this disclosure, such as Figure 3 As shown, the output stage includes inductor L, capacitor C4, switch S9, and switch S1. 10 Switch S 11 Wherein: one end of inductor L is connected to one output terminal of the input stage, and the other end is connected to the load through the output node; one end of capacitor C4 is connected to the other output terminal of the input stage through node SW7, and the other end of capacitor C4 is connected to switch S. 11 After grounding, flying capacitor C4 and switch S 11 Node SW8 is set between them, and nodes SW7 and SW8 are connected by switches S9 and S1 respectively. 10 Connect to the output node.

[0050] According to embodiments of this disclosure, in conjunction with Figure 3 and Figure 4 As shown, the dual-path DC-DC converter includes a first operating phase (Phase 1 or φ1) and a second operating phase (Phase 2 or φ2). In the first operating phase, capacitor C4 in the output stage discharges, inductor L is magnetized, and the load simultaneously receives the discharged charge from capacitor C4 and the inductor charge. In the second operating phase, capacitor C4 in the output stage charges, inductor L is demagnetized, and the load simultaneously receives the charged charge from capacitor C4 and the inductor charge.

[0051] Specifically, in the first working phase state, such as Figure 4 As shown in part (a), switches S0, S2, S4, S6, S9, and S... 11On, switches S1, S3, S5, S7, S8, and S1 are connected. 10 When the circuit is turned off, flying capacitors C1 and C3 are charged, flying capacitors C2 and C4 are discharged, inductor L is magnetized, and the inductor current increases; flying capacitor C1 is powered by power supply V. IN In direct charging, the sum of the charging charge of flying capacitor C1 and the discharging charge of flying capacitor C2 constitutes the charging charge of flying capacitor C3, and the inductor L is the amount of charge transferred to the output node. Simultaneously, flying capacitor C4 directly supplies power to the load through the output node. In the second operating phase state, as... Figure 4 As shown in (b), switches S0, S2, S4, S6, S9, and S... 11 Off, switches S1, S3, S5, S7, S8, and S... 10 When the circuit is turned on, flying capacitors C1 and C3 discharge, flying capacitors C2 and C4 charge, inductor L is demagnetized, and inductor current decreases. The series charge path of flying capacitors C1 and C2 is connected in parallel with the discharge path of flying capacitor C3 to charge flying capacitor C4. At this time, the load simultaneously receives charging charge from flying capacitor C4 and charge from the inductor.

[0052] The above inductor magnetization sequence corresponds to Phase 1, with a working time of DT. The inductor demagnetization corresponds to Phase 2, with a working time of (1-D)T. However, it is not limited to this definition and the working time can also be set in the opposite way.

[0053] According to embodiments of this disclosure, in conjunction with Figure 4 and Figure 5 As shown, when the dual-path DC-DC converter operates in the two working phases mentioned above, the steady-state voltage of each capacitor can be easily calculated:

[0054] steady-state voltage of flying capacitor C1 for:

[0055] (3-1);

[0056] steady-state voltage of flying capacitor C2 for: (3-2);

[0057] steady-state voltage of flying capacitor C3 for: (3-3);

[0058] steady-state voltage of flying capacitor C4 for: (3-4);

[0059] Based on the volt-second balance between the magnetized and demagnetized states of an inductor, we can obtain:

[0060] (4);

[0061] but:

[0062] (5);

[0063] The voltage conversion ratio M of the DC-DC converter is:

[0064] (6);

[0065] Where D represents the duty cycle of the switch control signal, 0 <D<1, The input voltage is the power supply voltage. This is the output voltage.

[0066] The switched capacitors in the output stage can be used as part of a Fibonacci switched capacitor, which is equivalent to using a 4-stage Fibonacci switched capacitor structure. Therefore, the minimum achievable conversion ratio can be given under the condition of using a Fibonacci switched capacitor circuit structure with a total of k flying capacitors. for:

[0067] (7);

[0068] F represents the Fibonacci sequence {1(F0), 1(F1), 2(F2), 3(F3), 5(F4), 8(F5), ...}. The minimum conversion ratio when using k (k=4) flying capacitors is then determined. If the value is F5=8, then the equivalent conduction time is approximately 8 times longer than that of a traditional Buck converter. Figure 1 The existing converter structure shown uses 6 flying capacitors to achieve a 7x improvement, while the converter disclosed in this invention has a higher conversion ratio and avoids the design challenges posed by extremely short on-time to the control and drive circuits.

[0069] The above scheme can be applied to designs targeting voltage conversion ratio to evaluate the minimum number of flying capacitors required to achieve a specific conversion ratio range, thus avoiding the waste of flying capacitors and improving power density.

[0070] According to embodiments of this disclosure, the ratio of the average inductor current to the load current can be obtained based on the charge conservation principle of the capacitor:

[0071] (8);

[0072] in, The average current of the inductor. This is the load current.

[0073] Combined Figure 6As shown, the converter of the present invention achieves lower inductor current across the entire duty cycle using only four flying capacitors, compared to... Figure 1 The converter shown, employing six flying capacitors, can achieve an additional 18% reduction in inductor current. Because the average inductor current is significantly reduced, conduction losses (DCR) are further decreased. Therefore, this invention achieves higher system efficiency, removing limitations on inductor DCR and saturation current. It allows for size reduction by using small-sized inductors with large DCR and low saturation current while maintaining high efficiency, thereby increasing power density and making it more suitable for high-conversion-ratio voltage conversion applications.

[0074] According to embodiments of this disclosure, such as Figure 7 As shown, all switches in the high-conversion-ratio DC-DC converter can also be implemented using NMOS transistors. Bootstrap circuits, level shifting circuits, and drive circuits are used to control the gate terminals of the NMOS transistors (e.g., the generation method of the drive bootstrap voltage acting on NMOS transistor S10 in the figure), and loop control is performed in conjunction with PWM control. The PWM generator generates a PWM signal, which is then used by a dead-time generation circuit to generate two non-overlapping complementary signals, PWM_P and PWM_N, as control signals for each power switch. There are multiple possibilities for the implementation of the switches in this invention, including but not limited to various voltage-rated NMOS and PMOS transistors; some switches can even use diodes.

[0075] In summary, the input stage of this invention employs a Fibonacci switched capacitor topology, maximizing the use of flying capacitors to reduce output voltage. Compared to traditional Buck DC-DC converters, this invention extends the equivalent on-time, and compared to existing converters using the same number of capacitors, it achieves a higher conversion ratio, making it more suitable for high conversion ratio applications. The output stage uses a dual-path topology with an inductor and a switched capacitor in parallel. The output voltage is modulated by the inductor, while the capacitor supplies power to the output load in all operating states in parallel with the inductor. This effectively reduces the average inductor current, decreases the inductor's DCR conduction loss, and improves system efficiency. Simultaneously, the reduced inductor current eliminates the reliance on large, high-performance inductors, allowing the system to use small-sized inductors with high DCR and low saturation current, achieving system miniaturization, increasing power density, and reducing cost. The above technical solutions can be applied to designs targeting voltage conversion ratio, used to evaluate the minimum number of flying capacitors required to achieve a specific conversion ratio range, avoiding wasted flying capacitors and contributing to increased power density.

[0076] The embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. It should be noted that implementations not illustrated or described in the drawings or the main text of the specification are forms known to those skilled in the art and are not described in detail. Furthermore, the definitions of the various elements and methods described above are not limited to the specific structures, shapes, or methods mentioned in the embodiments, and those skilled in the art can easily modify or substitute them.

[0077] In summary, this disclosure provides a high-conversion-ratio dual-path DC-DC converter. The input stage employs a Fibonacci switched-capacitor topology to maximize the utilization of flying capacitors and improve the voltage conversion ratio. The output stage uses a dual-path topology with an inductor and a switched capacitor in parallel for output voltage modulation. Compared with existing architectures, this invention improves the utilization of flying capacitors, achieves a higher conversion ratio output, extends the equivalent on-time, and avoids the design challenges posed by excessively narrow duty cycles to control and drive circuits. Furthermore, this invention always has one flying capacitor path connected in parallel with an inductor to power the output, reducing the average inductor current, decreasing the inductor's DCR conduction loss, and improving system efficiency. It relaxes the requirements for large-size, small-DCR, high-saturation-current inductors, allowing for system miniaturization using small-size, large-DCR, low-saturation-current inductors while maintaining high system efficiency, thus improving power density and reducing cost. This invention can also be used to evaluate the minimum number of flying capacitors required to achieve a specific conversion ratio range, avoiding waste of flying capacitors and contributing to improved power density.

[0078] It should be noted that, unless otherwise specified herein, having "a" element is not limited to having a single element, but may include one or more of the element.

[0079] Furthermore, unless otherwise specified, the ordinal numbers such as "first," "second," etc., used herein are merely for distinguishing multiple elements with the same name and do not indicate any hierarchy, order of execution, or process sequence among them. A "first" element and a "second" element may appear together in the same component or separately in different components. The presence of an element with a higher ordinal number does not necessarily indicate the presence of another element with a lower ordinal number.

[0080] In this document, unless otherwise specified, the term "characteristic A" or "and / or" and "characteristic B" means that A exists alone, B exists alone, or A and B exist simultaneously; the term "characteristic A" and "and" or "and" and "and" and "characteristic B" means that A and B exist simultaneously; the terms "including", "containing", "having", and "containing" refer to, but are not limited to, these.

[0081] Furthermore, in this document, terms such as "up," "down," "left," "right," "front," "back," or "between" are used only to describe the relative positions of multiple elements and can be extended to include translation, rotation, or mirroring. Additionally, unless otherwise specified, the statement "one element is on another element" or similar statements do not necessarily indicate that the element is in contact with the other element.

[0082] Furthermore, unless specifically described or required to occur in a specific order, the order of the above steps is not limited to those listed above and can be varied or rearranged according to the desired design. Moreover, the above embodiments can be used in combination with each other or with other embodiments based on design and reliability considerations; that is, technical features from different embodiments can be freely combined to form more embodiments.

[0083] The specific embodiments described above further illustrate the purpose, technical solutions, and beneficial effects of this disclosure. It should be understood that the above descriptions are merely specific embodiments of this disclosure and are not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A dual-path DC-DC converter, comprising: The input stage adopts a multi-stage Fibonacci switched capacitor topology circuit structure. The output stage, connected to the input stage, adopts a dual-path topology circuit structure with inductor L and flying capacitor C4 connected in parallel. Specifically, by controlling the linkage of the switches in the input stage and the output stage, the flying capacitor C4 in the output stage is charged and discharged, and the inductor L is magnetized and demagnetized, so as to realize the full-cycle parallel current shunting of the flying capacitor C4 and the inductor L in the output stage and improve the voltage conversion ratio. The input stage includes switches S0, S1, S4, and S7 connected in sequence. A node SW1 is located between switches S0 and S1, a node SW3 is located between switches S1 and S4, and a node SW5 is located between switches S4 and S7. Switch S7 is connected to switch S9 via node SW7. Node SW1 is connected to flying capacitor C1 and switch S3 and then grounded. A node SW2 is located between flying capacitor C1 and switch S3, and node SW2 is connected to node SW5 via switch S2. Node SW3 is connected to flying capacitor C2 and switch S6 and then grounded. A node SW4 is located between flying capacitor C2 and switch S6, and node SW4 is connected to node SW7 via switch S5. Node SW5 is connected to flying capacitor C3 and switch S8 and then grounded. A node SW6 is located between flying capacitor C3 and switch S8. The front end of switch S0 is connected to the input power supply, and the rear end of switch S7 is connected to the output stage.

2. The dual-path DC-DC converter according to claim 1, wherein the output stage comprises: One end of the inductor L is connected to an output terminal of the input stage, and the other end is connected to the load through the output node; One end of the flying capacitor C4 is connected to the other output terminal of the input stage through node SW7, and the other end of the flying capacitor C4 is connected to switch S. 11 After grounding, flying capacitor C4 and switch S 11 Node SW8 is set between them, and nodes SW7 and SW8 are connected by switches S9 and S1 respectively. 10 Connect to the output node.

3. The dual-path DC-DC converter according to claim 2 includes a first operating phase state, in which the flying capacitor C4 in the output stage of the first operating phase state is discharged, the inductor L is magnetized, and the load simultaneously receives the discharged charge from the flying capacitor C4 and the inductor charge.

4. The dual-path DC-DC converter according to claim 2, including a second operating phase state, wherein the flying capacitor C4 in the output stage of the second operating phase state is charged, the inductor L is demagnetized, and the load simultaneously receives charging charge from the flying capacitor C4 and inductor charge.

5. The dual-path DC-DC converter according to claim 3, in the first operating phase state, switches S0, S2, S4, S6, S9, and S1... 11 On, switches S1, S3, S5, S7, S8, and S1 are connected. 10 When the circuit is turned off, flying capacitors C1 and C3 are charging, flying capacitors C2 and C4 are discharging, inductor L is magnetized, and the inductor current increases. Flying capacitor C1 is directly charged by the input power supply. The sum of the charging charge of flying capacitor C1 and the discharging charge of flying capacitor C2 constitutes the charging charge of flying capacitor C3 and the charge transferred by inductor L to the output node. At the same time, flying capacitor C4 directly supplies power to the load through the output node.

6. The dual-path DC-DC converter according to claim 4, in the second operating phase state, switches S0, S2, S4, S6, S9, and S1... 11 Off, switches S1, S3, S5, S7, S8, and S... 10 When the circuit is turned on, flying capacitors C1 and C3 discharge, flying capacitors C2 and C4 charge, inductor L is demagnetized, and inductor current decreases. The series charge path of flying capacitors C1 and C2 is connected in parallel with the discharge path of flying capacitor C3 to charge flying capacitor C4. At this time, the load simultaneously receives charging charge from flying capacitor C4 and charge from the inductor.

7. The dual-path DC-DC converter according to claim 5 or 6, wherein, steady-state voltage of flying capacitor C1 for: ; steady-state voltage of flying capacitor C2 for: ; steady-state voltage of flying capacitor C3 for: ; steady-state voltage of flying capacitor C4 for: ; Based on the volt-second balance between the magnetized and demagnetized states of the inductor: ； but: ； The voltage conversion ratio M of the DC-DC converter is: ； Where D represents the duty cycle of the switch control signal, 0 <D<1, The input power supply voltage. This is the output voltage.

8. The dual-path DC-DC converter according to claim 7, wherein the ratio of the average inductor current to the load current is obtained based on the charge conservation of the flying capacitor: ； in, The average current of the inductor. This is the load current.

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