Hybrid DC-DC converter circuit

Abstract

The invention provides a hybrid DC-DC converter circuit which can be applied to the technical field of hybrid DC-DC converter topology construction. The circuit comprises: an input unit comprising an inductor; a plurality of first capacitor units, wherein each first capacitor unit comprises a first capacitor and a first switch subunit; a plurality of second capacitor units, wherein each second capacitor unit comprises a second capacitor and a second switch subunit; wherein the first capacitor units and the second capacitor units are cascaded alternately, and the input unit is cascaded with the first first capacitor unit; the circuit is used for responding to a control signal and controlling the plurality of first switch subunits and the plurality of second switch subunits to switch working states in a working period so as to control the plurality of first capacitors and the plurality of second capacitors to alternately charge / discharge in the working period.

Description

Technical Field

[0001] The present disclosure relates to the technical field of hybrid DC-DC converter topology structure, and more specifically, to a hybrid DC-DC converter circuit. Background Art

[0002] The hybrid DC-DC converter is a power-level topology that is easy to achieve high efficiency and high current density, and has become a research hotspot in many fields in recent years. At the same time, due to the introduction of flying capacitors to reduce the voltage drop or conduction current of the switch tube or inductor, it has gradually replaced the traditional inductive DC-DC converter.

[0003] In the process of implementing the concept of the present disclosure, the inventors discovered that the hybrid DC-DC converter in the related art has at least the technical problems of low capacitor utilization and limited reduction range of inductor current. Summary of the invention

[0004] In view of this, the present disclosure provides a hybrid DC-DC converter circuit.

[0005] One aspect of the present disclosure provides a hybrid DC-DC converter circuit, comprising:

[0006] An input unit includes an inductor; a plurality of first capacitor units, each of which includes a first capacitor and a first switch sub-unit; a plurality of second capacitor units, each of which includes a second capacitor and a second switch sub-unit; wherein each first capacitor unit is alternately cascaded with each second capacitor unit, and the input unit is cascaded with the first first capacitor unit; and the circuit is used to respond to a control signal to control the plurality of first switch sub-units and the plurality of second switch sub-units to switch working states respectively within a working cycle, so as to control the plurality of first capacitors and the plurality of second capacitors to alternately charge / discharge within a working cycle.

[0007] According to an embodiment of the present disclosure, the working cycle includes a first time period corresponding to a first charging and discharging state and a second time period corresponding to a second charging and discharging state, and the input unit also includes an input capacitor and a control switch subunit; in the first charging and discharging state, the input capacitor is charged, and for each first capacitor unit, the first switch subunit switches to the first working state to control the discharge of the first capacitor, and for each second capacitor unit, the second switch subunit switches to the second working state to control the charging of the second capacitor; in the second charging and discharging state, the input capacitor is discharged, and for each first capacitor unit, the first switch subunit switches to the second working state to control the charging of the first capacitor, and for each second capacitor unit, the second switch subunit switches to the first working state to control the discharge of the second capacitor.

[0008] According to an embodiment of the present disclosure, the control switch subunit includes a first control switch, a second control switch and a third control switch, the first end of the first control switch is connected to a power supply, the second end of the first control switch and the first end of the second control switch are both connected to the first plate of the input capacitor, the first end of the third control switch and the first end of the inductor are both connected to the second plate of the input capacitor, the second end of the third control switch is grounded, and the second end of the second control switch and the second end of the inductor are both connected to the first plate of the first capacitor in the first first capacitor unit.

[0009] According to an embodiment of the present disclosure, the first switch subunit includes a first switch, a second switch, and a third switch. For the nth first switch subunit, the first plate of the first capacitor is connected to the first end of the first switch, and the second plate of the first capacitor is connected to the first end of the second switch and the first end of the third switch; the second end of the third switch is grounded, and the second end of the first switch and the second end of the second switch are both connected to the first plate of the second capacitor in the nth second capacitor unit.

[0010] According to an embodiment of the present disclosure, the second switch subunit includes a fourth switch, a fifth switch, and a sixth switch. For the nth second switch subunit, the first plate of the second capacitor is connected to the first end of the fourth switch, and the second plate of the second capacitor is connected to the first end of the fifth switch and the first end of the sixth switch; the second end of the sixth switch is grounded, and the second end of the fourth switch and the second end of the fifth switch are both connected to the first plate of the first capacitor in the n+1th first capacitor unit.

[0011] According to an embodiment of the present disclosure, in the first charge and discharge state, the first control switch is closed, the second control switch and the third control switch are opened, and for the nth first switch subunit, the first switch and the third switch are closed, and the second switch is opened; for the nth second switch subunit, the fifth switch is closed, and the fourth switch and the sixth switch are opened.

[0012] According to an embodiment of the present disclosure, in the second charge and discharge state, the first control switch is disconnected, and the second and third control switches are closed. For the nth first switch subunit, the first switch and the third switch are disconnected, and the second switch is closed; for the nth second switch subunit, the fifth switch is disconnected, and the fourth and sixth switches are closed.

[0013] According to an embodiment of the present disclosure, in the second charge-discharge state, the charge of the first capacitor is expressed as follows:

[0014]

[0015] in, represents the charge of the ath first capacitor, represents the charge of the a-1th second capacitor, represents the charge of the a-1th first capacitor, where a is a positive integer. represents the inductor charge, Represents the charge of the input capacitor.

[0016] According to an embodiment of the present disclosure, in the first charge-discharge state, the charge of the second capacitor is expressed as follows:

[0017]

[0018] in, represents the charge of the ath second capacitor, represents the charge of the a-1th second capacitor, represents the charge of the ath first capacitor, where a is a positive integer. represents the charge of the first capacitor, Represents the charge of the input capacitor.

[0019] According to an embodiment of the present disclosure, the circuit further includes an output load unit, and the ratio Y of the current of the inductor to the current of the output load unit is expressed as the following formula:

[0020]

[0021] in, represents the inductor current, Represents the current of the output load unit, represents the charge of the inductor, represents the charge of the Ath first capacitor, A is the total number of first capacitors, represents the charge of the Bth second capacitor, where B is the total number of second capacitors.

[0022] According to an embodiment of the present disclosure, each first capacitor unit is alternately cascaded with each second capacitor unit, and the input unit is cascaded with the first first capacitor unit. Multiple first switch sub-units and multiple second switch sub-units are controlled by a control signal to switch working states within a working cycle, so that multiple first capacitors and multiple second capacitors are alternately charged / discharged within a working cycle, ensuring that the charges of all first capacitors and second capacitors are conserved within a working cycle, and the charges of each first capacitor and second capacitor are accumulated and reused step by step, which is conducive to maximizing the current diversion of the capacitor to the inductor, thereby reducing the DC impedance conduction loss of the inductor; at the same time, when the inductor current reduction amplitude is specified, the minimum number of capacitors can be selected to achieve the maximum reduction of the inductor current. Each first capacitor unit is alternately cascaded with each second capacitor unit, and the input unit is cascaded with the first first capacitor unit. Each first capacitor unit is alternately cascaded with each second capacitor unit, and the input unit is cascaded with the first first capacitor unit. Each first capacitor unit is alternately cascaded with each second capacitor unit, and the input unit is cascaded with the first first capacitor unit. The utilization rate of the capacitor is improved and the power consumption of the circuit is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0024] Figure 1a The circuit diagram of a dual-channel series capacitance type DC-DC sensor in the related art is schematically shown.

[0025] Figure 1b The equivalent circuit diagram of a dual-channel series capacitor type DC-DC sensor in the related art in a first working state is schematically shown.

[0026] Figure 1c The equivalent circuit diagram of the dual-channel series capacitance type DC-DC sensor in the related art in the second working state is schematically shown.

[0027] Figure 2a The circuit diagram of a multi-channel buck DC-DC sensor in the related art is schematically shown.

[0028] Figure 2b The equivalent circuit diagram of a multi-channel buck DC-DC sensor in the related art in a first working state is schematically shown.

[0029] Figure 2c The equivalent circuit diagram of a multi-channel buck DC-DC sensor in the related art in the second working state is schematically shown.

[0030] Figure 3A schematic diagram of a hybrid DC-DC converter circuit according to an embodiment of the present disclosure is schematically shown.

[0031] Figure 4a The equivalent circuit diagram of the hybrid DC-DC converter in the first charging and discharging state according to the embodiment of the present disclosure is schematically shown.

[0032] Figure 4b The equivalent circuit diagram of the hybrid DC-DC converter in the second charge and discharge state according to the embodiment of the present disclosure is schematically shown.

[0033] Figure 5 The diagram schematically shows a curve showing a change in the ratio of the inductor current to the output load unit current of various DC-DC converters according to an embodiment of the present disclosure as a function of the duty cycle.

[0034] Figure 6a A circuit diagram of a hybrid DC-DC converter according to an embodiment of the present disclosure is schematically shown.

[0035] Figure 6b A circuit diagram of a hybrid DC-DC converter in a first charging and discharging state according to an embodiment of the present disclosure is schematically shown.

[0036] Figure 6c A circuit diagram of a hybrid DC-DC converter in a second charge and discharge state according to an embodiment of the present disclosure is schematically shown.

[0037] Figure 7a A circuit diagram of another hybrid DC-DC converter in a first charging and discharging state according to an embodiment of the present disclosure is schematically shown.

[0038] Figure 7b A circuit diagram of another hybrid DC-DC converter in a second charge and discharge state according to an embodiment of the present disclosure is schematically shown.

[0039] Figure 8a A circuit diagram of another hybrid DC-DC converter in a first charging and discharging state according to an embodiment of the present disclosure is schematically shown.

[0040] Figure 8b A circuit diagram of another hybrid DC-DC converter in a second charge and discharge state according to an embodiment of the present disclosure is schematically shown. DETAILED DESCRIPTION

[0041] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In the following detailed description, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0042] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise", "include", etc. used herein indicate the existence of the features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0043] All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0044] When using expressions such as "at least one of A, B, and C, etc.", they should generally be interpreted according to the meaning of the expression commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0045] Hybrid DC-DC converters are widely used in various power supply scenarios, such as high conversion ratio power supply in data centers, buck-boost power supply for lithium battery input in mobile devices, etc., by introducing flying capacitors to reduce the voltage drop or conduction current of switches or inductors. Among them, the dual-channel hybrid DC-DC converter is a type of hybrid DC-DC converter topology that uses the shunt concept to reduce the current of inductors and each switch tube to improve efficiency and current density. The dual-channel hybrid DC-DC converter introduces flying capacitors in parallel with the inductor and charges the load at the same time. Compared with the traditional DC-DC converter that only uses the inductor to power the load, it reduces the inductor current, reduces the conduction loss of the inductor DC resistance (DCR), improves efficiency, and eliminates the dependence on large-size, high-performance inductors under the same inductance value. At the same time, the shunt effect of the flying capacitor and the inductor also reduces the conduction current of the switch tube. This current dispersion effect is also beneficial to the reduction of the conduction loss of the switch tube and the improvement of overall efficiency.

[0046] However, the dual-channel hybrid DC-DC converter in the related art has low capacitor utilization and limited reduction of inductor current. In particular, at certain specific conversion ratios, the inductor current approaches the inductor current in the traditional DC-DC converter, which has little effect on reducing the inductor DCR conduction loss. At the same time, there is a lack of topological structure that targets a specific reduction in inductor current, making it difficult to achieve the maximum shunting effect of the flying capacitor on the inductor, which easily leads to waste of the flying capacitor.

[0047] Figure 1a The circuit diagram of a dual-channel series capacitance type DC-DC sensor in the related art is schematically shown.

[0048] like Figure 1a As shown, this embodiment includes switches S1, S2, S3, S4, S5, S6, S7, and a flying capacitor C F1 , C F2 , C F3 , C F4 , inductance L, load capacitance C o , load current source I o .

[0049] Figure 1b The equivalent circuit diagram of a dual-channel series capacitor type DC-DC sensor in the related art in a first working state is schematically shown.

[0050] Figure 1c The equivalent circuit diagram of the dual-channel series capacitance type DC-DC sensor in the related art in the second working state is schematically shown.

[0051] like Figure 1b and Figure 1c As shown, by switching the disconnection or conduction of each switch, the first working state and the second working state are alternately performed in one working cycle. In one working state (Phase 1), S1, S3, S5, S7 are closed, S2, S4, S6 are disconnected, and the flying capacitor C F1 , C F3 Charging, flying capacitor C F2 , C F4 Discharge, inductor L is charged, and the charge / discharge amount of each flying capacitor is 1 / 3I L DT, D is the switching duty cycle, and T is the period.

[0052] In the second working state (Phase 2), the flying capacitor C F1 , C F3 Discharge, S1, S3, S5, S7 are disconnected, S2, S4, S6 are closed, the flying capacitor C F2 , C F4During charging, the inductor L discharges, that is, the flying capacitors achieve charge conservation respectively within one working cycle. The flying capacitor C F1 is in series with C F2 to supply power to the load output additionally. The flying capacitor C F3 is in series with C F4 to supply power to the load output additionally. Therefore, the charge quantity Q of the flying capacitor C can be expressed by the following formula (1).

[0053] (1)

[0054] where, I L represents the average current of the inductor, T represents the switching period of the converter, D represents the duty cycle of the power switch control signal (0 < D < 1), and DT represents the conduction time of the switch tube within each period. The total charge Q of the output load O can be expressed by the following formula (2).

[0055] (2)

[0056] where, Q L represents the current provided by the inductor to the load. Therefore, the ratio of the average inductor current I L to the load current I O can be expressed by the following formula (3).

[0057] (3)

[0058] According to the embodiments of the present disclosure, the ratio range of the average inductor current of the converter to the load current in the above formula (3) is (3 / 5, 1). From formula (1), the charge Q provided by the flying capacitor to the load C decreases as the duty cycle decreases. When the duty cycle approaches 0, the flying capacitor hardly provides charge to the load, the ratio approaches 1, and the inductor current does not decrease compared with the traditional DC-DC converter. Therefore, Figure 1a the dual-path hybrid DC-DC sensor shown has limited ability to reduce the inductor current, which is not conducive to reducing the inductor size and increasing the current density.

[0059] Figure 2a Schematically shows the circuit diagram of a multi-path buck DC-DC sensor in the related art.

[0060] As Figure 2a shown, this embodiment includes switches S1, S2, S3, S4, S5, S6, S7, S8, S9, S 10 , S 11 , S 12 , flying capacitors C F1 and C F2, C F3 , C F4 , inductance L, load capacitance C o , load current source I o .

[0061] Figure 2b The equivalent circuit diagram of a multi-channel buck DC-DC sensor in the related art in a first working state is schematically shown.

[0062] Figure 2c The equivalent circuit diagram of a multi-channel buck DC-DC sensor in the related art in the second working state is schematically shown.

[0063] like Figure 1b and Figure 1c As shown, in Phase 1, the flying capacitor C F1 , C F3 Charging, flying capacitor C F2 , C F4 Discharge, inductor L charging, S1, S4, S5, S9, S 10 , S 11 Closed, S2, S3, S6, S7, S8, S 12 Disconnect, C F1 The charge amount is I L DT; In Phase 2, the flying capacitor C F1 , C F3 Discharge, flying capacitor C F2 , C F4 Charging, inductor L discharge, S1, S4, S5, S9, S 10 , S 11 Disconnect, S2, S3, S6, S7, S8, S 12 Closed, C F2 The charging amount is I L T. The charge of each flying capacitor can be expressed as the following formula (4).

[0064] (4)

[0065] Among them, Q C3 Represents C F3 The charge, Q C4 Represents C F4 The charge, Q C1 Represents C F1 The charge, Q C2 Represents C F2 The total charge Q provided by the flying capacitor to the load output in the two working states is O It can be expressed as the following formula (5).

[0066] (5)

[0067] Inductance mean I L Current and load current I O The ratio can be expressed as the following formula (6).

[0068] (6)

[0069] According to the embodiment of the present disclosure, the converter has an inductor close to the input, C F2 , C F3 , C F4 Both can play a certain role in amplifying the charge transferred by the inductor. The ratio of the inductor mean current to the load current in the above formula (6) is in the range of (1 / 7, 1 / 4). However, it is still difficult to fully utilize the flying capacitor to reduce the inductor current. The inductor mean current has not yet reached the theoretical limit, and it has no design guidance significance for the topology design for reducing the inductor current.

[0070] In view of this, an embodiment of the present disclosure provides a hybrid DC-DC converter circuit, comprising: an input unit, comprising an inductor; a plurality of first capacitor units, each first capacitor unit comprising a first capacitor and a first switch sub-unit; a plurality of second capacitor units, each second capacitor unit comprising a second capacitor and a second switch sub-unit; wherein each first capacitor unit is alternately cascaded with each second capacitor unit, and the input unit is cascaded with the first first capacitor unit; the circuit is used to control the plurality of first switch sub-units and the plurality of second switch sub-units to switch working states respectively within a working cycle in response to a control signal, so as to control the plurality of first capacitors and the plurality of second capacitors to alternately charge / discharge within a working cycle.

[0071] Figure 3 A schematic diagram of a hybrid DC-DC converter circuit according to an embodiment of the present disclosure is schematically shown.

[0072] like Figure 3 As shown, the embodiment 300 includes an input unit 310, a first capacitor unit 320, and a second capacitor unit 330, wherein each first capacitor unit 320 includes a first capacitor 321 and a first switch subunit 322, and each second capacitor unit 330 includes a second capacitor 331 and a second switch subunit 332.

[0073] According to an embodiment of the present disclosure, each first capacitor unit and each second capacitor unit are inductor shunts of the input unit, each capacitor is a flying capacitor, each first capacitor unit and each second capacitor unit are alternately cascaded, and the input unit is cascaded with the first first capacitor unit, and the circuit is used to respond to the control signal, control multiple first switch subunits and multiple second switch subunits to switch working states in one working cycle, respectively, to control multiple first capacitors and multiple second capacitors to alternately charge / discharge in one working cycle, and ensure the conservation of charge of each capacitor. It can be seen that each first capacitor can be connected in parallel with the second capacitor of the previous stage to charge the second capacitor of the next stage in the discharge state, and each second capacitor can be connected in parallel with the first capacitor of the previous stage to charge the first capacitor of the next stage in the discharge state. When each first / second capacitor is charged, it is connected in series with the parallel network formed by the first capacitor and the second capacitor of the first two stages, which can realize the maximization of the amount of self-charged charge while transferring charge to the next stage, and the whole can constitute a flying capacitor series-parallel interlaced topological structure. Therefore, the charge of each first / second capacitor increases with the large number of stages, and the effect of step-by-step multiplication of charge is achieved.

[0074] According to the embodiments of the present disclosure, the connection method of the switches in each first / second switch sub-unit is not limited herein, as long as it is ensured that the alternating charging / discharging of each first / second capacitor can be achieved by switching its working state, and it can be increased or decreased according to the actual situation based on the timing within the working cycle.

[0075] According to an embodiment of the present disclosure, each first capacitor unit is alternately cascaded with each second capacitor unit, and the input unit is cascaded with the first first capacitor unit. Multiple first switch sub-units and multiple second switch sub-units are controlled by a control signal to switch working states within a working cycle, so that multiple first capacitors and multiple second capacitors are alternately charged / discharged within a working cycle, ensuring that the charges of all first capacitors and second capacitors are conserved within a working cycle, and the charges of each first capacitor and second capacitor are accumulated and reused step by step, which is conducive to maximizing the current diversion of the capacitor to the inductor, thereby reducing the DC impedance conduction loss of the inductor; at the same time, when the inductor current reduction amplitude is specified, the minimum number of capacitors can be selected to achieve the maximum reduction of the inductor current. Each first capacitor unit is alternately cascaded with each second capacitor unit, and the input unit is cascaded with the first first capacitor unit. Each first capacitor unit is alternately cascaded with each second capacitor unit, and the input unit is cascaded with the first first capacitor unit. Each first capacitor unit is alternately cascaded with each second capacitor unit, and the input unit is cascaded with the first first capacitor unit. The utilization rate of the capacitor is improved and the power consumption of the circuit is reduced.

[0076] According to an embodiment of the present disclosure, the working cycle includes a first time period corresponding to a first charging and discharging state and a second time period corresponding to a second charging and discharging state, and the input unit also includes an input capacitor and a control switch subunit; in the first charging and discharging state, the input capacitor is charged, and for each first capacitor unit, the first switch subunit switches to the first working state to control the discharge of the first capacitor, and for each second capacitor unit, the second switch subunit switches to the second working state to control the charging of the second capacitor; in the second charging and discharging state, the input capacitor is discharged, and for each first capacitor unit, the first switch subunit switches to the second working state to control the charging of the first capacitor, and for each second capacitor unit, the second switch subunit switches to the first working state to control the discharge of the second capacitor.

[0077] Figure 4a The equivalent circuit diagram of the hybrid DC-DC converter in the first charging and discharging state according to the embodiment of the present disclosure is schematically shown.

[0078] Figure 4b The equivalent circuit diagram of the hybrid DC-DC converter in the second charge and discharge state according to the embodiment of the present disclosure is schematically shown.

[0079] like Figure 4a and Figure 4b As shown, taking 2k-1 (k is a positive integer) first / second capacitors as an example, that is, the circuit includes k first capacitors and k-1 second capacitors, C1 represents the input capacitor, C2 represents the first first capacitor, C3 represents the first second capacitor, and C 2k is the kth first capacitor, C 2k-1 is the k-1th second capacitor. In the first charge and discharge state (Phase 1), it can be regarded as C1, C3...C 2k-1 They are connected in series, and C2 is connected in parallel with C1 to discharge, and provide charging charge for C3. At the same time, C4 is connected in parallel with C3, C4 is discharged, and the charging charge of C5 comes from C3 and C4, that is, all the first capacitors are discharged, and all the second capacitors are charged.

[0080] According to the embodiment of the present disclosure, in the second charge and discharge state (Phase 2), it can be regarded as C2, C4...C 2k They are connected in series, and C2 and C3 are discharged in parallel, providing charge for C4. At the same time, C1 is connected in parallel with the inductor to provide charge for C2, that is, all the second capacitors are discharged and all the first capacitors are charged.

[0081] According to an embodiment of the present disclosure, in the case of 2k first / second capacitors, the circuit includes k first capacitors and k second capacitors. The difference from the circuit of the above-mentioned 2k-1 first / second capacitors is only the number of capacitors connected in series with the subsequent circuit unit, which is not elaborated here.

[0082] It should be noted that, in actual circuit layout, the settings of the switches in the first switch sub-unit, the second switch sub-unit and the control sub-unit must meet the above requirements. Figure 4a and Figure 4b The series / parallel connection mode of each capacitor in the first / second charging and discharging state is not specifically limited.

[0083] It can be seen from this that Figure 4a and 4b It can be regarded as the inductor and output V O A two-port switched capacitor network is inserted between the input V IN Directly connected only to the inductor, the switched capacitor network acts as a charge amplifier and can multiply a smaller inductor current into a higher load current. Solving the minimum inductor current problem is equivalent to solving the maximum charge ratio of the switched capacitor network. The Fibonacci-type switched capacitor network can achieve the maximum voltage conversion ratio and charge conversion ratio.

[0084] According to an embodiment of the present disclosure, in the second charge-discharge state, the charge of the first capacitor is expressed as the following formula (7).

[0085] (7)

[0086] in, represents the charge of the ath first capacitor, represents the charge of the a-1th second capacitor, represents the charge of the a-1th first capacitor, where a is a positive integer, represents the inductor charge, represents the charge of the input capacitor.

[0087] According to an embodiment of the present disclosure, in the first charge-discharge state, the charge of the second capacitor is expressed as the following formula (8).

[0088] (8)

[0089] in, represents the charge of the ath first capacitor, represents the charge of the a-1th second capacitor, represents the charge of the a-1th first capacitor, where a is a positive integer, represents the inductor charge, represents the charge of the input capacitor.

[0090] According to the embodiments of the present disclosure, by switching the working states of the first switch subunits and the second switch subunits and the first / second charge-discharge states of the switching circuit, the step-by-step accumulation and increase of the first / second capacitors at each level are achieved, which complies with the Fibonacci sequence law, and the step-by-step accumulation, reuse and multiplication of the flying capacitors for storing and transmitting charges are achieved. Therefore, the flying capacitors can be used to shunt the inductors to the maximum extent, thereby minimizing the inductor current, providing the minimum limit of the inductor mean current, reducing the inductor DCR conduction loss, saving the number of flying capacitors, and relaxing the demand for large-size, small-DCR inductors.

[0091] According to an embodiment of the present disclosure, the circuit further includes an output load unit, and a ratio Y of the current of the inductor to the current of the output load unit is expressed as the following formula (9).

[0092] (9)

[0093] in, represents the current of the inductor, represents the output current of the load unit, represents the charge of the inductor, represents the charge of the Ath first capacitor, A is the total number of the first capacitors, represents the charge of the Bth second capacitor, where B is the total number of the second capacitors.

[0094] According to the embodiments of the present disclosure, when the inductor current is relatively small, the current of the output load unit can still be multiplied by the first / second capacitors.

[0095] According to an embodiment of the present disclosure, when the working time corresponding to the first charge-discharge state is DT and the circuit includes 2k-1 first / second capacitors, the charge of the input capacitor is DI L T,. That is, the above (9) can be equivalent to the following formula (10).

[0096] (10)

[0097] Among them, the Fibonacci sequence F={1(F0), 1(F1), 3, 5, 8, 13...}, that is, when D approaches 0, the current ratio is the smallest, and when D approaches 1, the current ratio is the largest.

[0098] Figure 5 The diagram schematically shows a curve showing a change in the ratio of the inductor current to the output load unit current of various DC-DC converters according to an embodiment of the present disclosure as a function of the duty cycle.

[0099] like Figure 5As shown, the three DC-DC converters are all composed of a total of 4 capacitors including the input capacitor. The current ratio of the Fibonacci hybrid DC-DC converter of the embodiment of the present disclosure is smaller than the current ratio of other DC-DC converters in the related art, that is, the first / second capacitors can be fully utilized to achieve the lowest inductor current.

[0100] According to an embodiment of the present disclosure, the control switch subunit includes a first control switch, a second control switch and a third control switch, the first end of the first control switch is connected to a power supply, the second end of the first control switch and the first end of the second control switch are both connected to the first plate of the input capacitor, the first end of the third control switch and the first end of the inductor are both connected to the second plate of the input capacitor, the second end of the third control switch is grounded, and the second end of the second control switch and the second end of the inductor are both connected to the first plate of the first capacitor in the first first capacitor unit.

[0101] According to an embodiment of the present disclosure, the first switch subunit includes a first switch, a second switch, and a third switch. For the nth first switch subunit, the first plate of the first capacitor is connected to the first end of the first switch, and the second plate of the first capacitor is connected to the first end of the second switch and the first end of the third switch; the second end of the third switch is grounded, and the second end of the first switch and the second end of the second switch are both connected to the first plate of the second capacitor in the nth second capacitor unit.

[0102] According to an embodiment of the present disclosure, the second switch subunit includes a fourth switch, a fifth switch, and a sixth switch. For the nth second switch subunit, the first plate of the second capacitor is connected to the first end of the fourth switch, and the second plate of the second capacitor is connected to the first end of the fifth switch and the first end of the sixth switch; the second end of the sixth switch is grounded, and the second end of the fourth switch and the second end of the fifth switch are both connected to the first plate of the first capacitor in the n+1th first capacitor unit.

[0103] In order to better understand the connection relationship between the control switch subunit and each switch in each first / second switch subunit in the embodiment of the present disclosure, the following takes two first capacitor units and one second capacitor unit, that is, a total of four capacitors including the input capacitor, as an example. Figure 6a~Figure 6c The connection relationship of the entire circuit is explained.

[0104] Figure 6a A circuit diagram of a hybrid DC-DC converter according to an embodiment of the present disclosure is schematically shown.

[0105] like Figure 6aAs shown, the control switch subunit includes a first control switch S1, a second control switch S2 and a third control switch S3, the first switch subunit includes a first switch, a second switch and a third switch, and the second switch subunit includes a fourth switch, a fifth switch and a sixth switch.

[0106] It should be noted that, for the input unit, the positions of the input capacitor and the inductor are not limited, and the figure only shows one case, and the positions of the input capacitor and the inductor can also be swapped.

[0107] According to an embodiment of the present disclosure, a first end of the first control switch S1 is connected to a power supply, a second end of the first control switch S1 and a first end of the second control switch S2 are both connected to a first plate of an input capacitor C1, a first end of the third control switch S3 and a first end of an inductor L are both connected to a second plate of the input capacitor C1, a second end of the third control switch S3 is grounded, and a second end of the second control switch S2 and a second end of the inductor L are both connected to a first plate of a first capacitor C2 in the first first capacitor unit.

[0108] According to an embodiment of the present disclosure, for the first first switch subunit, the first plate of the first capacitor C2 is connected to the first end of the first switch S4, and the second plate of the first capacitor C2 is connected to the first end of the second switch S5 and the first end of the third switch S6; the second end of the third switch S6 is grounded, and the second end of the first switch S4 and the second end of the second switch S5 are both connected to the first plate of the second capacitor C3 in the first second capacitor unit.

[0109] According to an embodiment of the present disclosure, for the first second switch subunit, the first electrode plate of the second capacitor C3 is connected to the first end of the fourth switch S7, the second electrode plate of the second capacitor C3 is connected to the first end of the fifth switch S8 and the first end of the sixth switch S9; the second end of the sixth switch S9 is grounded, and the second end of the fourth switch S7 and the second end of the fifth switch S8 are both connected to the first electrode plate of the first capacitor C4 in the second first capacitor unit. For the second first switch subunit, the first electrode plate of the first capacitor C4 is connected to the first switch S 10 The first end of the first capacitor C4 is connected to the second switch S 11 The first end of the third switch S 12 The first end of the third switch S 12 The second end of the first switch S 10 The second end of the second switch S 11 The second end is connected to the output capacitor C of the output load unit o .

[0110] According to an embodiment of the present disclosure, in the first charge and discharge state, the first control switch is closed, the second control switch and the third control switch are opened, and for the nth first switch subunit, the first switch and the third switch are closed, and the second switch is opened; for the nth second switch subunit, the fifth switch is closed, and the fourth switch and the sixth switch are opened. In the second charge and discharge state, the first control switch is opened, the second control switch and the third control switch are closed, and for the nth first switch subunit, the first switch and the third switch are opened, and the second switch is closed; for the nth second switch subunit, the fifth switch is opened, and the fourth switch and the sixth switch are closed.

[0111] According to the embodiments of the present disclosure, the types of the switches in the control switch subunit, the first switch subunit and the second switch subunit may be various voltage-resistant NMOS tubes, PMOS tubes, and some switches may even be diodes.

[0112] Figure 6b A circuit diagram of a hybrid DC-DC converter in a first charging and discharging state according to an embodiment of the present disclosure is schematically shown.

[0113] like Figure 6b As shown, in the first charge and discharge state, the first capacitor is discharged, and the input capacitor and the second capacitor are charged. 10 , S 12 Closed, the first capacitors C2 and C4 are grounded.

[0114] Figure 6c A circuit diagram of a hybrid DC-DC converter in a second charge and discharge state according to an embodiment of the present disclosure is schematically shown.

[0115] like Figure 6c As shown, in the second charge and discharge state, the second capacitor and the input capacitor are discharged, and the first capacitor is charged. 11 Closed, the second capacitor C3 is grounded.

[0116] According to an embodiment of the present disclosure, in the above Figure 6a In the circuit shown, the charge of each first / second capacitor, i.e., input capacitor, can be expressed as the following formula (11).

[0117] (11)

[0118] Among them, Q C1 is the charge of the input capacitor C1, Q C2 is the charge of the first capacitor C2, Q C3 is the charge of the first second capacitor C3, Q C4 is the charge of the second first capacitor C4.

[0119] According to an embodiment of the present disclosure, the total charge Q provided by each capacitor to the output load unit is O It can be expressed as the following formula (12).

[0120] (12)

[0121] According to an embodiment of the present disclosure, the ratio Y of the current of the inductor to the current of the output load unit is expressed as the following formula (13).

[0122] (13)

[0123] It can be seen that, compared with the above-mentioned formula (3) and formula (6) of the related art, the reduction of the inductor current in the embodiment of the present disclosure is more obvious.

[0124] According to the embodiments of the present disclosure, for a given number of first / second capacitors, the circuit can maximize the degree of reduction in the inductor current. At the same time, for a given reduction in the inductor current, a minimum number of first / second capacitors can be used to avoid waste of capacitors, thereby improving the efficiency of the entire system.

[0125] In addition to the two first capacitor units and the one second capacitor unit, a DC-DC converter consisting of one first capacitor unit and one second capacitor unit, that is, a total of three capacitors including an input capacitor, may also be used.

[0126] Figure 7a A circuit diagram of another hybrid DC-DC converter in a first charging and discharging state according to an embodiment of the present disclosure is schematically shown.

[0127] like Figure 7a As shown, in the first charge and discharge state, switches S1, S4, S6, and S8 are closed, C1 and C3 are charged, and C2 is discharged. At this time, C1 and C2 are connected in parallel to supply power to C3.

[0128] Figure 7b A circuit diagram of another hybrid DC-DC converter in a second charge and discharge state according to an embodiment of the present disclosure is schematically shown.

[0129] like Figure 7b As shown, in the second charge and discharge state, switches S2, S3, S5, S7, and S9 are closed, C1 and the inductor are discharged, C2 is charged, and at this time C2 and C3 are connected in parallel to form C O powered by.

[0130] In addition, a first capacitor unit, that is, a DC-DC converter composed of two capacitors including an input capacitor, may also be used.

[0131] Figure 8aA circuit diagram of another hybrid DC-DC converter in a first charging and discharging state according to an embodiment of the present disclosure is schematically shown.

[0132] like Figure 8a As shown, in the first charge and discharge state, switches S2, S4, and S6 are closed, and C1 and C2 are connected in parallel to form C O powered by.

[0133] Figure 8b A circuit diagram of another hybrid DC-DC converter in a second charge and discharge state according to an embodiment of the present disclosure is schematically shown.

[0134] like Figure 8b As shown, in the second charge and discharge state, switches S1, S3, and S5 are closed, C1 and the inductor are discharged in parallel to supply power to C2, and at this time C2 is C O powered by.

[0135] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram may represent a module, a program segment, or a part of a code, and the above-mentioned module, program segment, or a part of the code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box may also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart, can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions. It can be understood by those skilled in the art that the features recorded in the various embodiments of the present disclosure can be combined and / or combined in a variety of ways, even if such a combination or combination is not explicitly recorded in the present disclosure. In particular, without departing from the spirit and teaching of the present disclosure, the features described in the various embodiments of the present disclosure may be combined and / or combined in a variety of ways. All of these combinations and / or combinations fall within the scope of the present disclosure.

[0136] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes and are not intended to limit the scope of the present disclosure. Although the embodiments are described above, this does not mean that the measures in the various embodiments cannot be used in combination to advantage. Without departing from the scope of the present disclosure, those skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A hybrid DC-DC converter circuit, characterized in that: include: An input unit including an inductor; A plurality of first capacitor units, each of which comprises a first capacitor and a first switch sub-unit; A plurality of second capacitor units, each of which comprises a second capacitor and a second switch sub-unit; Wherein, each of the first capacitor units and each of the second capacitor units are alternately cascaded, and the input unit is cascaded with the first of the first capacitor units; The circuit is used to control the first switch subunits and the second switch subunits to switch working states in one working cycle in response to a control signal, so as to control the first capacitors and the second capacitors to charge / discharge alternately in one working cycle.

2. The circuit according to claim 1, characterized in that The working cycle includes a first period corresponding to the first charge-discharge state and a second period corresponding to the second charge-discharge state, and the input unit also includes an input capacitor and a control switch subunit; In the first charge-discharge state, the input capacitor is charged, and for each of the first capacitor units, the first switch subunit is switched to the first working state to control the first capacitor to discharge, and for each of the second capacitor units, the second switch subunit is switched to the second working state to control the second capacitor to charge; In the second charging and discharging state, the input capacitor discharges, and for each of the first capacitor units, the first switch subunit switches to the second working state to control the charging of the first capacitor, and for each of the second capacitor units, the second switch subunit switches to the first working state to control the discharging of the second capacitor.

3. The circuit according to claim 2, characterized in that The control switch subunit includes a first control switch, a second control switch and a third control switch, wherein the first end of the first control switch is connected to a power supply, the second end of the first control switch and the first end of the second control switch are both connected to the first plate of the input capacitor, the first end of the third control switch and the first end of the inductor are both connected to the second plate of the input capacitor, the second end of the third control switch is grounded, and the second end of the second control switch and the second end of the inductor are both connected to the first plate of the first capacitor in the first first capacitor unit.

4. The circuit according to claim 3, characterized in that The first switch subunit includes a first switch, a second switch, and a third switch. For the nth first switch subunit, the first plate of the first capacitor is connected to the first end of the first switch, and the second plate of the first capacitor is connected to the first end of the second switch and the first end of the third switch; the second end of the third switch is grounded, and the second end of the first switch and the second end of the second switch are both connected to the first plate of the second capacitor in the nth second capacitor unit.

5. The circuit according to claim 4, characterized in that The second switch subunit includes a fourth switch, a fifth switch, and a sixth switch. For the nth second switch subunit, the first plate of the second capacitor is connected to the first end of the fourth switch, and the second plate of the second capacitor is connected to the first end of the fifth switch and the first end of the sixth switch; the second end of the sixth switch is grounded, and the second end of the fourth switch and the second end of the fifth switch are both connected to the first plate of the first capacitor in the n+1th first capacitor unit.

6. The circuit according to claim 5, characterized in that In the first charge and discharge state, the first control switch is closed, the second control switch and the third control switch are opened, and for the nth first switch subunit, the first switch and the third switch are closed, and the second switch is opened; For the nth second switch subunit, the fifth switch is closed, and the fourth switch and the sixth switch are opened.

7. The circuit according to claim 5, characterized in that In the second charge and discharge state, the first control switch is opened, the second control switch and the third control switch are closed, and for the nth first switch subunit, the first switch and the third switch are opened, and the second switch is closed; For the nth second switch subunit, the fifth switch is opened, and the fourth switch and the sixth switch are closed.

8. The circuit according to claim 2, characterized in that In the second charge-discharge state, the charge of the first capacitor is expressed as follows: in, represents the charge of the ath first capacitor, represents the charge of the a-1th second capacitor, represents the charge of the a-1th first capacitor, where a is a positive integer, represents the inductor charge, represents the charge of the input capacitor.

9. The circuit according to claim 2, characterized in that In the first charging and discharging state, the charging charge of the second capacitor is expressed as follows: in, represents the charge of the ath second capacitor, represents the charge of the a-1th second capacitor, represents the charge of the ath capacitor, where a is a positive integer. represents the charge of the first capacitor, represents the charge of the input capacitor.

10. The circuit according to claim 1, characterized in that The circuit further includes an output load unit, and the ratio Y of the current of the inductor to the current of the output load unit is expressed as the following formula: in, represents the current of the inductor, represents the output current of the load unit, represents the charge of the inductor, represents the charge of the Ath first capacitor, A is the total number of the first capacitors, represents the charge of the Bth second capacitor, where B is the total number of the second capacitors.

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