System for suppressing ringing effect of DCDC converter

Abstract

The invention discloses a suppression system for a ringing effect of a DCDC converter. The suppression system comprises a zero-cross detection circuit, a logic control circuit and a DCDC power level circuit, the DCDC power level circuit is connected with the zero cross detection circuit and the logic control circuit in sequence; relates to the technical field of DCDC converters, and solves the technical problems that LC resonance can occur between an inductor and a parasitic capacitor, a remarkable oscillation phenomenon is generated, and obvious oscillation waveforms of high-frequency oscillation signals can appear at a switch node (SW end). By providing the design of a power tube lower tube NMOS (N-channel metal oxide semiconductor) under dynamic segmented control, the power tube lower tube NMOS is divided into three parts of nmos1, nmos2 and nmos3, the on-off state of the power tube lower tube NMOS is dynamically adjusted in a time-sharing manner, different working conditions are adapted in a dynamic adjustment manner, a fixed damping resistor does not need to be selected, the system adaptability is improved, and the efficiency is kept while ringing is inhibited to the maximum extent.

Description

Technical Field

[0001] The invention belongs to the technical field of DCDC converters, and in particular is a system for suppressing the ringing effect of a DCDC converter. Background Art

[0002] In the power management module, the DCDC converter has become a vital component due to its large driving capability and high efficiency. Especially in today's microcontroller (MCU) and other chips, most electronic devices are in standby mode for a long time, causing the MCU to be almost unloaded or lightly loaded for a long time. At this time, the BUCK type DCDC usually enters the discontinuous conduction mode (DCM) working mode. In this working mode, the inductor current will be reduced to 0. When the power tube is suddenly turned off, due to the parasitic capacitance from the SW end to the ground of the power tube and the inductance of the power stage in the loop, LC resonance is inevitably generated, and ringing occurs. Since the size of the inductance and parasitic capacitance cannot be ignored, this oscillation may affect the normal operation of the circuit.

[0003] In the discontinuous conduction mode (DCM) operation mode, when the load current is small, the inductor current will return to zero in each switching cycle. At this time, the upper tube and the lower tube work alternately, and the falling slope of the inductor current is -VOUT / L, which means that the current will gradually decrease until it returns to zero during the conduction period of the lower tube, and reverse flow may occur. In order to prevent energy loss caused by this current reverse flow, especially to avoid charge leakage in the output capacitor, the current design introduces an inductor current zero-crossing detection circuit, which is used to detect whether the inductor current has reached zero. When it crosses zero, it will immediately trigger the operation of shutting down the lower tube, thereby preventing the current from continuing to flow back. This mechanism effectively prevents unnecessary current backflow and improves system efficiency. However, in this process, due to the presence of parasitic capacitance between the lower tube of the power tube and the inductor, LC oscillation is inevitably formed in the loop. When the lower tube is turned off, the parasitic capacitance and the inductor work together, which may cause ringing and generate unnecessary high-frequency noise.

[0004] In the process According to KCL's law: L -i C -i R =0(4); Combining the above formulas (2) and (3), we can get the quadratic differential equation: Its characteristic equation is: The characteristic roots of the characteristic equation are: The characteristic root indicates that the RLC circuit will have different damping states depending on the inductance, capacitance and resistance: When , it is in over-damping state; when When , it is in critical damping state; when When the lower tube is turned off, due to the presence of parasitic capacitance, the resistance R in the circuit will be approximately infinite, causing the system to be in an underdamped state. In this state, LC resonance will occur between the inductor and the parasitic capacitance, resulting in significant oscillation. These high-frequency oscillation signals will not only show obvious oscillation waveforms at the switch node (SW end), but may also leak through the inductor's magnetic field, or couple with other circuits through parasitic capacitance, especially interfering with sensitive circuits such as radio frequency (RF). This interference may affect the normal operation of the system, causing noise, distortion, or even functional failure. Summary of the invention

[0005] The present invention aims to solve at least one of the technical problems existing in the prior art; to this end, the present invention proposes a suppression system for the ringing effect of a DCDC converter, which is used to solve the above technical problems. The present invention proposes a design of a power tube NMOS under dynamic segmented control, divides the power tube NMOS under the power tube into three parts, nmos1, nmos2, and nmos3, and the gates are respectively controlled by CTRL1, CTRL2, and CTRL3 signals generated by a logic control circuit, and dynamically adjusts their switch states in time-sharing to solve the above problems.

[0006] To achieve the above object, a first aspect of the present invention provides a system for suppressing the ringing effect of a DCDC converter, comprising: a zero-crossing detection circuit, a logic control circuit and a DCDC power stage circuit; the DCDC power stage circuit is connected to the zero-crossing detection circuit and the logic control circuit in sequence;

[0007] The DCDC power stage circuit comprises an upper power tube PMOS and a lower power tube NMOS; wherein the lower power tube NMOS is divided into nmos1, nmos2 and nmos3 according to the number of power tubes connected in parallel; the source and drain of nmos1, nmos2 and nmos3 are arranged in parallel, and the gates of nmos1, nmos2 and nmos3 are respectively connected to the control terminals CTRL1, CTRL2 and CTRL3 of the logic control circuit;

[0008] The drains of the upper power tube PMOS and the lower power tube NMOS are connected to the connection end of the power supply voltage at the SW end; the SW end is connected to the MOS tube gate at the positive input end of the zero-crossing detection circuit.

[0009] The logic control circuit includes a dead zone control circuit, a power tube driving circuit, a delay circuit and a data selector.

[0010] It should be noted that the size of each group of NMOS lower tubes mentioned above is different. This setting allows the damping resistor to have different resistance values ​​when different groups of lower tubes are turned on, thereby ensuring the linearity of the resistance increase of the damping resistor.

[0011] Preferably, the SW terminal of the DCDC power stage circuit is connected to the positive input terminal of the zero-crossing detection circuit; and the output terminal of the zero-crossing detection circuit is connected to the zero-crossing control signal input terminal of the logic control circuit.

[0012] Preferably, the dead zone control circuit connects the oscillator to the input ends of the two power tube drive circuits respectively, and the output end Hctrl of the upper tube drive circuit corresponding to the upper tube PMOS of the power tube is connected to the gate of the upper tube of the power tube. Through this connection, the logic control circuit can turn on or off the upper tube according to the state of the PWM signal to realize the control of the conduction time of the upper tube; the output end Lctr1 of the power tube drive circuit corresponding to the lower tube NMOS of the power tube is connected to the input end of the AND gate, the output end of the AND gate is connected to the input end of the power tube drive circuit, and the other input end of the AND gate is connected to the output of the zero-crossing detection circuit; the outputs CTRL1, CTRL2, and CTRL3 of the dead zone control circuit are connected to the gates of nmos1, nmos2 and nmos3, the input end of the delay circuit is respectively connected to the outputs CTRL1 and CTRL2 of the dead zone control circuit, and the input end of the delay circuit is connected to the output end of the AND gate.

[0013] Preferably, the zero-crossing detection circuit is started when the PMOS on the power tube is turned off, and the zero-crossing detection circuit is turned off and outputs a zero-crossing signal when the PMOS on the power tube is turned on;

[0014] When the upper tube PMOS of the power tube is turned off, the zero-crossing detection outputs a zero-crossing signal when the voltage at the SW terminal is lower than 0, and the logic control circuit controls the control terminals CTRL1, CTRL2, and CTRL3 through the lower tube NMOS of the power tube and turns off nmos1, nmos2, and nmos3 in sequence through the delay circuit.

[0015] Preferably, the control terminals CTRL1, CTRL2 and CTRL3 of the logic control circuit are respectively connected to the gates of nmos1, nmos2 and nmos3 in the power lower tubes, the zero-crossing signal terminal of the zero-crossing detection circuit is connected to the control terminal of the logic control circuit, and the zero-crossing detection circuit is used to detect the voltage value of the SW terminal of the DCDC power stage circuit, and provide a zero-crossing signal to the logic control circuit when the voltage value of the SW terminal becomes a positive number.

[0016] Preferably, the output end of the zero-crossing detection circuit is connected to the input end A of the AND gate in the logic control circuit, and the other input end B of the AND gate in the logic control circuit is connected to the output end of the PWM generator, and the PWM generator is used to output control signals to the upper power tube PMOS and the lower power tube NMOS; wherein the control signal includes closing and conducting.

[0017] Preferably, when the PWM generator gives a control signal to turn off the upper power tube PMOS and turn on the lower power tube NMOS, and the zero-crossing detection circuit does not give a zero-crossing signal, the AND gate output is a high level.

[0018] Preferably, the output end of the AND gate is connected to the selection end of the data selector, and the output end of the data selector is connected to the input end of the power tube driving circuit; the data selector includes a signal input end a and a signal input end b;

[0019] It should be noted that the data selector includes MUX1 and MUX2. When the output of the AND gate is at a high level, MUX1 and MUX2 simultaneously select the signal input terminal a for input signal. When the output of the AND gate is at a low level, MUX1 and MUX2 simultaneously select the signal input terminal b for input signal.

[0020] Preferably, the signal input terminal a of the data selector is connected to the output terminal of the power supply voltage, the signal input terminal b of the data selector is connected to the AND gate, the inputs of the AND gate are respectively the output signal of the control terminal LCTR1 of the logic control circuit and the output of the zero-crossing detection circuit connected to the inverter, and the output terminal of the data selector is connected to the input terminal CTRL2 of the power tube drive circuit.

[0021] Preferably, the signal input terminal a of the data selector is connected to the input terminal of the power supply voltage, the signal input terminal b of the data selector is connected to the input terminal of the AND gate, the inputs of the AND gate are respectively the output signal CTRL2 of the logic control circuit through the delay circuit and the output of the zero-crossing detection circuit through the inverter, and the output terminal of the data selector is connected to the output terminal CTRL3 of the power tube driving circuit.

[0022] Preferably, the zero-crossing detection circuit is started when the control signal of the upper power tube PMOS of the DCDC power stage circuit is turned off and the control signal of the lower power tube NMOS is turned on;

[0023] When the voltage at the SW terminal is a positive voltage, there is no zero-crossing signal at the output end of the zero-crossing detection circuit; the output end of the AND gate is at a high level, and the data selector signal input end a outputs a signal. At this time, the voltages at the output ends LCTR1, CTRL2 and CTRL3 of the logic control circuit are all power supply voltages, and nmos1, nmos2 and nmos3 in the lower tube of the power tube are turned on at the same time.

[0024] When the voltage at the SW terminal is a negative voltage, the output terminal of the zero-crossing detection circuit outputs a zero-crossing signal, the output terminal of the AND gate is at a low level, and the output terminal CTRL1 of the logic control circuit is at a low level;

[0025] When nmos1 is turned off and nmos2 and nmos3 are turned on, noos2 and nmos3 act as damping resistors to achieve rapid suppression of ringing. The low-level signal of the selection signal input terminal b of the data selector reaches the signal input terminal B of the data selector through the delay circuit after a delay time T0, and CTRL2 is at a low level.

[0026] When nmos1 and nmos2 are turned off and nmos3 is turned on, nmos3 acts as a damping resistor, and the low-level signal of CTRL2 reaches the B terminal of MUX2 through the delay circuit after a delay time T0, and at this time CTRL3 is at a low level;

[0027] When the nmos1, nmos2 and nmos3 are turned off; Based on KCL law L -i C -i R =0 to get the formula The characteristic equation is Characteristic roots of characteristic equation when When , it is in over-damping state; when When , it is in critical damping state; when When , it is underdamped; where Vsw is the voltage at the SW terminal, L is the power stage inductor, C is the lower tube parasitic capacitance, Vo is the output voltage, R is the resistance from the SW terminal to the ground, i L is the current flowing through the inductor, S is the symbol in the S domain representing the complex frequency in the time domain, and RC is the product of R and C.

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] (1) The present invention proposes a dynamic segmented control power tube NMOS design, which divides the power tube NMOS into three parts: nmos1, nmos2, and nmos3. The gates are controlled by CTRL1, CTRL2, and CTRL3 signals generated by a logic control circuit, respectively, and their switch states are dynamically adjusted in time. The segmented control design enables different NMOS to switch in a gradient manner at different ringing stages, effectively adjusting the size of the equivalent damping resistance. In the early stage of ringing, i.e., when the ringing is strong, nmos1, nmos2, and nmos3 are all turned on, with a small resistance value, which can quickly reduce large oscillations; after the ringing is attenuated, i.e., when the ringing is weak, nmos1 and nmos2 are gradually turned off, and only nmos3 is retained, further increasing the damping resistance to avoid excessive loss of output energy. The dynamic adjustment method adapts to different working conditions, and there is no need to select a fixed damping resistance, thereby improving the system adaptability and maximally suppressing the ringing while maintaining efficiency.

[0030] (2) The logic control circuit of the present invention realizes time-sharing control. A delay unit is added to the logic control circuit. By time-sharing delay, nmos1, nmos2 and nmos3 are turned off, and the damping resistance is gradually increased to avoid discontinuous oscillation or energy leakage caused by one-time shutdown. The delay unit ensures smooth transition between each level of NMOS, and gradually increases the damping resistance in a time series to make the ringing suppression process more stable, while avoiding excessive energy loss to the damping path. This design effectively solves the problem of the inability to balance ringing and efficiency in traditional methods, improves the stability of system operation, avoids secondary oscillation in the ringing suppression process, reduces output capacitor energy loss, and further improves conversion efficiency.

[0031] (3) The NMOS damping resistors mentioned in the present invention are all realized by the power tube bottom tube existing in the original DCDC topology, without adding other damping resistors, effectively reducing the layout area and saving costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0033] Figure 1 The framework diagram of a Buck type DC / DC converter with an anti-ringing module circuit added in the present invention;

[0034] Figure 2 is a circuit schematic diagram of the logic control circuit in the present invention;

[0035] Figure 3 It is a partial circuit diagram of the existing Buck type DC / DC converter in the present invention;

[0036] Figure 4 It is a waveform diagram of the SW end of the existing Buck type DC / DC converter in the present invention working in the DCM state;

[0037] Figure 5 Partial schematic diagram of a Buck type DC / DC converter with an anti-ringing module circuit added in the present invention

[0038] Figure 6 The waveform diagram of the SW end of the Buck type DC / DC converter with an anti-ringing module circuit added in the present invention working in the DCM state;

[0039] In the figure, 101 is a DCDC power stage circuit; 102 is a zero-crossing detection circuit; 103 is a logic control circuit; 201 is a dead zone control circuit; 202 is a power tube driving circuit; 203 is a delay circuit; and 204 is a data selector. DETAILED DESCRIPTION

[0040] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0041] See also Figure 1-Figure 6 , the first aspect of the present invention provides a system for suppressing the ringing effect of a DCDC converter, comprising: a zero-crossing detection circuit 102, a logic control circuit 103 and a DCDC power stage circuit 101; the DCDC power stage circuit 101 is connected to the zero-crossing detection circuit 102 and the logic control circuit 103 in sequence;

[0042] See also Figure 1 , 3 As shown in , 5, the DCDC power stage circuit 101 includes a power tube upper tube PMOS and a power tube lower tube NMOS; wherein the power tube lower tube NMOS is divided into nmos1, nmos2 and nmos3 according to the number of power tubes connected in parallel; the source and drain of nmos1, nmos2 and nmos3 are arranged in parallel, and the gates of nmos1, nmos2 and nmos3 are respectively connected to the control terminals LCTR1, CTRL2 and CTRL3 of the logic control circuit 103;

[0043] The drains of the upper power tube PMOS and the lower power tube NMOS are connected to the connection end of the power supply voltage at the SW end; the SW end is connected to the gate of the MOS tube at the positive input end of the zero-crossing detection circuit 102, the input end of the logic control circuit 103 is connected to the output end of the zero-crossing detection circuit 102, and the output end Hctrl of the logic control circuit 103 is connected to the gate of the upper power tube PMOS in the DCDC power stage circuit 101.

[0044] See also Figure 2 As shown, the logic control circuit 103 includes a dead zone control circuit 201 , a power tube driving circuit 202 , a delay circuit 203 and a data selector 204 .

[0045] It should be noted that the size of each group of NMOS lower tubes mentioned above is different. This setting allows the damping resistor to have different resistance values ​​when different groups of lower tubes are turned on, thereby ensuring the linearity of the resistance increase of the damping resistor.

[0046] The SW terminal of the DCDC power stage circuit 101 is connected to the positive input terminal of the zero-crossing detection circuit 102 ; the output terminal of the zero-crossing detection circuit 102 is connected to the zero-crossing control signal input terminal of the logic control circuit 103 .

[0047] See also Figure 2 As shown, the dead zone control circuit 201 connects the oscillator to the input ends of the upper power tube PMOS and the lower power tube NMOS respectively, and the dead zone control circuit converts the output of the oscillator into a two-phase non-overlapping clock and gives it through the power tube driving circuit 202. The output end Hctrl of the power tube driving circuit 202 corresponding to the upper power tube PMOS is connected to the gate of the upper power tube. Through this connection, the logic control circuit 103 can turn on or off the upper tube according to the state of the PWM signal to achieve control of the conduction time of the upper tube; the output end of the power tube driving circuit 202 corresponding to the lower power tube NMOS is connected to the input end of the AND gate, and the outputs CTRL1, CTRL2 and CTRL3 of the dead zone control circuit 201 are respectively connected to the gates of nmos1, nmos2 and nmos3. The output of the zero-crossing detection circuit 102ZCD is usually 1, so when Lctrl is 1, CTRL1, CTRL2, and CTRL3 are all 1, and nmos1, nmos2, and nmos3 are turned on at the same time. After all nmos are turned on, if ZCD=0, first CTRL_MUX=CTRL1=0, nmos1 is turned off, and all MUXs select input terminal B; CTRL1 is connected to the input terminal B of MUX through Delay, that is, CTRL2=0 after delay; similarly, CRTL3=0 after delay to realize the shutdown of nmos one by one.

[0048] In this embodiment, the zero-crossing detection circuit 102 is started when the upper tube PMOS of the power tube is turned off, detects the voltage at the SW terminal, and provides a zero-crossing detection signal to the logic control circuit 103. The control terminals CTRL1, CTRL2, and CTRL3 in the logic control circuit 103 control the off state of the lower tube NMOS of the power tube in the DCDC power stage circuit 101 to suppress the ringing effect in the DCM working state. The zero-crossing detection circuit 102 is turned off when the upper tube PMOS of the power tube is turned on and outputs a zero-crossing signal.

[0049] The specific working principle of the above ringing suppression circuit is as follows:

[0050] First, when the PMOS on the power tube in the DCDC power stage circuit 101 is turned off, the zero-crossing detection circuit 102 is started to detect the voltage at the SW terminal in the DCDC power stage circuit 101. When the voltage is detected to be greater than 0V or less than 0V, the following two situations occur.

[0051] The first case: if the zero-crossing detection circuit 102 determines that the voltage at the SW end is less than 0V during the entire lower tube conduction time, it is determined that the inductor current has a zero trend. When there is a zero-crossing trend, nmos1, nmos2, nmos3 start at the same time and are turned off in sequence. If there is no zero-crossing trend, the lower tubes nmos1, nmos2, nmos3 are turned on and off at the same time. When the power tube lower tube conduction time ends, the logic control circuit 103 turns off the power tube lower tubes at the same time through the power tube lower tube NMOS control terminals CTRL1, CTRL2, and CTRL3.

[0052] The second case: if the zero-crossing detection circuit 102 determines that the voltage at the SW end is greater than 0V during the conduction time of the lower tube, it is determined that the inductor current has a trend of crossing zero. When there is a trend of crossing zero, nmos1, nmos2, nmos3 start at the same time and are turned off in sequence. If there is no trend of crossing zero, the lower tubes nmos1, nmos2, nmos3 are turned on and off at the same time. At this time, the potential of the control end LCTR1 of the logic control circuit 103 changes from high to low. After the delay time T0, the potential of the control end CTRL2 of the logic control circuit 103 changes from high to low. After the delay time T0, the potential of the control end CTRL3 of the logic control circuit 103 changes from high to low. Correspondingly, nmos1, nmos2, and nmos3 in the lower tube NMOS of the power tube are also turned off in sequence after the delay T0. The damping resistor in parallel with the parasitic capacitance gradually decreases through nmos2 and nmos3 and finally turns off the path, effectively slowing down the ringing effect.

[0053] In this embodiment, when the upper tube PMOS of the power tube is turned off, the zero-crossing detection outputs a zero-crossing signal when the voltage at the SW terminal is lower than 0, and the logic control circuit 103 controls the control terminals CTRL1, CTRL2, and CTRL3 through the lower tube NMOS of the power tube to turn off nmos1, nmos2, and nmos3 in sequence through the delay circuit 203.

[0054] In this embodiment, the control terminals LCTR1, CTRL2 and CTRL3 of the logic control circuit 103 are respectively connected to the gates of nmos1, nmos2 and nmos3 in the power lower tubes, and the zero-crossing signal terminal of the zero-crossing detection circuit 102 is connected to the control terminal of the logic control circuit 103. The zero-crossing detection circuit 102 is used to detect the voltage value of the SW terminal of the DCDC power stage circuit 101, and provide a zero-crossing signal to the logic control circuit 103 when the voltage value of the SW terminal becomes a positive number.

[0055] In this embodiment, the output end of the zero-crossing detection circuit 102 is connected to the input end A of the AND gate in the logic control circuit 103, and the other input end B of the AND gate in the logic control circuit 103 is connected to the output end of the PWM generator. The PWM generator is used to output control signals to the upper power tube PMOS and the lower power tube NMOS; wherein the control signal includes closing and conducting.

[0056] In this embodiment, when the PWM generator gives a control signal to turn off the upper power tube PMOS and turn on the lower power tube NMOS, and the zero-crossing detection circuit 102 does not give a zero-crossing signal, the AND gate output is high level.

[0057] In this embodiment, the output end of the AND gate is connected to the selection end of the data selector 204MUX1 and MUX2 and the input end LCTR1 of the power tube driving circuit 202, and the data selector 204 includes a signal input end a and a signal input end b;

[0058] It should be noted that: when the output end of the AND gate is at a high level, MUX1 and MUX2 simultaneously select the signal input end a to input the signal; when the output end of the AND gate is at a low level, MUX1 and MUX2 simultaneously select the signal input end b to input the signal.

[0059] In this embodiment, the signal input terminal a of the data selector 204MUX1 is connected to the output terminal of the power supply voltage, the signal input terminal b of the data selector 204 is connected to the AND gate, the inputs of the AND gate are respectively the output signal of the control terminal LCTR1 of the logic control circuit 103 and the output of the zero-crossing detection circuit 102 connected through the inverter, and the output terminal of the data selector 204MUX1 is connected to the input terminal CTRL2 of the power tube driving circuit 202.

[0060] In this embodiment, the signal input terminal a of MUX1 in the data selector 204 is connected to the input terminal of the power supply voltage, the signal input terminal b of MUX1 in the data selector 204, and the input of the AND gate are respectively the output signal CTRL2 of the logic control circuit 103 through the delay circuit 203 and the output of the zero-crossing detection circuit 102 through the inverter, and the output terminal of MUX2 in the data selector 204 is connected to the output terminal CTRL3 of the power tube driving circuit 202.

[0061] In this embodiment, the zero-crossing detection circuit 102 is started when the control signal of the upper power tube PMOS of the DCDC power stage circuit 101 is turned off and the control signal of the lower power tube NMOS is turned on;

[0062] When the SW terminal voltage is a positive voltage, there is no zero-crossing signal at the output end of the zero-crossing detection circuit 102; the output end of the AND gate is a high level, and the data selectors 204MUX1 and MUX2 select the signal input end a of MUX1. At this time, CTRL1, CTRL2, and CTRL3 are all power supply voltages, and nmos1, nmos2, and nmos3 in the lower tube of the power tube are turned on at the same time.

[0063] When the voltage at the SW terminal is a negative voltage, the output terminal of the zero-crossing detection circuit 102 outputs a zero-crossing signal, the output terminal of the AND gate is at a low level, and at this time, LCTR1 is at a low level;

[0064] When nmos1 is turned off and nmos2 and nmos3 are turned on, noos2 and nmos3 act as damping resistors to achieve rapid suppression of ringing. MUX1 and MUX2 in the data selector 204 select data path B. When the low-level signal of LCTR1 passes through the delay circuit 203 and reaches the signal input terminal B of MUX1 after a delay time T0, CTRL2 is at a low level.

[0065] When nmos1 and nmos2 are turned off and nmos3 is turned on, nmos3 acts as a damping resistor, and the low level signal of CTRL2 passes through the delay circuit 203 and reaches the B terminal of MUX2 after a delay time T0, at which time CTRL3 is at a low level;

[0066] When the nmos1, nmos2 and nmos3 are turned off; Based on KCL law L -i C -i R =0 to get the formula The characteristic equation is Characteristic roots of characteristic equation Where Vsw is the voltage at the SW terminal, L is the power stage inductor, C is the parasitic capacitance of the lower tube, Vo is the output voltage, R is the resistance from the SW terminal to the ground, and i L is the current flowing through the inductor, S is the symbol of the S domain, which represents the complex frequency in the time domain, and RC is the product of R and C; nmos2 and nmos3 work in the linear region, which are both switches in the DCDC topology and act as parallel damping resistors of parasitic capacitance. The characteristic roots show that the RLC loop will have different damping states according to the different inductance, capacitance and resistance: when When , it is in over-damping state; when When , it is in critical damping state; when When nmos2 and nmos3 are turned on, they act as a damping resistor with a very small resistance to quickly attenuate the oscillation. At this time, the resonance caused at the SW end of the DCDC topology is effectively suppressed. As nmos2 and nmos3 are turned off, the damping resistor gradually increases and finally turns off completely, avoiding the loss of efficiency caused by the loss of output capacitor charge.

[0067] See also Figure 3 As shown, under this structure, when the load current is relatively low, the DCDC power stage circuit 101 enters the DCM working state. At this time, if the inductor current is reduced to 0, resonance will occur between the parasitic capacitance of the power tube and the inductor. Since the parasitic capacitance is smaller than the output capacitance, this frequency is a relatively high frequency, so a more obvious voltage oscillation will be generated at the SW terminal.

[0068] See also Figure 4 Figure 1 shows the voltage waveform of the SW terminal of the BUCK type DCDC converter in discontinuous conduction mode (DCM). In this circuit, since no damping resistor is introduced at the parasitic capacitor, the structure exhibits an underdamped characteristic. When the NMOS under the power tube is just turned off, the inductor current changes rapidly, causing oscillation between the inductor and the parasitic capacitor, forming a ringing effect with slow decay.

[0069] Specifically, when the NMOS of the power tube is turned off, due to the lack of damping between the inductor and the parasitic capacitor, the circuit enters an underdamped oscillation state, and the sudden change in current causes the voltage waveform at the SW end to oscillate. This oscillation starts at the moment the lower tube is turned off and slowly decays at a certain frequency, which has an adverse effect on the circuit performance. The ringing effect in the underdamped state will not only reduce the conversion efficiency of the DCDC converter, but may also generate electromagnetic interference (EMI), affecting the normal operation of other sensitive electronic devices. Therefore, in order to improve the efficiency and stability of the DCDC converter, it is necessary to introduce a suitable ringing suppression circuit to alleviate the underdamped oscillation through the damping resistor and suppress the ringing effect at the SW end.

[0070] See also Figure 5As shown, under the above structure, when the load current is relatively low, the DCDC enters the DCM working state. When the inductor current drops to zero, nmos1 is turned off first, while nmos2 and nmos3 remain on. At this time, nmos2 and nmos3 together form a damping resistor in parallel with the parasitic capacitor, which effectively limits the voltage change rate on the parasitic capacitor and quickly attenuates the oscillation; then, as the control signal is transmitted step by step, nmos2 is also turned off, leaving only nmos3 to continue to be turned on. At this time, the damping resistor of the parasitic capacitor is only composed of nmos3. Compared with the initial stage, the resistance of the damping resistor gradually increases, so that the oscillation gradually slows down, providing a smooth transition for the subsequent shutdown. When nmos3 is also turned off, the damping resistor is approximately infinite, completely cutting off the current path from the SW terminal to the ground. This configuration effectively avoids the energy leakage of the output capacitor when the DCDC works in the DCM mode, further reducing the power loss.

[0071] Therefore, when the lower tube is turned off in DCM, by connecting a dynamic damping resistor that changes gradually from small to large in parallel between the SW terminal and the ground, the ringing suppression circuit provides different damping effects at different stages of the lower tube shutdown: when the resistance value is small, the oscillation is quickly suppressed, and when the resistance value is large, the system stability and efficiency are guaranteed.

[0072] Figure 6 The voltage waveform at the SW terminal of the BUCK type DCDC with a ringing suppression circuit added is shown when working in DCM. When the zero-crossing detection circuit 102 determines that the inductor current crosses zero, the lower tubes of the power tube are turned off in sequence, and the damping resistor causes the oscillation to decay rapidly. Compared with the case where the ringing suppression circuit is not added, the oscillation frequency and oscillation amplitude are significantly reduced.

[0073] Part of the data in the above formula is calculated by removing the dimension and taking its numerical value. The formula is a formula closest to the actual situation obtained by software simulation of a large amount of collected data; the preset parameters and preset thresholds in the formula are set by technical personnel in this field according to actual conditions or obtained through simulation of a large amount of data.

[0074] The above embodiments are only used to illustrate the technical method of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical method of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical method of the present invention.

Claims

1. A system for suppressing the ringing effect of a DCDC converter, characterized in that: include: A zero-crossing detection circuit (102), a logic control circuit (103) and a DCDC power stage circuit (101); the DCDC power stage circuit (101) is sequentially connected to the zero-crossing detection circuit (102) and the logic control circuit (103); The DCDC power stage circuit (101) comprises an upper power tube PMOS and a lower power tube NMOS; wherein the lower power tube NMOS is divided into nmos1, nmos2 and nmos3 according to the number of power tubes connected in parallel; the source and drain of nmos1, nmos2 and nmos3 are arranged in parallel, and the gates of nmos1, nmos2 and nmos3 are respectively connected to the control terminals CTRL1, CTRL2 and CTRL3 of the logic control circuit (103); The drains of the power tube upper tube PMOS and the power tube lower tube NMOS are connected to the connection end of the power supply voltage at the SW end; the SW end is connected to the MOS tube gate at the positive input end of the zero-crossing detection circuit (102); The logic control circuit (103) comprises a dead zone control circuit (201), a power tube driving circuit (202), a delay circuit (203) and a data selector (204).

2. A system for suppressing the ringing effect of a DCDC converter according to claim 1, characterized in that: The SW end of the DCDC power stage circuit (101) is connected to the positive input end of the zero-crossing detection circuit (102), and the output end of the zero-crossing detection circuit (102) is connected to the zero-crossing control signal input end of the logic control circuit (103).

3. A system for suppressing ringing effect of a DCDC converter according to claim 1, characterized in that: The dead zone control circuit (201) connects the oscillator to the input ends of the two power tube drive circuits (202) respectively; the output end Hctrl of the upper tube drive circuit corresponding to the upper tube PMOS of the power tube is connected to the gate of the upper tube of the power tube; the output end Lctr1 of the power tube drive circuit (202) corresponding to the lower tube NMOS of the power tube is connected to the input end of the AND gate; the output end of the AND gate is connected to the input end of the power tube drive circuit (202); the other input end of the AND gate is connected to the output of the zero-crossing detection circuit (102); the outputs CTRL1, CTRL2 and CTRL3 of the dead zone control circuit (201) are connected to the gates of nmos1, nmos2 and nmos3; the input end of the delay circuit (203) is respectively connected to the outputs CTRL1 and CTRL2 of the dead zone control circuit (201); and the input end of the delay circuit (203) is connected to the output end of the AND gate.

4. A system for suppressing the ringing effect of a DCDC converter according to claim 3, characterized in that: The zero-crossing detection circuit (102) is started when the PMOS on the power tube is turned off, and the zero-crossing detection circuit (102) is turned off and outputs a zero-crossing signal when the PMOS on the power tube is turned on; When the upper tube PMOS of the power tube is turned off, the zero-crossing detection outputs a zero-crossing signal when the voltage at the SW terminal is lower than 0, and the logic control circuit (103) controls the control terminals CTRL1, CTRL2, CTRL3 through the lower tube NMOS of the power tube to turn off nmos1, nmos2, nmos3 in sequence via the delay circuit (203).

5. A system for suppressing the ringing effect of a DCDC converter according to claim 4, characterized in that: The control terminals CTRL1, CTRL2 and CTRL3 of the logic control circuit (103) are respectively connected to the gates of nmos1, nmos2 and nmos3 in the power lower tubes; the zero-crossing signal terminal of the zero-crossing detection circuit (102) is connected to the control terminal of the logic control circuit (103); the zero-crossing detection circuit (102) is used to detect the voltage value of the SW terminal of the DCDC power stage circuit (101), and provide a zero-crossing signal to the logic control circuit (103) when the voltage value of the SW terminal becomes a positive number.

6. A system for suppressing the ringing effect of a DCDC converter according to claim 3, characterized in that: The output end of the zero-crossing detection circuit (102) is connected to the input end of an AND gate in the logic control circuit (103); the other input end of the AND gate in the logic control circuit (103) is connected to the output end of a PWM generator; the PWM generator is used to output a control signal to the upper power tube PMOS and the lower power tube NMOS; wherein the control signal includes closing and conducting; When the PWM generator gives a control signal to turn off the upper power tube PMOS and a control signal to turn on the lower power tube NMOS, and the zero-crossing detection circuit (102) does not give a zero-crossing signal, the AND gate output is a high level.

7. A system for suppressing the ringing effect of a DCDC converter according to claim 3, characterized in that: The output end of the AND gate is connected to the selection end of a data selector (204), and the output end of the data selector (204) is connected to the input end of a power tube driving circuit (202); the data selector (204) comprises a signal input end a and a signal input end b.

8. A system for suppressing the ringing effect of a DCDC converter according to claim 7, characterized in that: The signal input terminal a of the data selector (204) is connected to the output terminal of the power supply voltage, the signal input terminal b of the data selector (204) is connected to an AND gate, the inputs of the AND gate are respectively the output signal of the control terminal LCTR1 of the logic control circuit (103) and the output of the zero-crossing detection circuit (102) connected through an inverter, and the output terminal of the data selector (204) is connected to the input terminal CTRL2 of the power tube drive circuit (202).

9. A system for suppressing the ringing effect of a DCDC converter according to claim 8, characterized in that: The signal input terminal a of the data selector (204) is connected to the input terminal of the power supply voltage, the signal input terminal b of the data selector (204) is connected to the input terminal of the AND gate, the inputs of the AND gate are respectively the output signal CTRL2 of the logic control circuit (103) through the delay circuit (203) and the output of the zero-crossing detection circuit (102) through the inverter, and the output terminal of the data selector (204) is connected to the output terminal CTRL3 of the power tube drive circuit (202).

10. A system for suppressing the ringing effect of a DCDC converter according to claim 9, characterized in that: The zero-crossing detection circuit (102) is started when the control signal of the upper power tube PMOS of the DCDC power stage circuit (101) is turned off and the control signal of the lower power tube NMOS is turned on; When the voltage at the SW terminal is a positive voltage, there is no zero-crossing signal at the output terminal of the zero-crossing detection circuit (102); the output terminal of the AND gate is at a high level, and the signal input terminal a of the data selector (204) outputs a signal. At this time, the voltages at the output terminals LCTR1, CTRL2 and CTRL3 of the logic control circuit (103) are all power supply voltages, and the nmos1, nmos2 and nmos3 are turned on at the same time; When the voltage at the SW terminal is a negative voltage, the output terminal of the zero-crossing detection circuit (102) outputs a zero-crossing signal, the output terminal of the AND gate is at a low level, and at this time, the output terminal CTRL1 of the logic control circuit (103) is at a low level; When nmos1 is turned off and nmos2 and nmos3 are turned on, noos2 and nmos3 act as damping resistors to achieve rapid suppression of ringing. The low-level signal of the selection signal input terminal b of the data selector (204) reaches the signal input terminal B of the data selector (204) through the delay circuit (203) after a delay time T0, and CTRL2 is at a low level. When nmos1 and nmos2 are turned off and nmos3 is turned on, nmos3 acts as a damping resistor, and the low level signal of CTRL2 reaches the B terminal of MUX2 through the delay circuit (203) after a delay time T0, and at this time CTRL3 is at a low level; When the nmos1, nmos2 and nmos3 are turned off; Based on KCL law L -i C -i R =0 to get the formula The characteristic equation is Characteristic roots of characteristic equation when When , it is in over-damping state; when When , it is in critical damping state; when When , it is underdamped; where Vsw is the voltage at the SW terminal, L is the power stage inductor, C is the lower tube parasitic capacitance, Vo is the output voltage, R is the resistance from the SW terminal to the ground, i L is the current flowing through the inductor, S is the symbol in the S domain representing the complex frequency in the time domain, and RC is the product of R and C.

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