Heterogeneous integrated filter structure with transient voltage protection and manufacturing method

Abstract

The invention provides a heterogeneous integrated filter structure with transient voltage protection and a manufacturing method, the filter structure comprises an insulating substrate, the upper surface of the insulating substrate is provided with a mounting groove, and a semiconductor chip with a transient voltage protection function is arranged in the mounting groove. A double-layer spiral inductor is arranged on the upper surface of the insulating substrate and comprises a first plane inductance coil and a second plane inductance coil which are arranged in a stacked mode, and a first passivation layer is arranged between the semiconductor chip and the first plane inductance coil. A first passivation layer is arranged between the first planar inductance coil and the second planar inductance coil, a second passivation layer is arranged between the first planar inductance coil and the second planar inductance coil, a third passivation layer is arranged on the upper surface of the second planar inductance coil, the first passivation layer and the second passivation layer are both provided with through holes used for electrically connecting an upper layer and a lower layer, and filter pins are arranged on the third passivation layer. And the filter pin is electrically connected with the second planar inductance coil. The differential mode bandwidth index of the filter can be improved.

Description

Technical Field

[0001] The present invention relates to the field of filter structures, in particular to a heterogeneous integrated filter structure with transient voltage protection, and also to a filter structure manufacturing method for manufacturing the heterogeneous integrated filter structure with transient voltage protection. Background Art

[0002] As electronic devices become increasingly complex and powerful, the electromagnetic interference (EMI) they are subject to during operation is also increasing. For example, when there is a strong external electromagnetic field, the device will induce voltages in the same direction in adjacent wires through electromagnetic induction, forming a common-mode voltage. Or inside electronic devices, parasitic capacitance and inductance between different circuits are coupled through internal circuits, which may generate common-mode noise.

[0003] Common-mode noise can interfere with the normal operation of electronic devices. For example, in communication systems, common-mode noise superimposed on signals can increase the bit error rate of data transmission, and in severe cases, can cause communication interruption. In wireless communications, common-mode noise can interfere with the antenna's received signal, affecting the communication distance and quality. Therefore, in order to reduce the impact of common-mode noise on signals, common-mode filters or common-mode chokes are usually used to suppress common-mode noise.

[0004] In addition to common-mode noise, electronic equipment is also extremely susceptible to electrostatic discharge and transient surges. Transient Voltage Suppressor (TVS) is a semiconductor component that can effectively protect electronic equipment from damage by transient overvoltages (such as electrostatic discharge, lightning surges, etc.). It has been widely used in various electronic devices.

[0005] In order to suppress common-mode noise and protect against transient overvoltage, researchers have designed a common-mode filter with electrostatic protection function. The equivalent circuit of the common-mode filter is as follows: Figure 1 As shown in the figure, the common-mode inductor is integrated with two TVS components, which can significantly save area. However, the common-mode inductor here is implemented using a silicon-based planar spiral inductor. This type of integrated device has the following problems: (1) The planar spiral inductor will be affected by the loss of the silicon substrate underneath it, resulting in a lower quality factor and deteriorating the matching of the double-layer inductor, ultimately deteriorating the differential mode bandwidth index of the filter; (2) Planar spiral inductors usually occupy a large layout area, which will undoubtedly significantly increase the silicon wafer area and increase manufacturing costs.

[0006] Therefore, the existing common-mode filter design with electrostatic protection function can no longer meet market demand, and a new solution is urgently needed to meet the new requirements of electronic equipment for device performance and cost. Summary of the invention

[0007] In order to solve the problems in the prior art, the present invention provides a heterogeneous integrated filter structure with transient voltage protection, and also provides a filter structure manufacturing method for manufacturing the heterogeneous integrated filter structure with transient voltage protection. By synergistically optimizing the layout of the semiconductor chip and the wiring of the packaging metal layer, the silicon wafer area can be significantly reduced on the basis of realizing the dual functions of electrostatic protection and filtering, and the differential mode bandwidth index of the product can be improved.

[0008] The heterogeneous integrated filter structure with transient voltage protection of the present invention comprises an insulating substrate, a mounting groove is provided on the upper surface of the insulating substrate, a semiconductor chip with transient voltage protection function is provided in the mounting groove, a double-layer spiral inductor is provided on the upper surface of the insulating substrate, the double-layer spiral inductor comprises a first planar inductor coil and a second planar inductor coil which are stacked, a first passivation layer is provided between the semiconductor chip and the first planar inductor coil, a second passivation layer is provided between the first planar inductor coil and the second planar inductor coil, a third passivation layer is provided on the upper surface of the second planar inductor coil, both the first passivation layer and the second passivation layer are provided with through holes for electrically connecting the upper and lower layers, a filter pin is provided on the third passivation layer, and the filter pin is electrically connected to the second planar inductor coil.

[0009] Furthermore, the internal metal circuit of the semiconductor chip is replaced by an external metal circuit layer, and the filter structure also includes a metal circuit layer arranged between the semiconductor chip and the first passivation layer, and the metal circuit layer is used for jumper connection between the semiconductor chip electrode and the first planar inductor coil, and a fourth passivation layer is provided between the semiconductor chip and the metal circuit layer.

[0010] Furthermore, the semiconductor chip without internal metal circuits is completely separated from the double-layer spiral inductor on the vertical projection plane.

[0011] Furthermore, the insulating substrate is made of glass, ceramic or FR4 board.

[0012] Furthermore, the manufacturing process of the filter pins includes implanting solder balls or wire bonding.

[0013] Furthermore, the filter structure includes a common mode filter, a low-pass LC filter or a high-pass LC filter.

[0014] Furthermore, the double-layer spiral inductor is manufactured through a metal layer or a redistribution layer in an integrated circuit process, or is manufactured using a metal layer or a redistribution layer in a packaging process, and the material of the double-layer spiral inductor is a metal conductor.

[0015] Furthermore, the preparation process of the semiconductor chip includes a semiconductor silicon process, a III-V compound semiconductor process or a silicon carbide process.

[0016] The present invention also provides a filter structure manufacturing method for manufacturing the heterogeneous integrated filter structure with transient voltage protection, comprising the following steps: S101: processing a mounting groove on the insulating substrate, wherein the size and depth of the mounting groove are adapted to the size and thickness of the semiconductor chip; S102: depositing a buffer adhesion layer on the upper surface of the insulating substrate, and then etching back the buffer adhesion layer in an area other than the mounting groove; S103: embedding a semiconductor chip in the mounting groove, wherein the upper surface of the semiconductor chip is flush with the upper surface of the insulating substrate; S104: manufacturing a double-layer spiral inductor on the upper surface of the insulating substrate, firstly depositing a first passivation layer and processing a through hole for electrical connection, and then forming a first planar inductor coil on the upper surface of the first passivation layer; then depositing a second passivation layer and processing a through hole for electrical connection, and then forming a second planar inductor coil on the upper surface of the second passivation layer; S105: depositing a third passivation layer on the upper surface of the second planar inductor coil, and then processing filter pins for external connection on the third passivation layer.

[0017] The present invention also provides another filter structure manufacturing method for manufacturing the heterogeneous integrated filter structure with transient voltage protection, comprising the following steps: S201: processing a mounting groove on the insulating substrate, wherein the size and depth of the mounting groove are adapted to the size and thickness of the semiconductor chip; S202: depositing a buffer adhesion layer on the upper surface of the insulating substrate, and then etching back the buffer adhesion layer in an area other than the mounting groove; S203: embedding a semiconductor chip in the mounting groove, wherein the upper surface of the semiconductor chip is flush with the upper surface of the insulating substrate; S204: manufacturing a metal circuit layer for jumper connection on the upper surface of the insulating substrate, firstly, depositing a fourth passivation layer and processing a through hole for electrical connection with the semiconductor chip, and then constructing a metal circuit on the upper surface of the fourth passivation layer; S205: manufacturing a double-layer spiral inductor on the upper surface of the insulating substrate, firstly depositing a first passivation layer and processing a through hole for electrical connection, and then forming a first planar inductor coil on the upper surface of the first passivation layer; then depositing a second passivation layer and processing a through hole for electrical connection, and then forming a second planar inductor coil on the upper surface of the second passivation layer; S206: depositing a third passivation layer on the upper surface of the second planar inductor coil, and then processing filter pins for external connection on the third passivation layer.

[0018] Compared with the prior art, the beneficial effects of the present invention are as follows: compared with the common mode filter directly manufactured on the traditional silicon substrate, the differential mode bandwidth index is expected to be optimized by 30% to 50%. The present invention adopts an insulating substrate such as glass to replace the silicon substrate of the semiconductor device, and then opens a mounting groove on the upper surface of the insulating substrate, and places the semiconductor chip in the mounting groove. Since the semiconductor device itself is very small, the hollow part of the coil of the double-layer spiral inductor has little overlap with the silicon, thereby significantly suppressing the substrate eddy current effect, and avoiding the deterioration of the quality factor and inductance matching of the double-layer inductor by the semiconductor silicon substrate to the greatest extent, thereby improving the differential mode bandwidth index of the filter. In addition, the present invention can significantly reduce the use of silicon wafers, thereby effectively reducing the manufacturing cost; By setting an external metal circuit layer to replace the internal metal circuit of the semiconductor chip, the jumper connection is realized. In this design, only the electrode lead of the semiconductor chip will use the internal metal of the silicon chip. Therefore, the area of ​​the silicon chip used in this example can be further reduced, reducing the cost; the coil of the double-layer spiral inductor can be completely separated from the semiconductor chip in the vertical projection direction, thereby avoiding any substrate loss and further improving the differential mode bandwidth. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the present invention or the solutions in the prior art, a brief introduction is given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0020] Figure 1 The equivalent circuit diagram of the existing common mode filter with electrostatic protection function; Figure 2 This is a schematic diagram of the layout structure of the first embodiment of the present invention; Figure 3 A flow chart of a filter structure manufacturing method according to a first embodiment of the present invention; Figure 4 This is a schematic diagram of the layout structure of the second embodiment of the present invention; Figure 5FIG. 4 is a flow chart of a filter structure manufacturing method according to a second embodiment of the present invention. DETAILED DESCRIPTION

[0021] Unless otherwise defined, all technical and scientific terms used in the present invention have the same meanings as those commonly understood by those skilled in the art to which the present invention belongs; the terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention; the terms "including" and "having" and any variations thereof in the specification and claims of the present invention and the above-mentioned drawings are intended to cover non-exclusive inclusions. The terms "first", "second", etc. in the specification and claims of the present invention or the above-mentioned drawings are used to distinguish different objects, not to describe a specific order.

[0022] Reference to "embodiments" in the present invention means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it mutually exclusive, independent, or alternative to other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described in the present invention may be combined with other embodiments.

[0023] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings.

[0024] like Figure 2-Figure 5 As shown, the heterogeneous integrated filter structure with transient voltage protection of the present invention includes an insulating substrate, a mounting groove is provided on the upper surface of the insulating substrate, a semiconductor chip with transient voltage protection function is provided in the mounting groove, a double-layer spiral inductor is provided on the upper surface of the insulating substrate, the double-layer spiral inductor includes a first planar inductor coil and a second planar inductor coil stacked, a first passivation layer is provided between the semiconductor chip and the first planar inductor coil, a second passivation layer is provided between the first planar inductor coil and the second planar inductor coil, a third passivation layer is provided on the upper surface of the second planar inductor coil, the first passivation layer and the second passivation layer are both provided with through holes for electrically connecting the upper and lower layers, a filter pin is provided on the third passivation layer, and the filter pin is electrically connected to the second planar inductor coil.

[0025] like Figure 2As shown, as the first embodiment of the present invention, the filter structure of this example is a common mode filter, and its insulating substrate adopts a glass substrate 100. The entire common mode filter is composed of a TVS silicon chip 220 embedded in the glass substrate 100 and a double-layer spiral inductor located above the glass substrate 100. The double-layer spiral inductor of this example includes a first planar inductor coil 110 and a second planar inductor coil 111 provided with N turns, wherein the first planar inductor coil 110 and the second planar inductor coil 111 are provided with a hollow area 130, where the magnetic field intensity is the largest. Since the entire filter structure needs to use the "internal metal of the TVS silicon chip 220" to achieve jumper connection, the TVS silicon chip 220 cannot be completely separated from the inductor coil in the vertical projection direction, and there will be a certain overlap. However, it can be seen from the structure that the hollow area 130 of the inductor coil overlaps very little with silicon, thereby significantly suppressing the substrate eddy current effect, and avoiding the deterioration of the quality factor and inductance matching of the double-layer spiral inductor by the semiconductor silicon substrate to the greatest extent, thereby improving the differential mode bandwidth index of the filter.

[0026] The material of the first planar inductor coil 110 and the second planar inductor coil 111 in this example is a conductor, preferably a metal conductor, and can be made of aluminum, copper, aluminum-copper alloy, etc. In addition to the rectangle of this example, the shape of the double-layer spiral inductor in this example can also be square, circular, octagonal, quasi-circular, etc. The double-layer spiral inductor can be manufactured using a metal layer or a redistribution layer in an integrated circuit process, and can also be manufactured using a metal layer or a redistribution layer in a packaging process.

[0027] In this example, the first planar inductor coil 110 and the second planar inductor coil 111 are both made of redistribution layers. To achieve the best magnetic field matching, the layout and routing of the double-layer coils should be as consistent as possible, and the metal material and thickness should also be as similar as possible.

[0028] The insulating substrate may also be a common insulating material substrate such as a ceramic substrate, an FR4 board, etc. The TVS silicon chip 220 of this example may be various common electrostatic protection devices / circuits or surge protection devices / circuits. The process platform based on which the TVS silicon chip 220 of this example is manufactured may adopt a typical semiconductor process platform, including but not limited to semiconductor silicon process, III-V compound semiconductor process, silicon carbide process, etc. This example is described by taking the redistribution layer manufacturing process as an example.

[0029] like Figure 3 As shown in the figure, as one of the embodiments of the first embodiment of the present invention, the packaging process of the common mode filter of this example adopts the 3P3M process (i.e., three passivation layers and three metal layers), and the manufacturing method of the common mode filter of this example is: S101: processing a mounting groove 270 on the glass substrate 200, wherein the size and depth of the mounting groove 270 are adapted to the size and thickness of the semiconductor chip.

[0030] Before processing, a glass substrate 200 is provided. The thickness of the glass substrate 200 is determined by the mechanical strength and the packaging height of the finished filter. In this example, a thicker glass substrate may be used first, and then thinned after step S105 is executed.

[0031] The size and depth of the mounting groove in this example are determined by the "TVS silicon chip" to be embedded later. The mounting groove can be opened by mechanical cutting or laser etching. The process of processing the mounting groove 270 is detailed in Figure 3 (a) and (b) of .

[0032] S102: depositing a buffer adhesion layer 210 on the upper surface of the glass substrate, and then etching back the buffer adhesion layer in the area except the mounting groove.

[0033] The buffer adhesion layer in this example can be a single layer structure, or can be divided into a buffer layer + adhesion layer layered buffer adhesion layer, wherein the buffer layer is used to relieve the mechanical stress and thermal stress between silicon and glass, and the adhesion layer is similar to an insulating glue, which is used to adhere the TVS silicon chip to the mounting groove 270 of the glass substrate 200. Back etching is used to remove the excess "buffer + adhesion" layer on the upper surface of the glass substrate 200, which can be done by etching or grinding. The specific processing process is shown in Figure 3 (c) and (d).

[0034] S103: embedding a TVS silicon chip 220 in the mounting groove 270. The TVS silicon chip 220 is manufactured using silicon technology and can generally be a device such as an avalanche diode, NPN, PNP, silicon controlled rectifier, MOSFET, etc. A metal pad 230 is provided on the upper surface of the TVS silicon chip 220; the upper surface of the TVS silicon chip 220 is flush with the upper surface of the glass substrate 200. For details of the processing process, see Figure 3 (e).

[0035] S104: manufacturing a double-layer spiral inductor on the upper surface of the glass substrate.

[0036] First, a first passivation layer 240 is deposited and a first electrical connection through hole 280 is processed. Subsequently, a first redistribution layer 250 is formed on the upper surface of the first passivation layer 240, and then a first planar inductor coil is etched out of the first redistribution layer 250; then, a second passivation layer 241 is deposited and a second electrical connection through hole 281 is processed. Subsequently, a second redistribution layer 251 is formed on the upper surface of the second passivation layer 241, and then a second planar inductor coil is etched out of the second redistribution layer 251.

[0037] The two redistribution layers each form a planar inductor coil. To ensure matching, in addition to the layout, the material, thickness and other process parameters of the two redistribution layers must be kept consistent as much as possible. The material of the two redistribution layers can preferably be copper. Figure 3 (f)~(i).

[0038] S105: depositing a third passivation layer 242 on the upper surface of the second redistribution layer 251, then opening a pin hole 282 on the third passivation layer 242, and finally processing a filter pin 260 for external connection at the pin hole 282. The manufacturing process of the filter pin can be common process methods such as implanting solder balls or wire bonding. In this example, solder balls are implanted in the pin holes 282 as the external pins of the entire filter product. The solder balls are internally connected to the second redistribution layer 251 inside the filter. For details of the processing process, see Figure 3 (j) and (k).

[0039] The heterogeneous integration process proposed in the present invention is not only applicable to common mode filters, but also to other filter structures containing both "semiconductor chips" and "inductor elements", such as low-pass LC filters, high-pass LC filters, etc.

[0040] like Figure 4 As shown, as the second embodiment of the present invention, based on the first embodiment, a metal line 330 is constructed on the upper surface of the common mode filter glass substrate 300 to replace the internal metal line of the TVS silicon chip, which is used for the jumper connection between the first planar inductor coil 310, the second planar inductor coil 311 and the TVS silicon chip 420, so that the first planar inductor coil 310, the second planar inductor coil 311 and the TVS silicon chip 420 can be completely separated in the vertical projection direction, thereby avoiding any substrate loss and further improving the differential mode bandwidth. At this time, only the electrode of the TVS silicon chip 420 is led to the surface of the TVS silicon chip 420, which will use the metal inside the silicon chip. Therefore, this embodiment can further reduce the area of ​​the silicon chip and effectively reduce the manufacturing cost.

[0041] like Figure 5 As shown, compared with the packaging process (3P3M process) of the first embodiment, this embodiment adopts a 4P4M packaging process, that is, a process of 4 passivation layers and 4 metal layers. The manufacturing method of the filter structure of this embodiment is: S201: processing a mounting groove 470 on the glass substrate 400, wherein the size and depth of the mounting groove 470 are adapted to the size and thickness of the semiconductor chip.

[0042] Before processing, a glass substrate 400 is provided. The thickness of the glass substrate 400 is determined by the mechanical strength and the packaging height of the finished filter product. In this example, a thicker glass substrate can be used first, and then thinned after step S206 is executed to obtain the final product.

[0043] The size and depth of the mounting groove in this example are determined by the "TVS silicon chip" to be embedded later. The mounting groove can be opened by mechanical cutting or laser etching. The process of processing the mounting groove 470 is detailed in Figure 5 (a) and (b) of .

[0044] S202: depositing a buffer adhesion layer 410 on the upper surface of the glass substrate, and then etching back the buffer adhesion layer in the area except the mounting groove.

[0045] The buffer adhesion layer in this example can be a single layer structure, or can be divided into a buffer layer + adhesion layer layered buffer adhesion layer, wherein the buffer layer is used to relieve the mechanical stress and thermal stress between silicon and glass, and the adhesion layer is similar to an insulating glue, which is used to adhere the TVS silicon chip to the mounting groove 470 of the glass substrate 400. Back etching is used to remove the excess "buffer + adhesion" layer on the upper surface of the glass substrate 400, which can be done by etching or grinding. The specific processing process is shown in Figure 5 (c) and (d).

[0046] S203: embed the TVS silicon chip 420 in the mounting groove 470, and the upper surface of the TVS silicon chip 420 is provided with a metal pad 430; the upper surface of the TVS silicon chip 420 is flush with the upper surface of the glass substrate 400. Figure 5 (e).

[0047] S204: manufacturing a metal circuit layer for jumper connection on the upper surface of the glass substrate 400.

[0048] First, the fourth passivation layer 440 is deposited and the third electrical connection through hole 480 electrically connected to the TVS silicon chip 420 is processed, and then the third redistribution layer 450 is formed on the upper surface of the fourth passivation layer 440, and then the metal circuit is etched for the third redistribution layer 450. The processing process of this step is detailed in Figure 5 (f).

[0049] S205: manufacturing a double-layer spiral inductor on the upper surface of the glass substrate.

[0050] First, a first passivation layer 441 is deposited on the upper surface of the metal circuit layer and a first through hole 481 for electrical connection is processed. Subsequently, a first redistribution layer 451 is formed on the upper surface of the first passivation layer 441, and then a first planar inductor coil is etched out of the first redistribution layer 451. Then, a second passivation layer 442 is deposited and a second through hole 482 for electrical connection is processed. Subsequently, a second redistribution layer 452 is formed on the upper surface of the second passivation layer 442, and then a second planar inductor coil is etched out of the second redistribution layer 452. The two redistribution layers each form a planar inductor coil. To ensure matching, in addition to the layout, the material, thickness and other process parameters of the two redistribution layers should be kept as consistent as possible. The material of the two redistribution layers can preferably be copper. For details of the processing process of this step, see Figure 5 (h)~(k).

[0051] S206: depositing a third passivation layer 443 on the upper surface of the second redistribution layer 452, then opening a pin hole 483 on the third passivation layer 443, and finally processing a solder ball 460 for external connection at the pin hole 483 as an external pin of the entire filter product, and the solder ball is inwardly connected to the second redistribution layer 452 inside the filter. For details of the processing process, see Figure 5 (l) and (m).

[0052] Compared with the common mode filter directly manufactured on the traditional silicon substrate, the differential mode bandwidth index of the present invention is expected to be optimized by 30% to 50%. The present invention uses an insulating substrate such as glass to replace the silicon substrate of the semiconductor device, and then opens a mounting groove on the upper surface of the insulating substrate, and places the semiconductor chip in the mounting groove. Since the semiconductor device itself is very small, the hollow part of the double-layer spiral inductor coil of the present invention has little overlap with silicon, thereby significantly suppressing the substrate eddy current effect, and avoiding the deterioration of the quality factor and inductance matching of the double-layer inductor by the semiconductor silicon substrate to the greatest extent, thereby improving the differential mode bandwidth index of the filter. In addition, the present invention can significantly reduce the use of silicon wafers, thereby effectively reducing the manufacturing cost; By setting an external metal circuit layer to replace the internal metal circuit of the semiconductor chip, the jumper connection is realized. In this design, only the electrode lead of the semiconductor chip will use the internal metal of the silicon chip. Therefore, the area of ​​the silicon chip used in this example can be further reduced, reducing the cost; the coil of the double-layer spiral inductor can be completely separated from the semiconductor chip in the vertical projection direction, thereby avoiding any substrate loss and further improving the differential mode bandwidth.

[0053] The specific implementation modes described above are preferred implementation modes of the present invention, and are not intended to limit the specific implementation scope of the present invention. The scope of the present invention includes but is not limited to the specific implementation modes, and all equivalent changes made according to the present invention are within the protection scope of the present invention.

Claims

1. A heterogeneous integrated filter structure with transient voltage protection, characterized in that: The invention comprises an insulating substrate, wherein an installation groove is provided on the upper surface of the insulating substrate, a semiconductor chip with transient voltage protection function is provided in the installation groove, a double-layer spiral inductor is provided on the upper surface of the insulating substrate, the double-layer spiral inductor comprises a first planar inductor coil and a second planar inductor coil which are stacked, a first passivation layer is provided between the semiconductor chip and the first planar inductor coil, a second passivation layer is provided between the first planar inductor coil and the second planar inductor coil, a third passivation layer is provided on the upper surface of the second planar inductor coil, both the first passivation layer and the second passivation layer are provided with through holes for electrically connecting the upper and lower layers, a filter pin is provided on the third passivation layer, and the filter pin is electrically connected to the second planar inductor coil.

2. The heterogeneous integrated filter structure with transient voltage protection according to claim 1 is characterized in that: The internal metal circuit of the semiconductor chip is replaced by an external metal circuit layer. The filter structure also includes a metal circuit layer arranged between the semiconductor chip and the first passivation layer. The metal circuit layer is used for jumper connection between the semiconductor chip electrode and the first planar inductor coil. A fourth passivation layer is provided between the semiconductor chip and the metal circuit layer.

3. The heterogeneous integrated filter structure with transient voltage protection according to claim 2, characterized in that: The semiconductor chip without internal metal circuits is completely separated from the double-layer spiral inductor on a vertical projection plane.

4. The heterogeneous integrated filter structure with transient voltage protection according to any one of claims 1 to 3, characterized in that: The insulating substrate is made of glass, ceramic or FR4 board.

5. The heterogeneous integrated filter structure with transient voltage protection according to any one of claims 1 to 3, characterized in that: The manufacturing process of the filter pins includes implanting solder balls or wire bonding.

6. The heterogeneous integrated filter structure with transient voltage protection according to any one of claims 1 to 3, characterized in that: The filter structure includes a common mode filter, a low-pass LC filter or a high-pass LC filter.

7. The heterogeneous integrated filter structure with transient voltage protection according to any one of claims 1 to 3, characterized in that: The double-layer spiral inductor is manufactured through a metal layer or a redistribution layer in an integrated circuit process, or is manufactured using a metal layer or a redistribution layer in a packaging process, and the material of the double-layer spiral inductor is a metal conductor.

8. The heterogeneous integrated filter structure with transient voltage protection according to any one of claims 1 to 3, characterized in that: The manufacturing process of the semiconductor chip includes semiconductor silicon process, III-V compound semiconductor process or silicon carbide process.

9. A filter structure manufacturing method, used to manufacture the heterogeneous integrated filter structure with transient voltage protection according to claim 1, characterized in that: The steps include: S101: processing a mounting groove on the insulating substrate, wherein the size and depth of the mounting groove are adapted to the size and thickness of the semiconductor chip; S102: depositing a buffer adhesion layer on the upper surface of the insulating substrate, and then etching back the buffer adhesion layer in an area other than the mounting groove; S103: embedding a semiconductor chip in the mounting groove, wherein the upper surface of the semiconductor chip is flush with the upper surface of the insulating substrate; S104: Fabricate a double-layer spiral inductor on the upper surface of an insulating substrate. Firstly, a first passivation layer is deposited and a through hole for electrical connection is processed, and then a first planar inductor is formed on the upper surface of the first passivation layer; then a second passivation layer is deposited and a through hole for electrical connection is processed, and then a second planar inductor is formed on the upper surface of the second passivation layer; S105: depositing a third passivation layer on the upper surface of the second planar inductor coil, and then processing filter pins for external connection on the third passivation layer.

10. A filter structure manufacturing method, used to manufacture the heterogeneous integrated filter structure with transient voltage protection according to claim 2, characterized in that: The steps include: S201: processing a mounting groove on the insulating substrate, wherein the size and depth of the mounting groove are adapted to the size and thickness of the semiconductor chip; S202: depositing a buffer adhesion layer on the upper surface of the insulating substrate, and then etching back the buffer adhesion layer in an area other than the mounting groove; S203: embedding a semiconductor chip in the mounting groove, wherein the upper surface of the semiconductor chip is flush with the upper surface of the insulating substrate; S204: manufacturing a metal circuit layer for jumper connection on the upper surface of the insulating substrate, firstly, depositing a fourth passivation layer and processing a through hole for electrical connection with the semiconductor chip, and then constructing a metal circuit on the upper surface of the fourth passivation layer; S205: manufacturing a double-layer spiral inductor on the upper surface of the insulating substrate, firstly depositing a first passivation layer and processing a through hole for electrical connection, and then forming a first planar inductor coil on the upper surface of the first passivation layer; then depositing a second passivation layer and processing a through hole for electrical connection, and then forming a second planar inductor coil on the upper surface of the second passivation layer; S206: depositing a third passivation layer on the upper surface of the second planar inductor coil, and then processing filter pins for external connection on the third passivation layer.

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