Digital channelization implementation method based on fractional-multiple oversampling multiphase filter bank

Abstract

The invention provides a digital channelization implementation method based on a fractional-multiple oversampling multiphase filter bank, the method works in a parallel pipeline mode, the number of input parallel paths is Ain, the number of output parallel paths is A, the number of channels is M, the length of each phase of sub-filter is L, the length of the total filter is L * M, and M = M1 * A, Aint; a, M1, Ain, A and L are all positive integers. The method comprises the following steps: shaping input Ain-path parallel data into A-path parallel data through a data shaping module; the input data is rearranged according to M phases through an input data rearrangement module, and A * L data are output in parallel under each clock; a sub-filter and a scheduling module of the sub-filter call a filter coefficient according to the parallelism A for filtering; channel frequency shifting is carried out through a parallel hierarchical FFT module; and finally, correcting phase deflection caused by oversampling through a phase rotation module to obtain a channelized result. According to the invention, large-bandwidth and multi-channel real-time digital channelization is realized based on the multi-phase filter bank in limited resources, the channel division is flexible, and the problem of frequency spectrum attenuation of a traditional multi-phase filtering channel is solved.

Description

Technical Field

[0001] The invention relates to the field of signal processing, and in particular to a digital channelization implementation method based on a fractional oversampling polyphase filter bank. Background Art

[0002] With the increasing demand for signals and the development of semiconductor, signal processing and other technologies, signal bandwidth is getting larger, signal processing speed is getting faster, and signal processing accuracy is getting higher. For example, radio telescope terminal equipment, radar detection systems, etc. require the receiver to work on a very wide frequency band and divide this wide frequency band into multiple independent sub-bands evenly through channelization algorithms, so that the signal of any frequency band on the frequency band can be captured and processed accurately at any time.

[0003] Because field programmable gate arrays (FPGAs) provide a powerful parallel computing architecture, FPGA-based digital signal processing systems are ideal for high-performance applications that require fast, real-time processing and large data bandwidth.

[0004] Polyphase filter banks (PFBs) are a popular choice for channelization algorithms because they effectively apply windowing filters before discrete Fourier transforms, which minimize spectral leakage between subbands, but the transition bands of the filters can cause spectral attenuation of wideband signals.

[0005] Oversampled polyphase filter banks (OPFBs) are an extension of the PFBs algorithm. The data is overlapped and used. The subband spacing remains unchanged, but the subband bandwidth and sampling rate are increased. Spectral overlap occurs between adjacent subbands, reducing the spectral attenuation of the transition band. Compared with PFBs, OPFBs not only need to overlap and serpentine the input data, but also need to compensate the phase offset caused by oversampling for the output data. In the case of many phases, multiple parallel channels and real-time processing, especially when the oversampling multiple is a fractional multiple, the implementation logic is very complex. At present, there are many digital channelization FPGA implementations based on PFBs, and there are also studies on digital channelization FPGA implementations based on integer oversampling OPFBs, but there is no specific digital channelization FPGA implementation based on fractional oversampling OPFBs. An article introduces the serpentine data multiplexing method of fractional oversampling OPFBs, but the memory in the FPGA cannot realize this function and can only be realized through registers. In the case of large bandwidth and multiple channels, the demand for registers is huge, which will lead to difficulties in layout and routing, reduce the working clock frequency, and greatly affect the processing speed of the system. Summary of the invention

[0006] The purpose of the present invention is to provide a real-time digital channelization FPGA implementation method based on fractional oversampling polyphase filter banks, which solves the problem of sub-band spectrum attenuation in digital channelization based on PFBs and improves the processing performance and speed of the system.

[0007] To achieve the above purpose, the technical solution adopted by the present invention is as follows:

[0008] The present invention works in parallel pipeline mode, and the number of input parallel paths is A in , the number of parallel output paths is A, the number of channels is M, the length of each phase sub-filter is L, and the total filter length is L*M, where M=M1*A, M=M1*A, A in <A,M1、A in , A, L are all positive integers. The oversampling multiple is A / A in , output extraction multiple D = M * A in / A=D1*A. M1 is the channel intermediate parameter, and D1 is the extraction parameter. Since the system output is A-channel parallel, D needs to be an integer multiple of A, and D1 is a positive integer.

[0009] Assume that the bandwidth of the input signal x(n) is f s , the frequency band range is (Note: The spectrum of discrete signals is periodic. The frequency band is equivalent to ), divided into M sub-bands, the sub-band bandwidth is The center frequency of the mth sub-band is The down-converted signal d m (n) As shown in formula (1):

[0010]

[0011] Perform a low-pass filter on it. Here, h(k) is set as the inverse result of the low-pass filter response. The filter order is LM. The filtering result b m (n) As shown in formula (2):

[0012]

[0013] After 1 / D sampling, we get y m (n) As shown in formula (3):

[0014]

[0015] The ones in the round brackets () are polyphase filtering, the ones in the square brackets [] are FFT, and the ones outside the brackets are phase rotation.

[0016] On the one hand, the present invention discloses a method for realizing digital channelization based on a fractional oversampling polyphase filter bank, characterized in that the method works in a parallel pipeline mode and comprises the following steps:

[0017] 1) Full input A in Reshape the A-way parallel data into A-way parallel data;

[0018] 2) using an input data rearrangement module to rearrange the input A-channel parallel data according to M phases, and outputting A*L data in parallel at each clock, including: using a BRAM write control unit to store the data shaped in step 1) in sequence into a BRAM storage space, using a BRAM read control unit to read out the data in the BRAM storage space in sequence, using a data rearrangement control state machine to control the states of the BRAM write control unit and the BRAM read control unit, and using a read data reordering unit to rearrange the data read from the storage space at each clock cycle according to the sequence required by the subsequent stage;

[0019] 3) calling the filter coefficient according to the parallelism A to filter the data output from step 2);

[0020] 4) Shift the channel frequency of the filtered data;

[0021] 5) Multiply the frequency-shifted signal by the correction rotation factor to correct the phase deviation caused by oversampling and obtain the channelized result.

[0022] On the other hand, the present invention provides a digital channelization realization system based on a fractional oversampling polyphase filter bank for implementing the above method, characterized in that it comprises:

[0023] Data shaping module, used to convert the full input A in Reshape the A-way parallel data into A-way parallel data;

[0024] An input data rearrangement module includes a BRAM write control unit, a BRAM read control unit, a data rearrangement control state machine and a read data reordering unit. The BRAM write control unit stores the reshaped data in sequence to the BRAM storage space, the BRAM read control unit reads the data in the BRAM storage space in sequence, and the data rearrangement control state machine controls the states of the BRAM write control unit and the BRAM read control unit; the read data reordering unit reorders the data read from the storage space in each clock cycle according to the sequence required by the subsequent stage;

[0025] A sub-filter and a scheduling module thereof, which filters the data output by the input data rearrangement module by calling the filter coefficient according to the parallelism A;

[0026] The parallel hierarchical FFT module performs channel frequency shifting on the data filtered by the sub-filter and its scheduling module;

[0027] The phase rotation module multiplies the frequency-shifted signal of the parallel hierarchical FFT module by the correction rotation factor to correct the phase deviation caused by oversampling and obtain the channelized result.

[0028] The beneficial effects of the present invention are:

[0029] The present invention realizes large bandwidth, multi-channel real-time digital channelization based on oversampling polyphase filter banks within limited resources, and the channel division is flexible and solves the problem of spectrum attenuation in the traditional channelization technology based on polyphase filter banks, and occupies less resources. It is conducive to the FPGA implementation of digital channelization technology with higher accuracy and better performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solution of the present invention, the accompanying drawings required for use in the description of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0031] Figure 1 The overall functional block diagram of a real-time digital channelization FPGA implementation method based on a fractional oversampling polyphase filter bank provided by the present invention;

[0032] Figure 2 A functional block diagram of an input data rearrangement module provided by the present invention;

[0033] Figure 3 A schematic diagram of the state transition of the input data rearrangement module control state machine provided by the present invention;

[0034] Figure 4 The functional block diagram of the sub-filter and its scheduling module provided by the present invention;

[0035] Figure 5 The functional block diagram of the parallel hierarchical FFT module provided by the present invention;

[0036] Figure 6 A functional block diagram of a phase rotation module provided by the present invention;

[0037] Figure 7 A schematic diagram of writing an input data rearrangement module into a BRAM according to an embodiment of the present invention;

[0038] Figure 8 A schematic diagram of state transition of a control state machine of an input data rearrangement module provided in an embodiment of the present invention;

[0039] Fig. 9 A schematic diagram of BRAM reading of an input data rearrangement module provided in an embodiment of the present invention;

[0040] Fig.10 A schematic diagram of reordering data read out of an input data reordering module BRAM provided in an embodiment of the present invention;

[0041] Fig.11 A simplified schematic diagram of a phase rotation module provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0042] The following will be combined with the accompanying drawings in the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0043] In this embodiment, the system bandwidth is 1.96608Gps, the sampling quantization bit width is 12bit, the system works in parallel pipeline mode, the input signal duty cycle is 1, and the number of parallel paths is A. in is 6, the output signal duty cycle is 1, the number of parallel paths A is 8, the number of channels M is 2048, and the extraction multiple D = M*A in / A=1536, the length of each phase sub-filter L is 4, the total filter length L*M is 8192, the sub-band bandwidth is 1.28Mps, and the inter-sub-band spacing is 0.96M. The channel intermediate parameter M1=M / A=256, and the extraction parameter D1=D / A=192.

[0044] like Figure 1 As shown, a digital channelization implementation method based on a fractional oversampling polyphase filter bank is exemplified, which includes:

[0045] 1) Full input A in Reshape the A-way parallel data into A-way parallel data;

[0046] 2) using an input data rearrangement module to rearrange the input A-channel parallel data according to M phases, and outputting A*L data in parallel at each clock, including: using a BRAM write control unit to sequentially store the data shaped in step 1) into a BRAM storage space, using a BRAM read control unit to sequentially read the data in the BRAM storage space, using a data rearrangement control state machine to control the states of the BRAM write control unit and the BRAM read control unit, and using a read data reordering unit to reorder and output the data read from the storage space at each clock cycle according to the order required by the subsequent stage;

[0047] 3) calling the filter coefficient according to the parallelism A to filter the data output from step 2);

[0048] 4) Shift the channel frequency of the filtered data;

[0049] 5) Multiply the frequency-shifted signal by the correction rotation factor to correct the phase deviation caused by oversampling and obtain the channelized result.

[0050] In a specific embodiment of the present invention, a real-time digital channelized FPGA implementation system based on a fractional oversampling polyphase filter group is provided to implement the above method, including five parts: a data shaping module (for implementing step 1), an input data rearrangement module (for implementing step 2), a sub-filter and its scheduling module (for implementing step 3), a parallel hierarchical FFT module (for implementing step 4) and a phase rotation module (for implementing step 5).

[0051] The function of the data shaping module is to convert the A input of the full time slot into in The parallel data is shaped into effective data with a duty cycle of A in In this embodiment, 6 parallel data inputted in full time slots are shaped into 8 parallel data with effective data duty cycle of 3 / 4.

[0052] The function of the input data rearrangement module is as follows Figure 2 As shown, it is mainly composed of four parts: a BRAM write control unit, a data rearrangement control state machine, a BRAM read control unit, and a read data reordering unit. Among them, the BRAM write control unit is used to store the signal input to the data rearrangement module in sequence to the BRAM storage space, the data rearrangement control state machine is used to control the state of the BRAM write control unit and the BRAM read control unit, the BRAM read control unit is used to read the signal in the BRAM storage space in sequence, and the read data reordering unit is used to reorder and output the signal read from the storage space in each clock cycle according to the order required by the subsequent stage.

[0053] like Figure 2 As shown: Considering the IQ two-way orthogonal input mode, L bits with a width of A*data bit width*2 and a depth of M / A*2 are opened in the FPGA x Block random access memory (BRAM) space, where x = 0, 1, ..., the value of x is determined according to the length of a single BRAM in the selected FPGA and M1. The purpose is to use space expansion to reduce the complexity of the data rearrangement control state machine (x = 0 is used for explanation below).

[0054] Specifically in this embodiment, it is necessary to open up 4 BRAM spaces with a bit width of 8*12*2=192 bits (8 represents the number of parallel paths, 12 represents the quantization bit width of ADC sampling, and 2 represents the real and imaginary parts of the signal) and a depth of 2048 / 8=256 (2048 represents the number of channels, and 8 represents the number of parallel paths) in the FPGA.

[0055] The clock of the input signal is counted, and the count value is t1, t1=0, 1, ..., M1*L-1. When t1=M1*L-1, the next moment t1=0. According to the value of t1, the input data is stored. The A data input at moment t1 are stored in the position where the address of the l+1th BRAM is rem(t1 / M1), where l=mod(t1 / M1), rem() represents the remainder operation, and mod() represents the modulo operation.

[0056] The clock of the output signal is counted, and the count value is t2, t2 = 0, 1, ..., M1-1. When t2 = M1-1, the next moment t2 = 0. The data rearrangement control state machine jump is controlled according to the values ​​of t1 and t2. Since the state of the state machine is related to M1, D1, L, and x, the state machine needs to be customized for each coefficient.

[0057] Specifically in this embodiment, the BRAM write control unit needs to count the clock of the signal (A-channel parallel data after shaping) input by the data shaping module. In this embodiment, the input signal is represented by a matrix X, as shown in formula (4):

[0058]

[0059] Among them: the matrix has 8 rows and countless columns, each column represents the signal of one clock cycle that is input into the data rearrangement module in 8-way parallel mode after shaping, x(a,b) represents the ath signal of the bth extraction cycle, a=1, 2, …, 1536, b=1, 2, ….

[0060] The number of columns of the input signal is counted, and the count value is t1, t1 = 0, 1, ..., 1023. When t1 = 1023, the next moment t1 = 0, and the storage of the input data is controlled according to the value of t1. The schematic diagram of writing into BRAM is shown in Figure 7 As shown:

[0061] When t1=0~255, the control input data is stored in the t1 address of the first BRAM space;

[0062] When t1=256~511, the control input data is stored in the t1-256 address of the second BRAM space;

[0063] When t1=512~767, the control input data is stored in the t1-512 address of the third BRAM space;

[0064] When t1=768~1023, the control input data is stored in the address t1-768 of the 4th BRAM space.

[0065] The BRAM read control unit counts the clock of the signal output to the sub-filter and its scheduling module, and the count value is t2, t2=0, 1, ..., 255 (M1-1), and when t2=255, the next time t2=0. The jump of the data rearrangement control state machine (hereinafter referred to as the state machine) is controlled according to the values ​​of t1 and t2.

[0066] The state machine of the present invention jumps as follows Figure 3 As shown in the figure: In the initial stage, when l = L-1 and rem(t1 / D1) = D1-1, the state machine jumps to the read-write state, and t2 starts counting; the read-write state is divided into several sub-states, the initial state is read-write state 1, and when t2 = f1(M1, D1, L, x, 1), it jumps to read-write state 2; when t2 = f i (M1, D1, L, x, i) jumps to the read-write state i+1; suppose there are I read-write sub-states, i=1, 2, ..., I, when i=I, the next state is i=1, where f i Indicates the condition for the i-th read / write substate to jump to the i+1-th read / write substate. i The value is M1-1 or rem(d*(M1-D1)-1 / M1), where d is the number of times t2 counts to M1 from read-write state 1. The condition is true if t2 counts to whichever one first. I is the end position of the read-write sub-state cycle. At this time, d=L*M1 / gcd(M1,D1), where gcd() represents the greatest common divisor.

[0067] The state transition diagram of the state machine in this embodiment is as follows: Figure 8 As shown:

[0068] When the system starts, the state machine is in the initial stage. When t1=959, the state machine jumps to read-write state 1, and t2 starts counting;

[0069] In read-write state 1, when t2=255, the state machine jumps to read-write state 2;

[0070] In read-write state 2, when t2=63, the state machine jumps to read-write state 3;

[0071] In read-write state 3, when t2=255, the state machine jumps to read-write state 4;

[0072] In read-write state 4, when t2=127, the state machine jumps to read-write state 5;

[0073] In read-write state 5, when t2=255, the state machine jumps to read-write state 6;

[0074] In read-write state 6, when t2=191, the state machine jumps to read-write state 7;

[0075] In read-write state 7, when t2=255, the state machine jumps to read-write state 8;

[0076] In read-write state 8, when t2=255, the state machine jumps to read-write state 9;

[0077] In read-write state 9, when t2=63, the state machine jumps to read-write state 10;

[0078] In read-write state 10, when t2=255, the state machine jumps to read-write state 11;

[0079] In the read-write state 11, when t2=127, the state machine jumps to the read-write state 12;

[0080] In read-write state 12, when t2=255, the state machine jumps to read-write state 13;

[0081] In the read-write state 13, when t2=191, the state machine jumps to the read-write state 14;

[0082] In read-write state 14, when t2=255, the state machine jumps to read-write state 15;

[0083] In read-write state 15, when t2=255, the state machine jumps to read-write state 16;

[0084] In the read-write state 16, when t2=63, the state machine jumps to the read-write state 17;

[0085] In the read-write state 17, when t2=255, the state machine jumps to the read-write state 18;

[0086] In the read-write state 18, when t2=127, the state machine jumps to the read-write state 19;

[0087] In the read-write state 19, when t2=255, the state machine jumps to the read-write state 20;

[0088] In the read-write state 20, when t2=112, the state machine jumps to the read-write state 21;

[0089] In the read-write state 21, when t2=255, the state machine jumps to the read-write state 22;

[0090] In the read-write state 22, when t2=255, the state machine jumps to the read-write state 23;

[0091] In the read-write state 23, when t2=63, the state machine jumps to the read-write state 24;

[0092] In the read-write state 24, when t2=255, the state machine jumps to the read-write state 25;

[0093] In the read-write state 25, when t2=127, the state machine jumps to the read-write state 26;

[0094] In the read-write state 26, when t2=255, the state machine jumps to the read-write state 27;

[0095] In the read-write state 27, when t2=191, the state machine jumps to the read-write state 28;

[0096] In read-write state 28, when t2=255, the state machine jumps to read-write state 1;

[0097] The cycle continues in sequence.

[0098] BRAM read control needs to control the read address according to t2 in the read and write state of the state machine, and read the address f in L BRAMs at the same time. addri (M1, D1, L, x, i, t2) data, where f addri represents the function of the read address and t2 in the i-th read / write sub-state. addri The value of is rem((t2+d*D1) / M1). Specifically in this embodiment, the BRAM read control is as follows Fig. 9 As shown:

[0099] In read / write state 1, the data at address t2 in the four BRAMs are read out simultaneously;

[0100] In read / write state 2, the data at address t2+191 in 4 BRAMs are read out simultaneously;

[0101] In read / write state 3, data at addresses t2-64 in 4 BRAMs are read out simultaneously;

[0102] In read / write state 4, the data at address t2+128 in 4 BRAMs are read out simultaneously;

[0103] In read / write state 5, data at address t2-128 in 4 BRAMs are read out simultaneously;

[0104] In read / write state 6, the data at address t2+64 in 4 BRAMs are read out simultaneously;

[0105] In read / write state 7, the data at address t2-192 in 4 BRAMs are read out simultaneously;

[0106] In read / write state 8, the data at address t2 in 4 BRAMs are read out simultaneously;

[0107] In read / write state 9, the data at address t2+191 in 4 BRAMs are read out simultaneously;

[0108] In read / write state 10, data at addresses t2-64 in 4 BRAMs are read out simultaneously;

[0109] In read / write state 11, the data at address t2+128 in 4 BRAMs are read out simultaneously;

[0110] In read / write state 12, data at address t2-128 in 4 BRAMs are read out simultaneously;

[0111] In read / write state 13, the data at address t2+64 in 4 BRAMs are read out simultaneously;

[0112] In read / write state 14, data at address t2-192 in 4 BRAMs are read out simultaneously;

[0113] In the read / write state 15, the data at address t2 in the four BRAMs are read out simultaneously;

[0114] In read / write state 16, the data at address t2+191 in 4 BRAMs are read out simultaneously;

[0115] In read / write state 17, data at addresses t2-64 in 4 BRAMs are read out simultaneously;

[0116] In read / write state 18, the data at address t2+128 in 4 BRAMs are read out simultaneously;

[0117] In read / write state 19, data at address t2-128 in 4 BRAMs are read out simultaneously;

[0118] In the read / write state 20, the data at address t2+64 in the four BRAMs are read out simultaneously;

[0119] In read / write state 21, data at address t2-192 in 4 BRAMs are read out simultaneously;

[0120] In the read / write state 22, the data at address t2 in the four BRAMs are read out simultaneously;

[0121] In the read / write state 23, the data at address t2+191 in the four BRAMs are read out simultaneously;

[0122] In read / write state 24, data at addresses t2-64 in 4 BRAMs are read out simultaneously;

[0123] In the read / write state 25, the data at address t2+128 in the four BRAMs are read out simultaneously;

[0124] In read / write state 26, data at address t2-128 in 4 BRAMs are read out simultaneously;

[0125] In read / write state 27, the data at address t2+64 in 4 BRAMs are read out simultaneously;

[0126] In the read / write state 28, data at address t2-192 in the four BRAMs are read out simultaneously.

[0127] In order to make the read data correspond one-to-one with the filter coefficients of the sub-filter and its scheduling module, the data in the BRAM read out simultaneously needs to be sorted. The sorting method is to move the numbers read out from the first mod((t2+d*D1) / M1) BRAMs to after the numbers read out from the Lth BRAM.

[0128] Specifically in this embodiment, assuming that the number read from the first BRAM is bram1, the number read from the second BRAM is bram2, the number read from the third BRAM is bram3, and the number read from the fourth BRAM is bram4, then the order of data directly read from the four BRAMs is [bram1, bram2, bram3, bram4], and the read data is sorted as follows: Fig.10 As shown:

[0129] In read-write state 1, the data position remains unchanged, and the output data is [bram1, bram2, bram3, bram4];

[0130] In read-write state 2, the data position remains unchanged, and the output data is [bram1, bram2, bram3, bram4];

[0131] In read / write state 3, the number read from the first BRAM is moved to the end, and the output data is [bram2, bram3, bram4, bram1];

[0132] In read / write state 4, the number read from the first BRAM is moved to the end, and the output data is [bram2, bram3, bram4, bram1];

[0133] In read / write state 5, the numbers read from the first and second BRAMs are moved to the end in order, and the output data is [bram3, bram4, bram1, bram2];

[0134] In read / write state 6, the numbers read from the first and second BRAMs are moved to the end in order, and the output data is [bram3, bram4, bram1, bram2];

[0135] In read / write state 7, the numbers read from the first, second and third BRAMs are moved to the end in order, and the output data is [bram4, bram1, bram2, bram3];

[0136] In read / write state 8, the numbers read from the first, second and third BRAMs are moved to the end in order, and the output data is [bram4, bram1, bram2, bram3];

[0137] In read / write state 9, the numbers read from the first, second and third BRAMs are moved to the end in order, and the output data is [bram4, bram1, bram2, bram3];

[0138] In read / write state 10, the data position remains unchanged, and the output data is [bram1, bram2, bram3, bram4];

[0139] In read / write state 11, the data position remains unchanged, and the output data is [bram1, bram2, bram3, bram4];

[0140] In read / write state 12, the number read from the first BRAM is moved to the end, and the output data is [bram2, bram3, bram4, bram1];

[0141] In read / write state 13, the number read from the first BRAM is moved to the end, and the output data is [bram2, bram3, bram4, bram1];

[0142] In the read / write state 14, the numbers read from the first and second BRAMs are moved to the end in order, and the output data is [bram3, bram4, bram1, bram2];

[0143] In the read / write state 15, the numbers read from the first and second BRAMs are moved to the end in order, and the output data is [bram3, bram4, bram1, bram2];

[0144] In read / write state 16, the numbers read from the first and second BRAMs are moved to the end in order, and the output data is [bram3, bram4, bram1, bram2];

[0145] In read / write state 17, the numbers read from the first, second and third BRAMs are moved to the end in order, and the output data is [bram4, bram1, bram2, bram3];

[0146] In read / write state 18, the numbers read from the first, second and third BRAMs are moved to the end in order, and the output data is [bram4, bram1, bram2, bram3];

[0147] In read / write state 19, the data position remains unchanged, and the output data is [bram1, bram2, bram3, bram4];

[0148] In the read / write state 20, the data position remains unchanged, and the output data is [bram1, bram2, bram3, bram4];

[0149] In read / write state 21, the number read from the first BRAM is moved to the end, and the output data is [bram2, bram3, bram4, bram1];

[0150] In read / write state 22, the number read from the first BRAM is moved to the end, and the output data is [bram2, bram3, bram4, bram1];

[0151] In read / write state 23, the number read from the first BRAM is moved to the end, and the output data is [bram2, bram3, bram4, bram1];

[0152] In the read / write state 24, the numbers read from the first and second BRAMs are moved to the end in order, and the output data is [bram3, bram4, bram1, bram2];

[0153] In the read / write state 25, the numbers read from the first and second BRAMs are moved to the end in order, and the output data is [bram3, bram4, bram1, bram2;

[0154] In the read / write state 26, the numbers read from the first, second and third BRAMs are moved to the end in order, and the output data is [bram4, bram1, bram2, bram3];

[0155] In read / write state 27, the numbers read from the first, second and third BRAMs are moved to the end in order, and the output data is [bram4, bram1, bram2, bram3];

[0156] In read / write state 28, the data position remains unchanged, and the output data is [bram1, bram2, bram3, bram4];

[0157] The sorted data is output to the sub-filter and its scheduling module.

[0158] In a specific embodiment of the present invention, the sub-filter and its scheduling module extract the coefficients of the t2*A+1~(t2+1)*A sub-filters according to the above count value t2, the coefficients are pre-stored in the ROM of the FPGA, and convolution filtering is performed with the output of the input data rearrangement module, and the filtered data is output to the parallel hierarchical FFT module according to the parallelism A. Specifically in this embodiment, the functional block diagram of the sub-filter and its scheduling module is as follows: Figure 4 As shown: the sub-filter parameters are pre-stored in the FPGA's ROM according to a bit width of 4*8*16 bits (4 represents the sub-filter length, 8 represents the parallelism, and 16 bits represents the bit width of a single filter coefficient), and the total address length is 256. They are read out in sequence according to t2, and the convolution operation is performed with the sorted number to obtain the filtered data, which is sent to the parallel hierarchical FFT module.

[0159] In a specific embodiment of the present invention, the parallel hierarchical FFT module divides the filtered data into blocks, each block contains A parallel data, totaling M1 clock cycles. First, the data output by the FFT module of A M1 points is multiplied by the rotation factor, and then the A channel is fused through the parallel FFT of point A to obtain the frequency-shifted data output to the phase rotation module. Specifically in this embodiment, the functional block diagram of the parallel hierarchical FFT module is as follows: Figure 5 As shown in the figure: First, 8 independent 256-point IP cores are called, then multiplied by the rotation factor, and then 8-channel fusion is performed through 8-point FFT operation and sent to the phase rotation module. The 8-point FFT operation is implemented using a 3-level butterfly operation.

[0160] In a specific embodiment of the present invention, the phase rotation module multiplies the frequency-shifted signal by a correction rotation factor to correct the phase, such as Figure 6 Further, the functional block diagram of the phase rotation module is as follows Fig.11 As shown: Generally, the phase rotation factor is stored in the ROM in the FPGA and read out in sequence according to t2; in this embodiment, since D / M=3 / 4, the rotation factor has only four cases of +1, -1, +i, -i, which respectively correspond to the unchanged data, negation, swapping the real and imaginary parts and negating the real part, swapping the real and imaginary parts and negating the imaginary parts, and no complex multiplication is required. It should be noted that the signal after the parallel hierarchical FFT is in a block transposed relationship of 2048 points (8 rows and 256 columns) relative to the input signal, that is, the jth row of each block is the time domain signal of the (j-1)*256~j*256-1th sub-channel, j=1, 2, ..., 8. According to the rotation factor e -j2πnmD / M, where m and n represent the nth timing signal of the mth subband, m=0, 1, ..., M-1, n=0, 1, .... When n=0: the rotation factor is +1, and the signal is not rotated. When n=1: the signal in the first clock cycle is the signal of the (j-1)*256th subchannel, the rotation factor is +1, and the signal is not rotated; the signal in the second clock cycle is the signal of the (j-1)*256+1th subchannel, the rotation factor is -i, the real part and the imaginary part of the signal are swapped and the imaginary part is inverted; the signal in the third clock cycle is the signal of the (j-1)*256+2th subchannel, the rotation factor is -1, and the signal is inverted; the signal in the fourth clock cycle is the signal of the (j-1)*256+3th subchannel, the rotation factor is i, the real part and the imaginary part of the signal are swapped and the real part is inverted; the fifth clock cycle is the same as the first cycle, and it is cycled to the 256th clock cycle in sequence. When n=2: the signal in the first clock cycle is the signal of the (j-1)*256th subchannel, the rotation factor is +1, and the signal is not rotated; the signal in the second clock cycle is the signal of the (j-1)*256+1th subchannel, the rotation factor is -1, and the signal is inverted; the third clock cycle is the same as the first cycle, and it cycles in sequence to the 256th clock cycle. When n=3: the signal in the first clock cycle is the signal of the (j-1)*256th subchannel, the rotation factor is +1, and the signal is not rotated; the signal in the second clock cycle is the signal of the (j-1)*256+1th subchannel, the rotation factor is i, the real part and the imaginary part of the signal are swapped and the real part is inverted; the fifth clock cycle is the same as the first cycle, and it is cycled to the 256th clock cycle in sequence; the signal in the third clock cycle is the signal of the (j-1)*256+2th subchannel, the rotation factor is -1, and the signal is inverted; the signal in the fourth clock cycle is the signal of the (j-1)*256+3th subchannel, the rotation factor is -i, the real part and the imaginary part of the signal are swapped and the imaginary part is inverted; the fifth clock cycle is the same as the first cycle, and it is cycled to the 256th clock cycle in sequence. Finally, the channelized data is obtained.

[0161] As can be seen from the above embodiments, the method of the present invention converts the full input A into in The parallel data of each channel is shaped into A parallel data, and the effective data duty cycle is A in / A; then the input data is rearranged according to M phases through the input data rearrangement module, and the (M-D+1)th to Mth phase data of each M phase data are multiplexed, and A*L data are output in parallel under each clock, and the effective data duty cycle is 1; the sub-filter and its scheduling module call the filter coefficient according to the parallelism A for filtering; then the channel frequency is shifted through the parallel hierarchical FFT module; finally, the phase rotation module corrects the phase deflection caused by oversampling to obtain the channelized result. The method of the present invention realizes large-bandwidth, multi-channel real-time digital channelization based on an oversampling polyphase filter group within limited resources. The channel division is flexible and solves the problem of spectrum attenuation in the traditional channelization technology based on the polyphase filter group, and the resource occupancy is small. It is conducive to the FPGA implementation of digital channelization technology with higher accuracy and better performance.

[0162] The above-described embodiments only express the more specific and detailed embodiments described in this application, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of this application, which all belong to the protection scope of this application. Therefore, the protection scope of the patent application shall be based on the attached claims.

Claims

1. A digital channelization implementation method based on fractional oversampling polyphase filter bank, characterized in that: The method works in parallel pipeline mode, and the number of input parallel paths is A in , the number of parallel output paths is A, the number of channels is M, the length of each phase sub-filter is L, and the total filter length is L*M, where A in <A,A in , A, L are all positive integers, and the oversampling multiple is A / A in ; The method comprises the following steps: 1) Full input A in Reshape the A-way parallel data into A-way parallel data; 2) using an input data rearrangement module to rearrange the input A-channel parallel data according to M phases, and outputting A*L data in parallel at each clock, including: using a BRAM write control unit to sequentially store the data shaped in step 1) into a BRAM storage space, using a BRAM read control unit to sequentially read the data in the BRAM storage space, using a data rearrangement control state machine to control the states of the BRAM write control unit and the BRAM read control unit, and using a read data reordering unit to reorder and output the data read from the storage space at each clock cycle according to the order required by the subsequent stage; 3) calling the filter coefficient according to the parallelism A to filter the data output from step 2); 4) Shift the channel frequency of the filtered data; 5) Multiply the frequency-shifted signal by the correction rotation factor to correct the phase deviation caused by oversampling and obtain the channelized result.

2. The method according to claim 1, characterized in that In step 1), the input signal at each clock is valid, and the valid signal duty cycle is 1; in The parallel data of each channel is shaped into A parallel data, and the duty cycle of the output valid data is A in / A.

3. The method according to claim 1, characterized in that The step 2) comprises: Open up L bits with a width of A×data bit width×2 and a depth of M / A×2 x BRAM space of , where x is the depth coefficient, and its value is an integer greater than or equal to 0; The signal clock of the data after shaping in step 1) is counted, and the count value is t1, t1=0, 1, ..., M1*L-1, where M1 is the channel intermediate parameter and M1=M / A; when t1=M1*L-1, the next time t1=0; the A data input at time t1 are stored in the position where the address of the l+1th BRAM is rem(t1 / M1), where the BRAM label l=mod(t1 / M1), rem() represents the remainder operation, and mod() represents the modulo operation; The clock of the signal output by the input data rearrangement module is counted, and the count value is t2, t2=0, 1, ..., M1-1. When t2=M1-1, the next moment t2=0; the input data rearrangement module controls the jump of the data rearrangement control state machine according to the values ​​of t1 and t2.

4. The method according to claim 3, characterized in that The step of controlling the jump of the data rearrangement control state machine according to the values ​​of t1 and t2 includes: The change of count value t1 causes l to change. When l = L-1 and rem(t1 / D1) = D1-1, the state machine jumps to the read-write state, and t2 starts counting at the same time; the read-write state is divided into I sub-states, initially in read-write state 1, and jumps to read-write state 2 when t2 = f1; when t2 = f i When it jumps to the read-write state i+1, where i=1, 2, ..., I; when i=I, the next state is i=1, where f i Indicates the condition for the i-th read-write substate to jump to the i+1-th read-write substate, f i The value of is M1-1 or rem((d*(M1-D1)-1) / M1), whichever condition is met when t2 counts first, d is the number of times t2 counts to M1 from read / write state 1; in the read / write state of the data rearrangement control state machine, the address f in L BRAM is read out at the same time addri The data to be read out is sorted so that the data corresponds to the filter coefficients one by one, where f addri represents the function of the read address and t2 in the i-th read / write sub-state; f addri The value of is rem((t2+d*D1) / M1).

5. The method according to claim 4, characterized in that The reordering of the data to be read includes: moving the numbers read out from the first mod((t2+d*D1) / M1) BRAMs to after the numbers read out from the Lth BRAM.

6. The method according to claim 3, characterized in that: The step 3) is: according to the clock count value t2 of the output signal, the coefficients of the t2×A+1 to (t2+1)×A sub-filters are extracted, the coefficients are pre-stored in the ROM of the FPGA, and convolution filtering is performed with the output data of step 2), and the filtered data is output according to the parallelism A.

7. The method according to claim 5, characterized in that The step 4) is: divide the data filtered in step 3) into blocks, each block contains A parallel data, totaling M1 clock cycles; first call the data output by the FFT module of A M1 points to multiply the rotation factor, and then fuse the A channels through the A point parallel FFT to obtain the frequency-shifted data.

8. The method according to claim 5, characterized in that In step 5), the value of the correction rotation factor is: e -j2πnmD / M , where m and n represent the nth timing signal of the mth subband, m=0, 1, …, M-1, n=0, 1, ….

9. A digital channelization implementation system based on a fractional oversampling polyphase filter bank for implementing the method according to any one of claims 1 to 8, characterized in that: include: Data shaping module, used to convert the full input A in Reshape the A-way parallel data into A-way parallel data; An input data rearrangement module includes a BRAM write control unit, a BRAM read control unit, a data rearrangement control state machine and a read data reordering unit. The BRAM write control unit stores the reshaped data in sequence to the BRAM storage space, the BRAM read control unit reads the data in the BRAM storage space in sequence, and the data rearrangement control state machine controls the states of the BRAM write control unit and the BRAM read control unit; the read data reordering unit reorders the data read from the storage space in each clock cycle according to the sequence required by the subsequent stage; A sub-filter and a scheduling module thereof, which filters the data output by the input data rearrangement module by calling the filter coefficient according to the parallelism A; The parallel hierarchical FFT module performs channel frequency shifting on the data filtered by the sub-filter and its scheduling module; The phase rotation module multiplies the frequency-shifted signal of the parallel hierarchical FFT module by the correction rotation factor to correct the phase deviation caused by oversampling and obtain the channelized result.

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