High-speed dynamic comparator
By introducing a discharge path into the two-tail comparator, the discharge current of the first-stage output node is used to accelerate the start-up and comparison process of the second-stage circuit, the problems of dynamic power consumption waste and conversion time waste are solved, and a high-speed and low-power dynamic comparator design is realized.
Patent Information
- Application Number
- CN202411918647.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-24
- Publication Date
- 2025-04-25
Smart Images
Figure CN119892024A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and in particular to a high-speed dynamic comparator. Background Art
[0002] In recent years, comparators have been widely used in the field of analog-to-digital converters (ADCs). As the direct source of ADC quantitative data, comparators have become the core of ADC design. With the continuous advancement of process nodes, the optimization of comparator power consumption and speed indicators in ADCs has become the key to improving ADC performance, which is directly related to the realization of the overall ADC's high sampling rate and low power consumption goals.
[0003] In the development of comparators, two types of comparators have emerged: static comparators and dynamic comparators. Today, dynamic comparators have gradually replaced static comparators with the advantages of zero static power consumption and medium and high speed, and many structures have been produced. Among dynamic comparators, the double-tail comparator has the most advantages, that is, a two-stage dynamic comparator consisting of a pre-amplifier stage and a latch stage, which can achieve zero dynamic power consumption and high-speed comparison, because the startup of the two stages has a sequence, which saves a certain amount of dynamic power consumption, and realizes high-speed comparison based on the positive feedback latch architecture.
[0004] However, there are some problems with the double-tailed comparator. On the one hand, the dynamic power consumption of the two stages of the comparator is independent, and the dynamic power consumption of the first stage is wasted by the discharge of the first stage output node, and the second stage output node is charged to the stable logic levels 0 and 1, which requires a large power consumption and is difficult to ignore in low-power design; on the other hand, the voltage of the first stage output node discharges linearly with time, and the second stage cannot be started in the initial discharge time, and the second stage is not started until it is discharged to a threshold voltage lower than the power supply voltage, so there is a certain waste of conversion time. Summary of the invention
[0005] 1. Technical issues to be resolved
[0006] In view of the above-mentioned shortcomings, the main purpose of the present invention is to provide a high-speed dynamic comparator. During the comparison process of the high-speed dynamic comparator, on the one hand, the discharge path can amplify the signal together with the first-stage input pair of the double-tail comparator body to speed up the time for the second-stage circuit to start the comparison; on the other hand, the discharge path can use a part of the first-stage discharge current to charge the second-stage comparison result, which not only maintains the zero static power consumption and high-speed advantages of the dynamic comparator, but also realizes the reasonable use of current during the comparison process, improves the comparison speed, and finally the high-speed discharge path can realize self-shutdown when the comparison is completed.
[0007] (II) Technical solution
[0008] In order to achieve the above-mentioned object, the present invention provides a high-speed dynamic comparator, including a double-tail comparator body and a discharge path, the discharge path includes a first discharge path and a second discharge path, the first discharge path and the second discharge path are symmetrically arranged on both sides of the double-tail comparator body along a first direction; wherein the first discharge path includes a first-stage output FP node, a second-stage output OUT+ node and an input VIN+ node, and the second discharge path includes a first-stage output FN node, a second-stage output OUT- node and an input VIN- node; and the first discharge path and the second discharge path both include a first NMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube; in the first discharge path In the path, the gate of the first NMOS tube is connected to the CLK clock, the drain of the first NMOS tube is connected to the first-stage output FP node, the source of the first NMOS tube is respectively connected to the drain of the second NMOS tube, the gate and the drain of the third NMOS tube, the gate of the second NMOS tube is connected to CLK0, and the source of the second NMOS tube is connected to the ground line; and the gate of the third NMOS tube is respectively connected to the drain of the third NMOS tube, the source of the first NMOS tube and the drain of the second NMOS tube, the source of the third NMOS tube is connected to the drain of the fourth NMOS tube, the gate of the fourth NMOS tube is connected to the input VIN+ node, and the source of the fourth NMOS tube is connected to the second-stage output OUT+ node.
[0009] In the above scheme, in the second discharge path, the gate of the first NMOS tube is connected to the CLK clock, the drain of the first NMOS tube is connected to the first-stage output FN node, the source of the first NMOS tube is respectively connected to the drain of the second NMOS tube, the gate and the drain of the third NMOS tube, the gate of the second NMOS tube is connected to CLK0, and the source of the second NMOS tube is connected to the ground line; and the gate of the third NMOS tube is respectively connected to the drain of the third NMOS tube, the source of the first NMOS tube and the drain of the second NMOS tube, the source of the third NMOS tube is connected to the drain of the fourth NMOS tube, the gate of the fourth NMOS tube is connected to the input VIN-node, and the source of the fourth NMOS tube is connected to the second-stage output OUT-node.
[0010] In the above scheme, the comparison result of the high-speed dynamic comparator is a logic value, and the logic value includes logic 0 and logic 1; and the logic value is reflected in the second-stage output OUT+ node and the second-stage output OUT- node according to the size of the input differential signal.
[0011] In the above solution, the high-speed dynamic comparator includes a reset phase and a comparison phase, wherein the comparison phase includes a first comparison phase, a second comparison phase and a third comparison phase.
[0012] In the above scheme, the first NMOS tube is cut off in the reset stage and turned on in the comparison stage to open the discharge path; the second NMOS tube is cut off in the comparison stage and turned on in the reset stage to eliminate the asymmetry of the parasitic capacitances generated by the source of the first NMOS tube, the gate and drain of the third NMOS tube, and the drain of the fourth NMOS tube in the discharge path, and can partially absorb the charge generated by the charge injection effect of the first NMOS tube; the third NMOS tube is cut off in the reset stage and turned on in the comparison stage to provide a forward voltage drop from the drain to the source of the third NMOS tube that is greater than the threshold voltage; the fourth NMOS tube enters the linear region in the reset stage and is in the saturation region in the first comparison stage to amplify the input differential signal.
[0013] In the above scheme, in the reset stage, the drains of the two fourth NMOS tubes in the discharge path are both discharged to the ground; and when the second NMOS tube is turned on so that the gate and drain of the third NMOS tube are both discharged to the ground, the discharge path has no static power consumption and is in the off state in the reset stage.
[0014] In the above scheme, the discharge path amplifies the input signal in the comparison stage, and absorbs part of the discharge current of the first-stage output node and inputs it to the second-stage output node, wherein the first-stage output node includes the first-stage output FP node and the first-stage output FN node, and the second-stage output node includes the second-stage output OUT+ node and the second-stage output OUT- node; wherein, when the drain discharge voltage of the third NMOS tube is lower than the threshold voltage of the third NMOS tube, the discharge path is self-shutoff; the discharge speed of the first-stage output node is greater than the charging speed of the second-stage output node, and when the source voltage and the drain voltage of the fourth NMOS tube in the discharge path are both greater than the gate input voltage of the fourth NMOS tube minus a threshold voltage value, the discharge path is shut off; when the source voltage of the fourth NMOS tube in the discharge path is greater than the drain voltage, the discharge path is shut off due to the third NMOS tube, and the second-stage output node realizes the output of logic 0 and logic 1.
[0015] In the above scheme, the voltage discharge of the first-stage output node is nonlinear discharge.
[0016] In the above scheme, as the input common mode voltage decreases, the fourth NMOS tube in the discharge path of the comparator stays in the saturation region for a longer time, so as to improve the amplification and comparison speed of the input signal.
[0017] In the above solution, as the threshold voltage of the third NMOS tube decreases, the saturation region time of the fourth NMOS tube is correspondingly prolonged.
[0018] (III) Beneficial effects
[0019] The technical solution of the embodiment of the present invention has at least the following beneficial effects:
[0020] (1) Adding a discharge path, by providing an additional discharge path for amplifying the signal at the initial stage of discharge of the first-stage output node in the comparison phase, speeds up the discharge speed. At the same time, the discharge current of the first-stage output node is used to raise the voltage of the second-stage output node, thereby speeding up the regeneration of the comparator at the second-stage output node.
[0021] (2) After the high-speed dynamic comparator completes the comparison, the double-tail dynamic comparator can realize self-shutdown and maintain zero static power consumption.
[0022] (3) The high-speed dynamic comparator is based on adding a second NMOS tube to eliminate non-ideal effects such as charge injection caused by the discharge path, thereby improving the comparison accuracy of the comparator. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 A schematic diagram of a circuit principle diagram of a high-speed dynamic comparator according to an embodiment of the present invention is shown;
[0024] Figure 2 A schematic diagram showing a comparison of a certain transient simulation speed of a high-speed dynamic comparator according to an embodiment of the present invention and a traditional double-tail comparator in a comparison phase is shown;
[0025] Figure 3 The figure schematically shows the power consumption simulation result of the high-speed dynamic comparator according to the embodiment of the present invention. DETAILED DESCRIPTION
[0026] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.
[0027] Figure 1 The circuit principle diagram of a high-speed dynamic comparator according to an embodiment of the present invention is schematically shown.
[0028] Please refer to Figure 1 An embodiment of the present invention provides a high-speed dynamic comparator, including a double-tailed comparator body 101 and a discharge path, the discharge path includes a first discharge path 2 and a second discharge path 3, the first discharge path 2 and the second discharge path 3 are symmetrically arranged on both sides of the double-tailed comparator body 101 along a first direction X1.
[0029] Among them, the double-tail comparator body 101 includes a pre-amplifier stage 1011 and a latch stage 1012, the pre-amplifier stage 1011 includes a first-stage input pair tube 10111, the first discharge path 2 includes a first-stage output FP node 21, a second-stage output OUT+ node 22 and an input VIN+ node 23, and the second discharge path 3 includes a first-stage output FN node 31, a second-stage output OUT- node 32 and an input VIN- node 33.
[0030] In the embodiment of the present invention, the first discharge path 2 and the second discharge path 3 both include a first NMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube. In the first discharge path 2, the gate of the first NMOS tube is connected to the CLK clock, the drain of the first NMOS tube is connected to the first-stage output FP node 21, the source of the first NMOS tube is respectively connected to the drain of the second NMOS tube, the gate and the drain of the third NMOS tube, the gate of the second NMOS tube is connected to CLK0, and the source of the second NMOS tube is connected to the ground line; and the gate of the third NMOS tube is respectively connected to the drain of the third NMOS tube, the source of the first NMOS tube and the drain of the second NMOS tube, the source of the third NMOS tube is connected to the drain of the fourth NMOS tube, the gate of the fourth NMOS tube is connected to the input VIN+ node 23, and the source of the fourth NMOS tube is connected to the second-stage output OUT+ node 22.
[0031] In the second discharge path 3, the gate of the first NMOS tube is connected to the CLK clock, the drain of the first NMOS tube is connected to the first-stage output FN node 31, the source of the first NMOS tube is respectively connected to the drain of the second NMOS tube, the gate and the drain of the third NMOS tube, the gate of the second NMOS tube is connected to CLK0, and the source of the second NMOS tube is connected to the ground line; and the gate of the third NMOS tube is respectively connected to the drain of the third NMOS tube, the source of the first NMOS tube and the drain of the second NMOS tube, the source of the third NMOS tube is connected to the drain of the fourth NMOS tube, the gate of the fourth NMOS tube is connected to the input VIN-node 33, and the source of the fourth NMOS tube is connected to the second-stage output OUT-node 32.
[0032] Specifically, if Figure 1 As shown, in the embodiment of the present invention, in the discharge path structure, the first discharge path 2 includes four NMOS transistors, namely a first NMOS transistor 102 , a second NMOS transistor 105 , a third NMOS transistor 103 , and a fourth NMOS transistor 104 .
[0033] Among them, the gate of the first NMOS tube 102 is connected to the CLK clock, the drain of the first NMOS tube 102 is connected to the first-stage output FP node 21, and the source of the first NMOS tube 102 is respectively connected to the drain of the second NMOS tube 105 and the gate and drain of the third NMOS tube 103; the gate of the second NMOS tube 105 is connected to CLK0, that is, the same swing clock with a phase difference of 180° with the CLK clock, and the source of the second NMOS tube 105 is connected to the ground line.
[0034] Among them, the gate of the third NMOS tube 103 is respectively connected to the drain of the third NMOS tube 103, the source of the first NMOS tube 102 and the drain of the second NMOS tube 105, and the source of the third NMOS tube 103 is connected to the drain of the fourth NMOS tube 104; the gate of the fourth NMOS tube 104 is connected to the input VIN+ node 23, and the source of the fourth NMOS tube 104 is connected to the second-stage output OUT+ node 22 on the opposite side.
[0035] Further, such as Figure 1 As shown, the second discharge path 3 includes four NMOS transistors, namely the first NMOS transistor 106, the second NMOS transistor 109, the third NMOS transistor 107, and the fourth NMOS transistor 108. The gate of the first NMOS transistor 106 is connected to the CLK clock, the drain of the first NMOS transistor 106 is connected to the first-stage output FN node 31, and the source of the first NMOS transistor 106 is connected to the drain of the second NMOS transistor 109 and the gate and drain of the third NMOS transistor 107; the gate of the second NMOS transistor 109 is connected to CLK0, that is, the same swing clock with a phase difference of 180° from the CLK clock, and the source of the second NMOS transistor 109 is connected to the ground line.
[0036] Among them, the gate of the third NMOS tube 107 is respectively connected to the drain of the third NMOS tube 107, the source of the first NMOS tube 106 and the drain of the second NMOS tube 109, and the source of the third NMOS tube 107 is connected to the drain of the fourth NMOS tube 108; the gate of the fourth NMOS tube 108 is connected to the input VIN-node 33, and the source of the fourth NMOS tube 108 is connected to the second-stage output OUT-node 32 on the opposite side.
[0037] In an embodiment of the present invention, the comparison result of the high-speed dynamic comparator is a logic value, which includes logic 0 and logic 1; and the logic value is reflected in the second-stage output OUT+ node 22 and the second-stage output OUT- node 32 according to the size of the input differential signal.
[0038] Specifically, a discharge path is arranged on both sides of the double-tailed comparator body 101, so that the discharge current of the first-stage output FP node 21 and the first-stage output FN node 31 are shunted, and a part of the current is used to not only produce a current amplification effect, but also supply it to the second-stage output OUT+ node 22 and the second-stage output OUT- node 32, so that the initial discharge time of the first-stage output node is utilized to quickly turn on the second stage. The final comparison result of the comparator is logic 0 and logic 1, and the logic value is reflected in the second-stage output OUT+ node 22 and the second-stage output OUT- node 32 according to the size of the input differential signal.
[0039] In the embodiment of the present invention, the high-speed dynamic comparator includes a reset phase and a comparison phase, wherein the comparison phase includes a first comparison phase, a second comparison phase and a third comparison phase. The following first describes in detail the different functions of the NMOS tube in the discharge path at different phases.
[0040] In the embodiment of the present invention, the first discharge path 2 and the second discharge path 3 in the discharge path both include a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor, and these four NMOS transistors have different functions in different stages.
[0041] In an embodiment of the present invention, the first NMOS tube is cut off in the reset stage and turned on in the comparison stage to open the discharge path; the second NMOS tube is cut off in the comparison stage and turned on in the reset stage to eliminate the asymmetry of parasitic capacitances generated by the source of the first NMOS tube, the gate and drain of the third NMOS tube, and the drain of the fourth NMOS tube in the discharge path, and can partially absorb the charge generated by the charge injection effect of the first NMOS tube; the third NMOS tube is cut off in the reset stage and turned on in the comparison stage to provide a forward voltage drop from the drain to the source of the third NMOS tube that is greater than the threshold voltage; the fourth NMOS tube enters the linear region in the reset stage and is in the saturation region in the first comparison stage to amplify the input differential signal.
[0042] Specifically, the first NMOS tube driven by CLK is cut off in the reset stage and turned on in the comparison stage to open the discharge path; the second NMOS tube driven by CLK0 is cut off in the comparison stage and turned on in the reset stage to eliminate the asymmetry of the parasitic capacitances generated by the source of the first NMOS, the gate and drain of the third NMOS tube, and the drain of the fourth NMOS tube in the two discharge paths, thereby eliminating the dynamic offset of the comparator and partially absorbing the charge generated by the charge injection effect of the first NMOS tube; the third NMOS tube is cut off in the reset stage and turned on in the comparison stage to provide a forward voltage drop from the drain to the source of the third NMOS tube that is greater than the threshold voltage.
[0043] Furthermore, the fourth NMOS tube enters the linear region in the reset phase and is in the saturation region at the beginning of the comparison phase, and is used to amplify the input differential signal, generate a larger differential discharge current at the first-stage output node, i.e., the first-stage output FP node 21 and the first-stage output FN node 31, and inject the current into the second-stage output node, i.e., the second-stage output OUT+ node 22 and the second-stage output OUT- node 32. As the drain of the fourth NMOS tube gradually discharges, the tube gradually approaches or enters the linear region from the saturation region. When the comparison is completed, the fourth NMOS tube connected to the second-stage output node of logic 1 eventually enters the cut-off region, and the fourth NMOS tube connected to the second-stage output node of logic 0 eventually remains in the linear region.
[0044] In an embodiment of the present invention, in the reset stage, the drains of the two fourth NMOS tubes in the discharge path are both discharged to the ground; and when the conduction of the second NMOS tube causes the gate and drain of the third NMOS tube to be discharged to the ground, the discharge path has no static power consumption and is in the off state in the reset stage.
[0045] In an embodiment of the present invention, the discharge path amplifies the input signal in the comparison stage, and absorbs part of the discharge current of the first-stage output node and inputs it into the second-stage output node, wherein the first-stage output node includes the first-stage output FP node 21 and the first-stage output FN node 31, and the second-stage output node includes the second-stage output OUT+ node 22 and the second-stage output OUT- node 32; wherein, when the drain discharge voltage of the third NMOS tube is lower than the threshold voltage of the third NMOS tube, the discharge path is self-shutoff; the discharge speed of the first-stage output node is greater than the charging speed of the second-stage output node, and when the source voltage and the drain voltage of the fourth NMOS tube in the discharge path are both greater than the gate input voltage of the fourth NMOS tube minus a threshold voltage value, the discharge path is shut off; when the source voltage of the fourth NMOS tube in the discharge path is greater than the drain voltage, the discharge path is shut off by the third NMOS tube, and the second-stage output node realizes the output of logic 0 and logic 1.
[0046] Specifically, when the drain discharge voltage of the third NMOS tube is lower than the threshold voltage of the third NMOS tube, the discharge path is self-shutoff, which generally occurs at the output node with a logic 0 output.
[0047] Furthermore, the discharge speed of the first-stage output node is controlled to be greater than the charging speed of the second-stage output node. When the source voltage and the drain voltage of the fourth NMOS tube in the discharge path are both greater than the gate input voltage value VIN+ or VIN- of the fourth NMOS tube minus a threshold voltage value, even if the drain of the third NMOS tube has not been discharged below the threshold voltage of the third NMOS tube, the discharge path will also be turned off. This situation generally occurs at the output node whose output is logic 1.
[0048] In an embodiment of the present invention, the voltage discharge of the first-stage output node is a non-linear discharge.
[0049] Specifically, the voltage discharge of the first-stage output node is not linear discharge, but nonlinear discharge, because the discharge path is gradually turned off during the discharge process. The discharge speed is fastest at the initial stage, and the discharge speed of the first-stage output node slows down in the later stage of discharge, and the speed gradually tends to the linear discharge of the traditional dynamic comparator.
[0050] Furthermore, the high-speed, low-power dynamic comparator has an acceleration effect in the comparison process. In the comparison stage, the voltage discharge of the first-stage output node is not a linear discharge, but a nonlinear discharge. At the initial stage of the discharge of the first-stage output node, the discharge path and the first-stage input pair of the double-tail comparator body discharge the first-stage output node at the same time and amplify the differential signal, but the source voltage of the fourth NMOS tube of the discharge path will rise with the discharge, affecting the transconductance of the fourth NMOS tube, and then continuously weakening the amplification effect of the discharge path. This effect is a nonlinear change, so the discharge speed is the fastest at the initial stage, and the discharge speed of the first-stage output node slows down in the later stage of the discharge until the discharge path is turned off, and the speed gradually tends to the linear discharge of the traditional dynamic comparator. At this time, only the first-stage input pair discharges the first-stage output node.
[0051] In the embodiment of the present invention, as the input common mode voltage decreases, the fourth NMOS tube of the discharge path in the comparator is in the saturation region for a longer time, so as to improve the amplification and comparison speed of the input signal.
[0052] Specifically, under the premise that the input common-mode voltage will not cause the fourth NMOS tube to be cut off in the first stage of comparison, the lower the input common-mode voltage, the better the speed improvement of the high-speed, low-power dynamic comparator of this embodiment relative to the traditional two-input double-tail comparator; the lower the input common-mode voltage, the longer the input tube in the discharge path is in the saturation zone, the more obvious the amplification effect on the input signal, and the more time saved for subsequent fast comparison.
[0053] In the embodiment of the present invention, as the threshold voltage of the third NMOS transistor decreases, the saturation region time of the fourth NMOS transistor is correspondingly prolonged.
[0054] Specifically, the third NMOS tube of the discharge path can select a smaller threshold voltage to extend the saturation time of the input tube of the discharge path and enhance the amplification capability.
[0055] Through the embodiments disclosed herein, during the comparison process of the high-speed dynamic comparator, on the one hand, the discharge path can amplify the signal together with the first-stage input pair of the double-tail comparator body, thereby accelerating the time for the second-stage circuit to start the comparison; on the other hand, the discharge path can utilize a portion of the first-stage discharge current to charge the second-stage comparison result, thereby maintaining the zero static power consumption and high-speed advantages of the dynamic comparator, realizing reasonable use of current during the comparison process, improving the comparison speed, and finally, when the comparison is completed, the high-speed discharge path can realize self-shutdown.
[0056] Based on the fact that the NMOS tube in the above-mentioned discharge path has different functions at different stages, the implementation process of the high-speed dynamic comparator at different stages is described in detail below.
[0057] Exemplarily, in the reset stage of the high-speed dynamic comparator, the first NMOS tube 102 and the first NMOS tube 106 driven by CLK are turned off in the reset stage; the second NMOS tube 105 and the second NMOS tube 109 driven by CLK0 are turned on in the reset stage, which are used to eliminate the asymmetry of the gate and drain of the third NMOS tube 103 and the third NMOS tube 107 in the two discharge paths, eliminate the dynamic offset of the comparator, and at the same time partially absorb the charge generated by the charge injection effect of the first NMOS tube 102 and the first NMOS tube 106; the third NMOS tube 103 and the third NMOS tube 107 are turned off in the reset stage; the fourth NMOS tube 104 and the fourth NMOS tube 108 enter the linear region in the reset stage, and the source and drain voltages are close to the ground.
[0058] With the rising edge trigger of CLK and the falling edge trigger of CLK0, the high-speed dynamic comparator enters the first comparison stage. The first NMOS tube 102 and the first NMOS tube 106 driven by CLK are turned on in the comparison stage to open the discharge path; the second NMOS tube 105 and the second NMOS tube 109 driven by CLK0 are turned off in the comparison stage; the third NMOS tube 103 and the third NMOS tube 107 are turned on in the comparison stage to provide a threshold voltage drop from the drain to the source; the fourth NMOS tube 104 and the NMOS tube 108 are in the saturation region to amplify the input differential signal, generate a larger differential discharge current at the first-stage output node, and inject the current into the second-stage output node.
[0059] Further, the high-speed dynamic comparator enters the second comparison stage. When the drains of the third NMOS tube 103 and the third NMOS tube 107 are discharged to the threshold voltages of the third NMOS tubes 103 and 107, the discharge path is self-shutdown. This situation generally occurs at the output node with a logic 0 output. In addition, as the drains of the fourth NMOS tube 104 and the fourth NMOS tube 108 are gradually discharged, the tube gradually approaches or enters the linear region from the saturation region, wherein the discharge speed of the first-stage output node is greater than the charging speed of the second-stage output node. When the source voltage and the drain voltage of the fourth NMOS tube in the discharge path are both greater than the gate input voltage value VIN+ or VIN- of the fourth NMOS tube minus a threshold voltage value, even if the drain of the third NMOS tube has not been discharged below the threshold voltage of the third NMOS tube, the discharge path will also be shut down. This situation generally occurs at the output node with a logic 1 output.
[0060] Furthermore, the high-speed dynamic comparator enters the third comparison stage, the discharge path is turned off, the output node generates logic 1 and logic 0 levels, the fourth NMOS tube 104 or the fourth NMOS tube 108 connected to the second-level output node of logic 1 eventually enters the cut-off region, and the fourth NMOS tube 104 or the fourth NMOS tube 108 connected to the logic 0 node eventually remains in the linear region.
[0061] Furthermore, after the comparison phase of the high-speed dynamic comparator ends, with the triggering of the falling edge of the clock CLK and the rising edge of CLK0, the comparator returns to the reset state and enters the reset phase again, and then further performs the above-mentioned comparison phase process, and repeats the cycle.
[0062] It should be noted that, in the comparison stage of the high-speed dynamic comparator, the voltage discharge of the first-stage output FP node 21 and the first-stage output FN node 31 is a nonlinear discharge. At the initial stage of discharge of the first-stage output FP node 21 and the first-stage output FN node 31, the discharge path and the first-stage input pair 10111 in the double-tail comparator body 101 discharge the first-stage output FP node 21 and the first-stage output FN node 31 at the same time, and amplify the differential signal, but the source voltage of the fourth NMOS tube 104 and the fourth NMOS tube 108 in the discharge path will rise with the discharge, so that the transconductance of the fourth NMOS tube 104 and the fourth NMOS tube 108 decreases, thereby continuously weakening the amplification effect of the discharge path. This effect is a nonlinear change, so the discharge speed is the fastest at the initial stage, and the discharge speed of the first-stage output node slows down in the later stage of discharge until the discharge path is turned off, and the speed gradually tends to the linear discharge of the traditional dynamic comparator. At this time, only the first-stage input pair 10111 in the double-tail comparator body 101 discharges the first-stage output FP node 21 and the first-stage output FN node 31.
[0063] In addition, under the premise that the input common mode voltage will not cause the fourth NMOS tube to be cut off in the first stage of comparison, the lower the input common mode voltage, the better the speed improvement compared with the traditional two-input double-tail comparator; the lower the input common mode voltage, the longer the fourth NMOS tube 104 and the fourth NMOS tube 108 in the discharge path are in the saturation region, the more obvious the amplification effect on the input signal, and the more time is saved for subsequent fast comparison. The third NMOS tube 103 and the third NMOS tube 107 of the discharge path can select a smaller threshold voltage to extend the saturation region time of the discharge path input tube and enhance the amplification capability.
[0064] Through the embodiments of the present invention, a discharge path is added, and an additional discharge path for amplifying the signal is provided at the initial stage of discharge of the first-stage output node in the comparison phase, so that the discharge speed is accelerated, and at the same time, the discharge current is used to raise the voltage of the second-stage output node, thereby accelerating the regeneration of the comparator at the second-stage output node; after the comparison of the high-speed dynamic comparator is completed, the double-tail dynamic comparator can achieve self-shutdown and maintain zero static power consumption; the high-speed dynamic comparator is based on adding a second NMOS tube to eliminate non-ideal effects such as charge injection caused by the discharge path, thereby improving the comparison accuracy of the comparator.
[0065] Figure 2 A schematic diagram shows a comparison of transient simulation speeds of a high-speed dynamic comparator according to an embodiment of the present invention and a traditional double-tail comparator in a comparison phase.
[0066] like Figure 2 As shown, the high-speed dynamic comparator of this embodiment has certain advantages in the compromise between power consumption, area and speed. The size of the second-stage PMOS input pair of the double-tail comparator body is reduced, and a discharge path of a certain area is added to ensure that the total area of the discharge path and the second-stage PMOS input pair of the double-tail comparator body is basically the same. At this time, the parasitic capacitance of the second-stage input pair is basically the same in the two circuits, so the dynamic power consumption can also be guaranteed to be basically the same, and the speed can be compared at this time.
[0067] When the high-speed dynamic comparator in this embodiment does not have a discharge path (i.e., a traditional double-tail comparator), the transient simulation results are shown in the upper half. FP, FN, OUT+, and OUT- are Figure 1 The transient simulation results when the discharge path (the high-speed dynamic comparator of this embodiment) is added are shown in the following half. FP2, FN2, OUT2+, and OUT2- correspond to Figure 1 FP, FN, OUT+, OUT- nodes; the horizontal axis is time, the vertical axis is voltage, 0ns~2ns is the comparison stage, 2ns~4ns is the reset stage, the input terminal VIN+ is 1.21V, VIN- is 1.2V, the power supply VDD is 3.3V, the simulation time is 1ns, and it is measured that the time taken for the comparator output differential value to reach 0.5*VDD before the improvement is 670ps, while the time taken for the comparator output differential value to reach 0.5*VDD after the improvement is 519ps, and the speed is improved by about 22%. It can be seen that the FP node and FN node before the improvement show linear discharge characteristics, and the FP node and FN node after the improvement show nonlinear characteristics. The OUT+ and OUT- nodes before the improvement did not rise significantly in the early stage of comparison, but rose after 250ps, while the OUT+ and OUT- after the improvement rose significantly in the early stage of comparison, which shows that the addition of the discharge path can improve the regeneration speed of the second-stage output node.
[0068] Figure 3 The figure schematically shows the power consumption simulation result of the high-speed dynamic comparator according to the embodiment of the present invention.
[0069] like Figure 3 As shown, further looking at the power consumption waveform of the high-speed dynamic comparator, the horizontal axis is time, the vertical axis is current, under the premise of the same output load, the clock CLK and CLK0 cycle is 4ns, the duty cycle is 50%, the phase is 180° and completely symmetrical, because the stable time for the dynamic current to drop to 0 is less than 1ns, the average current within 1ns after the CLK trigger is simulated, and the two are used as references for comparison. The average current is divided into the average current during reset and the average current during comparison. 0ns~2ns is the comparison stage, and 2ns~4ns is the reset stage. It can be seen that in the double-tail comparator body, the average current within 1ns of the comparison stage is 56.10μA, and the average current within 1ns of the reset stage is 49.31μA; after adding the discharge path, the average current within 1ns of the comparison stage is 66.08μA, and the average current within 1ns of the reset stage is 43.49μA. In general, the overall power consumption increases by less than 5%, the area remains basically unchanged, and the speed can be increased by about 22%.
[0070] Through the embodiments of the present invention, the high-speed dynamic comparator not only realizes zero static power consumption and high-speed advantages, but also realizes reasonable utilization of current during the comparison process, thereby improving the comparison speed and comparison accuracy.
[0071] The above specific embodiments further illustrate the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.
Claims
1. A high-speed dynamic comparator, characterized in that: It comprises a double-tail comparator body (101) and a discharge path, the discharge path comprising a first discharge path (2) and a second discharge path (3), the first discharge path (2) and the second discharge path (3) being symmetrically arranged on both sides of the double-tail comparator body (101) along a first direction; wherein the first discharge path (2) comprises a first-stage output FP node (21), a second-stage output OUT+ node (22) and an input VIN+ node (23), and the second discharge path (3) comprises a first-stage output FN node (31), a second-stage output OUT- node (32) and an input VIN- node (33); and The first discharge path (2) and the second discharge path (3) both comprise a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor; In the first discharge path (2), the gate of the first NMOS tube is connected to the CLK clock, the drain of the first NMOS tube is connected to the first-stage output FP node (21), the source of the first NMOS tube is respectively connected to the drain of the second NMOS tube and the gate and drain of the third NMOS tube, the gate of the second NMOS tube is connected to CLK0, and the source of the second NMOS tube is connected to the ground line; and The gate of the third NMOS tube is respectively connected to the drain of the third NMOS tube, the source of the first NMOS tube and the drain of the second NMOS tube, the source of the third NMOS tube is connected to the drain of the fourth NMOS tube, the gate of the fourth NMOS tube is connected to the input VIN+ node (23), and the source of the fourth NMOS tube is connected to the second-stage output OUT+ node (22).
2. The high-speed dynamic comparator according to claim 1, characterized in that: In the second discharge path (3), the gate of the first NMOS tube is connected to the CLK clock, the drain of the first NMOS tube is connected to the first-stage output FN node (31), the source of the first NMOS tube is respectively connected to the drain of the second NMOS tube and the gate and drain of the third NMOS tube, the gate of the second NMOS tube is connected to CLK0, and the source of the second NMOS tube is connected to the ground line; and The gate of the third NMOS tube is respectively connected to the drain of the third NMOS tube, the source of the first NMOS tube and the drain of the second NMOS tube, the source of the third NMOS tube is connected to the drain of the fourth NMOS tube, the gate of the fourth NMOS tube is connected to the input VIN-node (33), and the source of the fourth NMOS tube is connected to the second-stage output OUT-node (32).
3. The high-speed dynamic comparator according to claim 1, characterized in that: The comparison result of the high-speed dynamic comparator is a logic value, and the logic value includes logic 0 and logic 1; and The logic value is reflected in the second-stage output OUT+ node (22) and the second-stage output OUT- node (32) according to the size of the input differential signal.
4. The high-speed dynamic comparator according to claim 1 or 2, characterized in that: The high-speed dynamic comparator includes a reset phase and a comparison phase, wherein the comparison phase includes a first comparison phase, a second comparison phase and a third comparison phase.
5. The high-speed dynamic comparator according to claim 4, characterized in that: The first NMOS tube is turned off in the reset phase and turned on in the comparison phase, so as to open the discharge path; The second NMOS tube is turned off in the comparison phase and turned on in the reset phase, so as to eliminate the asymmetry of the parasitic capacitances respectively generated by the source of the first NMOS tube, the gate and drain of the third NMOS tube, and the drain of the fourth NMOS tube in the discharge path, and partially absorb the charge generated by the charge injection effect of the first NMOS tube; The third NMOS transistor is turned off in the reset phase and turned on in the comparison phase, and is used to provide a forward voltage drop from the drain to the source of the third NMOS transistor that is greater than the threshold voltage; The fourth NMOS transistor enters the linear region in the reset phase and is in the saturation region in the first comparison phase, and is used to amplify the input differential signal.
6. The high-speed dynamic comparator according to claim 1 or 5, characterized in that: In the reset phase, the drains of the two fourth NMOS transistors in the discharge path are both discharged to the ground; and When the conduction of the second NMOS tube causes both the gate and the drain of the third NMOS tube to discharge to the ground, the discharge path has no static power consumption and is in a cut-off state in the reset phase.
7. The high-speed dynamic comparator according to claim 6, characterized in that: The discharge path amplifies the input signal in the comparison stage and absorbs part of the discharge current of the first-stage output node and inputs it into the second-stage output node, wherein the first-stage output node includes a first-stage output FP node (21) and a first-stage output FN node (31), and the second-stage output node includes a second-stage output OUT+ node (22) and a second-stage output OUT- node (32); Wherein, when the drain discharge voltage of the third NMOS tube is lower than the threshold voltage of the third NMOS tube, the discharge path is self-shutdown; The discharge speed of the first-stage output node is greater than the charge speed of the second-stage output node, and when the source voltage and the drain voltage of the fourth NMOS tube of the discharge path are both greater than the gate input voltage of the fourth NMOS tube minus a threshold voltage value, the discharge path is turned off; When the source voltage of the fourth NMOS tube in the discharge path is greater than the drain voltage, the discharge path is turned off by the third NMOS tube, and the second-stage output node realizes the output of logic 0 and logic 1.
8. The high-speed dynamic comparator according to claim 7, characterized in that: The voltage discharge of the first-stage output node is non-linear discharge.
9. The high-speed dynamic comparator according to claim 1 or 8, characterized in that: As the input common mode voltage decreases, the fourth NMOS tube in the discharge path of the comparator stays in the saturation region for a longer time, so as to improve the amplification and comparison speed of the input signal.
10. The high-speed dynamic comparator according to claim 1 or 5, characterized in that: As the threshold voltage of the third NMOS tube decreases, the saturation region time of the fourth NMOS tube is prolonged accordingly.