Level conversion circuit for suppressing PVT fluctuation

Abstract

The invention relates to the technical field of switch control and semiconductor integrated circuits, and discloses a level conversion circuit for suppressing PVT fluctuation, comprising a comparator circuit for comparing a comparison voltage with a reference voltage by using a differential amplifier and converting the comparison voltage into a corresponding first target level according to a comparison result; the logic level conversion circuit is used for converting the first target level output by the comparator circuit into a second target level corresponding to the first target level through diode voltage drop; and the output circuit is used for reversely outputting the second target level output by the logic level conversion circuit as a complementary high-low level corresponding to the second target level. The differential comparator circuit structure is adopted, the threshold voltage is irrelevant to temperature and process fluctuation, the phenomenon that the output level of a traditional level conversion circuit is unstable along with PVT fluctuation is restrained, and the output level of the level conversion circuit is more stable.

Description

Technical Field

[0001] The present invention relates to the field of switch control technology and semiconductor integrated circuit technology, and in particular to a level conversion circuit for suppressing PVT fluctuations. Background Art

[0002] In order to control the control type monolithic microwave integrated circuits such as attenuators, phase shifters, and delay devices in semiconductor integrated circuits, it is often necessary to integrate digital drivers on the chip. The digital driver circuit is responsible for outputting the commonly used +5V / 0V voltage to the switch to control its opening or closing. In monolithic microwave integrated circuits, the ED mode of GaAs pHEMT is usually used to design the level conversion circuit. Compared with the silicon-based process, the GaAs pHEMT process has higher output power, lower noise, and higher isolation.

[0003] The switching tubes commonly used in the design of control-type monolithic microwave integrated circuits are depletion-type field-effect tubes. Their turn-on voltage range is generally -0.7V~1V, and their turn-off voltage range is -5V~-1V. There are slight differences between different process manufacturers. Therefore, as long as the level conversion circuit controls the output voltage within this range, it is sufficient to drive the switch tube on and off. Under normal circumstances, the output voltage of the level conversion circuit is 0V / -5V.

[0004] With the continuous improvement of integrated circuit design technology and manufacturing process, the requirements for circuit performance are getting higher and higher. The process fluctuations of chip production and the temperature and power supply voltage fluctuations under chip application will affect the output voltage of the level conversion circuit, so how to suppress these effects is a difficult problem that needs to be solved urgently. Summary of the invention

[0005] In view of the above-mentioned deficiencies in the prior art, the present invention provides a level conversion circuit for suppressing PVT fluctuations.

[0006] In order to achieve the above-mentioned object of the invention, the technical solution adopted by the present invention is: A level conversion circuit for suppressing PVT fluctuations, comprising: a comparator circuit, configured to compare a comparison voltage with a reference voltage using a differential amplifier, and convert the comparison voltage into a corresponding first target level according to a comparison result; a logic level conversion circuit, used for converting a first target level output by the comparator circuit into a second target level corresponding to the first target level through a diode voltage drop; The output circuit is used to reversely output the second target level output by the logic level conversion circuit into a complementary high and low level corresponding to the second target level.

[0007] In an optional implementation, when comparing the comparison voltage with the reference voltage, If the comparison voltage is greater than the reference voltage, the comparator circuit converts the comparison voltage to a first target level of 0V, the logic level conversion circuit converts the first target level of 0V to a second target level of -3V, and the output circuit reversely outputs the second target level of -3V to complementary high and low levels of -5V and 0V; If the comparison voltage is less than the reference voltage, the comparator circuit converts the comparison voltage to a first target level of -3.5V, the logic level conversion circuit converts the first target level of -3.5V to a second target level of -5V, and the output circuit reversely outputs the second target level of -5V to complementary high and low levels of 0V and -5V.

[0008] In an optional embodiment, the comparator circuit includes a differential amplifier, a self-biased constant current source, and a load transistor; The differential amplifier is used to compare the comparison voltage with the reference voltage and output the load driving current; The self-biased constant current source is used to provide bias current to the differential amplifier; The load transistor is used to convert the load driving current into a corresponding first target level.

[0009] In an optional implementation, the differential amplifier includes a first transistor and a second transistor; wherein the gate of the first transistor is connected to the input voltage through a first resistor and is connected to a -5V power supply through a second resistor; the source of the first transistor is connected to the source of the second transistor; the drain of the first transistor and the drain of the second transistor are both connected to a load transistor; the gate of the second transistor is connected to a -5V power supply through a seventh resistor and is grounded through a sixth resistor; The self-biased constant current source includes a third transistor; the gate of the third transistor is connected to a -5V power supply through a third resistor; the source of the third transistor is connected to a -5V power supply through a fourth resistor; the drain of the third transistor is connected to the source of the first transistor and the source of the second transistor; The load transistor includes a fourth transistor and a fifth transistor; the source of the fourth transistor is connected to the drain of the first transistor; the gate of the fourth transistor and the source of the second transistor are connected to the gate of the fifth transistor, and are connected to the source of the fifth transistor through a fifth resistor; the drain of the fourth transistor and the drain of the fifth transistor are grounded.

[0010] In an optional embodiment, the logic level conversion circuit includes a source follower and a diode drop circuit; The source follower is used to output the first target level output by the comparator circuit in equal amount; The diode drop circuit is used to generate a level shift using a diode drop chain, converting an equal output of a first target level into a second target level corresponding to the first target level.

[0011] In an optional implementation, the source follower includes a sixth transistor; the gate of the sixth transistor is connected to the first target level output by the comparator circuit; the drain of the sixth transistor is grounded through an eighth resistor; the source of the sixth transistor is connected to the diode drop circuit; The diode drop circuit includes a seventh transistor, an eighth transistor and a ninth transistor; the source and drain of each transistor are connected, and the gate of the latter transistor is connected to the drain and source of the previous transistor; the gate of the seventh transistor is connected to the source of the sixth transistor; the source and drain of the ninth transistor are connected to a -5V power supply through a ninth resistor.

[0012] In an optional implementation, the diode voltage drop circuit further includes a tenth resistor; one end of the tenth resistor is connected to the source and drain of the ninth transistor, and the other end of the tenth resistor is connected to the output circuit.

[0013] In an optional embodiment, the output circuit includes an inverting logic circuit and a load circuit; The inversion logic circuit is used for performing logic inversion on the second target level output by the logic level conversion circuit; The load circuit is used to perform a resistance voltage drop on the logic inversion signal by using a complementary active load, and output complementary high and low levels corresponding to the second target level.

[0014] In an optional implementation, the reverse logic circuit includes a tenth transistor, an eleventh transistor, a fourteenth transistor, and a fifteenth transistor; the gate of the tenth transistor is connected to the second target level output by the logic level conversion circuit; the drain of the tenth transistor is respectively connected to the gate of the eleventh transistor and the gate of the fifteenth transistor; the drain of the eleventh transistor is connected to the gate of the fourteenth transistor; the source of the tenth transistor, the source of the eleventh transistor, the source of the fourteenth transistor, and the source of the fifteenth transistor are connected to a -5V power supply; The load circuit includes a twelfth transistor, a thirteenth transistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor and a fifteenth resistor; one end of the twelfth resistor is connected to the drain of the tenth transistor; one end of the thirteenth resistor is connected to the drain of the eleventh transistor; the other ends of the twelfth resistor and the thirteenth resistor are grounded through the eleventh resistor; the gate of the twelfth transistor is connected to the drain of the fourteenth transistor; the source of the twelfth transistor is connected to the drain of the fourteenth transistor through the fourteenth resistor; the gate of the thirteenth transistor is connected to the drain of the fifteenth transistor; the source of the thirteenth transistor is connected to the drain of the fifteenth transistor through the fifteenth resistor; the drain of the twelfth transistor and the drain of the thirteenth transistor are grounded.

[0015] The present invention has the following beneficial effects: The present invention adopts a differential comparator circuit structure, and the threshold voltage is independent of temperature and process fluctuations, thereby preventing the instability of the output level of a traditional level conversion circuit with PVT fluctuations and making the output level of the level conversion circuit more stable. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is an overall block diagram of the present invention; Figure 2 is a circuit structure diagram of the present invention; Figure 3 A schematic diagram showing the change of node voltage with input voltage in the present invention; Figure 4 It is a schematic diagram of the change of output voltage with input voltage in the present invention; Figure 5 It is a schematic diagram of the change of the threshold voltage and the output voltage with the input voltage in the present invention. DETAILED DESCRIPTION

[0017] The specific implementation modes of the present invention are described below so that those skilled in the art can understand the present invention. However, it should be clear that the present invention is not limited to the scope of the specific implementation modes. For those of ordinary skill in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the attached claims, these changes are obvious, and all inventions and creations utilizing the concept of the present invention are protected.

[0018] like Figure 1 and Figure 2 As shown, a level conversion circuit for suppressing PVT fluctuations provided by an embodiment of the present invention includes: a comparator circuit, configured to compare a comparison voltage with a reference voltage using a differential amplifier, and convert the comparison voltage into a corresponding first target level according to a comparison result; a logic level conversion circuit, used for converting a first target level output by the comparator circuit into a second target level corresponding to the first target level through a diode voltage drop; The output circuit is used to reversely output the second target level output by the logic level conversion circuit into a complementary high and low level corresponding to the second target level.

[0019] This embodiment uses a comparator circuit to perform an accurate comparison between the comparison voltage and the reference voltage, outputs a preliminary logic level, and then uses a logic level conversion circuit to convert the logic level output by the comparator into the negative gate voltage required by the subsequent circuit. Finally, the output circuit is used to perform logical inversion on the signal after level conversion, thereby realizing a high-speed, low-power, and highly anti-interference level conversion circuit, which can effectively suppress the impact of PVT fluctuations on the level conversion circuit.

[0020] In an optional embodiment of the present invention, when the comparison voltage is compared with the reference voltage, If the comparison voltage is greater than the reference voltage, the comparator circuit converts the comparison voltage to a first target level of 0V, the logic level conversion circuit converts the first target level of 0V to a second target level of -3V, and the output circuit reversely outputs the second target level of -3V to complementary high and low levels of -5V and 0V; If the comparison voltage is less than the reference voltage, the comparator circuit converts the comparison voltage to a first target level of -3.5V, the logic level conversion circuit converts the first target level of -3.5V to a second target level of -5V, and the output circuit reversely outputs the second target level of -5V to complementary high and low levels of 0V and -5V.

[0021] This embodiment uses a logic level conversion circuit to accurately drop the first output level, and uses an output circuit to perform an inverted output, thereby achieving a stable output waveform and improving load capacity.

[0022] In an optional embodiment of the present invention, the comparator circuit includes a differential amplifier, a self-biased constant current source, and a load transistor; The differential amplifier is used to compare the comparison voltage with the reference voltage and output the load driving current; The self-biased constant current source is used to provide bias current to the differential amplifier; The load transistor is used to convert the load driving current into a corresponding first target level.

[0023] In this embodiment, the differential amplifier includes a first transistor T1 and a second transistor T2; wherein the gate of the first transistor T1 is connected to the input voltage V via a first resistor R1. in , and connected to a -5V power supply through a second resistor R2; the source of the first transistor T1 is connected to the source of the second transistor T2; the drain of the first transistor T1 and the drain of the second transistor T2 are both connected to the load transistor; the gate of the second transistor T2 is connected to a -5V power supply through a seventh resistor R7, and is grounded through a sixth resistor R6; In this embodiment, the self-biased constant current source includes a third transistor T3; the gate of the third transistor T3 is connected to a -5V power supply through a third resistor R3; the source of the third transistor T3 is connected to a -5V power supply through a fourth resistor R4; the drain of the third transistor T3 is connected to the source of the first transistor T1 and the source of the second transistor T2; In this embodiment, the load transistor includes a fourth transistor T4 and a fifth transistor T5; the source of the fourth transistor T4 is connected to the drain of the first transistor T1; the gate of the fourth transistor T4 and the source of the second transistor T2 are connected to the gate of the fifth transistor T5, and are connected to the source of the fifth transistor T5 through the fifth resistor R5; the drain of the fourth transistor T4 and the drain of the fifth transistor T5 are grounded.

[0024] The comparator circuit of this embodiment includes a self-biased constant current source differential amplifier and a resistor voltage divider network. The differential pair tube provides a stable operating current through a constant current source, and its gate potential is accurately set by the voltage divider resistor to ensure that the current does not fluctuate with temperature or process; the voltage divider network generates a reference voltage through a resistor ratio rather than an absolute value, so that the comparator flip threshold is determined only by a geometric ratio. This structure suppresses temperature drift through a constant current source, and at the same time uses the resistor matching characteristics to eliminate process deviations, achieving high-stability threshold detection, and providing a trigger signal for the subsequent stage that is not affected by the environment or process. Compared with the prior art, the threshold voltage of the comparator circuit of this embodiment is less affected by PVT fluctuations.

[0025] In an optional embodiment of the present invention, the logic level conversion circuit includes a source follower and a diode drop circuit; The source follower is used to output the first target level output by the comparator circuit in equal amount; The diode drop circuit is used to generate a level shift using a diode drop chain, converting an equal output of a first target level into a second target level corresponding to the first target level.

[0026] In this embodiment, the source follower includes a sixth transistor T6; the gate of the sixth transistor T6 is connected to the first target level output by the comparator circuit; the drain of the sixth transistor T6 is grounded through an eighth resistor R8; the source of the sixth transistor T6 is connected to the diode drop circuit. Compared with the prior art, the source follower of this embodiment outputs the first level equally and is less affected by the load.

[0027] In this embodiment, the diode voltage drop circuit includes a seventh transistor T7, an eighth transistor T8 and a ninth transistor T9; the source and drain of each transistor are connected, and the gate of the latter transistor is connected to the drain and source of the former transistor; the gate of the seventh transistor T7 is connected to the source of the sixth transistor T6; the source and drain of the ninth transistor T9 are connected to a -5V power supply through a ninth resistor R9. Compared with the prior art, the present invention uses a diode composed of three D-mode transistors with connected sources and drains, and realizes unidirectional conduction through the gate, which can achieve precise voltage drop without being affected by temperature.

[0028] In this embodiment, the diode voltage drop circuit further includes a tenth resistor R 10 ; The tenth resistor R10 One end of the tenth resistor R 10 The other end of the resistor R is connected to the output circuit. 10 is a large resistor that can limit the drive current without affecting the tenth transistor T 10 The bias.

[0029] The logic level conversion circuit of this embodiment includes a source follower and a diode voltage drop circuit. The source follower transmits the input signal to the subsequent stage with low distortion to isolate the load interference; the multi-stage diode uses the cumulative effect of the device threshold voltage to perform a fixed offset on the input level, and the temperature characteristics of the diode threshold and the resistor network complement each other to offset the voltage drop drift caused by temperature changes, and finally converts the input signal to the target level range, and the conversion accuracy remains stable in a wide temperature range.

[0030] In an optional embodiment of the present invention, the output circuit includes an inverting logic circuit and a load circuit; The inversion logic circuit is used for performing logic inversion on the second target level output by the logic level conversion circuit; The load circuit is used to perform a resistance voltage drop on the logic inversion signal by using a complementary active load, and output complementary high and low levels corresponding to the second target level.

[0031] In this embodiment, the reverse logic circuit includes a tenth transistor T 10 , the eleventh transistor T 11 , the fourteenth transistor T 14 and the fifteenth transistor T 15 ; The tenth transistor T 10 The gate of the tenth transistor T is connected to the second target level output by the logic level conversion circuit; 10 The drain of the eleventh transistor T 11 The gate of the fifteenth transistor T 15 The gate of the eleventh transistor T 11 The drain of the fourteenth transistor T 14 The gate of the tenth transistor T 10 The source of the eleventh transistor T 11 The source of the fourteenth transistor T 14 The source of the fifteenth transistor T 15 The source is connected to the -5V power supply; In this embodiment, the load circuit includes a twelfth transistor T 12 , the thirteenth transistor T 13 11th resistor R 11 , the twelfth resistor R 12 、Thirteenth resistor R 13 , the fourteenth resistor R14 and the fifteenth resistor R 15 ; Twelfth resistor R 12 One end of the tenth transistor T 10 The drain connection; the thirteenth resistor R 13 One end of the eleventh transistor T 11 The drain connection of the twelfth resistor R 12 and the thirteenth resistor R 13 The other end passes through the eleventh resistor R 11 Ground; twelfth transistor T 12 The gate of the fourteenth transistor T 14 The drain of the twelfth transistor T 12 The source of 14 With the fourteenth transistor T 14 The drain of the thirteenth transistor T 13 The gate of the fifteenth transistor T 15 The drain of the thirteenth transistor T 13 The source of the 15 With the fifteenth transistor T 15 The drain of the twelfth transistor T 12 The drain of the thirteenth transistor T 13 The drain is grounded.

[0032] In the output circuit of this embodiment, the tenth transistor T is controlled according to the second level after the voltage drop. 10 To turn on or off, the eleventh transistor T 11 and the fifteenth transistor T 15 According to the tenth transistor T 10 The fourteenth transistor T 14 According to the eleventh transistor T 11 The drain voltage of the switch on or off is different to realize the switch on and off, according to the eleventh resistor R 11 , the twelfth resistor R 12 、Thirteenth resistor R 13 The voltage drop of the twelfth transistor T in the load circuit 12 , the fourteenth resistor R 14 and the thirteenth transistor T 13 , the fifteenth resistor R 15 The reverse output can be achieved by reducing the voltage drop.

[0033] The output circuit of this embodiment is based on a push-pull inverter and a dynamic load design. The push-pull structure achieves signal polarity reversal through complementary drive tubes, and accelerates level jumps with low-impedance dynamic loads; the bias voltage is stabilized by a voltage divider network inside the inverter to ensure strict definition of the output high and low levels. This structure utilizes the fast turn-on characteristics of high-speed devices and the transient response optimization of dynamic loads to achieve nanosecond signal reversal while maintaining driving capability, and effectively suppresses output overshoot and oscillation.

[0034] A level conversion circuit for suppressing PVT fluctuations designed in this embodiment includes a comparator circuit, a logic level conversion circuit, and an output circuit. The comparator circuit is composed of a self-biased constant current source differential amplifier. The input voltage is compared with the reference voltage after a resistor voltage divider. When it is greater than the reference voltage, the comparator outputs 0V, and when it is less than the reference voltage, it outputs -3.5V. The logic level conversion circuit converts the comparator output voltage to -5V / -3V through a diode voltage drop. The output circuit is composed of a series of voltage inverters, which convert the logic voltage into a control voltage output of -5V / 0V. Since the comparator circuit uses a constant current source differential circuit, the threshold voltage is independent of temperature and process fluctuations, so this level conversion circuit can effectively suppress PVT fluctuations. The logic level conversion circuit uses a diode precise voltage drop, which can allow the output level to quickly flip between -5V~0V.

[0035] Combine the following Figure 2-Figure 5 The specific working principle and process of the present invention are introduced: In the comparator circuit, when the input level is V in When the voltage is divided by the first resistor R1 and the second resistor R2, the voltage V at point a is output. a =(V in +5)×(R1 / (R1+R2))+V in . T1 and T2 are E-mode transistors forming a differential pair, T3 is a D-mode transistor forming a self-biased constant current source, providing current bias for T1 and T2, the third resistor R3 is a pull-up resistor of transistor T3, and the fourth resistor R4 acts as a voltage divider to increase the voltage at point b so that T3 always works in the saturation region. T4 is a D-mode transistor, serving as the load of the T1 transistor. T5 is a D-mode transistor, which is equivalent to a large resistor close to the cut-off state with the fifth resistor R5.

[0036] When V in When it is smaller, V a Much smaller than V ref, the overdrive voltage of differential transistor T1 is much smaller than that of differential transistor T2. Transistor T2 can divide most of the current from the self-biased constant current source T3, so transistor T2 is in saturation state and transistor T1 is in cut-off state. Due to the voltage drop effect of the large resistor formed by T5 and R5, the voltage V c is the saturation voltage of the comparator, which is approximately -3.5V.

[0037] In the logic level conversion circuit, T6 is an E-mode transistor, which forms a source follower with resistor R8 to convert the input voltage V c For equal output, when the voltage difference across the seventh D-tube T7, the eighth D-tube T8, and the ninth D-tube T9 is sufficient, the three diodes are turned on, and the voltage drop of each diode is about 1V. When the comparator circuit outputs a voltage of -3.5V, V d The voltage drops to a minimum of -5V.

[0038] In the output circuit, the tenth transistor T 10 It is an E-mode transistor, the gate and source voltages are uniformly -5V, in the cut-off state, the eleventh resistor R 11 and the twelfth resistor R 12 As a large resistor, the transistor T 10 Drain voltage bias V e At -4.3V, -4.3V is the E-mode transistor T 11 and T 15 The gate voltage of transistor T 11 and T 15 In the saturation region, through the large resistor R 11 and R 13 After the voltage drop, transistor T 11 The drain voltage V f is -5V, and the E-mode transistor T 14 The gate voltage is -5V, which is in the off state. 12 and the fourteenth resistor R 14 、D-mode transistor T 13 and the fifteenth resistor R 15 It is equivalent to two large resistors close to the cut-off state. After the voltage drop across these two resistors, the output voltage V out1 With V out2 0V and -5V respectively.

[0039] When V inWhen the voltage is larger, similar to the above principle, the overdrive voltage of the differential transistor T1 is much larger than the overdrive voltage of the differential transistor T2. The transistor T1 can divide most of the current from the self-biased constant current source T3, so the transistor T1 is in a saturated state and the transistor T2 is in a cut-off state. Due to the voltage drop effect of the large resistor formed by T5 and R5, the voltage V c About 0V. After the voltage drop of diodes T7, T8, and T9, V d The voltage of transistor T is about -3V. 10 and T 14 In saturation state, transistor T 11 and T 15 In the cut-off state, after T 12 and R 14 , T 13 and R 15 After the voltage drop, the output voltage V out1 With V out2 -5V and 0V respectively.

[0040] When V in The value of V a and V ref When V c = -2V, after the voltage drop through diodes T7, T8, T9 is exactly -5V, at this time the output level V out1 and V out2 The output levels are -5V and 0V, and the node V a 、V c 、V d and reference voltage V ref With input voltage V in Changes such as Figure 3 As shown, the output voltage V out1 With V out2 With input voltage V in Changes such as Figure 4 So -2V is V c The flip voltage is between -3.5V and 0V. At this time, V in It is also the output voltage V out1 With V out2 The threshold voltage V is between -5V and 0V. T , V T =[(R1 / R2-R6 / R7) / (1-R6 / R7)]×5, threshold voltage V T For the ratio of resistance, it can better suppress PVT fluctuations. When R1=50k , R2=R7=20k , R6=30k , we get VT =2V.

[0041] It should be noted that for DC voltage drop, resistors R5 and R 11 , R 12 , R 13 , R 14 , R 15 It should be at least a large resistor of kilo-ohm level, and the sizes of other resistors and transistors need to be determined according to the actual situation of the specific circuit.

[0042] Finally, the input level is compared with the reference level to convert the input level into a complementary high and low level output V out1 is -5V / 0V, V out2 is 0V / -5V, such as Figure 3 The complementary level output V out1 and V out2 To drive the switch tube in the microwave integrated circuit to turn on and off. Since the comparator circuit adopts a differential amplifier structure, it can effectively suppress PVT fluctuations. The logic level conversion circuit accurately controls the voltage drop through the diode, which can enable the output level to be quickly flipped between -5V and 0V. The threshold voltage V T And the output level at the threshold voltage V out1 and V out2 The temperature change curve is as follows Figure 5 shown.

[0043] The present invention uses specific embodiments to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

[0044] Those skilled in the art will appreciate that the embodiments described herein are intended to help readers understand the principles of the present invention, and should be understood that the protection scope of the present invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific variations and combinations that do not deviate from the essence of the present invention based on the technical revelations disclosed by the present invention, and these variations and combinations are still within the protection scope of the present invention.

Claims

1. A level conversion circuit for suppressing PVT fluctuations, characterized in that: include: a comparator circuit, configured to compare a comparison voltage with a reference voltage using a differential amplifier, and convert the comparison voltage into a corresponding first target level according to a comparison result; a logic level conversion circuit, used for converting a first target level output by the comparator circuit into a second target level corresponding to the first target level through a diode voltage drop; The output circuit is used to reversely output the second target level output by the logic level conversion circuit into a complementary high and low level corresponding to the second target level.

2. A level conversion circuit for suppressing PVT fluctuations according to claim 1, characterized in that: When comparing the comparison voltage with the reference voltage, If the comparison voltage is greater than the reference voltage, the comparator circuit converts the comparison voltage to a first target level of 0V, the logic level conversion circuit converts the first target level of 0V to a second target level of -3V, and the output circuit reversely outputs the second target level of -3V to complementary high and low levels of -5V and 0V; If the comparison voltage is less than the reference voltage, the comparator circuit converts the comparison voltage to a first target level of -3.5V, the logic level conversion circuit converts the first target level of -3.5V to a second target level of -5V, and the output circuit reversely outputs the second target level of -5V to complementary high and low levels of 0V and -5V.

3. A level conversion circuit for suppressing PVT fluctuations according to claim 1, characterized in that: The comparator circuit includes a differential amplifier, a self-biased constant current source and a load transistor; The differential amplifier is used to compare the comparison voltage with the reference voltage and output the load driving current; The self-biased constant current source is used to provide bias current to the differential amplifier; The load transistor is used to convert the load driving current into a corresponding first target level.

4. A level conversion circuit for suppressing PVT fluctuations according to claim 3, characterized in that: The differential amplifier includes a first transistor and a second transistor; wherein the gate of the first transistor is connected to the input voltage through a first resistor and is connected to a -5V power supply through a second resistor; the source of the first transistor is connected to the source of the second transistor; the drain of the first transistor and the drain of the second transistor are both connected to a load transistor; The gate of the second transistor is connected to a -5V power supply through a seventh resistor and is grounded through a sixth resistor; The self-biased constant current source includes a third transistor; the gate of the third transistor is connected to a -5V power supply through a third resistor; The source of the third transistor is connected to a -5V power supply via a fourth resistor; the drain of the third transistor is connected to the source of the first transistor and the source of the second transistor; The load transistor includes a fourth transistor and a fifth transistor; The source of the fourth transistor is connected to the drain of the first transistor; the gate of the fourth transistor and the source of the second transistor are connected to the gate of the fifth transistor, and are connected to the source of the fifth transistor through the fifth resistor; the drain of the fourth transistor and the drain of the fifth transistor are grounded.

5. A level conversion circuit for suppressing PVT fluctuations according to claim 1, characterized in that: The logic level conversion circuit includes a source follower and a diode voltage drop circuit; The source follower is used to output the first target level output by the comparator circuit in equal amount; The diode drop circuit is used to generate a level shift using a diode drop chain, converting an equal output of a first target level into a second target level corresponding to the first target level.

6. A level conversion circuit for suppressing PVT fluctuations according to claim 5, characterized in that: The source follower includes a sixth transistor; the gate of the sixth transistor is connected to the first target level output by the comparator circuit; the drain of the sixth transistor is grounded through an eighth resistor; the source of the sixth transistor is connected to the diode drop circuit; The diode drop circuit includes a seventh transistor, an eighth transistor and a ninth transistor; the source and the drain of each transistor are connected, and the gate of the latter transistor is connected to the drain and the source of the former transistor; the gate of the seventh transistor is connected to the source of the sixth transistor; The source and drain of the ninth transistor are connected to a -5V power supply via a ninth resistor.

7. A level conversion circuit for suppressing PVT fluctuations according to claim 6, characterized in that: The diode voltage drop circuit also includes a tenth resistor; one end of the tenth resistor is connected to the source and drain of the ninth transistor, and the other end of the tenth resistor is connected to the output circuit.

8. The level conversion circuit for suppressing PVT fluctuation according to claim 1, characterized in that: The output circuit includes an inverting logic circuit and a load circuit; The inversion logic circuit is used for performing logic inversion on the second target level output by the logic level conversion circuit; The load circuit is used to perform a resistance voltage drop on the logic inversion signal by using a complementary active load, and output complementary high and low levels corresponding to the second target level.

9. A level conversion circuit for suppressing PVT fluctuations according to claim 8, characterized in that: The reverse logic circuit includes a tenth transistor, an eleventh transistor, a fourteenth transistor and a fifteenth transistor; the gate of the tenth transistor is connected to the second target level output by the logic level conversion circuit; the drain of the tenth transistor is respectively connected to the gate of the eleventh transistor and the gate of the fifteenth transistor; the drain of the eleventh transistor is connected to the gate of the fourteenth transistor; the source of the tenth transistor, the source of the eleventh transistor, the source of the fourteenth transistor and the source of the fifteenth transistor are connected to a -5V power supply; The load circuit includes a twelfth transistor, a thirteenth transistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor and a fifteenth resistor; one end of the twelfth resistor is connected to the drain of the tenth transistor; one end of the thirteenth resistor is connected to the drain of the eleventh transistor; the other ends of the twelfth resistor and the thirteenth resistor are grounded through the eleventh resistor; the gate of the twelfth transistor is connected to the drain of the fourteenth transistor; the source of the twelfth transistor is connected to the drain of the fourteenth transistor through the fourteenth resistor; the gate of the thirteenth transistor is connected to the drain of the fifteenth transistor; the source of the thirteenth transistor is connected to the drain of the fifteenth transistor through the fifteenth resistor; the drain of the twelfth transistor and the drain of the thirteenth transistor are grounded.

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